1288aaacfSAlexey Brodkin /* 2288aaacfSAlexey Brodkin * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved. 3288aaacfSAlexey Brodkin * 4288aaacfSAlexey Brodkin * SPDX-License-Identifier: GPL-2.0+ 5288aaacfSAlexey Brodkin */ 6288aaacfSAlexey Brodkin 7288aaacfSAlexey Brodkin #ifndef _ASM_ARC_ARCREGS_H 8288aaacfSAlexey Brodkin #define _ASM_ARC_ARCREGS_H 9288aaacfSAlexey Brodkin 10812980bdSAlexey Brodkin #include <asm/cache.h> 11812980bdSAlexey Brodkin 12288aaacfSAlexey Brodkin /* 13288aaacfSAlexey Brodkin * ARC architecture has additional address space - auxiliary registers. 14288aaacfSAlexey Brodkin * These registers are mostly used for configuration purposes. 15288aaacfSAlexey Brodkin * These registers are not memory mapped and special commands are used for 16288aaacfSAlexey Brodkin * access: "lr"/"sr". 17288aaacfSAlexey Brodkin */ 18288aaacfSAlexey Brodkin 19288aaacfSAlexey Brodkin #define ARC_AUX_IDENTITY 0x04 20288aaacfSAlexey Brodkin #define ARC_AUX_STATUS32 0x0a 21288aaacfSAlexey Brodkin 22288aaacfSAlexey Brodkin /* Instruction cache related auxiliary registers */ 23288aaacfSAlexey Brodkin #define ARC_AUX_IC_IVIC 0x10 24288aaacfSAlexey Brodkin #define ARC_AUX_IC_CTRL 0x11 25288aaacfSAlexey Brodkin #define ARC_AUX_IC_IVIL 0x19 265ff40f3dSAlexey Brodkin #if (CONFIG_ARC_MMU_VER == 3) 27288aaacfSAlexey Brodkin #define ARC_AUX_IC_PTAG 0x1E 28288aaacfSAlexey Brodkin #endif 29f8cf3d1eSIgor Guryanov #define ARC_BCR_IC_BUILD 0x77 3064f47426SEugeniy Paltsev #define AUX_AUX_CACHE_LIMIT 0x5D 3164f47426SEugeniy Paltsev #define ARC_AUX_NON_VOLATILE_LIMIT 0x5E 3264f47426SEugeniy Paltsev 3364f47426SEugeniy Paltsev /* ICCM and DCCM auxiliary registers */ 3464f47426SEugeniy Paltsev #define ARC_AUX_DCCM_BASE 0x18 /* DCCM Base Addr ARCv2 */ 3564f47426SEugeniy Paltsev #define ARC_AUX_ICCM_BASE 0x208 /* ICCM Base Addr ARCv2 */ 36288aaacfSAlexey Brodkin 37288aaacfSAlexey Brodkin /* Timer related auxiliary registers */ 38288aaacfSAlexey Brodkin #define ARC_AUX_TIMER0_CNT 0x21 /* Timer 0 count */ 39288aaacfSAlexey Brodkin #define ARC_AUX_TIMER0_CTRL 0x22 /* Timer 0 control */ 40288aaacfSAlexey Brodkin #define ARC_AUX_TIMER0_LIMIT 0x23 /* Timer 0 limit */ 41288aaacfSAlexey Brodkin 42ad9b5f77SVlad Zakharov #define ARC_AUX_TIMER1_CNT 0x100 /* Timer 1 count */ 43ad9b5f77SVlad Zakharov #define ARC_AUX_TIMER1_CTRL 0x101 /* Timer 1 control */ 44ad9b5f77SVlad Zakharov #define ARC_AUX_TIMER1_LIMIT 0x102 /* Timer 1 limit */ 45ad9b5f77SVlad Zakharov 46288aaacfSAlexey Brodkin #define ARC_AUX_INTR_VEC_BASE 0x25 47288aaacfSAlexey Brodkin 48288aaacfSAlexey Brodkin /* Data cache related auxiliary registers */ 49288aaacfSAlexey Brodkin #define ARC_AUX_DC_IVDC 0x47 50288aaacfSAlexey Brodkin #define ARC_AUX_DC_CTRL 0x48 51288aaacfSAlexey Brodkin 52288aaacfSAlexey Brodkin #define ARC_AUX_DC_IVDL 0x4A 53288aaacfSAlexey Brodkin #define ARC_AUX_DC_FLSH 0x4B 54288aaacfSAlexey Brodkin #define ARC_AUX_DC_FLDL 0x4C 555ff40f3dSAlexey Brodkin #if (CONFIG_ARC_MMU_VER == 3) 56288aaacfSAlexey Brodkin #define ARC_AUX_DC_PTAG 0x5C 57288aaacfSAlexey Brodkin #endif 58f8cf3d1eSIgor Guryanov #define ARC_BCR_DC_BUILD 0x72 596eb15e50SAlexey Brodkin #define ARC_BCR_SLC 0xce 60ef639e6fSAlexey Brodkin #define ARC_AUX_SLC_CONFIG 0x901 61ef639e6fSAlexey Brodkin #define ARC_AUX_SLC_CTRL 0x903 626eb15e50SAlexey Brodkin #define ARC_AUX_SLC_FLUSH 0x904 636eb15e50SAlexey Brodkin #define ARC_AUX_SLC_INVALIDATE 0x905 64ef639e6fSAlexey Brodkin #define ARC_AUX_SLC_IVDL 0x910 65ef639e6fSAlexey Brodkin #define ARC_AUX_SLC_FLDL 0x912 66*41cada4dSEugeniy Paltsev #define ARC_AUX_SLC_RGN_START 0x914 67*41cada4dSEugeniy Paltsev #define ARC_AUX_SLC_RGN_START1 0x915 68*41cada4dSEugeniy Paltsev #define ARC_AUX_SLC_RGN_END 0x916 69*41cada4dSEugeniy Paltsev #define ARC_AUX_SLC_RGN_END1 0x917 70db6ce231SAlexey Brodkin #define ARC_BCR_CLUSTER 0xcf 71db6ce231SAlexey Brodkin 72*41cada4dSEugeniy Paltsev /* MMU Management regs */ 73*41cada4dSEugeniy Paltsev #define ARC_AUX_MMU_BCR 0x06f 74*41cada4dSEugeniy Paltsev 75db6ce231SAlexey Brodkin /* IO coherency related auxiliary registers */ 76db6ce231SAlexey Brodkin #define ARC_AUX_IO_COH_ENABLE 0x500 77db6ce231SAlexey Brodkin #define ARC_AUX_IO_COH_PARTIAL 0x501 78db6ce231SAlexey Brodkin #define ARC_AUX_IO_COH_AP0_BASE 0x508 79db6ce231SAlexey Brodkin #define ARC_AUX_IO_COH_AP0_SIZE 0x509 80288aaacfSAlexey Brodkin 81288aaacfSAlexey Brodkin #ifndef __ASSEMBLY__ 82288aaacfSAlexey Brodkin /* Accessors for auxiliary registers */ 83288aaacfSAlexey Brodkin #define read_aux_reg(reg) __builtin_arc_lr(reg) 84288aaacfSAlexey Brodkin 85288aaacfSAlexey Brodkin /* gcc builtin sr needs reg param to be long immediate */ 86288aaacfSAlexey Brodkin #define write_aux_reg(reg_immed, val) \ 87288aaacfSAlexey Brodkin __builtin_arc_sr((unsigned int)val, reg_immed) 88e59c3797SEugeniy Paltsev 89e59c3797SEugeniy Paltsev /* ARCNUM [15:8] - field to identify each core in a multi-core system */ 90e59c3797SEugeniy Paltsev #define CPU_ID_GET() ((read_aux_reg(ARC_AUX_IDENTITY) & 0xFF00) >> 8) 91288aaacfSAlexey Brodkin #endif /* __ASSEMBLY__ */ 92288aaacfSAlexey Brodkin 93288aaacfSAlexey Brodkin #endif /* _ASM_ARC_ARCREGS_H */ 94