1*288aaacfSAlexey Brodkin /* 2*288aaacfSAlexey Brodkin * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved. 3*288aaacfSAlexey Brodkin * 4*288aaacfSAlexey Brodkin * SPDX-License-Identifier: GPL-2.0+ 5*288aaacfSAlexey Brodkin */ 6*288aaacfSAlexey Brodkin 7*288aaacfSAlexey Brodkin #ifndef _ASM_ARC_ARCREGS_H 8*288aaacfSAlexey Brodkin #define _ASM_ARC_ARCREGS_H 9*288aaacfSAlexey Brodkin 10*288aaacfSAlexey Brodkin /* 11*288aaacfSAlexey Brodkin * ARC architecture has additional address space - auxiliary registers. 12*288aaacfSAlexey Brodkin * These registers are mostly used for configuration purposes. 13*288aaacfSAlexey Brodkin * These registers are not memory mapped and special commands are used for 14*288aaacfSAlexey Brodkin * access: "lr"/"sr". 15*288aaacfSAlexey Brodkin */ 16*288aaacfSAlexey Brodkin 17*288aaacfSAlexey Brodkin #define ARC_AUX_IDENTITY 0x04 18*288aaacfSAlexey Brodkin #define ARC_AUX_STATUS32 0x0a 19*288aaacfSAlexey Brodkin 20*288aaacfSAlexey Brodkin /* Instruction cache related auxiliary registers */ 21*288aaacfSAlexey Brodkin #define ARC_AUX_IC_IVIC 0x10 22*288aaacfSAlexey Brodkin #define ARC_AUX_IC_CTRL 0x11 23*288aaacfSAlexey Brodkin #define ARC_AUX_IC_IVIL 0x19 24*288aaacfSAlexey Brodkin #if (CONFIG_ARC_MMU_VER > 2) 25*288aaacfSAlexey Brodkin #define ARC_AUX_IC_PTAG 0x1E 26*288aaacfSAlexey Brodkin #endif 27*288aaacfSAlexey Brodkin 28*288aaacfSAlexey Brodkin /* Timer related auxiliary registers */ 29*288aaacfSAlexey Brodkin #define ARC_AUX_TIMER0_CNT 0x21 /* Timer 0 count */ 30*288aaacfSAlexey Brodkin #define ARC_AUX_TIMER0_CTRL 0x22 /* Timer 0 control */ 31*288aaacfSAlexey Brodkin #define ARC_AUX_TIMER0_LIMIT 0x23 /* Timer 0 limit */ 32*288aaacfSAlexey Brodkin 33*288aaacfSAlexey Brodkin #define ARC_AUX_INTR_VEC_BASE 0x25 34*288aaacfSAlexey Brodkin 35*288aaacfSAlexey Brodkin /* Data cache related auxiliary registers */ 36*288aaacfSAlexey Brodkin #define ARC_AUX_DC_IVDC 0x47 37*288aaacfSAlexey Brodkin #define ARC_AUX_DC_CTRL 0x48 38*288aaacfSAlexey Brodkin 39*288aaacfSAlexey Brodkin #define ARC_AUX_DC_IVDL 0x4A 40*288aaacfSAlexey Brodkin #define ARC_AUX_DC_FLSH 0x4B 41*288aaacfSAlexey Brodkin #define ARC_AUX_DC_FLDL 0x4C 42*288aaacfSAlexey Brodkin #if (CONFIG_ARC_MMU_VER > 2) 43*288aaacfSAlexey Brodkin #define ARC_AUX_DC_PTAG 0x5C 44*288aaacfSAlexey Brodkin #endif 45*288aaacfSAlexey Brodkin 46*288aaacfSAlexey Brodkin #ifndef __ASSEMBLY__ 47*288aaacfSAlexey Brodkin /* Accessors for auxiliary registers */ 48*288aaacfSAlexey Brodkin #define read_aux_reg(reg) __builtin_arc_lr(reg) 49*288aaacfSAlexey Brodkin 50*288aaacfSAlexey Brodkin /* gcc builtin sr needs reg param to be long immediate */ 51*288aaacfSAlexey Brodkin #define write_aux_reg(reg_immed, val) \ 52*288aaacfSAlexey Brodkin __builtin_arc_sr((unsigned int)val, reg_immed) 53*288aaacfSAlexey Brodkin #endif /* __ASSEMBLY__ */ 54*288aaacfSAlexey Brodkin 55*288aaacfSAlexey Brodkin #endif /* _ASM_ARC_ARCREGS_H */ 56