1/* 2 * Copyright (C) 2017 Synopsys, Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6/dts-v1/; 7 8#include "skeleton.dtsi" 9#include "dt-bindings/clock/snps,hsdk-cgu.h" 10 11/ { 12 #address-cells = <1>; 13 #size-cells = <1>; 14 15 aliases { 16 console = &uart0; 17 spi0 = &spi0; 18 }; 19 20 cpu_card { 21 core_clk: core_clk { 22 #clock-cells = <0>; 23 compatible = "fixed-clock"; 24 clock-frequency = <1000000000>; 25 u-boot,dm-pre-reloc; 26 }; 27 }; 28 29 clk-fmeas { 30 clocks = <&cgu_clk CLK_ARC_PLL>, <&cgu_clk CLK_SYS_PLL>, 31 <&cgu_clk CLK_TUN_PLL>, <&cgu_clk CLK_DDR_PLL>, 32 <&cgu_clk CLK_ARC>, <&cgu_clk CLK_HDMI_PLL>, 33 <&cgu_clk CLK_TUN_TUN>, <&cgu_clk CLK_HDMI>, 34 <&cgu_clk CLK_SYS_APB>, <&cgu_clk CLK_SYS_AXI>, 35 <&cgu_clk CLK_SYS_ETH>, <&cgu_clk CLK_SYS_USB>, 36 <&cgu_clk CLK_SYS_SDIO>, <&cgu_clk CLK_SYS_HDMI>, 37 <&cgu_clk CLK_SYS_GFX_CORE>, <&cgu_clk CLK_SYS_GFX_DMA>, 38 <&cgu_clk CLK_SYS_GFX_CFG>, <&cgu_clk CLK_SYS_DMAC_CORE>, 39 <&cgu_clk CLK_SYS_DMAC_CFG>, <&cgu_clk CLK_SYS_SDIO_REF>, 40 <&cgu_clk CLK_SYS_SPI_REF>, <&cgu_clk CLK_SYS_I2C_REF>, 41 <&cgu_clk CLK_SYS_UART_REF>, <&cgu_clk CLK_SYS_EBI_REF>, 42 <&cgu_clk CLK_TUN_ROM>, <&cgu_clk CLK_TUN_PWM>; 43 clock-names = "cpu-pll", "sys-pll", 44 "tun-pll", "ddr-clk", 45 "cpu-clk", "hdmi-pll", 46 "tun-clk", "hdmi-clk", 47 "apb-clk", "axi-clk", 48 "eth-clk", "usb-clk", 49 "sdio-clk", "hdmi-sys-clk", 50 "gfx-core-clk", "gfx-dma-clk", 51 "gfx-cfg-clk", "dmac-core-clk", 52 "dmac-cfg-clk", "sdio-ref-clk", 53 "spi-clk", "i2c-clk", 54 "uart-clk", "ebi-clk", 55 "rom-clk", "pwm-clk"; 56 }; 57 58 cgu_clk: cgu-clk@f0000000 { 59 compatible = "snps,hsdk-cgu-clock"; 60 reg = <0xf0000000 0x10>, <0xf00014B8 0x4>; 61 #clock-cells = <1>; 62 }; 63 64 uart0: serial0@f0005000 { 65 compatible = "snps,dw-apb-uart"; 66 reg = <0xf0005000 0x1000>; 67 reg-shift = <2>; 68 reg-io-width = <4>; 69 }; 70 71 ethernet@f0008000 { 72 #interrupt-cells = <1>; 73 compatible = "altr,socfpga-stmmac"; 74 reg = <0xf0008000 0x2000>; 75 phy-mode = "gmii"; 76 }; 77 78 ehci@0xf0040000 { 79 compatible = "generic-ehci"; 80 reg = <0xf0040000 0x100>; 81 }; 82 83 ohci@0xf0060000 { 84 compatible = "generic-ohci"; 85 reg = <0xf0060000 0x100>; 86 }; 87 88 spi0: spi@f0020000 { 89 compatible = "snps,dw-apb-ssi"; 90 reg = <0xf0020000 0x1000>; 91 #address-cells = <1>; 92 #size-cells = <0>; 93 spi-max-frequency = <4000000>; 94 clocks = <&cgu_clk CLK_SYS_SPI_REF>; 95 clock-names = "spi_clk"; 96 cs-gpio = <&cs_gpio 0>; 97 spi_flash@0 { 98 compatible = "spi-flash"; 99 reg = <0>; 100 spi-max-frequency = <4000000>; 101 }; 102 }; 103 104 cs_gpio: gpio@f00014b0 { 105 compatible = "snps,hsdk-creg-gpio"; 106 reg = <0xf00014b0 0x4>; 107 gpio-controller; 108 #gpio-cells = <1>; 109 gpio-bank-name = "hsdk-spi-cs"; 110 gpio-count = <1>; 111 }; 112}; 113