1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2017 Synopsys, Inc. All rights reserved. 4 */ 5/dts-v1/; 6 7#include "skeleton.dtsi" 8#include "dt-bindings/clock/snps,hsdk-cgu.h" 9 10/ { 11 model = "snps,hsdk"; 12 13 #address-cells = <1>; 14 #size-cells = <1>; 15 16 aliases { 17 console = &uart0; 18 spi0 = &spi0; 19 }; 20 21 cpu_card { 22 core_clk: core_clk { 23 #clock-cells = <0>; 24 compatible = "fixed-clock"; 25 clock-frequency = <500000000>; 26 u-boot,dm-pre-reloc; 27 }; 28 }; 29 30 clk-fmeas { 31 clocks = <&cgu_clk CLK_ARC_PLL>, <&cgu_clk CLK_SYS_PLL>, 32 <&cgu_clk CLK_TUN_PLL>, <&cgu_clk CLK_DDR_PLL>, 33 <&cgu_clk CLK_ARC>, <&cgu_clk CLK_HDMI_PLL>, 34 <&cgu_clk CLK_TUN_TUN>, <&cgu_clk CLK_HDMI>, 35 <&cgu_clk CLK_SYS_APB>, <&cgu_clk CLK_SYS_AXI>, 36 <&cgu_clk CLK_SYS_ETH>, <&cgu_clk CLK_SYS_USB>, 37 <&cgu_clk CLK_SYS_SDIO>, <&cgu_clk CLK_SYS_HDMI>, 38 <&cgu_clk CLK_SYS_GFX_CORE>, <&cgu_clk CLK_SYS_GFX_DMA>, 39 <&cgu_clk CLK_SYS_GFX_CFG>, <&cgu_clk CLK_SYS_DMAC_CORE>, 40 <&cgu_clk CLK_SYS_DMAC_CFG>, <&cgu_clk CLK_SYS_SDIO_REF>, 41 <&cgu_clk CLK_SYS_SPI_REF>, <&cgu_clk CLK_SYS_I2C_REF>, 42 <&cgu_clk CLK_SYS_UART_REF>, <&cgu_clk CLK_SYS_EBI_REF>, 43 <&cgu_clk CLK_TUN_ROM>, <&cgu_clk CLK_TUN_PWM>; 44 clock-names = "cpu-pll", "sys-pll", 45 "tun-pll", "ddr-clk", 46 "cpu-clk", "hdmi-pll", 47 "tun-clk", "hdmi-clk", 48 "apb-clk", "axi-clk", 49 "eth-clk", "usb-clk", 50 "sdio-clk", "hdmi-sys-clk", 51 "gfx-core-clk", "gfx-dma-clk", 52 "gfx-cfg-clk", "dmac-core-clk", 53 "dmac-cfg-clk", "sdio-ref-clk", 54 "spi-clk", "i2c-clk", 55 "uart-clk", "ebi-clk", 56 "rom-clk", "pwm-clk"; 57 }; 58 59 cgu_clk: cgu-clk@f0000000 { 60 compatible = "snps,hsdk-cgu-clock"; 61 reg = <0xf0000000 0x10>, <0xf00014B8 0x4>; 62 #clock-cells = <1>; 63 }; 64 65 uart0: serial0@f0005000 { 66 compatible = "snps,dw-apb-uart"; 67 reg = <0xf0005000 0x1000>; 68 reg-shift = <2>; 69 reg-io-width = <4>; 70 }; 71 72 ethernet@f0008000 { 73 #interrupt-cells = <1>; 74 compatible = "altr,socfpga-stmmac"; 75 reg = <0xf0008000 0x2000>; 76 phy-mode = "gmii"; 77 }; 78 79 ehci@0xf0040000 { 80 compatible = "generic-ehci"; 81 reg = <0xf0040000 0x100>; 82 }; 83 84 ohci@0xf0060000 { 85 compatible = "generic-ohci"; 86 reg = <0xf0060000 0x100>; 87 }; 88 89 spi0: spi@f0020000 { 90 compatible = "snps,dw-apb-ssi"; 91 reg = <0xf0020000 0x1000>; 92 #address-cells = <1>; 93 #size-cells = <0>; 94 spi-max-frequency = <4000000>; 95 clocks = <&cgu_clk CLK_SYS_SPI_REF>; 96 clock-names = "spi_clk"; 97 cs-gpio = <&cs_gpio 0>; 98 spi_flash@0 { 99 compatible = "spi-flash"; 100 reg = <0>; 101 spi-max-frequency = <4000000>; 102 }; 103 }; 104 105 cs_gpio: gpio@f00014b0 { 106 compatible = "snps,creg-gpio"; 107 reg = <0xf00014b0 0x4>; 108 gpio-controller; 109 #gpio-cells = <1>; 110 gpio-bank-name = "hsdk-spi-cs"; 111 gpio-count = <1>; 112 gpio-first-shift = <0>; 113 gpio-bit-per-line = <2>; 114 gpio-activate-val = <2>; 115 gpio-deactivate-val = <3>; 116 gpio-default-val = <1>; 117 }; 118}; 119