1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2017 Synopsys, Inc. All rights reserved. 4 */ 5/dts-v1/; 6 7#include "skeleton.dtsi" 8#include "dt-bindings/clock/snps,hsdk-cgu.h" 9 10/ { 11 #address-cells = <1>; 12 #size-cells = <1>; 13 14 aliases { 15 console = &uart0; 16 spi0 = &spi0; 17 }; 18 19 cpu_card { 20 core_clk: core_clk { 21 #clock-cells = <0>; 22 compatible = "fixed-clock"; 23 clock-frequency = <1000000000>; 24 u-boot,dm-pre-reloc; 25 }; 26 }; 27 28 clk-fmeas { 29 clocks = <&cgu_clk CLK_ARC_PLL>, <&cgu_clk CLK_SYS_PLL>, 30 <&cgu_clk CLK_TUN_PLL>, <&cgu_clk CLK_DDR_PLL>, 31 <&cgu_clk CLK_ARC>, <&cgu_clk CLK_HDMI_PLL>, 32 <&cgu_clk CLK_TUN_TUN>, <&cgu_clk CLK_HDMI>, 33 <&cgu_clk CLK_SYS_APB>, <&cgu_clk CLK_SYS_AXI>, 34 <&cgu_clk CLK_SYS_ETH>, <&cgu_clk CLK_SYS_USB>, 35 <&cgu_clk CLK_SYS_SDIO>, <&cgu_clk CLK_SYS_HDMI>, 36 <&cgu_clk CLK_SYS_GFX_CORE>, <&cgu_clk CLK_SYS_GFX_DMA>, 37 <&cgu_clk CLK_SYS_GFX_CFG>, <&cgu_clk CLK_SYS_DMAC_CORE>, 38 <&cgu_clk CLK_SYS_DMAC_CFG>, <&cgu_clk CLK_SYS_SDIO_REF>, 39 <&cgu_clk CLK_SYS_SPI_REF>, <&cgu_clk CLK_SYS_I2C_REF>, 40 <&cgu_clk CLK_SYS_UART_REF>, <&cgu_clk CLK_SYS_EBI_REF>, 41 <&cgu_clk CLK_TUN_ROM>, <&cgu_clk CLK_TUN_PWM>; 42 clock-names = "cpu-pll", "sys-pll", 43 "tun-pll", "ddr-clk", 44 "cpu-clk", "hdmi-pll", 45 "tun-clk", "hdmi-clk", 46 "apb-clk", "axi-clk", 47 "eth-clk", "usb-clk", 48 "sdio-clk", "hdmi-sys-clk", 49 "gfx-core-clk", "gfx-dma-clk", 50 "gfx-cfg-clk", "dmac-core-clk", 51 "dmac-cfg-clk", "sdio-ref-clk", 52 "spi-clk", "i2c-clk", 53 "uart-clk", "ebi-clk", 54 "rom-clk", "pwm-clk"; 55 }; 56 57 cgu_clk: cgu-clk@f0000000 { 58 compatible = "snps,hsdk-cgu-clock"; 59 reg = <0xf0000000 0x10>, <0xf00014B8 0x4>; 60 #clock-cells = <1>; 61 }; 62 63 uart0: serial0@f0005000 { 64 compatible = "snps,dw-apb-uart"; 65 reg = <0xf0005000 0x1000>; 66 reg-shift = <2>; 67 reg-io-width = <4>; 68 }; 69 70 ethernet@f0008000 { 71 #interrupt-cells = <1>; 72 compatible = "altr,socfpga-stmmac"; 73 reg = <0xf0008000 0x2000>; 74 phy-mode = "gmii"; 75 }; 76 77 ehci@0xf0040000 { 78 compatible = "generic-ehci"; 79 reg = <0xf0040000 0x100>; 80 }; 81 82 ohci@0xf0060000 { 83 compatible = "generic-ohci"; 84 reg = <0xf0060000 0x100>; 85 }; 86 87 spi0: spi@f0020000 { 88 compatible = "snps,dw-apb-ssi"; 89 reg = <0xf0020000 0x1000>; 90 #address-cells = <1>; 91 #size-cells = <0>; 92 spi-max-frequency = <4000000>; 93 clocks = <&cgu_clk CLK_SYS_SPI_REF>; 94 clock-names = "spi_clk"; 95 cs-gpio = <&cs_gpio 0>; 96 spi_flash@0 { 97 compatible = "spi-flash"; 98 reg = <0>; 99 spi-max-frequency = <4000000>; 100 }; 101 }; 102 103 cs_gpio: gpio@f00014b0 { 104 compatible = "snps,creg-gpio"; 105 reg = <0xf00014b0 0x4>; 106 gpio-controller; 107 #gpio-cells = <1>; 108 gpio-bank-name = "hsdk-spi-cs"; 109 gpio-count = <1>; 110 gpio-first-shift = <0>; 111 gpio-bit-per-line = <2>; 112 gpio-activate-val = <2>; 113 gpio-deactivate-val = <3>; 114 gpio-default-val = <1>; 115 }; 116}; 117