1*83d290c5STom Rini// SPDX-License-Identifier: GPL-2.0+ 20c77092eSVlad Zakharov/* 30c77092eSVlad Zakharov * Copyright (C) 2017 Synopsys, Inc. All rights reserved. 40c77092eSVlad Zakharov */ 50c77092eSVlad Zakharov 60c77092eSVlad Zakharov/ { 70c77092eSVlad Zakharov axs10x_mb@e0000000 { 80c77092eSVlad Zakharov compatible = "simple-bus"; 90c77092eSVlad Zakharov #address-cells = <1>; 100c77092eSVlad Zakharov #size-cells = <1>; 110c77092eSVlad Zakharov ranges = <0x00000000 0xe0000000 0x10000000>; 120c77092eSVlad Zakharov u-boot,dm-pre-reloc; 130c77092eSVlad Zakharov 140c77092eSVlad Zakharov clocks { 150c77092eSVlad Zakharov compatible = "simple-bus"; 160c77092eSVlad Zakharov u-boot,dm-pre-reloc; 170c77092eSVlad Zakharov 180c77092eSVlad Zakharov apbclk: apbclk { 190c77092eSVlad Zakharov compatible = "fixed-clock"; 200c77092eSVlad Zakharov clock-frequency = <50000000>; 210c77092eSVlad Zakharov #clock-cells = <0>; 220c77092eSVlad Zakharov }; 230c77092eSVlad Zakharov 240c77092eSVlad Zakharov uartclk: uartclk { 250c77092eSVlad Zakharov compatible = "fixed-clock"; 260c77092eSVlad Zakharov clock-frequency = <33333333>; 270c77092eSVlad Zakharov #clock-cells = <0>; 280c77092eSVlad Zakharov u-boot,dm-pre-reloc; 290c77092eSVlad Zakharov }; 300c77092eSVlad Zakharov }; 310c77092eSVlad Zakharov 320c77092eSVlad Zakharov ethernet@18000 { 330c77092eSVlad Zakharov compatible = "altr,socfpga-stmmac"; 340c77092eSVlad Zakharov reg = < 0x18000 0x2000 >; 350c77092eSVlad Zakharov phy-mode = "gmii"; 360c77092eSVlad Zakharov snps,pbl = < 32 >; 370c77092eSVlad Zakharov clocks = <&apbclk>; 380c77092eSVlad Zakharov clock-names = "stmmaceth"; 390c77092eSVlad Zakharov max-speed = <100>; 400c77092eSVlad Zakharov }; 410c77092eSVlad Zakharov 420c77092eSVlad Zakharov ehci@0x40000 { 430c77092eSVlad Zakharov compatible = "generic-ehci"; 440c77092eSVlad Zakharov reg = < 0x40000 0x100 >; 450c77092eSVlad Zakharov }; 460c77092eSVlad Zakharov 470c77092eSVlad Zakharov ohci@0x60000 { 480c77092eSVlad Zakharov compatible = "generic-ohci"; 490c77092eSVlad Zakharov reg = < 0x60000 0x100 >; 500c77092eSVlad Zakharov }; 510c77092eSVlad Zakharov 520c77092eSVlad Zakharov uart0: serial0@22000 { 530c77092eSVlad Zakharov compatible = "snps,dw-apb-uart"; 540c77092eSVlad Zakharov reg = <0x22000 0x100>; 550c77092eSVlad Zakharov clocks = <&uartclk>; 560c77092eSVlad Zakharov reg-shift = <2>; 570c77092eSVlad Zakharov reg-io-width = <4>; 580c77092eSVlad Zakharov }; 590c77092eSVlad Zakharov }; 600c77092eSVlad Zakharov}; 61