1*0c77092eSVlad Zakharov/* 2*0c77092eSVlad Zakharov * Copyright (C) 2017 Synopsys, Inc. All rights reserved. 3*0c77092eSVlad Zakharov * 4*0c77092eSVlad Zakharov * SPDX-License-Identifier: GPL-2.0+ 5*0c77092eSVlad Zakharov */ 6*0c77092eSVlad Zakharov 7*0c77092eSVlad Zakharov/ { 8*0c77092eSVlad Zakharov axs10x_mb@e0000000 { 9*0c77092eSVlad Zakharov compatible = "simple-bus"; 10*0c77092eSVlad Zakharov #address-cells = <1>; 11*0c77092eSVlad Zakharov #size-cells = <1>; 12*0c77092eSVlad Zakharov ranges = <0x00000000 0xe0000000 0x10000000>; 13*0c77092eSVlad Zakharov u-boot,dm-pre-reloc; 14*0c77092eSVlad Zakharov 15*0c77092eSVlad Zakharov clocks { 16*0c77092eSVlad Zakharov compatible = "simple-bus"; 17*0c77092eSVlad Zakharov u-boot,dm-pre-reloc; 18*0c77092eSVlad Zakharov 19*0c77092eSVlad Zakharov apbclk: apbclk { 20*0c77092eSVlad Zakharov compatible = "fixed-clock"; 21*0c77092eSVlad Zakharov clock-frequency = <50000000>; 22*0c77092eSVlad Zakharov #clock-cells = <0>; 23*0c77092eSVlad Zakharov }; 24*0c77092eSVlad Zakharov 25*0c77092eSVlad Zakharov uartclk: uartclk { 26*0c77092eSVlad Zakharov compatible = "fixed-clock"; 27*0c77092eSVlad Zakharov clock-frequency = <33333333>; 28*0c77092eSVlad Zakharov #clock-cells = <0>; 29*0c77092eSVlad Zakharov u-boot,dm-pre-reloc; 30*0c77092eSVlad Zakharov }; 31*0c77092eSVlad Zakharov }; 32*0c77092eSVlad Zakharov 33*0c77092eSVlad Zakharov ethernet@18000 { 34*0c77092eSVlad Zakharov #interrupt-cells = <1>; 35*0c77092eSVlad Zakharov compatible = "altr,socfpga-stmmac"; 36*0c77092eSVlad Zakharov reg = < 0x18000 0x2000 >; 37*0c77092eSVlad Zakharov interrupts = < 25 >; 38*0c77092eSVlad Zakharov interrupt-names = "macirq"; 39*0c77092eSVlad Zakharov phy-mode = "gmii"; 40*0c77092eSVlad Zakharov snps,pbl = < 32 >; 41*0c77092eSVlad Zakharov clocks = <&apbclk>; 42*0c77092eSVlad Zakharov clock-names = "stmmaceth"; 43*0c77092eSVlad Zakharov max-speed = <100>; 44*0c77092eSVlad Zakharov }; 45*0c77092eSVlad Zakharov 46*0c77092eSVlad Zakharov ehci@0x40000 { 47*0c77092eSVlad Zakharov compatible = "generic-ehci"; 48*0c77092eSVlad Zakharov reg = < 0x40000 0x100 >; 49*0c77092eSVlad Zakharov interrupts = < 8 >; 50*0c77092eSVlad Zakharov }; 51*0c77092eSVlad Zakharov 52*0c77092eSVlad Zakharov ohci@0x60000 { 53*0c77092eSVlad Zakharov compatible = "generic-ohci"; 54*0c77092eSVlad Zakharov reg = < 0x60000 0x100 >; 55*0c77092eSVlad Zakharov interrupts = < 8 >; 56*0c77092eSVlad Zakharov }; 57*0c77092eSVlad Zakharov 58*0c77092eSVlad Zakharov uart0: serial0@22000 { 59*0c77092eSVlad Zakharov compatible = "snps,dw-apb-uart"; 60*0c77092eSVlad Zakharov reg = <0x22000 0x100>; 61*0c77092eSVlad Zakharov clocks = <&uartclk>; 62*0c77092eSVlad Zakharov reg-shift = <2>; 63*0c77092eSVlad Zakharov reg-io-width = <4>; 64*0c77092eSVlad Zakharov }; 65*0c77092eSVlad Zakharov }; 66*0c77092eSVlad Zakharov}; 67