1#include "macros.inc" 2 3#define CCOUNT_SHIFT 4 4#define WAIT_LOOPS 20 5 6.macro make_ccount_delta target, delta 7 rsr \delta, ccount 8 rsr \target, ccount 9 sub \delta, \target, \delta 10 slli \delta, \delta, CCOUNT_SHIFT 11 add \target, \target, \delta 12.endm 13 14test_suite timer 15 16test ccount 17 rsr a3, ccount 18 rsr a4, ccount 19 assert ne, a3, a4 20test_end 21 22test ccount_write 23 rsr a3, ccount 24 rsr a4, ccount 25 sub a4, a4, a3 26 movi a2, 0x12345678 27 wsr a2, ccount 28 esync 29 rsr a3, ccount 30 sub a3, a3, a2 31 slli a4, a4, 2 32 assert ltu, a3, a4 33test_end 34 35test ccount_update_deadline 36 movi a2, 0 37 wsr a2, intenable 38 rsr a2, interrupt 39 wsr a2, intclear 40 movi a2, 0 41 wsr a2, ccompare1 42 wsr a2, ccompare2 43 movi a2, 0x12345678 44 wsr a2, ccompare0 45 rsr a3, interrupt 46 assert eqi, a3, 0 47 movi a2, 0x12345677 48 wsr a2, ccount 49 esync 50 nop 51 rsr a2, interrupt 52 movi a3, 1 << XCHAL_TIMER0_INTERRUPT 53 assert eq, a2, a3 54test_end 55 56test ccompare 57 movi a2, 0 58 wsr a2, intenable 59 rsr a2, interrupt 60 wsr a2, intclear 61 movi a2, 0 62 wsr a2, ccompare1 63 wsr a2, ccompare2 64 65 make_ccount_delta a2, a15 66 wsr a2, ccompare0 671: 68 rsr a3, interrupt 69 rsr a4, ccount 70 rsr a5, interrupt 71 sub a4, a4, a2 72 bgez a4, 2f 73 assert eqi, a3, 0 74 j 1b 752: 76 assert nei, a5, 0 77test_end 78 79test ccompare0_interrupt 80 set_vector kernel, 2f 81 movi a2, 0 82 wsr a2, intenable 83 rsr a2, interrupt 84 wsr a2, intclear 85 movi a2, 0 86 wsr a2, ccompare1 87 wsr a2, ccompare2 88 89 movi a3, WAIT_LOOPS 90 make_ccount_delta a2, a15 91 wsr a2, ccompare0 92 rsync 93 rsr a2, interrupt 94 assert eqi, a2, 0 95 96 movi a2, 1 << XCHAL_TIMER0_INTERRUPT 97 wsr a2, intenable 98 rsil a2, 0 99 loop a3, 1f 100 nop 1011: 102 test_fail 1032: 104 rsr a2, exccause 105 assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */ 106test_end 107 108test ccompare1_interrupt 109 set_vector level3, 2f 110 movi a2, 0 111 wsr a2, intenable 112 rsr a2, interrupt 113 wsr a2, intclear 114 movi a2, 0 115 wsr a2, ccompare0 116 wsr a2, ccompare2 117 118 movi a3, WAIT_LOOPS 119 make_ccount_delta a2, a15 120 wsr a2, ccompare1 121 rsync 122 rsr a2, interrupt 123 assert eqi, a2, 0 124 movi a2, 1 << XCHAL_TIMER1_INTERRUPT 125 wsr a2, intenable 126 rsil a2, 2 127 loop a3, 1f 128 nop 1291: 130 test_fail 1312: 132test_end 133 134test ccompare2_interrupt 135 set_vector level5, 2f 136 movi a2, 0 137 wsr a2, intenable 138 rsr a2, interrupt 139 wsr a2, intclear 140 movi a2, 0 141 wsr a2, ccompare0 142 wsr a2, ccompare1 143 144 movi a3, WAIT_LOOPS 145 make_ccount_delta a2, a15 146 wsr a2, ccompare2 147 rsync 148 rsr a2, interrupt 149 assert eqi, a2, 0 150 movi a2, 1 << XCHAL_TIMER2_INTERRUPT 151 wsr a2, intenable 152 rsil a2, 4 153 loop a3, 1f 154 nop 1551: 156 test_fail 1572: 158test_end 159 160test ccompare_interrupt_masked 161 set_vector kernel, 2f 162 movi a2, 0 163 wsr a2, intenable 164 rsr a2, interrupt 165 wsr a2, intclear 166 movi a2, 0 167 wsr a2, ccompare2 168 169 movi a3, 2 * WAIT_LOOPS 170 make_ccount_delta a2, a15 171 wsr a2, ccompare1 172 add a2, a2, a15 173 wsr a2, ccompare0 174 rsync 175 rsr a2, interrupt 176 assert eqi, a2, 0 177 178 movi a2, 1 << XCHAL_TIMER0_INTERRUPT 179 wsr a2, intenable 180 rsil a2, 0 181 loop a3, 1f 182 nop 1831: 184 test_fail 1852: 186 rsr a2, exccause 187 assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */ 188test_end 189 190test ccompare_interrupt_masked_waiti 191 set_vector kernel, 2f 192 movi a2, 0 193 wsr a2, intenable 194 rsr a2, interrupt 195 wsr a2, intclear 196 movi a2, 0 197 wsr a2, ccompare2 198 199 movi a3, 2 * WAIT_LOOPS 200 make_ccount_delta a2, a15 201 wsr a2, ccompare1 202 add a2, a2, a15 203 wsr a2, ccompare0 204 rsync 205 rsr a2, interrupt 206 assert eqi, a2, 0 207 208 movi a2, 1 << XCHAL_TIMER0_INTERRUPT 209 wsr a2, intenable 210 waiti 0 211 test_fail 2122: 213 rsr a2, exccause 214 assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */ 215test_end 216 217test_suite_end 218