1#include "macros.inc" 2#include "fpu.h" 3 4test_suite fp0_div 5 6#if XCHAL_HAVE_FP_DIV 7 8.macro divs_seq q, a, b, r, y, y0, an, bn, e, ex 9 div0.s \y0, \b 10 nexp01.s \bn, \b 11 const.s \e, 1 12 maddn.s \e, \bn, \y0 13 mov.s \y, \y0 14 mov.s \ex, \b 15 nexp01.s \an, \a 16 maddn.s \y, \e, \y0 17 const.s \e, 1 18 const.s \q, 0 19 neg.s \r, \an 20 maddn.s \e, \bn, \y 21 maddn.s \q, \r, \y0 22 mkdadj.s \ex, \a 23 maddn.s \y, \e, \y 24 maddn.s \r, \bn, \q 25 const.s \e, 1 26 maddn.s \e, \bn, \y 27 maddn.s \q, \r, \y 28 neg.s \r, \an 29 maddn.s \y, \e, \y 30 maddn.s \r, \bn, \q 31 addexpm.s \q, \ex 32 addexp.s \y, \ex 33 divn.s \q, \r, \y 34.endm 35 36.macro div_s fr0, fr1, fr2 37 divs_seq \fr0, \fr1, \fr2, f9, f10, f11, f12, f13, f14, f15 38.endm 39 40.macro movfp fr, v 41 movi a2, \v 42 wfr \fr, a2 43.endm 44 45.macro check_res fr, r, sr 46 rfr a2, \fr 47 dump a2 48 movi a3, \r 49 assert eq, a2, a3 50 rur a2, fsr 51 movi a3, \sr 52 assert eq, a2, a3 53.endm 54 55test div_s 56 movi a2, 1 57 wsr a2, cpenable 58 59 test_op2 div_s, f0, f1, f2, 0x40000000, 0x40400000, \ 60 0x3f2aaaab, 0x3f2aaaaa, 0x3f2aaaab, 0x3f2aaaaa, \ 61 FSR_I, FSR_I, FSR_I, FSR_I 62 test_op2 div_s, f3, f4, f5, F32_1, F32_0, \ 63 F32_PINF, F32_PINF, F32_PINF, F32_PINF, \ 64 FSR_Z, FSR_Z, FSR_Z, FSR_Z 65 test_op2 div_s, f6, f7, f8, F32_0, F32_0, \ 66 F32_DNAN, F32_DNAN, F32_DNAN, F32_DNAN, \ 67 FSR_V, FSR_V, FSR_V, FSR_V 68 69 /* MAX_FLOAT / 0.5 = +inf/MAX_FLOAT */ 70 test_op2 div_s, f0, f1, f2, F32_MAX, F32_0_5, \ 71 F32_PINF, F32_MAX, F32_PINF, F32_MAX, \ 72 FSR_OI, FSR_OI, FSR_OI, FSR_OI 73 74 /* 0.5 / MAX_FLOAT = denorm */ 75 test_op2 div_s, f0, f1, f2, F32_0_5, F32_MAX, \ 76 0x00100000, 0x00100000, 0x00100001, 0x00100000, \ 77 FSR_UI, FSR_UI, FSR_UI, FSR_UI 78test_end 79 80#endif 81 82test_suite_end 83