1#include "macros.inc" 2 3.purgem test_init 4.macro test_init 5 call0 cache_unlock_invalidate 6.endm 7 8test_suite cache 9 10#if XCHAL_HAVE_PTP_MMU 11 12.macro pf_op op 13 \op a2, 0 14 \op a3, 0 15 \op a4, 0 16.endm 17 18test prefetch 19 movi a2, 0xd0000000 /* cacheable */ 20 movi a3, 0xd8000000 /* non-cacheable */ 21 movi a4, 0x00001235 /* unmapped */ 22 23#if XCHAL_DCACHE_SIZE 24 pf_op dpfr 25 pf_op dpfro 26 pf_op dpfw 27 pf_op dpfwo 28#endif 29#ifdef XCHAL_ICACHE_SIZE 30 pf_op ipf 31#endif 32#if XCHAL_HAVE_PTP_MMU && !XCHAL_HAVE_SPANNING_WAY 33#if XCHAL_DCACHE_LINE_LOCKABLE 34 dpfl a2, 0 35#endif 36#if XCHAL_ICACHE_LINE_LOCKABLE 37 ipfl a2, 0 38#endif 39#endif 40test_end 41 42.macro cache_fault op, addr, exc_code 43 set_vector kernel, 2f 44 45 movi a4, \addr 461: 47 \op a4, 0 48 test_fail 492: 50 rsr a2, epc1 51 movi a3, 1b 52 assert eq, a2, a3 53 rsr a2, excvaddr 54 assert eq, a2, a4 55 rsr a2, exccause 56 movi a3, \exc_code 57 assert eq, a2, a3 58.endm 59 60#if XCHAL_HAVE_PTP_MMU && !XCHAL_HAVE_SPANNING_WAY 61 62#if XCHAL_DCACHE_LINE_LOCKABLE 63test dpfl_tlb_miss 64 cache_fault dpfl, 0x00002345, 24 65test_end 66#endif 67 68#if XCHAL_DCACHE_SIZE 69#if XCHAL_DCACHE_IS_WRITEBACK 70test dhwb_tlb_miss 71 cache_fault dhwb, 0x00002345, 24 72test_end 73 74test dhwbi_tlb_miss 75 cache_fault dhwbi, 0x00002345, 24 76test_end 77#endif 78 79test dhi_tlb_miss 80 cache_fault dhi, 0x00002345, 24 81test_end 82 83#if XCHAL_DCACHE_LINE_LOCKABLE 84test dhu_tlb_miss 85 cache_fault dhu, 0x00002345, 24 86test_end 87#endif 88#endif 89 90#if XCHAL_ICACHE_SIZE 91#if XCHAL_ICACHE_LINE_LOCKABLE 92test ipfl_tlb_miss 93 cache_fault ipfl, 0x00002345, 16 94test_end 95 96test ihu_tlb_miss 97 cache_fault ihu, 0x00002345, 16 98test_end 99#endif 100 101test ihi_tlb_miss 102 cache_fault ihi, 0x00002345, 16 103test_end 104#endif 105 106#endif 107 108#endif 109 110test_suite_end 111 112cache_unlock_invalidate: 113#if XCHAL_DCACHE_SIZE 114 movi a2, 0 115 movi a3, XCHAL_DCACHE_SIZE 1161: 117#if XCHAL_DCACHE_LINE_LOCKABLE 118 diu a2, 0 119#endif 120 dii a2, 0 121 addi a2, a2, XCHAL_DCACHE_LINESIZE 122 bltu a2, a3, 1b 123#endif 124#if XCHAL_ICACHE_SIZE 125 movi a2, 0 126 movi a3, XCHAL_ICACHE_SIZE 1271: 128#if XCHAL_ICACHE_LINE_LOCKABLE 129 iiu a2, 0 130#endif 131 iii a2, 0 132 addi a2, a2, XCHAL_ICACHE_LINESIZE 133 bltu a2, a3, 1b 134#endif 135 ret 136