1.include "macros.inc" 2 3#define debug_level 6 4#define debug_vector level6 5 6test_suite break 7 8test break 9 set_vector debug_vector, 0 10 rsil a2, debug_level 11 _break 0, 0 12 13 set_vector debug_vector, 2f 14 rsil a2, debug_level - 1 151: 16 _break 0, 0 17 test_fail 182: 19 rsr a2, ps 20 movi a3, 0x1f 21 and a2, a2, a3 22 movi a3, 0x10 | debug_level 23 assert eq, a2, a3 24 rsr a2, epc6 25 movi a3, 1b 26 assert eq, a2, a3 27 rsr a2, debugcause 28 movi a3, 0x8 29 assert eq, a2, a3 30test_end 31 32test breakn 33 set_vector debug_vector, 0 34 rsil a2, debug_level 35 _break.n 0 36 37 set_vector debug_vector, 2f 38 rsil a2, debug_level - 1 391: 40 _break.n 0 41 test_fail 422: 43 rsr a2, ps 44 movi a3, 0x1f 45 and a2, a2, a3 46 movi a3, 0x10 | debug_level 47 assert eq, a2, a3 48 rsr a2, epc6 49 movi a3, 1b 50 assert eq, a2, a3 51 rsr a2, debugcause 52 movi a3, 0x10 53 assert eq, a2, a3 54test_end 55 56test ibreak 57 set_vector debug_vector, 0 58 rsil a2, debug_level 59 movi a2, 1f 60 wsr a2, ibreaka0 61 movi a2, 1 62 wsr a2, ibreakenable 63 isync 641: 65 rsil a2, debug_level - 1 66 movi a2, 1f 67 wsr a2, ibreaka0 68 movi a2, 0 69 wsr a2, ibreakenable 70 isync 711: 72 set_vector debug_vector, 2f 73 movi a2, 1f 74 wsr a2, ibreaka0 75 movi a2, 1 76 wsr a2, ibreakenable 77 isync 781: 79 test_fail 802: 81 rsr a2, ps 82 movi a3, 0x1f 83 and a2, a2, a3 84 movi a3, 0x10 | debug_level 85 assert eq, a2, a3 86 rsr a2, epc6 87 movi a3, 1b 88 assert eq, a2, a3 89 rsr a2, debugcause 90 movi a3, 0x2 91 assert eq, a2, a3 92test_end 93 94test ibreak_priority 95 set_vector debug_vector, 2f 96 rsil a2, debug_level - 1 97 movi a2, 1f 98 wsr a2, ibreaka0 99 movi a2, 1 100 wsr a2, ibreakenable 101 isync 1021: 103 break 0, 0 104 test_fail 1052: 106 rsr a2, debugcause 107 movi a3, 0x2 108 assert eq, a2, a3 109test_end 110 111test icount 112 set_vector debug_vector, 2f 113 rsil a2, debug_level - 1 114 movi a2, -2 115 wsr a2, icount 116 movi a2, 1 117 wsr a2, icountlevel 118 isync 119 rsil a2, 0 120 nop 1211: 122 break 0, 0 123 test_fail 1242: 125 movi a2, 0 126 wsr a2, icountlevel 127 rsr a2, epc6 128 movi a3, 1b 129 assert eq, a2, a3 130 rsr a2, debugcause 131 movi a3, 0x1 132 assert eq, a2, a3 133test_end 134 135.macro check_dbreak dr 136 rsr a2, epc6 137 movi a3, 1b 138 assert eq, a2, a3 139 rsr a2, debugcause 140 movi a3, 0x4 | (\dr << 8) 141 assert eq, a2, a3 142 movi a2, 0 143 wsr a2, dbreakc\dr 144.endm 145 146.macro dbreak_test dr, ctl, break, access, op 147 set_vector debug_vector, 2f 148 rsil a2, debug_level - 1 149 movi a2, \ctl 150 wsr a2, dbreakc\dr 151 movi a2, \break 152 wsr a2, dbreaka\dr 153 movi a2, \access 154 isync 1551: 156 \op a3, a2, 0 157 test_fail 1582: 159 check_dbreak \dr 160 reset_ps 161.endm 162 163test dbreak_exact 164 dbreak_test 0, 0x4000003f, 0xd000007f, 0xd000007f, l8ui 165 dbreak_test 1, 0x4000003e, 0xd000007e, 0xd000007e, l16ui 166 dbreak_test 0, 0x4000003c, 0xd000007c, 0xd000007c, l32i 167 168 dbreak_test 1, 0x8000003f, 0xd000007f, 0xd000007f, s8i 169 dbreak_test 0, 0x8000003e, 0xd000007e, 0xd000007e, s16i 170 dbreak_test 1, 0x8000003c, 0xd000007c, 0xd000007c, s32i 171test_end 172 173test dbreak_overlap 174 dbreak_test 0, 0x4000003f, 0xd000007d, 0xd000007c, l16ui 175 dbreak_test 1, 0x4000003f, 0xd000007d, 0xd000007c, l32i 176 177 dbreak_test 0, 0x4000003e, 0xd000007e, 0xd000007f, l8ui 178 dbreak_test 1, 0x4000003e, 0xd000007e, 0xd000007c, l32i 179 180 dbreak_test 0, 0x4000003c, 0xd000007c, 0xd000007d, l8ui 181 dbreak_test 1, 0x4000003c, 0xd000007c, 0xd000007c, l16ui 182 183 dbreak_test 0, 0x40000038, 0xd0000078, 0xd000007b, l8ui 184 dbreak_test 1, 0x40000038, 0xd0000078, 0xd000007a, l16ui 185 dbreak_test 0, 0x40000038, 0xd0000078, 0xd000007c, l32i 186 187 dbreak_test 1, 0x40000030, 0xd0000070, 0xd0000075, l8ui 188 dbreak_test 0, 0x40000030, 0xd0000070, 0xd0000076, l16ui 189 dbreak_test 1, 0x40000030, 0xd0000070, 0xd0000078, l32i 190 191 dbreak_test 0, 0x40000020, 0xd0000060, 0xd000006f, l8ui 192 dbreak_test 1, 0x40000020, 0xd0000060, 0xd0000070, l16ui 193 dbreak_test 0, 0x40000020, 0xd0000060, 0xd0000074, l32i 194 195 196 dbreak_test 0, 0x8000003f, 0xd000007d, 0xd000007c, s16i 197 dbreak_test 1, 0x8000003f, 0xd000007d, 0xd000007c, s32i 198 199 dbreak_test 0, 0x8000003e, 0xd000007e, 0xd000007f, s8i 200 dbreak_test 1, 0x8000003e, 0xd000007e, 0xd000007c, s32i 201 202 dbreak_test 0, 0x8000003c, 0xd000007c, 0xd000007d, s8i 203 dbreak_test 1, 0x8000003c, 0xd000007c, 0xd000007c, s16i 204 205 dbreak_test 0, 0x80000038, 0xd0000078, 0xd000007b, s8i 206 dbreak_test 1, 0x80000038, 0xd0000078, 0xd000007a, s16i 207 dbreak_test 0, 0x80000038, 0xd0000078, 0xd000007c, s32i 208 209 dbreak_test 1, 0x80000030, 0xd0000070, 0xd0000075, s8i 210 dbreak_test 0, 0x80000030, 0xd0000070, 0xd0000076, s16i 211 dbreak_test 1, 0x80000030, 0xd0000070, 0xd0000078, s32i 212 213 dbreak_test 0, 0x80000020, 0xd0000060, 0xd000006f, s8i 214 dbreak_test 1, 0x80000020, 0xd0000060, 0xd0000070, s16i 215 dbreak_test 0, 0x80000020, 0xd0000060, 0xd0000074, s32i 216test_end 217 218test dbreak_invalid 219 dbreak_test 0, 0x40000030, 0xd0000071, 0xd0000070, l16ui 220 dbreak_test 1, 0x40000035, 0xd0000072, 0xd0000070, l32i 221test_end 222 223test_suite_end 224