1#include "macros.inc" 2 3test_suite break 4 5#if XCHAL_HAVE_DEBUG 6 7#define debug_level XCHAL_DEBUGLEVEL 8#define debug_vector glue(level, XCHAL_DEBUGLEVEL) 9#define EPC_DEBUG glue(epc, XCHAL_DEBUGLEVEL) 10 11test break 12 set_vector debug_vector, 0 13 rsil a2, debug_level 14 _break 0, 0 15 16 set_vector debug_vector, 2f 17 rsil a2, debug_level - 1 181: 19 _break 0, 0 20 test_fail 212: 22 rsr a2, ps 23 movi a3, 0x1f 24 and a2, a2, a3 25 movi a3, 0x10 | debug_level 26 assert eq, a2, a3 27 rsr a2, EPC_DEBUG 28 movi a3, 1b 29 assert eq, a2, a3 30 rsr a2, debugcause 31 movi a3, 0x8 32 assert eq, a2, a3 33test_end 34 35test breakn 36 set_vector debug_vector, 0 37 rsil a2, debug_level 38 _break.n 0 39 40 set_vector debug_vector, 2f 41 rsil a2, debug_level - 1 421: 43 _break.n 0 44 test_fail 452: 46 rsr a2, ps 47 movi a3, 0x1f 48 and a2, a2, a3 49 movi a3, 0x10 | debug_level 50 assert eq, a2, a3 51 rsr a2, EPC_DEBUG 52 movi a3, 1b 53 assert eq, a2, a3 54 rsr a2, debugcause 55 movi a3, 0x10 56 assert eq, a2, a3 57test_end 58 59#if XCHAL_NUM_IBREAK 60test ibreak 61 set_vector debug_vector, 0 62 rsil a2, debug_level 63 movi a2, 1f 64 wsr a2, ibreaka0 65 movi a2, 1 66 wsr a2, ibreakenable 67 isync 681: 69 rsil a2, debug_level - 1 70 movi a2, 1f 71 wsr a2, ibreaka0 72 movi a2, 0 73 wsr a2, ibreakenable 74 isync 751: 76 set_vector debug_vector, 2f 77 movi a2, 1f 78 wsr a2, ibreaka0 79 movi a2, 1 80 wsr a2, ibreakenable 81 isync 821: 83 test_fail 842: 85 rsr a2, ps 86 movi a3, 0x1f 87 and a2, a2, a3 88 movi a3, 0x10 | debug_level 89 assert eq, a2, a3 90 rsr a2, EPC_DEBUG 91 movi a3, 1b 92 assert eq, a2, a3 93 rsr a2, debugcause 94 movi a3, 0x2 95 assert eq, a2, a3 96test_end 97 98test ibreak_remove 99 set_vector debug_vector, 3f 100 rsil a2, debug_level - 1 101 movi a2, 2f 102 wsr a2, ibreaka0 103 movi a3, 1 1041: 105 wsr a3, ibreakenable 106 isync 1072: 108 beqz a3, 4f 109 test_fail 1103: 111 assert eqi, a3, 1 112 rsr a2, ps 113 movi a3, 0x1f 114 and a2, a2, a3 115 movi a3, 0x10 | debug_level 116 assert eq, a2, a3 117 rsr a2, EPC_DEBUG 118 movi a3, 2b 119 assert eq, a2, a3 120 rsr a2, debugcause 121 movi a3, 0x2 122 assert eq, a2, a3 123 124 movi a2, 0x40000 125 wsr a2, ps 126 isync 127 movi a3, 0 128 j 1b 1294: 130test_end 131 132test ibreak_break_priority 133 set_vector debug_vector, 2f 134 rsil a2, debug_level - 1 135 movi a2, 1f 136 wsr a2, ibreaka0 137 movi a2, 1 138 wsr a2, ibreakenable 139 isync 1401: 141 break 0, 0 142 test_fail 1432: 144 rsr a2, debugcause 145 movi a3, 0x2 146 assert eq, a2, a3 147test_end 148 149test ibreak_icount_priority 150 set_vector debug_vector, 2f 151 rsil a2, debug_level - 1 152 movi a2, 1f 153 wsr a2, ibreaka0 154 movi a2, 1 155 wsr a2, ibreakenable 156 movi a2, -2 157 wsr a2, icount 158 movi a2, 1 159 wsr a2, icountlevel 160 isync 161 rsil a2, 0 162 nop 1631: 164 break 0, 0 165 test_fail 1662: 167 rsr a2, debugcause 168 movi a3, 0x1 169 assert eq, a2, a3 170test_end 171#endif 172 173test icount 174 set_vector debug_vector, 2f 175 rsil a2, debug_level - 1 176 movi a2, -2 177 wsr a2, icount 178 movi a2, 1 179 wsr a2, icountlevel 180 isync 181 rsil a2, 0 182 nop 1831: 184 break 0, 0 185 test_fail 1862: 187 movi a2, 0 188 wsr a2, icountlevel 189 rsr a2, EPC_DEBUG 190 movi a3, 1b 191 assert eq, a2, a3 192 rsr a2, debugcause 193 movi a3, 0x1 194 assert eq, a2, a3 195test_end 196 197.macro check_dbreak dr 198 rsr a2, EPC_DEBUG 199 movi a3, 1b 200 assert eq, a2, a3 201 rsr a2, debugcause 202 movi a3, 0x4 | (\dr << 8) 203 assert eq, a2, a3 204 movi a2, 0 205 wsr a2, dbreakc\dr 206.endm 207 208.macro dbreak_test dr, ctl, break, access, op 209 set_vector debug_vector, 2f 210 rsil a2, debug_level - 1 211 movi a2, \ctl 212 wsr a2, dbreakc\dr 213 movi a2, \break 214 wsr a2, dbreaka\dr 215 movi a2, \access 216 isync 2171: 218 \op a3, a2, 0 219 test_fail 2202: 221 check_dbreak \dr 222 reset_ps 223.endm 224 225#if XCHAL_NUM_DBREAK 226#define DB0 0 227#if XCHAL_NUM_DBREAK > 1 228#define DB1 1 229#else 230#define DB1 0 231#endif 232test dbreak_exact 233 dbreak_test DB0, 0x4000003f, 0xd000007f, 0xd000007f, l8ui 234 dbreak_test DB1, 0x4000003e, 0xd000007e, 0xd000007e, l16ui 235 dbreak_test DB0, 0x4000003c, 0xd000007c, 0xd000007c, l32i 236 237 dbreak_test DB1, 0x8000003f, 0xd000007f, 0xd000007f, s8i 238 dbreak_test DB0, 0x8000003e, 0xd000007e, 0xd000007e, s16i 239 dbreak_test DB1, 0x8000003c, 0xd000007c, 0xd000007c, s32i 240test_end 241 242test DBdbreak_overlap 243 dbreak_test DB0, 0x4000003f, 0xd000007d, 0xd000007c, l16ui 244 dbreak_test DB1, 0x4000003f, 0xd000007d, 0xd000007c, l32i 245 246 dbreak_test DB0, 0x4000003e, 0xd000007e, 0xd000007f, l8ui 247 dbreak_test DB1, 0x4000003e, 0xd000007e, 0xd000007c, l32i 248 249 dbreak_test DB0, 0x4000003c, 0xd000007c, 0xd000007d, l8ui 250 dbreak_test DB1, 0x4000003c, 0xd000007c, 0xd000007c, l16ui 251 252 dbreak_test DB0, 0x40000038, 0xd0000078, 0xd000007b, l8ui 253 dbreak_test DB1, 0x40000038, 0xd0000078, 0xd000007a, l16ui 254 dbreak_test DB0, 0x40000038, 0xd0000078, 0xd000007c, l32i 255 256 dbreak_test DB1, 0x40000030, 0xd0000070, 0xd0000075, l8ui 257 dbreak_test DB0, 0x40000030, 0xd0000070, 0xd0000076, l16ui 258 dbreak_test DB1, 0x40000030, 0xd0000070, 0xd0000078, l32i 259 260 dbreak_test DB0, 0x40000020, 0xd0000060, 0xd000006f, l8ui 261 dbreak_test DB1, 0x40000020, 0xd0000060, 0xd0000070, l16ui 262 dbreak_test DB0, 0x40000020, 0xd0000060, 0xd0000074, l32i 263 264 265 dbreak_test DB0, 0x8000003f, 0xd000007d, 0xd000007c, s16i 266 dbreak_test DB1, 0x8000003f, 0xd000007d, 0xd000007c, s32i 267 268 dbreak_test DB0, 0x8000003e, 0xd000007e, 0xd000007f, s8i 269 dbreak_test DB1, 0x8000003e, 0xd000007e, 0xd000007c, s32i 270 271 dbreak_test DB0, 0x8000003c, 0xd000007c, 0xd000007d, s8i 272 dbreak_test DB1, 0x8000003c, 0xd000007c, 0xd000007c, s16i 273 274 dbreak_test DB0, 0x80000038, 0xd0000078, 0xd000007b, s8i 275 dbreak_test DB1, 0x80000038, 0xd0000078, 0xd000007a, s16i 276 dbreak_test DB0, 0x80000038, 0xd0000078, 0xd000007c, s32i 277 278 dbreak_test DB1, 0x80000030, 0xd0000070, 0xd0000075, s8i 279 dbreak_test DB0, 0x80000030, 0xd0000070, 0xd0000076, s16i 280 dbreak_test DB1, 0x80000030, 0xd0000070, 0xd0000078, s32i 281 282 dbreak_test DB0, 0x80000020, 0xd0000060, 0xd000006f, s8i 283 dbreak_test DB1, 0x80000020, 0xd0000060, 0xd0000070, s16i 284 dbreak_test DB0, 0x80000020, 0xd0000060, 0xd0000074, s32i 285test_end 286 287test DBdbreak_invalid 288 dbreak_test DB0, 0x40000030, 0xd0000071, 0xd0000070, l16ui 289 dbreak_test DB1, 0x40000035, 0xd0000072, 0xd0000070, l32i 290test_end 291#endif 292 293#endif 294 295test_suite_end 296