1.include "macros.inc" 2 3#define debug_level 6 4#define debug_vector level6 5 6test_suite break 7 8test break 9 set_vector debug_vector, 0 10 rsil a2, debug_level 11 _break 0, 0 12 13 set_vector debug_vector, 2f 14 rsil a2, debug_level - 1 151: 16 _break 0, 0 17 test_fail 182: 19 rsr a2, ps 20 movi a3, 0x1f 21 and a2, a2, a3 22 movi a3, 0x10 | debug_level 23 assert eq, a2, a3 24 rsr a2, epc6 25 movi a3, 1b 26 assert eq, a2, a3 27 rsr a2, debugcause 28 movi a3, 0x8 29 assert eq, a2, a3 30test_end 31 32test breakn 33 set_vector debug_vector, 0 34 rsil a2, debug_level 35 _break.n 0 36 37 set_vector debug_vector, 2f 38 rsil a2, debug_level - 1 391: 40 _break.n 0 41 test_fail 422: 43 rsr a2, ps 44 movi a3, 0x1f 45 and a2, a2, a3 46 movi a3, 0x10 | debug_level 47 assert eq, a2, a3 48 rsr a2, epc6 49 movi a3, 1b 50 assert eq, a2, a3 51 rsr a2, debugcause 52 movi a3, 0x10 53 assert eq, a2, a3 54test_end 55 56test ibreak 57 set_vector debug_vector, 0 58 rsil a2, debug_level 59 movi a2, 1f 60 wsr a2, ibreaka0 61 movi a2, 1 62 wsr a2, ibreakenable 63 isync 641: 65 rsil a2, debug_level - 1 66 movi a2, 1f 67 wsr a2, ibreaka0 68 movi a2, 0 69 wsr a2, ibreakenable 70 isync 711: 72 set_vector debug_vector, 2f 73 movi a2, 1f 74 wsr a2, ibreaka0 75 movi a2, 1 76 wsr a2, ibreakenable 77 isync 781: 79 test_fail 802: 81 rsr a2, ps 82 movi a3, 0x1f 83 and a2, a2, a3 84 movi a3, 0x10 | debug_level 85 assert eq, a2, a3 86 rsr a2, epc6 87 movi a3, 1b 88 assert eq, a2, a3 89 rsr a2, debugcause 90 movi a3, 0x2 91 assert eq, a2, a3 92test_end 93 94test ibreak_remove 95 set_vector debug_vector, 3f 96 rsil a2, debug_level - 1 97 movi a2, 2f 98 wsr a2, ibreaka0 99 movi a3, 1 1001: 101 wsr a3, ibreakenable 102 isync 1032: 104 beqz a3, 4f 105 test_fail 1063: 107 assert eqi, a3, 1 108 rsr a2, ps 109 movi a3, 0x1f 110 and a2, a2, a3 111 movi a3, 0x10 | debug_level 112 assert eq, a2, a3 113 rsr a2, epc6 114 movi a3, 2b 115 assert eq, a2, a3 116 rsr a2, debugcause 117 movi a3, 0x2 118 assert eq, a2, a3 119 120 movi a2, 0x40000 121 wsr a2, ps 122 isync 123 movi a3, 0 124 j 1b 1254: 126test_end 127 128test ibreak_priority 129 set_vector debug_vector, 2f 130 rsil a2, debug_level - 1 131 movi a2, 1f 132 wsr a2, ibreaka0 133 movi a2, 1 134 wsr a2, ibreakenable 135 isync 1361: 137 break 0, 0 138 test_fail 1392: 140 rsr a2, debugcause 141 movi a3, 0x2 142 assert eq, a2, a3 143test_end 144 145test icount 146 set_vector debug_vector, 2f 147 rsil a2, debug_level - 1 148 movi a2, -2 149 wsr a2, icount 150 movi a2, 1 151 wsr a2, icountlevel 152 isync 153 rsil a2, 0 154 nop 1551: 156 break 0, 0 157 test_fail 1582: 159 movi a2, 0 160 wsr a2, icountlevel 161 rsr a2, epc6 162 movi a3, 1b 163 assert eq, a2, a3 164 rsr a2, debugcause 165 movi a3, 0x1 166 assert eq, a2, a3 167test_end 168 169.macro check_dbreak dr 170 rsr a2, epc6 171 movi a3, 1b 172 assert eq, a2, a3 173 rsr a2, debugcause 174 movi a3, 0x4 | (\dr << 8) 175 assert eq, a2, a3 176 movi a2, 0 177 wsr a2, dbreakc\dr 178.endm 179 180.macro dbreak_test dr, ctl, break, access, op 181 set_vector debug_vector, 2f 182 rsil a2, debug_level - 1 183 movi a2, \ctl 184 wsr a2, dbreakc\dr 185 movi a2, \break 186 wsr a2, dbreaka\dr 187 movi a2, \access 188 isync 1891: 190 \op a3, a2, 0 191 test_fail 1922: 193 check_dbreak \dr 194 reset_ps 195.endm 196 197test dbreak_exact 198 dbreak_test 0, 0x4000003f, 0xd000007f, 0xd000007f, l8ui 199 dbreak_test 1, 0x4000003e, 0xd000007e, 0xd000007e, l16ui 200 dbreak_test 0, 0x4000003c, 0xd000007c, 0xd000007c, l32i 201 202 dbreak_test 1, 0x8000003f, 0xd000007f, 0xd000007f, s8i 203 dbreak_test 0, 0x8000003e, 0xd000007e, 0xd000007e, s16i 204 dbreak_test 1, 0x8000003c, 0xd000007c, 0xd000007c, s32i 205test_end 206 207test dbreak_overlap 208 dbreak_test 0, 0x4000003f, 0xd000007d, 0xd000007c, l16ui 209 dbreak_test 1, 0x4000003f, 0xd000007d, 0xd000007c, l32i 210 211 dbreak_test 0, 0x4000003e, 0xd000007e, 0xd000007f, l8ui 212 dbreak_test 1, 0x4000003e, 0xd000007e, 0xd000007c, l32i 213 214 dbreak_test 0, 0x4000003c, 0xd000007c, 0xd000007d, l8ui 215 dbreak_test 1, 0x4000003c, 0xd000007c, 0xd000007c, l16ui 216 217 dbreak_test 0, 0x40000038, 0xd0000078, 0xd000007b, l8ui 218 dbreak_test 1, 0x40000038, 0xd0000078, 0xd000007a, l16ui 219 dbreak_test 0, 0x40000038, 0xd0000078, 0xd000007c, l32i 220 221 dbreak_test 1, 0x40000030, 0xd0000070, 0xd0000075, l8ui 222 dbreak_test 0, 0x40000030, 0xd0000070, 0xd0000076, l16ui 223 dbreak_test 1, 0x40000030, 0xd0000070, 0xd0000078, l32i 224 225 dbreak_test 0, 0x40000020, 0xd0000060, 0xd000006f, l8ui 226 dbreak_test 1, 0x40000020, 0xd0000060, 0xd0000070, l16ui 227 dbreak_test 0, 0x40000020, 0xd0000060, 0xd0000074, l32i 228 229 230 dbreak_test 0, 0x8000003f, 0xd000007d, 0xd000007c, s16i 231 dbreak_test 1, 0x8000003f, 0xd000007d, 0xd000007c, s32i 232 233 dbreak_test 0, 0x8000003e, 0xd000007e, 0xd000007f, s8i 234 dbreak_test 1, 0x8000003e, 0xd000007e, 0xd000007c, s32i 235 236 dbreak_test 0, 0x8000003c, 0xd000007c, 0xd000007d, s8i 237 dbreak_test 1, 0x8000003c, 0xd000007c, 0xd000007c, s16i 238 239 dbreak_test 0, 0x80000038, 0xd0000078, 0xd000007b, s8i 240 dbreak_test 1, 0x80000038, 0xd0000078, 0xd000007a, s16i 241 dbreak_test 0, 0x80000038, 0xd0000078, 0xd000007c, s32i 242 243 dbreak_test 1, 0x80000030, 0xd0000070, 0xd0000075, s8i 244 dbreak_test 0, 0x80000030, 0xd0000070, 0xd0000076, s16i 245 dbreak_test 1, 0x80000030, 0xd0000070, 0xd0000078, s32i 246 247 dbreak_test 0, 0x80000020, 0xd0000060, 0xd000006f, s8i 248 dbreak_test 1, 0x80000020, 0xd0000060, 0xd0000070, s16i 249 dbreak_test 0, 0x80000020, 0xd0000060, 0xd0000074, s32i 250test_end 251 252test dbreak_invalid 253 dbreak_test 0, 0x40000030, 0xd0000071, 0xd0000070, l16ui 254 dbreak_test 1, 0x40000035, 0xd0000072, 0xd0000070, l32i 255test_end 256 257test_suite_end 258