1 /*
2 * QTest testcase for the SSE timer device
3 *
4 * Copyright (c) 2021 Linaro Limited
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 */
16
17 #include "qemu/osdep.h"
18 #include "libqtest-single.h"
19
20 /*
21 * SSE-123/SSE-300 timer in the mps3-an547 board, where it is driven
22 * at 32MHz, so 31.25ns per tick.
23 */
24 #define TIMER_BASE 0x48000000
25
26 /* PERIPHNSPPC0 register in the SSE-300 Secure Access Configuration block */
27 #define PERIPHNSPPC0 (0x50080000 + 0x70)
28
29 /* Base of the System Counter control frame */
30 #define COUNTER_BASE 0x58100000
31
32 /* SSE counter register offsets in the control frame */
33 #define CNTCR 0
34 #define CNTSR 0x4
35 #define CNTCV_LO 0x8
36 #define CNTCV_HI 0xc
37 #define CNTSCR 0x10
38
39 /* SSE timer register offsets */
40 #define CNTPCT_LO 0
41 #define CNTPCT_HI 4
42 #define CNTFRQ 0x10
43 #define CNTP_CVAL_LO 0x20
44 #define CNTP_CVAL_HI 0x24
45 #define CNTP_TVAL 0x28
46 #define CNTP_CTL 0x2c
47 #define CNTP_AIVAL_LO 0x40
48 #define CNTP_AIVAL_HI 0x44
49 #define CNTP_AIVAL_RELOAD 0x48
50 #define CNTP_AIVAL_CTL 0x4c
51
52 /* 4 ticks in nanoseconds (so we can work in integers) */
53 #define FOUR_TICKS 125
54
clock_step_ticks(uint64_t ticks)55 static void clock_step_ticks(uint64_t ticks)
56 {
57 /*
58 * Advance the qtest clock by however many nanoseconds we
59 * need to move the timer forward the specified number of ticks.
60 * ticks must be a multiple of 4, so we get a whole number of ns.
61 */
62 assert(!(ticks & 3));
63 clock_step(FOUR_TICKS * (ticks >> 2));
64 }
65
reset_counter_and_timer(void)66 static void reset_counter_and_timer(void)
67 {
68 /*
69 * Reset the system counter and the timer between tests. This
70 * isn't a full reset, but it's sufficient for what the tests check.
71 */
72 writel(COUNTER_BASE + CNTCR, 0);
73 writel(TIMER_BASE + CNTP_CTL, 0);
74 writel(TIMER_BASE + CNTP_AIVAL_CTL, 0);
75 writel(COUNTER_BASE + CNTCV_LO, 0);
76 writel(COUNTER_BASE + CNTCV_HI, 0);
77 }
78
test_counter(void)79 static void test_counter(void)
80 {
81 /* Basic counter functionality test */
82
83 reset_counter_and_timer();
84 /* The counter should start disabled: check that it doesn't move */
85 clock_step_ticks(100);
86 g_assert_cmpuint(readl(COUNTER_BASE + CNTCV_LO), ==, 0);
87 g_assert_cmpuint(readl(COUNTER_BASE + CNTCV_HI), ==, 0);
88 /* Now enable it and check that it does count */
89 writel(COUNTER_BASE + CNTCR, 1);
90 clock_step_ticks(100);
91 g_assert_cmpuint(readl(COUNTER_BASE + CNTCV_LO), ==, 100);
92 g_assert_cmpuint(readl(COUNTER_BASE + CNTCV_HI), ==, 0);
93 /* Check the counter scaling functionality */
94 writel(COUNTER_BASE + CNTCR, 0);
95 writel(COUNTER_BASE + CNTSCR, 0x00100000); /* 1/16th normal speed */
96 writel(COUNTER_BASE + CNTCR, 5); /* EN, SCEN */
97 clock_step_ticks(160);
98 g_assert_cmpuint(readl(COUNTER_BASE + CNTCV_LO), ==, 110);
99 g_assert_cmpuint(readl(COUNTER_BASE + CNTCV_HI), ==, 0);
100 }
101
test_timer(void)102 static void test_timer(void)
103 {
104 /* Basic timer functionality test */
105
106 reset_counter_and_timer();
107 /*
108 * The timer is behind a Peripheral Protection Controller, and
109 * qtest accesses are always non-secure (no memory attributes),
110 * so we must program the PPC to accept NS transactions. TIMER0
111 * is on port 0 of PPC0, controlled by bit 0 of this register.
112 */
113 writel(PERIPHNSPPC0, 1);
114 /* We must enable the System Counter or the timer won't run. */
115 writel(COUNTER_BASE + CNTCR, 1);
116
117 /* Timer starts disabled and with a counter of 0 */
118 g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 0);
119 g_assert_cmpuint(readl(TIMER_BASE + CNTPCT_LO), ==, 0);
120 g_assert_cmpuint(readl(TIMER_BASE + CNTPCT_HI), ==, 0);
121
122 /* Turn it on */
123 writel(TIMER_BASE + CNTP_CTL, 1);
124
125 /* Is the timer ticking? */
126 clock_step_ticks(100);
127 g_assert_cmpuint(readl(TIMER_BASE + CNTPCT_LO), ==, 100);
128 g_assert_cmpuint(readl(TIMER_BASE + CNTPCT_HI), ==, 0);
129
130 /* Set the CompareValue to 4000 ticks */
131 writel(TIMER_BASE + CNTP_CVAL_LO, 4000);
132 writel(TIMER_BASE + CNTP_CVAL_HI, 0);
133
134 /* Check TVAL view of the counter */
135 g_assert_cmpuint(readl(TIMER_BASE + CNTP_TVAL), ==, 3900);
136
137 /* Advance to the CompareValue mark and check ISTATUS is set */
138 clock_step_ticks(3900);
139 g_assert_cmpuint(readl(TIMER_BASE + CNTP_TVAL), ==, 0);
140 g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 5);
141
142 /* Now exercise the auto-reload part of the timer */
143 writel(TIMER_BASE + CNTP_AIVAL_RELOAD, 200);
144 writel(TIMER_BASE + CNTP_AIVAL_CTL, 1);
145
146 /* Check AIVAL was reloaded and that ISTATUS is now clear */
147 g_assert_cmpuint(readl(TIMER_BASE + CNTP_AIVAL_LO), ==, 4200);
148 g_assert_cmpuint(readl(TIMER_BASE + CNTP_AIVAL_HI), ==, 0);
149 g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 1);
150
151 /*
152 * Check that when we advance forward to the reload time the interrupt
153 * fires and the value reloads
154 */
155 clock_step_ticks(100);
156 g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 1);
157 clock_step_ticks(100);
158 g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 5);
159 g_assert_cmpuint(readl(TIMER_BASE + CNTP_AIVAL_LO), ==, 4400);
160 g_assert_cmpuint(readl(TIMER_BASE + CNTP_AIVAL_HI), ==, 0);
161
162 clock_step_ticks(100);
163 g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 5);
164 /* Check that writing 0 to CLR clears the interrupt */
165 writel(TIMER_BASE + CNTP_AIVAL_CTL, 1);
166 g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 1);
167 /* Check that when we move forward to the reload time it fires again */
168 clock_step_ticks(100);
169 g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 5);
170 g_assert_cmpuint(readl(TIMER_BASE + CNTP_AIVAL_LO), ==, 4600);
171 g_assert_cmpuint(readl(TIMER_BASE + CNTP_AIVAL_HI), ==, 0);
172
173 /*
174 * Step the clock far enough that we overflow the low half of the
175 * CNTPCT and AIVAL registers, and check that their high halves
176 * give the right values. We do the forward movement in
177 * non-autoinc mode because otherwise it takes forever as the
178 * timer has to emulate all the 'reload at t + N, t + 2N, etc'
179 * steps.
180 */
181 writel(TIMER_BASE + CNTP_AIVAL_CTL, 0);
182 clock_step_ticks(0x42ULL << 32);
183 g_assert_cmpuint(readl(TIMER_BASE + CNTPCT_LO), ==, 4400);
184 g_assert_cmphex(readl(TIMER_BASE + CNTPCT_HI), ==, 0x42);
185
186 /* Turn on the autoinc again to check AIVAL_HI */
187 writel(TIMER_BASE + CNTP_AIVAL_CTL, 1);
188 g_assert_cmpuint(readl(TIMER_BASE + CNTP_AIVAL_LO), ==, 4600);
189 g_assert_cmphex(readl(TIMER_BASE + CNTP_AIVAL_HI), ==, 0x42);
190 }
191
test_timer_scale_change(void)192 static void test_timer_scale_change(void)
193 {
194 /*
195 * Test that the timer responds correctly to counter
196 * scaling changes while it has an active timer.
197 */
198 reset_counter_and_timer();
199 /* Give ourselves access to the timer, and enable the counter and timer */
200 writel(PERIPHNSPPC0, 1);
201 writel(COUNTER_BASE + CNTCR, 1);
202 writel(TIMER_BASE + CNTP_CTL, 1);
203 /* Set the CompareValue to 4000 ticks */
204 writel(TIMER_BASE + CNTP_CVAL_LO, 4000);
205 writel(TIMER_BASE + CNTP_CVAL_HI, 0);
206 /* Advance halfway and check ISTATUS is not set */
207 clock_step_ticks(2000);
208 g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 1);
209 /* Reprogram the counter to run at 1/16th speed */
210 writel(COUNTER_BASE + CNTCR, 0);
211 writel(COUNTER_BASE + CNTSCR, 0x00100000); /* 1/16th normal speed */
212 writel(COUNTER_BASE + CNTCR, 5); /* EN, SCEN */
213 /* Advance to where the timer would have fired and check it has not */
214 clock_step_ticks(2000);
215 g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 1);
216 /* Advance to where the timer must fire at the new clock rate */
217 clock_step_ticks(29996);
218 g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 1);
219 clock_step_ticks(4);
220 g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 5);
221 }
222
main(int argc,char ** argv)223 int main(int argc, char **argv)
224 {
225 int r;
226
227 g_test_init(&argc, &argv, NULL);
228
229 qtest_start("-machine mps3-an547");
230
231 qtest_add_func("/sse-timer/counter", test_counter);
232 qtest_add_func("/sse-timer/timer", test_timer);
233 qtest_add_func("/sse-timer/timer-scale-change", test_timer_scale_change);
234
235 r = g_test_run();
236
237 qtest_end();
238
239 return r;
240 }
241