1 /* 2 * PowerNV XSCOM Bus 3 * 4 * Copyright (c) 2024, IBM Corporation. 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 */ 8 9 #ifndef PNV_XSCOM_H 10 #define PNV_XSCOM_H 11 12 #define SMT 4 /* some tests will break if less than 4 */ 13 14 typedef enum PnvChipType { 15 PNV_CHIP_POWER8E, /* AKA Murano (default) */ 16 PNV_CHIP_POWER8, /* AKA Venice */ 17 PNV_CHIP_POWER8NVL, /* AKA Naples */ 18 PNV_CHIP_POWER9, /* AKA Nimbus */ 19 PNV_CHIP_POWER10, 20 } PnvChipType; 21 22 typedef struct PnvChip { 23 PnvChipType chip_type; 24 const char *cpu_model; 25 uint64_t xscom_base; 26 uint64_t cfam_id; 27 uint32_t first_core; 28 uint32_t num_i2c; 29 } PnvChip; 30 31 static const PnvChip pnv_chips[] = { 32 { 33 .chip_type = PNV_CHIP_POWER8, 34 .cpu_model = "POWER8", 35 .xscom_base = 0x0003fc0000000000ull, 36 .cfam_id = 0x220ea04980000000ull, 37 .first_core = 0x1, 38 .num_i2c = 0, 39 }, { 40 .chip_type = PNV_CHIP_POWER8NVL, 41 .cpu_model = "POWER8NVL", 42 .xscom_base = 0x0003fc0000000000ull, 43 .cfam_id = 0x120d304980000000ull, 44 .first_core = 0x1, 45 .num_i2c = 0, 46 }, 47 { 48 .chip_type = PNV_CHIP_POWER9, 49 .cpu_model = "POWER9", 50 .xscom_base = 0x000603fc00000000ull, 51 .cfam_id = 0x220d104900008000ull, 52 .first_core = 0x0, 53 .num_i2c = 4, 54 }, 55 { 56 .chip_type = PNV_CHIP_POWER10, 57 .cpu_model = "POWER10", 58 .xscom_base = 0x000603fc00000000ull, 59 .cfam_id = 0x220da04980000000ull, 60 .first_core = 0x0, 61 .num_i2c = 4, 62 }, 63 }; 64 65 static inline uint64_t pnv_xscom_addr(const PnvChip *chip, uint32_t pcba) 66 { 67 uint64_t addr = chip->xscom_base; 68 69 if (chip->chip_type == PNV_CHIP_POWER10) { 70 addr |= ((uint64_t) pcba << 3); 71 } else if (chip->chip_type == PNV_CHIP_POWER9) { 72 addr |= ((uint64_t) pcba << 3); 73 } else { 74 addr |= (((uint64_t) pcba << 4) & ~0xffull) | 75 (((uint64_t) pcba << 3) & 0x78); 76 } 77 return addr; 78 } 79 80 #endif /* PNV_XSCOM_H */ 81