1 /* 2 * QTest testcase for PowerNV XSCOM bus 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or 7 * later. See the COPYING file in the top-level directory. 8 */ 9 #include "qemu/osdep.h" 10 11 #include "libqtest.h" 12 13 #include "pnv-xscom.h" 14 15 static uint64_t pnv_xscom_read(QTestState *qts, const PnvChip *chip, 16 uint32_t pcba) 17 { 18 return qtest_readq(qts, pnv_xscom_addr(chip, pcba)); 19 } 20 21 static void test_xscom_cfam_id(QTestState *qts, const PnvChip *chip) 22 { 23 uint64_t f000f = pnv_xscom_read(qts, chip, 0xf000f); 24 25 g_assert_cmphex(f000f, ==, chip->cfam_id); 26 } 27 28 static void test_cfam_id(const void *data) 29 { 30 const PnvChip *chip = data; 31 const char *machine = "powernv8"; 32 QTestState *qts; 33 34 if (chip->chip_type == PNV_CHIP_POWER9) { 35 machine = "powernv9"; 36 } else if (chip->chip_type == PNV_CHIP_POWER10) { 37 machine = "powernv10"; 38 } 39 40 qts = qtest_initf("-M %s -accel tcg -cpu %s", 41 machine, chip->cpu_model); 42 test_xscom_cfam_id(qts, chip); 43 qtest_quit(qts); 44 } 45 46 47 #define PNV_XSCOM_EX_CORE_BASE 0x10000000ull 48 #define PNV_XSCOM_EX_BASE(core) \ 49 (PNV_XSCOM_EX_CORE_BASE | ((uint64_t)(core) << 24)) 50 #define PNV_XSCOM_P9_EC_BASE(core) \ 51 ((uint64_t)(((core) & 0x1F) + 0x20) << 24) 52 #define PNV_XSCOM_P10_EC_BASE(core) \ 53 ((uint64_t)((((core) & ~0x3) + 0x20) << 24) + 0x20000 + \ 54 (0x1000 << (3 - (core & 0x3)))) 55 56 #define PNV_XSCOM_EX_DTS_RESULT0 0x50000 57 58 static void test_xscom_core(QTestState *qts, const PnvChip *chip) 59 { 60 if (chip->chip_type == PNV_CHIP_POWER10) { 61 uint32_t first_core_thread_state = 62 PNV_XSCOM_P10_EC_BASE(chip->first_core) + 0x412; 63 uint64_t thread_state; 64 65 thread_state = pnv_xscom_read(qts, chip, first_core_thread_state); 66 67 g_assert_cmphex(thread_state, ==, 0); 68 } else { 69 uint32_t first_core_dts0 = PNV_XSCOM_EX_DTS_RESULT0; 70 uint64_t dts0; 71 72 if (chip->chip_type == PNV_CHIP_POWER9) { 73 first_core_dts0 |= PNV_XSCOM_P9_EC_BASE(chip->first_core); 74 } else { /* POWER8 */ 75 first_core_dts0 |= PNV_XSCOM_EX_BASE(chip->first_core); 76 } 77 78 dts0 = pnv_xscom_read(qts, chip, first_core_dts0); 79 80 g_assert_cmphex(dts0, ==, 0x26f024f023f0000ull); 81 } 82 } 83 84 static void test_core(const void *data) 85 { 86 const PnvChip *chip = data; 87 QTestState *qts; 88 const char *machine = "powernv8"; 89 90 if (chip->chip_type == PNV_CHIP_POWER9) { 91 machine = "powernv9"; 92 } else if (chip->chip_type == PNV_CHIP_POWER10) { 93 machine = "powernv10"; 94 } 95 96 qts = qtest_initf("-M %s -accel tcg -cpu %s", 97 machine, chip->cpu_model); 98 test_xscom_core(qts, chip); 99 qtest_quit(qts); 100 } 101 102 static void add_test(const char *name, void (*test)(const void *data)) 103 { 104 int i; 105 106 for (i = 0; i < ARRAY_SIZE(pnv_chips); i++) { 107 char *tname = g_strdup_printf("pnv-xscom/%s/%s", name, 108 pnv_chips[i].cpu_model); 109 qtest_add_data_func(tname, &pnv_chips[i], test); 110 g_free(tname); 111 } 112 } 113 114 int main(int argc, char **argv) 115 { 116 g_test_init(&argc, &argv, NULL); 117 118 add_test("cfam_id", test_cfam_id); 119 add_test("core", test_core); 120 return g_test_run(); 121 } 122