1 /* 2 * QTest testcase for PowerNV 10 interrupt controller (xive2) 3 * 4 * Copyright (c) 2024, IBM Corporation. 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 */ 8 9 #ifndef TEST_PNV_XIVE2_COMMON_H 10 #define TEST_PNV_XIVE2_COMMON_H 11 12 #define PPC_BIT(bit) (0x8000000000000000ULL >> (bit)) 13 #define PPC_BIT32(bit) (0x80000000 >> (bit)) 14 #define PPC_BIT8(bit) (0x80 >> (bit)) 15 #define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs)) 16 #define PPC_BITMASK32(bs, be) ((PPC_BIT32(bs) - PPC_BIT32(be)) | \ 17 PPC_BIT32(bs)) 18 #include "qemu/bswap.h" 19 #include "hw/intc/pnv_xive2_regs.h" 20 #include "hw/ppc/xive_regs.h" 21 #include "hw/ppc/xive2_regs.h" 22 23 /* 24 * sizing: 25 * 128 interrupts 26 * => ESB BAR range: 16M 27 * 256 ENDs 28 * => END BAR range: 16M 29 * 256 VPs 30 * => NVPG,NVC BAR range: 32M 31 */ 32 #define MAX_IRQS 128 33 #define MAX_ENDS 256 34 #define MAX_VPS 256 35 36 #define XIVE_PAGE_SHIFT 16 37 38 #define XIVE_TRIGGER_PAGE 0 39 #define XIVE_EOI_PAGE 1 40 41 #define XIVE_IC_ADDR 0x0006030200000000ull 42 #define XIVE_IC_TM_INDIRECT (XIVE_IC_ADDR + (256 << XIVE_PAGE_SHIFT)) 43 #define XIVE_IC_BAR ((0x3ull << 62) | XIVE_IC_ADDR) 44 #define XIVE_TM_BAR 0xc006030203180000ull 45 #define XIVE_ESB_ADDR 0x0006050000000000ull 46 #define XIVE_ESB_BAR ((0x3ull << 62) | XIVE_ESB_ADDR) 47 #define XIVE_END_BAR 0xc006060000000000ull 48 #define XIVE_NVPG_ADDR 0x0006040000000000ull 49 #define XIVE_NVPG_BAR ((0x3ull << 62) | XIVE_NVPG_ADDR) 50 #define XIVE_NVC_ADDR 0x0006030208000000ull 51 #define XIVE_NVC_BAR ((0x3ull << 62) | XIVE_NVC_ADDR) 52 53 /* 54 * Memory layout 55 * A check is done when a table is configured to ensure that the max 56 * size of the resource fits in the table. 57 */ 58 #define XIVE_VST_SIZE 0x10000ull /* must be at least 4k */ 59 60 #define XIVE_MEM_START 0x10000000ull 61 #define XIVE_ESB_MEM XIVE_MEM_START 62 #define XIVE_EAS_MEM (XIVE_ESB_MEM + XIVE_VST_SIZE) 63 #define XIVE_END_MEM (XIVE_EAS_MEM + XIVE_VST_SIZE) 64 #define XIVE_NVP_MEM (XIVE_END_MEM + XIVE_VST_SIZE) 65 #define XIVE_NVG_MEM (XIVE_NVP_MEM + XIVE_VST_SIZE) 66 #define XIVE_NVC_MEM (XIVE_NVG_MEM + XIVE_VST_SIZE) 67 #define XIVE_SYNC_MEM (XIVE_NVC_MEM + XIVE_VST_SIZE) 68 #define XIVE_QUEUE_MEM (XIVE_SYNC_MEM + XIVE_VST_SIZE) 69 #define XIVE_QUEUE_SIZE 4096 /* per End */ 70 #define XIVE_REPORT_MEM (XIVE_QUEUE_MEM + XIVE_QUEUE_SIZE * MAX_VPS) 71 #define XIVE_REPORT_SIZE 256 /* two cache lines per NVP */ 72 #define XIVE_MEM_END (XIVE_REPORT_MEM + XIVE_REPORT_SIZE * MAX_VPS) 73 74 #define P10_XSCOM_BASE 0x000603fc00000000ull 75 #define XIVE_XSCOM 0x2010800ull 76 77 #define XIVE_ESB_RESET 0b00 78 #define XIVE_ESB_OFF 0b01 79 #define XIVE_ESB_PENDING 0b10 80 #define XIVE_ESB_QUEUED 0b11 81 82 #define XIVE_ESB_GET 0x800 83 #define XIVE_ESB_SET_PQ_00 0xc00 /* Load */ 84 #define XIVE_ESB_SET_PQ_01 0xd00 /* Load */ 85 #define XIVE_ESB_SET_PQ_10 0xe00 /* Load */ 86 #define XIVE_ESB_SET_PQ_11 0xf00 /* Load */ 87 88 #define XIVE_ESB_STORE_EOI 0x400 /* Store */ 89 90 91 extern uint64_t pnv_xive_xscom_read(QTestState *qts, uint32_t reg); 92 extern void pnv_xive_xscom_write(QTestState *qts, uint32_t reg, uint64_t val); 93 extern uint64_t xive_get_queue_addr(uint32_t end_index); 94 extern uint8_t get_esb(QTestState *qts, uint32_t index, uint8_t page, 95 uint32_t offset); 96 extern void set_esb(QTestState *qts, uint32_t index, uint8_t page, 97 uint32_t offset, uint32_t val); 98 extern void get_nvp(QTestState *qts, uint32_t index, Xive2Nvp* nvp); 99 extern void set_nvp(QTestState *qts, uint32_t index, uint8_t first); 100 extern void get_cl_pair(QTestState *qts, Xive2Nvp *nvp, uint8_t *cl_pair); 101 extern void set_cl_pair(QTestState *qts, Xive2Nvp *nvp, uint8_t *cl_pair); 102 extern void set_nvg(QTestState *qts, uint32_t index, uint8_t next); 103 extern void set_eas(QTestState *qts, uint32_t index, uint32_t end_index, 104 uint32_t data); 105 extern void set_end(QTestState *qts, uint32_t index, uint32_t nvp_index, 106 uint8_t priority, bool i); 107 108 109 void test_flush_sync_inject(QTestState *qts); 110 111 #endif /* TEST_PNV_XIVE2_COMMON_H */ 112