1 /* 2 * QTests for Nuvoton NPCM7xx/8xx GMAC Modules. 3 * 4 * Copyright 2024 Google LLC 5 * Authors: 6 * Hao Wu <wuhaotsh@google.com> 7 * Nabih Estefan <nabihestefan@google.com> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17 * for more details. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "libqos/libqos.h" 22 23 /* Name of the GMAC Device */ 24 #define TYPE_NPCM_GMAC "npcm-gmac" 25 26 typedef struct GMACModule { 27 int irq; 28 uint64_t base_addr; 29 } GMACModule; 30 31 typedef struct TestData { 32 const GMACModule *module; 33 } TestData; 34 35 /* Values extracted from hw/arm/npcm8xx.c */ 36 static const GMACModule gmac_module_list[] = { 37 { 38 .irq = 14, 39 .base_addr = 0xf0802000 40 }, 41 { 42 .irq = 15, 43 .base_addr = 0xf0804000 44 }, 45 { 46 .irq = 16, 47 .base_addr = 0xf0806000 48 }, 49 { 50 .irq = 17, 51 .base_addr = 0xf0808000 52 } 53 }; 54 55 /* Returns the index of the GMAC module. */ 56 static int gmac_module_index(const GMACModule *mod) 57 { 58 ptrdiff_t diff = mod - gmac_module_list; 59 60 g_assert_true(diff >= 0 && diff < ARRAY_SIZE(gmac_module_list)); 61 62 return diff; 63 } 64 65 /* 32-bit register indices. Taken from npcm_gmac.c */ 66 typedef enum NPCMRegister { 67 /* DMA Registers */ 68 NPCM_DMA_BUS_MODE = 0x1000, 69 NPCM_DMA_XMT_POLL_DEMAND = 0x1004, 70 NPCM_DMA_RCV_POLL_DEMAND = 0x1008, 71 NPCM_DMA_RCV_BASE_ADDR = 0x100c, 72 NPCM_DMA_TX_BASE_ADDR = 0x1010, 73 NPCM_DMA_STATUS = 0x1014, 74 NPCM_DMA_CONTROL = 0x1018, 75 NPCM_DMA_INTR_ENA = 0x101c, 76 NPCM_DMA_MISSED_FRAME_CTR = 0x1020, 77 NPCM_DMA_HOST_TX_DESC = 0x1048, 78 NPCM_DMA_HOST_RX_DESC = 0x104c, 79 NPCM_DMA_CUR_TX_BUF_ADDR = 0x1050, 80 NPCM_DMA_CUR_RX_BUF_ADDR = 0x1054, 81 NPCM_DMA_HW_FEATURE = 0x1058, 82 83 /* GMAC Registers */ 84 NPCM_GMAC_MAC_CONFIG = 0x0, 85 NPCM_GMAC_FRAME_FILTER = 0x4, 86 NPCM_GMAC_HASH_HIGH = 0x8, 87 NPCM_GMAC_HASH_LOW = 0xc, 88 NPCM_GMAC_MII_ADDR = 0x10, 89 NPCM_GMAC_MII_DATA = 0x14, 90 NPCM_GMAC_FLOW_CTRL = 0x18, 91 NPCM_GMAC_VLAN_FLAG = 0x1c, 92 NPCM_GMAC_VERSION = 0x20, 93 NPCM_GMAC_WAKEUP_FILTER = 0x28, 94 NPCM_GMAC_PMT = 0x2c, 95 NPCM_GMAC_LPI_CTRL = 0x30, 96 NPCM_GMAC_TIMER_CTRL = 0x34, 97 NPCM_GMAC_INT_STATUS = 0x38, 98 NPCM_GMAC_INT_MASK = 0x3c, 99 NPCM_GMAC_MAC0_ADDR_HI = 0x40, 100 NPCM_GMAC_MAC0_ADDR_LO = 0x44, 101 NPCM_GMAC_MAC1_ADDR_HI = 0x48, 102 NPCM_GMAC_MAC1_ADDR_LO = 0x4c, 103 NPCM_GMAC_MAC2_ADDR_HI = 0x50, 104 NPCM_GMAC_MAC2_ADDR_LO = 0x54, 105 NPCM_GMAC_MAC3_ADDR_HI = 0x58, 106 NPCM_GMAC_MAC3_ADDR_LO = 0x5c, 107 NPCM_GMAC_RGMII_STATUS = 0xd8, 108 NPCM_GMAC_WATCHDOG = 0xdc, 109 NPCM_GMAC_PTP_TCR = 0x700, 110 NPCM_GMAC_PTP_SSIR = 0x704, 111 NPCM_GMAC_PTP_STSR = 0x708, 112 NPCM_GMAC_PTP_STNSR = 0x70c, 113 NPCM_GMAC_PTP_STSUR = 0x710, 114 NPCM_GMAC_PTP_STNSUR = 0x714, 115 NPCM_GMAC_PTP_TAR = 0x718, 116 NPCM_GMAC_PTP_TTSR = 0x71c, 117 } NPCMRegister; 118 119 static uint32_t gmac_read(QTestState *qts, const GMACModule *mod, 120 NPCMRegister regno) 121 { 122 return qtest_readl(qts, mod->base_addr + regno); 123 } 124 125 /* Check that GMAC registers are reset to default value */ 126 static void test_init(gconstpointer test_data) 127 { 128 const TestData *td = test_data; 129 const GMACModule *mod = td->module; 130 QTestState *qts = qtest_init("-machine npcm845-evb"); 131 132 #define CHECK_REG32(regno, value) \ 133 do { \ 134 g_assert_cmphex(gmac_read(qts, mod, (regno)), ==, (value)); \ 135 } while (0) 136 137 CHECK_REG32(NPCM_DMA_BUS_MODE, 0x00020100); 138 CHECK_REG32(NPCM_DMA_XMT_POLL_DEMAND, 0); 139 CHECK_REG32(NPCM_DMA_RCV_POLL_DEMAND, 0); 140 CHECK_REG32(NPCM_DMA_RCV_BASE_ADDR, 0); 141 CHECK_REG32(NPCM_DMA_TX_BASE_ADDR, 0); 142 CHECK_REG32(NPCM_DMA_STATUS, 0); 143 CHECK_REG32(NPCM_DMA_CONTROL, 0); 144 CHECK_REG32(NPCM_DMA_INTR_ENA, 0); 145 CHECK_REG32(NPCM_DMA_MISSED_FRAME_CTR, 0); 146 CHECK_REG32(NPCM_DMA_HOST_TX_DESC, 0); 147 CHECK_REG32(NPCM_DMA_HOST_RX_DESC, 0); 148 CHECK_REG32(NPCM_DMA_CUR_TX_BUF_ADDR, 0); 149 CHECK_REG32(NPCM_DMA_CUR_RX_BUF_ADDR, 0); 150 CHECK_REG32(NPCM_DMA_HW_FEATURE, 0x100d4f37); 151 152 CHECK_REG32(NPCM_GMAC_MAC_CONFIG, 0); 153 CHECK_REG32(NPCM_GMAC_FRAME_FILTER, 0); 154 CHECK_REG32(NPCM_GMAC_HASH_HIGH, 0); 155 CHECK_REG32(NPCM_GMAC_HASH_LOW, 0); 156 CHECK_REG32(NPCM_GMAC_MII_ADDR, 0); 157 CHECK_REG32(NPCM_GMAC_MII_DATA, 0); 158 CHECK_REG32(NPCM_GMAC_FLOW_CTRL, 0); 159 CHECK_REG32(NPCM_GMAC_VLAN_FLAG, 0); 160 CHECK_REG32(NPCM_GMAC_VERSION, 0x00001032); 161 CHECK_REG32(NPCM_GMAC_WAKEUP_FILTER, 0); 162 CHECK_REG32(NPCM_GMAC_PMT, 0); 163 CHECK_REG32(NPCM_GMAC_LPI_CTRL, 0); 164 CHECK_REG32(NPCM_GMAC_TIMER_CTRL, 0x03e80000); 165 CHECK_REG32(NPCM_GMAC_INT_STATUS, 0); 166 CHECK_REG32(NPCM_GMAC_INT_MASK, 0); 167 CHECK_REG32(NPCM_GMAC_MAC0_ADDR_HI, 0x8000ffff); 168 CHECK_REG32(NPCM_GMAC_MAC0_ADDR_LO, 0xffffffff); 169 CHECK_REG32(NPCM_GMAC_MAC1_ADDR_HI, 0x0000ffff); 170 CHECK_REG32(NPCM_GMAC_MAC1_ADDR_LO, 0xffffffff); 171 CHECK_REG32(NPCM_GMAC_MAC2_ADDR_HI, 0x0000ffff); 172 CHECK_REG32(NPCM_GMAC_MAC2_ADDR_LO, 0xffffffff); 173 CHECK_REG32(NPCM_GMAC_MAC3_ADDR_HI, 0x0000ffff); 174 CHECK_REG32(NPCM_GMAC_MAC3_ADDR_LO, 0xffffffff); 175 CHECK_REG32(NPCM_GMAC_RGMII_STATUS, 0); 176 CHECK_REG32(NPCM_GMAC_WATCHDOG, 0); 177 CHECK_REG32(NPCM_GMAC_PTP_TCR, 0x00002000); 178 CHECK_REG32(NPCM_GMAC_PTP_SSIR, 0); 179 CHECK_REG32(NPCM_GMAC_PTP_STSR, 0); 180 CHECK_REG32(NPCM_GMAC_PTP_STNSR, 0); 181 CHECK_REG32(NPCM_GMAC_PTP_STSUR, 0); 182 CHECK_REG32(NPCM_GMAC_PTP_STNSUR, 0); 183 CHECK_REG32(NPCM_GMAC_PTP_TAR, 0); 184 CHECK_REG32(NPCM_GMAC_PTP_TTSR, 0); 185 186 qtest_quit(qts); 187 } 188 189 static void gmac_add_test(const char *name, const TestData* td, 190 GTestDataFunc fn) 191 { 192 g_autofree char *full_name = g_strdup_printf( 193 "npcm7xx_gmac/gmac[%d]/%s", gmac_module_index(td->module), name); 194 qtest_add_data_func(full_name, td, fn); 195 } 196 197 int main(int argc, char **argv) 198 { 199 TestData test_data_list[ARRAY_SIZE(gmac_module_list)]; 200 201 g_test_init(&argc, &argv, NULL); 202 203 for (int i = 0; i < ARRAY_SIZE(gmac_module_list); ++i) { 204 TestData *td = &test_data_list[i]; 205 206 td->module = &gmac_module_list[i]; 207 208 gmac_add_test("init", td, test_init); 209 } 210 211 return g_test_run(); 212 } 213