xref: /openbmc/qemu/tests/qtest/npcm7xx_emc-test.c (revision ab1b2ba9)
1 /*
2  * QTests for Nuvoton NPCM7xx EMC Modules.
3  *
4  * Copyright 2020 Google LLC
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms of the GNU General Public License as published by the
8  * Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14  * for more details.
15  */
16 
17 #include "qemu/osdep.h"
18 #include "libqos/libqos.h"
19 #include "qapi/qmp/qdict.h"
20 #include "qapi/qmp/qnum.h"
21 #include "qemu/bitops.h"
22 #include "qemu/iov.h"
23 
24 /* Name of the emc device. */
25 #define TYPE_NPCM7XX_EMC "npcm7xx-emc"
26 
27 /* Timeout for various operations, in seconds. */
28 #define TIMEOUT_SECONDS 10
29 
30 /* Address in memory of the descriptor. */
31 #define DESC_ADDR (1 << 20) /* 1 MiB */
32 
33 /* Address in memory of the data packet. */
34 #define DATA_ADDR (DESC_ADDR + 4096)
35 
36 #define CRC_LENGTH 4
37 
38 #define NUM_TX_DESCRIPTORS 3
39 #define NUM_RX_DESCRIPTORS 2
40 
41 /* Size of tx,rx test buffers. */
42 #define TX_DATA_LEN 64
43 #define RX_DATA_LEN 64
44 
45 #define TX_STEP_COUNT 10000
46 #define RX_STEP_COUNT 10000
47 
48 /* 32-bit register indices. */
49 typedef enum NPCM7xxPWMRegister {
50     /* Control registers. */
51     REG_CAMCMR,
52     REG_CAMEN,
53 
54     /* There are 16 CAMn[ML] registers. */
55     REG_CAMM_BASE,
56     REG_CAML_BASE,
57 
58     REG_TXDLSA = 0x22,
59     REG_RXDLSA,
60     REG_MCMDR,
61     REG_MIID,
62     REG_MIIDA,
63     REG_FFTCR,
64     REG_TSDR,
65     REG_RSDR,
66     REG_DMARFC,
67     REG_MIEN,
68 
69     /* Status registers. */
70     REG_MISTA,
71     REG_MGSTA,
72     REG_MPCNT,
73     REG_MRPC,
74     REG_MRPCC,
75     REG_MREPC,
76     REG_DMARFS,
77     REG_CTXDSA,
78     REG_CTXBSA,
79     REG_CRXDSA,
80     REG_CRXBSA,
81 
82     NPCM7XX_NUM_EMC_REGS,
83 } NPCM7xxPWMRegister;
84 
85 enum { NUM_CAMML_REGS = 16 };
86 
87 /* REG_CAMCMR fields */
88 /* Enable CAM Compare */
89 #define REG_CAMCMR_ECMP (1 << 4)
90 /* Accept Unicast Packet */
91 #define REG_CAMCMR_AUP (1 << 0)
92 
93 /* REG_MCMDR fields */
94 /* Software Reset */
95 #define REG_MCMDR_SWR (1 << 24)
96 /* Frame Transmission On */
97 #define REG_MCMDR_TXON (1 << 8)
98 /* Accept Long Packet */
99 #define REG_MCMDR_ALP (1 << 1)
100 /* Frame Reception On */
101 #define REG_MCMDR_RXON (1 << 0)
102 
103 /* REG_MIEN fields */
104 /* Enable Transmit Completion Interrupt */
105 #define REG_MIEN_ENTXCP (1 << 18)
106 /* Enable Transmit Interrupt */
107 #define REG_MIEN_ENTXINTR (1 << 16)
108 /* Enable Receive Good Interrupt */
109 #define REG_MIEN_ENRXGD (1 << 4)
110 /* ENable Receive Interrupt */
111 #define REG_MIEN_ENRXINTR (1 << 0)
112 
113 /* REG_MISTA fields */
114 /* Transmit Bus Error Interrupt */
115 #define REG_MISTA_TXBERR (1 << 24)
116 /* Transmit Descriptor Unavailable Interrupt */
117 #define REG_MISTA_TDU (1 << 23)
118 /* Transmit Completion Interrupt */
119 #define REG_MISTA_TXCP (1 << 18)
120 /* Transmit Interrupt */
121 #define REG_MISTA_TXINTR (1 << 16)
122 /* Receive Bus Error Interrupt */
123 #define REG_MISTA_RXBERR (1 << 11)
124 /* Receive Descriptor Unavailable Interrupt */
125 #define REG_MISTA_RDU (1 << 10)
126 /* DMA Early Notification Interrupt */
127 #define REG_MISTA_DENI (1 << 9)
128 /* Maximum Frame Length Interrupt */
129 #define REG_MISTA_DFOI (1 << 8)
130 /* Receive Good Interrupt */
131 #define REG_MISTA_RXGD (1 << 4)
132 /* Packet Too Long Interrupt */
133 #define REG_MISTA_PTLE (1 << 3)
134 /* Receive Interrupt */
135 #define REG_MISTA_RXINTR (1 << 0)
136 
137 typedef struct NPCM7xxEMCTxDesc NPCM7xxEMCTxDesc;
138 typedef struct NPCM7xxEMCRxDesc NPCM7xxEMCRxDesc;
139 
140 struct NPCM7xxEMCTxDesc {
141     uint32_t flags;
142     uint32_t txbsa;
143     uint32_t status_and_length;
144     uint32_t ntxdsa;
145 };
146 
147 struct NPCM7xxEMCRxDesc {
148     uint32_t status_and_length;
149     uint32_t rxbsa;
150     uint32_t reserved;
151     uint32_t nrxdsa;
152 };
153 
154 /* NPCM7xxEMCTxDesc.flags values */
155 /* Owner: 0 = cpu, 1 = emc */
156 #define TX_DESC_FLAG_OWNER_MASK (1 << 31)
157 /* Transmit interrupt enable */
158 #define TX_DESC_FLAG_INTEN (1 << 2)
159 
160 /* NPCM7xxEMCTxDesc.status_and_length values */
161 /* Transmission complete */
162 #define TX_DESC_STATUS_TXCP (1 << 19)
163 /* Transmit interrupt */
164 #define TX_DESC_STATUS_TXINTR (1 << 16)
165 
166 /* NPCM7xxEMCRxDesc.status_and_length values */
167 /* Owner: 0b00 = cpu, 0b10 = emc */
168 #define RX_DESC_STATUS_OWNER_SHIFT 30
169 #define RX_DESC_STATUS_OWNER_MASK 0xc0000000
170 /* Frame Reception Complete */
171 #define RX_DESC_STATUS_RXGD (1 << 20)
172 /* Packet too long */
173 #define RX_DESC_STATUS_PTLE (1 << 19)
174 /* Receive Interrupt */
175 #define RX_DESC_STATUS_RXINTR (1 << 16)
176 
177 #define RX_DESC_PKT_LEN(word) ((uint32_t) (word) & 0xffff)
178 
179 typedef struct EMCModule {
180     int rx_irq;
181     int tx_irq;
182     uint64_t base_addr;
183 } EMCModule;
184 
185 typedef struct TestData {
186     const EMCModule *module;
187 } TestData;
188 
189 static const EMCModule emc_module_list[] = {
190     {
191         .rx_irq     = 15,
192         .tx_irq     = 16,
193         .base_addr  = 0xf0825000
194     },
195     {
196         .rx_irq     = 114,
197         .tx_irq     = 115,
198         .base_addr  = 0xf0826000
199     }
200 };
201 
202 /* Returns the index of the EMC module. */
203 static int emc_module_index(const EMCModule *mod)
204 {
205     ptrdiff_t diff = mod - emc_module_list;
206 
207     g_assert_true(diff >= 0 && diff < ARRAY_SIZE(emc_module_list));
208 
209     return diff;
210 }
211 
212 #ifndef _WIN32
213 static void packet_test_clear(void *sockets)
214 {
215     int *test_sockets = sockets;
216 
217     close(test_sockets[0]);
218     g_free(test_sockets);
219 }
220 
221 static int *packet_test_init(int module_num, GString *cmd_line)
222 {
223     int *test_sockets = g_new(int, 2);
224     int ret = socketpair(PF_UNIX, SOCK_STREAM, 0, test_sockets);
225     g_assert_cmpint(ret, != , -1);
226 
227     /*
228      * KISS and use -nic. We specify two nics (both emc{0,1}) because there's
229      * currently no way to specify only emc1: The driver implicitly relies on
230      * emc[i] == nd_table[i].
231      */
232     if (module_num == 0) {
233         g_string_append_printf(cmd_line,
234                                " -nic socket,fd=%d,model=" TYPE_NPCM7XX_EMC " "
235                                " -nic user,model=" TYPE_NPCM7XX_EMC " ",
236                                test_sockets[1]);
237     } else {
238         g_string_append_printf(cmd_line,
239                                " -nic user,model=" TYPE_NPCM7XX_EMC " "
240                                " -nic socket,fd=%d,model=" TYPE_NPCM7XX_EMC " ",
241                                test_sockets[1]);
242     }
243 
244     g_test_queue_destroy(packet_test_clear, test_sockets);
245     return test_sockets;
246 }
247 #endif /* _WIN32 */
248 
249 static uint32_t emc_read(QTestState *qts, const EMCModule *mod,
250                          NPCM7xxPWMRegister regno)
251 {
252     return qtest_readl(qts, mod->base_addr + regno * sizeof(uint32_t));
253 }
254 
255 #ifndef _WIN32
256 static void emc_write(QTestState *qts, const EMCModule *mod,
257                       NPCM7xxPWMRegister regno, uint32_t value)
258 {
259     qtest_writel(qts, mod->base_addr + regno * sizeof(uint32_t), value);
260 }
261 
262 static void emc_read_tx_desc(QTestState *qts, uint32_t addr,
263                              NPCM7xxEMCTxDesc *desc)
264 {
265     qtest_memread(qts, addr, desc, sizeof(*desc));
266     desc->flags = le32_to_cpu(desc->flags);
267     desc->txbsa = le32_to_cpu(desc->txbsa);
268     desc->status_and_length = le32_to_cpu(desc->status_and_length);
269     desc->ntxdsa = le32_to_cpu(desc->ntxdsa);
270 }
271 
272 static void emc_write_tx_desc(QTestState *qts, const NPCM7xxEMCTxDesc *desc,
273                               uint32_t addr)
274 {
275     NPCM7xxEMCTxDesc le_desc;
276 
277     le_desc.flags = cpu_to_le32(desc->flags);
278     le_desc.txbsa = cpu_to_le32(desc->txbsa);
279     le_desc.status_and_length = cpu_to_le32(desc->status_and_length);
280     le_desc.ntxdsa = cpu_to_le32(desc->ntxdsa);
281     qtest_memwrite(qts, addr, &le_desc, sizeof(le_desc));
282 }
283 
284 static void emc_read_rx_desc(QTestState *qts, uint32_t addr,
285                              NPCM7xxEMCRxDesc *desc)
286 {
287     qtest_memread(qts, addr, desc, sizeof(*desc));
288     desc->status_and_length = le32_to_cpu(desc->status_and_length);
289     desc->rxbsa = le32_to_cpu(desc->rxbsa);
290     desc->reserved = le32_to_cpu(desc->reserved);
291     desc->nrxdsa = le32_to_cpu(desc->nrxdsa);
292 }
293 
294 static void emc_write_rx_desc(QTestState *qts, const NPCM7xxEMCRxDesc *desc,
295                               uint32_t addr)
296 {
297     NPCM7xxEMCRxDesc le_desc;
298 
299     le_desc.status_and_length = cpu_to_le32(desc->status_and_length);
300     le_desc.rxbsa = cpu_to_le32(desc->rxbsa);
301     le_desc.reserved = cpu_to_le32(desc->reserved);
302     le_desc.nrxdsa = cpu_to_le32(desc->nrxdsa);
303     qtest_memwrite(qts, addr, &le_desc, sizeof(le_desc));
304 }
305 
306 /*
307  * Reset the EMC module.
308  * The module must be reset before, e.g., TXDLSA,RXDLSA are changed.
309  */
310 static bool emc_soft_reset(QTestState *qts, const EMCModule *mod)
311 {
312     uint32_t val;
313     uint64_t end_time;
314 
315     emc_write(qts, mod, REG_MCMDR, REG_MCMDR_SWR);
316 
317     /*
318      * Wait for device to reset as the linux driver does.
319      * During reset the AHB reads 0 for all registers. So first wait for
320      * something that resets to non-zero, and then wait for SWR becoming 0.
321      */
322     end_time = g_get_monotonic_time() + TIMEOUT_SECONDS * G_TIME_SPAN_SECOND;
323 
324     do {
325         qtest_clock_step(qts, 100);
326         val = emc_read(qts, mod, REG_FFTCR);
327     } while (val == 0 && g_get_monotonic_time() < end_time);
328     if (val != 0) {
329         do {
330             qtest_clock_step(qts, 100);
331             val = emc_read(qts, mod, REG_MCMDR);
332             if ((val & REG_MCMDR_SWR) == 0) {
333                 /*
334                  * N.B. The CAMs have been reset here, so macaddr matching of
335                  * incoming packets will not work.
336                  */
337                 return true;
338             }
339         } while (g_get_monotonic_time() < end_time);
340     }
341 
342     g_message("%s: Timeout expired", __func__);
343     return false;
344 }
345 #endif /* _WIN32 */
346 
347 /* Check emc registers are reset to default value. */
348 static void test_init(gconstpointer test_data)
349 {
350     const TestData *td = test_data;
351     const EMCModule *mod = td->module;
352     QTestState *qts = qtest_init("-machine quanta-gsj");
353     int i;
354 
355 #define CHECK_REG(regno, value) \
356   do { \
357     g_assert_cmphex(emc_read(qts, mod, (regno)), ==, (value)); \
358   } while (0)
359 
360     CHECK_REG(REG_CAMCMR, 0);
361     CHECK_REG(REG_CAMEN, 0);
362     CHECK_REG(REG_TXDLSA, 0xfffffffc);
363     CHECK_REG(REG_RXDLSA, 0xfffffffc);
364     CHECK_REG(REG_MCMDR, 0);
365     CHECK_REG(REG_MIID, 0);
366     CHECK_REG(REG_MIIDA, 0x00900000);
367     CHECK_REG(REG_FFTCR, 0x0101);
368     CHECK_REG(REG_DMARFC, 0x0800);
369     CHECK_REG(REG_MIEN, 0);
370     CHECK_REG(REG_MISTA, 0);
371     CHECK_REG(REG_MGSTA, 0);
372     CHECK_REG(REG_MPCNT, 0x7fff);
373     CHECK_REG(REG_MRPC, 0);
374     CHECK_REG(REG_MRPCC, 0);
375     CHECK_REG(REG_MREPC, 0);
376     CHECK_REG(REG_DMARFS, 0);
377     CHECK_REG(REG_CTXDSA, 0);
378     CHECK_REG(REG_CTXBSA, 0);
379     CHECK_REG(REG_CRXDSA, 0);
380     CHECK_REG(REG_CRXBSA, 0);
381 
382 #undef CHECK_REG
383 
384     /* Skip over the MAC address registers, which is BASE+0 */
385     for (i = 1; i < NUM_CAMML_REGS; ++i) {
386         g_assert_cmpuint(emc_read(qts, mod, REG_CAMM_BASE + i * 2), ==,
387                          0);
388         g_assert_cmpuint(emc_read(qts, mod, REG_CAML_BASE + i * 2), ==,
389                          0);
390     }
391 
392     qtest_quit(qts);
393 }
394 
395 #ifndef _WIN32
396 static bool emc_wait_irq(QTestState *qts, const EMCModule *mod, int step,
397                          bool is_tx)
398 {
399     uint64_t end_time =
400         g_get_monotonic_time() + TIMEOUT_SECONDS * G_TIME_SPAN_SECOND;
401 
402     do {
403         if (qtest_get_irq(qts, is_tx ? mod->tx_irq : mod->rx_irq)) {
404             return true;
405         }
406         qtest_clock_step(qts, step);
407     } while (g_get_monotonic_time() < end_time);
408 
409     g_message("%s: Timeout expired", __func__);
410     return false;
411 }
412 
413 static bool emc_wait_mista(QTestState *qts, const EMCModule *mod, int step,
414                            uint32_t flag)
415 {
416     uint64_t end_time =
417         g_get_monotonic_time() + TIMEOUT_SECONDS * G_TIME_SPAN_SECOND;
418 
419     do {
420         uint32_t mista = emc_read(qts, mod, REG_MISTA);
421         if (mista & flag) {
422             return true;
423         }
424         qtest_clock_step(qts, step);
425     } while (g_get_monotonic_time() < end_time);
426 
427     g_message("%s: Timeout expired", __func__);
428     return false;
429 }
430 
431 static bool wait_socket_readable(int fd)
432 {
433     fd_set read_fds;
434     struct timeval tv;
435     int rv;
436 
437     FD_ZERO(&read_fds);
438     FD_SET(fd, &read_fds);
439     tv.tv_sec = TIMEOUT_SECONDS;
440     tv.tv_usec = 0;
441     rv = select(fd + 1, &read_fds, NULL, NULL, &tv);
442     if (rv == -1) {
443         perror("select");
444     } else if (rv == 0) {
445         g_message("%s: Timeout expired", __func__);
446     }
447     return rv == 1;
448 }
449 
450 /* Initialize *desc (in host endian format). */
451 static void init_tx_desc(NPCM7xxEMCTxDesc *desc, size_t count,
452                          uint32_t desc_addr)
453 {
454     g_assert(count >= 2);
455     memset(&desc[0], 0, sizeof(*desc) * count);
456     /* Leave the last one alone, owned by the cpu -> stops transmission. */
457     for (size_t i = 0; i < count - 1; ++i) {
458         desc[i].flags =
459             (TX_DESC_FLAG_OWNER_MASK | /* owner = 1: emc */
460              TX_DESC_FLAG_INTEN |
461              0 | /* crc append = 0 */
462              0 /* padding enable = 0 */);
463         desc[i].status_and_length =
464             (0 | /* collision count = 0 */
465              0 | /* SQE = 0 */
466              0 | /* PAU = 0 */
467              0 | /* TXHA = 0 */
468              0 | /* LC = 0 */
469              0 | /* TXABT = 0 */
470              0 | /* NCS = 0 */
471              0 | /* EXDEF = 0 */
472              0 | /* TXCP = 0 */
473              0 | /* DEF = 0 */
474              0 | /* TXINTR = 0 */
475              0 /* length filled in later */);
476         desc[i].ntxdsa = desc_addr + (i + 1) * sizeof(*desc);
477     }
478 }
479 
480 static void enable_tx(QTestState *qts, const EMCModule *mod,
481                       const NPCM7xxEMCTxDesc *desc, size_t count,
482                       uint32_t desc_addr, uint32_t mien_flags)
483 {
484     /* Write the descriptors to guest memory. */
485     for (size_t i = 0; i < count; ++i) {
486         emc_write_tx_desc(qts, desc + i, desc_addr + i * sizeof(*desc));
487     }
488 
489     /* Trigger sending the packet. */
490     /* The module must be reset before changing TXDLSA. */
491     g_assert(emc_soft_reset(qts, mod));
492     emc_write(qts, mod, REG_TXDLSA, desc_addr);
493     emc_write(qts, mod, REG_CTXDSA, ~0);
494     emc_write(qts, mod, REG_MIEN, REG_MIEN_ENTXCP | mien_flags);
495     {
496         uint32_t mcmdr = emc_read(qts, mod, REG_MCMDR);
497         mcmdr |= REG_MCMDR_TXON;
498         emc_write(qts, mod, REG_MCMDR, mcmdr);
499     }
500 }
501 
502 static void emc_send_verify1(QTestState *qts, const EMCModule *mod, int fd,
503                              bool with_irq, uint32_t desc_addr,
504                              uint32_t next_desc_addr,
505                              const char *test_data, int test_size)
506 {
507     NPCM7xxEMCTxDesc result_desc;
508     uint32_t expected_mask, expected_value, recv_len;
509     int ret;
510     char buffer[TX_DATA_LEN];
511 
512     g_assert(wait_socket_readable(fd));
513 
514     /* Read the descriptor back. */
515     emc_read_tx_desc(qts, desc_addr, &result_desc);
516     /* Descriptor should be owned by cpu now. */
517     g_assert((result_desc.flags & TX_DESC_FLAG_OWNER_MASK) == 0);
518     /* Test the status bits, ignoring the length field. */
519     expected_mask = 0xffff << 16;
520     expected_value = TX_DESC_STATUS_TXCP;
521     if (with_irq) {
522         expected_value |= TX_DESC_STATUS_TXINTR;
523     }
524     g_assert_cmphex((result_desc.status_and_length & expected_mask), ==,
525                     expected_value);
526 
527     /* Check data sent to the backend. */
528     recv_len = ~0;
529     ret = recv(fd, &recv_len, sizeof(recv_len), MSG_DONTWAIT);
530     g_assert_cmpint(ret, == , sizeof(recv_len));
531 
532     g_assert(wait_socket_readable(fd));
533     memset(buffer, 0xff, sizeof(buffer));
534     ret = recv(fd, buffer, test_size, MSG_DONTWAIT);
535     g_assert_cmpmem(buffer, ret, test_data, test_size);
536 }
537 
538 static void emc_send_verify(QTestState *qts, const EMCModule *mod, int fd,
539                             bool with_irq)
540 {
541     NPCM7xxEMCTxDesc desc[NUM_TX_DESCRIPTORS];
542     uint32_t desc_addr = DESC_ADDR;
543     static const char test1_data[] = "TEST1";
544     static const char test2_data[] = "Testing 1 2 3 ...";
545     uint32_t data1_addr = DATA_ADDR;
546     uint32_t data2_addr = data1_addr + sizeof(test1_data);
547     bool got_tdu;
548     uint32_t end_desc_addr;
549 
550     /* Prepare test data buffer. */
551     qtest_memwrite(qts, data1_addr, test1_data, sizeof(test1_data));
552     qtest_memwrite(qts, data2_addr, test2_data, sizeof(test2_data));
553 
554     init_tx_desc(&desc[0], NUM_TX_DESCRIPTORS, desc_addr);
555     desc[0].txbsa = data1_addr;
556     desc[0].status_and_length |= sizeof(test1_data);
557     desc[1].txbsa = data2_addr;
558     desc[1].status_and_length |= sizeof(test2_data);
559 
560     enable_tx(qts, mod, &desc[0], NUM_TX_DESCRIPTORS, desc_addr,
561               with_irq ? REG_MIEN_ENTXINTR : 0);
562 
563     /* Prod the device to send the packet. */
564     emc_write(qts, mod, REG_TSDR, 1);
565 
566     /*
567      * It's problematic to observe the interrupt for each packet.
568      * Instead just wait until all the packets go out.
569      */
570     got_tdu = false;
571     while (!got_tdu) {
572         if (with_irq) {
573             g_assert_true(emc_wait_irq(qts, mod, TX_STEP_COUNT,
574                                        /*is_tx=*/true));
575         } else {
576             g_assert_true(emc_wait_mista(qts, mod, TX_STEP_COUNT,
577                                          REG_MISTA_TXINTR));
578         }
579         got_tdu = !!(emc_read(qts, mod, REG_MISTA) & REG_MISTA_TDU);
580         /* If we don't have TDU yet, reset the interrupt. */
581         if (!got_tdu) {
582             emc_write(qts, mod, REG_MISTA,
583                       emc_read(qts, mod, REG_MISTA) & 0xffff0000);
584         }
585     }
586 
587     end_desc_addr = desc_addr + 2 * sizeof(desc[0]);
588     g_assert_cmphex(emc_read(qts, mod, REG_CTXDSA), ==, end_desc_addr);
589     g_assert_cmphex(emc_read(qts, mod, REG_MISTA), ==,
590                     REG_MISTA_TXCP | REG_MISTA_TXINTR | REG_MISTA_TDU);
591 
592     emc_send_verify1(qts, mod, fd, with_irq,
593                      desc_addr, end_desc_addr,
594                      test1_data, sizeof(test1_data));
595     emc_send_verify1(qts, mod, fd, with_irq,
596                      desc_addr + sizeof(desc[0]), end_desc_addr,
597                      test2_data, sizeof(test2_data));
598 }
599 
600 /* Initialize *desc (in host endian format). */
601 static void init_rx_desc(NPCM7xxEMCRxDesc *desc, size_t count,
602                          uint32_t desc_addr, uint32_t data_addr)
603 {
604     g_assert_true(count >= 2);
605     memset(desc, 0, sizeof(*desc) * count);
606     desc[0].rxbsa = data_addr;
607     desc[0].status_and_length =
608         (0b10 << RX_DESC_STATUS_OWNER_SHIFT | /* owner = 10: emc */
609          0 | /* RP = 0 */
610          0 | /* ALIE = 0 */
611          0 | /* RXGD = 0 */
612          0 | /* PTLE = 0 */
613          0 | /* CRCE = 0 */
614          0 | /* RXINTR = 0 */
615          0   /* length (filled in later) */);
616     /* Leave the last one alone, owned by the cpu -> stops transmission. */
617     desc[0].nrxdsa = desc_addr + sizeof(*desc);
618 }
619 
620 static void enable_rx(QTestState *qts, const EMCModule *mod,
621                       const NPCM7xxEMCRxDesc *desc, size_t count,
622                       uint32_t desc_addr, uint32_t mien_flags,
623                       uint32_t mcmdr_flags)
624 {
625     /*
626      * Write the descriptor to guest memory.
627      * FWIW, IWBN if the docs said the buffer needs to be at least DMARFC
628      * bytes.
629      */
630     for (size_t i = 0; i < count; ++i) {
631         emc_write_rx_desc(qts, desc + i, desc_addr + i * sizeof(*desc));
632     }
633 
634     /* Trigger receiving the packet. */
635     /* The module must be reset before changing RXDLSA. */
636     g_assert(emc_soft_reset(qts, mod));
637     emc_write(qts, mod, REG_RXDLSA, desc_addr);
638     emc_write(qts, mod, REG_MIEN, REG_MIEN_ENRXGD | mien_flags);
639 
640     /*
641      * We don't know what the device's macaddr is, so just accept all
642      * unicast packets (AUP).
643      */
644     emc_write(qts, mod, REG_CAMCMR, REG_CAMCMR_AUP);
645     emc_write(qts, mod, REG_CAMEN, 1 << 0);
646     {
647         uint32_t mcmdr = emc_read(qts, mod, REG_MCMDR);
648         mcmdr |= REG_MCMDR_RXON | mcmdr_flags;
649         emc_write(qts, mod, REG_MCMDR, mcmdr);
650     }
651 }
652 
653 static void emc_recv_verify(QTestState *qts, const EMCModule *mod, int fd,
654                             bool with_irq, bool pump_rsdr)
655 {
656     NPCM7xxEMCRxDesc desc[NUM_RX_DESCRIPTORS];
657     uint32_t desc_addr = DESC_ADDR;
658     uint32_t data_addr = DATA_ADDR;
659     int ret;
660     uint32_t expected_mask, expected_value;
661     NPCM7xxEMCRxDesc result_desc;
662 
663     /* Prepare test data buffer. */
664     const char test[RX_DATA_LEN] = "TEST";
665     int len = htonl(sizeof(test));
666     const struct iovec iov[] = {
667         {
668             .iov_base = &len,
669             .iov_len = sizeof(len),
670         },{
671             .iov_base = (char *) test,
672             .iov_len = sizeof(test),
673         },
674     };
675 
676     /*
677      * Reset the device BEFORE sending a test packet, otherwise the packet
678      * may get swallowed by an active device of an earlier test.
679      */
680     init_rx_desc(&desc[0], NUM_RX_DESCRIPTORS, desc_addr, data_addr);
681     enable_rx(qts, mod, &desc[0], NUM_RX_DESCRIPTORS, desc_addr,
682               with_irq ? REG_MIEN_ENRXINTR : 0, 0);
683 
684     /*
685      * If requested, prod the device to accept a packet.
686      * This isn't necessary, the linux driver doesn't do this.
687      * Test doing/not-doing this for robustness.
688      */
689     if (pump_rsdr) {
690         emc_write(qts, mod, REG_RSDR, 1);
691     }
692 
693     /* Send test packet to device's socket. */
694     ret = iov_send(fd, iov, 2, 0, sizeof(len) + sizeof(test));
695     g_assert_cmpint(ret, == , sizeof(test) + sizeof(len));
696 
697     /* Wait for RX interrupt. */
698     if (with_irq) {
699         g_assert_true(emc_wait_irq(qts, mod, RX_STEP_COUNT, /*is_tx=*/false));
700     } else {
701         g_assert_true(emc_wait_mista(qts, mod, RX_STEP_COUNT, REG_MISTA_RXGD));
702     }
703 
704     g_assert_cmphex(emc_read(qts, mod, REG_CRXDSA), ==,
705                     desc_addr + sizeof(desc[0]));
706 
707     expected_mask = 0xffff;
708     expected_value = (REG_MISTA_DENI |
709                       REG_MISTA_RXGD |
710                       REG_MISTA_RXINTR);
711     g_assert_cmphex((emc_read(qts, mod, REG_MISTA) & expected_mask),
712                     ==, expected_value);
713 
714     /* Read the descriptor back. */
715     emc_read_rx_desc(qts, desc_addr, &result_desc);
716     /* Descriptor should be owned by cpu now. */
717     g_assert((result_desc.status_and_length & RX_DESC_STATUS_OWNER_MASK) == 0);
718     /* Test the status bits, ignoring the length field. */
719     expected_mask = 0xffff << 16;
720     expected_value = RX_DESC_STATUS_RXGD;
721     if (with_irq) {
722         expected_value |= RX_DESC_STATUS_RXINTR;
723     }
724     g_assert_cmphex((result_desc.status_and_length & expected_mask), ==,
725                     expected_value);
726     g_assert_cmpint(RX_DESC_PKT_LEN(result_desc.status_and_length), ==,
727                     RX_DATA_LEN + CRC_LENGTH);
728 
729     {
730         char buffer[RX_DATA_LEN];
731         qtest_memread(qts, data_addr, buffer, sizeof(buffer));
732         g_assert_cmpstr(buffer, == , "TEST");
733     }
734 }
735 
736 static void emc_test_ptle(QTestState *qts, const EMCModule *mod, int fd)
737 {
738     NPCM7xxEMCRxDesc desc[NUM_RX_DESCRIPTORS];
739     uint32_t desc_addr = DESC_ADDR;
740     uint32_t data_addr = DATA_ADDR;
741     int ret;
742     NPCM7xxEMCRxDesc result_desc;
743     uint32_t expected_mask, expected_value;
744 
745     /* Prepare test data buffer. */
746 #define PTLE_DATA_LEN 1600
747     char test_data[PTLE_DATA_LEN];
748     int len = htonl(sizeof(test_data));
749     const struct iovec iov[] = {
750         {
751             .iov_base = &len,
752             .iov_len = sizeof(len),
753         },{
754             .iov_base = (char *) test_data,
755             .iov_len = sizeof(test_data),
756         },
757     };
758     memset(test_data, 42, sizeof(test_data));
759 
760     /*
761      * Reset the device BEFORE sending a test packet, otherwise the packet
762      * may get swallowed by an active device of an earlier test.
763      */
764     init_rx_desc(&desc[0], NUM_RX_DESCRIPTORS, desc_addr, data_addr);
765     enable_rx(qts, mod, &desc[0], NUM_RX_DESCRIPTORS, desc_addr,
766               REG_MIEN_ENRXINTR, REG_MCMDR_ALP);
767 
768     /* Send test packet to device's socket. */
769     ret = iov_send(fd, iov, 2, 0, sizeof(len) + sizeof(test_data));
770     g_assert_cmpint(ret, == , sizeof(test_data) + sizeof(len));
771 
772     /* Wait for RX interrupt. */
773     g_assert_true(emc_wait_irq(qts, mod, RX_STEP_COUNT, /*is_tx=*/false));
774 
775     /* Read the descriptor back. */
776     emc_read_rx_desc(qts, desc_addr, &result_desc);
777     /* Descriptor should be owned by cpu now. */
778     g_assert((result_desc.status_and_length & RX_DESC_STATUS_OWNER_MASK) == 0);
779     /* Test the status bits, ignoring the length field. */
780     expected_mask = 0xffff << 16;
781     expected_value = (RX_DESC_STATUS_RXGD |
782                       RX_DESC_STATUS_PTLE |
783                       RX_DESC_STATUS_RXINTR);
784     g_assert_cmphex((result_desc.status_and_length & expected_mask), ==,
785                     expected_value);
786     g_assert_cmpint(RX_DESC_PKT_LEN(result_desc.status_and_length), ==,
787                     PTLE_DATA_LEN + CRC_LENGTH);
788 
789     {
790         char buffer[PTLE_DATA_LEN];
791         qtest_memread(qts, data_addr, buffer, sizeof(buffer));
792         g_assert(memcmp(buffer, test_data, PTLE_DATA_LEN) == 0);
793     }
794 }
795 
796 static void test_tx(gconstpointer test_data)
797 {
798     const TestData *td = test_data;
799     GString *cmd_line = g_string_new("-machine quanta-gsj");
800     int *test_sockets = packet_test_init(emc_module_index(td->module),
801                                          cmd_line);
802     QTestState *qts = qtest_init(cmd_line->str);
803 
804     /*
805      * TODO: For pedantic correctness test_sockets[0] should be closed after
806      * the fork and before the exec, but that will require some harness
807      * improvements.
808      */
809     close(test_sockets[1]);
810     /* Defensive programming */
811     test_sockets[1] = -1;
812 
813     qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
814 
815     emc_send_verify(qts, td->module, test_sockets[0], /*with_irq=*/false);
816     emc_send_verify(qts, td->module, test_sockets[0], /*with_irq=*/true);
817 
818     qtest_quit(qts);
819 }
820 
821 static void test_rx(gconstpointer test_data)
822 {
823     const TestData *td = test_data;
824     GString *cmd_line = g_string_new("-machine quanta-gsj");
825     int *test_sockets = packet_test_init(emc_module_index(td->module),
826                                          cmd_line);
827     QTestState *qts = qtest_init(cmd_line->str);
828 
829     /*
830      * TODO: For pedantic correctness test_sockets[0] should be closed after
831      * the fork and before the exec, but that will require some harness
832      * improvements.
833      */
834     close(test_sockets[1]);
835     /* Defensive programming */
836     test_sockets[1] = -1;
837 
838     qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
839 
840     emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=*/false,
841                     /*pump_rsdr=*/false);
842     emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=*/false,
843                     /*pump_rsdr=*/true);
844     emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=*/true,
845                     /*pump_rsdr=*/false);
846     emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=*/true,
847                     /*pump_rsdr=*/true);
848     emc_test_ptle(qts, td->module, test_sockets[0]);
849 
850     qtest_quit(qts);
851 }
852 #endif /* _WIN32 */
853 
854 static void emc_add_test(const char *name, const TestData* td,
855                          GTestDataFunc fn)
856 {
857     g_autofree char *full_name = g_strdup_printf(
858             "npcm7xx_emc/emc[%d]/%s", emc_module_index(td->module), name);
859     qtest_add_data_func(full_name, td, fn);
860 }
861 #define add_test(name, td) emc_add_test(#name, td, test_##name)
862 
863 int main(int argc, char **argv)
864 {
865     TestData test_data_list[ARRAY_SIZE(emc_module_list)];
866 
867     g_test_init(&argc, &argv, NULL);
868 
869     for (int i = 0; i < ARRAY_SIZE(emc_module_list); ++i) {
870         TestData *td = &test_data_list[i];
871 
872         td->module = &emc_module_list[i];
873 
874         add_test(init, td);
875 #ifndef _WIN32
876         add_test(tx, td);
877         add_test(rx, td);
878 #endif
879     }
880 
881     return g_test_run();
882 }
883