1e6646167SDoug Evans /*
2e6646167SDoug Evans * QTests for Nuvoton NPCM7xx EMC Modules.
3e6646167SDoug Evans *
4e6646167SDoug Evans * Copyright 2020 Google LLC
5e6646167SDoug Evans *
6e6646167SDoug Evans * This program is free software; you can redistribute it and/or modify it
7e6646167SDoug Evans * under the terms of the GNU General Public License as published by the
8e6646167SDoug Evans * Free Software Foundation; either version 2 of the License, or
9e6646167SDoug Evans * (at your option) any later version.
10e6646167SDoug Evans *
11e6646167SDoug Evans * This program is distributed in the hope that it will be useful, but WITHOUT
12e6646167SDoug Evans * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13e6646167SDoug Evans * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14e6646167SDoug Evans * for more details.
15e6646167SDoug Evans */
16e6646167SDoug Evans
17e6646167SDoug Evans #include "qemu/osdep.h"
18e6646167SDoug Evans #include "libqos/libqos.h"
19e6646167SDoug Evans #include "qapi/qmp/qdict.h"
20e6646167SDoug Evans #include "qapi/qmp/qnum.h"
21e6646167SDoug Evans #include "qemu/bitops.h"
22e6646167SDoug Evans #include "qemu/iov.h"
23e6646167SDoug Evans
24e6646167SDoug Evans /* Name of the emc device. */
25e6646167SDoug Evans #define TYPE_NPCM7XX_EMC "npcm7xx-emc"
26e6646167SDoug Evans
27e6646167SDoug Evans /* Timeout for various operations, in seconds. */
28e6646167SDoug Evans #define TIMEOUT_SECONDS 10
29e6646167SDoug Evans
30e6646167SDoug Evans /* Address in memory of the descriptor. */
31e6646167SDoug Evans #define DESC_ADDR (1 << 20) /* 1 MiB */
32e6646167SDoug Evans
33e6646167SDoug Evans /* Address in memory of the data packet. */
34e6646167SDoug Evans #define DATA_ADDR (DESC_ADDR + 4096)
35e6646167SDoug Evans
36e6646167SDoug Evans #define CRC_LENGTH 4
37e6646167SDoug Evans
38e6646167SDoug Evans #define NUM_TX_DESCRIPTORS 3
39e6646167SDoug Evans #define NUM_RX_DESCRIPTORS 2
40e6646167SDoug Evans
41e6646167SDoug Evans /* Size of tx,rx test buffers. */
42e6646167SDoug Evans #define TX_DATA_LEN 64
43e6646167SDoug Evans #define RX_DATA_LEN 64
44e6646167SDoug Evans
45e6646167SDoug Evans #define TX_STEP_COUNT 10000
46e6646167SDoug Evans #define RX_STEP_COUNT 10000
47e6646167SDoug Evans
48e6646167SDoug Evans /* 32-bit register indices. */
49e6646167SDoug Evans typedef enum NPCM7xxPWMRegister {
50e6646167SDoug Evans /* Control registers. */
51e6646167SDoug Evans REG_CAMCMR,
52e6646167SDoug Evans REG_CAMEN,
53e6646167SDoug Evans
54e6646167SDoug Evans /* There are 16 CAMn[ML] registers. */
55e6646167SDoug Evans REG_CAMM_BASE,
56e6646167SDoug Evans REG_CAML_BASE,
57e6646167SDoug Evans
58e6646167SDoug Evans REG_TXDLSA = 0x22,
59e6646167SDoug Evans REG_RXDLSA,
60e6646167SDoug Evans REG_MCMDR,
61e6646167SDoug Evans REG_MIID,
62e6646167SDoug Evans REG_MIIDA,
63e6646167SDoug Evans REG_FFTCR,
64e6646167SDoug Evans REG_TSDR,
65e6646167SDoug Evans REG_RSDR,
66e6646167SDoug Evans REG_DMARFC,
67e6646167SDoug Evans REG_MIEN,
68e6646167SDoug Evans
69e6646167SDoug Evans /* Status registers. */
70e6646167SDoug Evans REG_MISTA,
71e6646167SDoug Evans REG_MGSTA,
72e6646167SDoug Evans REG_MPCNT,
73e6646167SDoug Evans REG_MRPC,
74e6646167SDoug Evans REG_MRPCC,
75e6646167SDoug Evans REG_MREPC,
76e6646167SDoug Evans REG_DMARFS,
77e6646167SDoug Evans REG_CTXDSA,
78e6646167SDoug Evans REG_CTXBSA,
79e6646167SDoug Evans REG_CRXDSA,
80e6646167SDoug Evans REG_CRXBSA,
81e6646167SDoug Evans
82e6646167SDoug Evans NPCM7XX_NUM_EMC_REGS,
83e6646167SDoug Evans } NPCM7xxPWMRegister;
84e6646167SDoug Evans
85e6646167SDoug Evans enum { NUM_CAMML_REGS = 16 };
86e6646167SDoug Evans
87e6646167SDoug Evans /* REG_CAMCMR fields */
88e6646167SDoug Evans /* Enable CAM Compare */
89e6646167SDoug Evans #define REG_CAMCMR_ECMP (1 << 4)
90e6646167SDoug Evans /* Accept Unicast Packet */
91e6646167SDoug Evans #define REG_CAMCMR_AUP (1 << 0)
92e6646167SDoug Evans
93e6646167SDoug Evans /* REG_MCMDR fields */
94e6646167SDoug Evans /* Software Reset */
95e6646167SDoug Evans #define REG_MCMDR_SWR (1 << 24)
96e6646167SDoug Evans /* Frame Transmission On */
97e6646167SDoug Evans #define REG_MCMDR_TXON (1 << 8)
98e6646167SDoug Evans /* Accept Long Packet */
99e6646167SDoug Evans #define REG_MCMDR_ALP (1 << 1)
100e6646167SDoug Evans /* Frame Reception On */
101e6646167SDoug Evans #define REG_MCMDR_RXON (1 << 0)
102e6646167SDoug Evans
103e6646167SDoug Evans /* REG_MIEN fields */
104e6646167SDoug Evans /* Enable Transmit Completion Interrupt */
105e6646167SDoug Evans #define REG_MIEN_ENTXCP (1 << 18)
106e6646167SDoug Evans /* Enable Transmit Interrupt */
107e6646167SDoug Evans #define REG_MIEN_ENTXINTR (1 << 16)
108e6646167SDoug Evans /* Enable Receive Good Interrupt */
109e6646167SDoug Evans #define REG_MIEN_ENRXGD (1 << 4)
110e6646167SDoug Evans /* ENable Receive Interrupt */
111e6646167SDoug Evans #define REG_MIEN_ENRXINTR (1 << 0)
112e6646167SDoug Evans
113e6646167SDoug Evans /* REG_MISTA fields */
114e6646167SDoug Evans /* Transmit Bus Error Interrupt */
115e6646167SDoug Evans #define REG_MISTA_TXBERR (1 << 24)
116e6646167SDoug Evans /* Transmit Descriptor Unavailable Interrupt */
117e6646167SDoug Evans #define REG_MISTA_TDU (1 << 23)
118e6646167SDoug Evans /* Transmit Completion Interrupt */
119e6646167SDoug Evans #define REG_MISTA_TXCP (1 << 18)
120e6646167SDoug Evans /* Transmit Interrupt */
121e6646167SDoug Evans #define REG_MISTA_TXINTR (1 << 16)
122e6646167SDoug Evans /* Receive Bus Error Interrupt */
123e6646167SDoug Evans #define REG_MISTA_RXBERR (1 << 11)
124e6646167SDoug Evans /* Receive Descriptor Unavailable Interrupt */
125e6646167SDoug Evans #define REG_MISTA_RDU (1 << 10)
126e6646167SDoug Evans /* DMA Early Notification Interrupt */
127e6646167SDoug Evans #define REG_MISTA_DENI (1 << 9)
128e6646167SDoug Evans /* Maximum Frame Length Interrupt */
129e6646167SDoug Evans #define REG_MISTA_DFOI (1 << 8)
130e6646167SDoug Evans /* Receive Good Interrupt */
131e6646167SDoug Evans #define REG_MISTA_RXGD (1 << 4)
132e6646167SDoug Evans /* Packet Too Long Interrupt */
133e6646167SDoug Evans #define REG_MISTA_PTLE (1 << 3)
134e6646167SDoug Evans /* Receive Interrupt */
135e6646167SDoug Evans #define REG_MISTA_RXINTR (1 << 0)
136e6646167SDoug Evans
137e6646167SDoug Evans typedef struct NPCM7xxEMCTxDesc NPCM7xxEMCTxDesc;
138e6646167SDoug Evans typedef struct NPCM7xxEMCRxDesc NPCM7xxEMCRxDesc;
139e6646167SDoug Evans
140e6646167SDoug Evans struct NPCM7xxEMCTxDesc {
141e6646167SDoug Evans uint32_t flags;
142e6646167SDoug Evans uint32_t txbsa;
143e6646167SDoug Evans uint32_t status_and_length;
144e6646167SDoug Evans uint32_t ntxdsa;
145e6646167SDoug Evans };
146e6646167SDoug Evans
147e6646167SDoug Evans struct NPCM7xxEMCRxDesc {
148e6646167SDoug Evans uint32_t status_and_length;
149e6646167SDoug Evans uint32_t rxbsa;
150e6646167SDoug Evans uint32_t reserved;
151e6646167SDoug Evans uint32_t nrxdsa;
152e6646167SDoug Evans };
153e6646167SDoug Evans
154e6646167SDoug Evans /* NPCM7xxEMCTxDesc.flags values */
155e6646167SDoug Evans /* Owner: 0 = cpu, 1 = emc */
156e6646167SDoug Evans #define TX_DESC_FLAG_OWNER_MASK (1 << 31)
157e6646167SDoug Evans /* Transmit interrupt enable */
158e6646167SDoug Evans #define TX_DESC_FLAG_INTEN (1 << 2)
159e6646167SDoug Evans
160e6646167SDoug Evans /* NPCM7xxEMCTxDesc.status_and_length values */
161e6646167SDoug Evans /* Transmission complete */
162e6646167SDoug Evans #define TX_DESC_STATUS_TXCP (1 << 19)
163e6646167SDoug Evans /* Transmit interrupt */
164e6646167SDoug Evans #define TX_DESC_STATUS_TXINTR (1 << 16)
165e6646167SDoug Evans
166e6646167SDoug Evans /* NPCM7xxEMCRxDesc.status_and_length values */
167e6646167SDoug Evans /* Owner: 0b00 = cpu, 0b10 = emc */
168e6646167SDoug Evans #define RX_DESC_STATUS_OWNER_SHIFT 30
169e6646167SDoug Evans #define RX_DESC_STATUS_OWNER_MASK 0xc0000000
170e6646167SDoug Evans /* Frame Reception Complete */
171e6646167SDoug Evans #define RX_DESC_STATUS_RXGD (1 << 20)
172e6646167SDoug Evans /* Packet too long */
173e6646167SDoug Evans #define RX_DESC_STATUS_PTLE (1 << 19)
174e6646167SDoug Evans /* Receive Interrupt */
175e6646167SDoug Evans #define RX_DESC_STATUS_RXINTR (1 << 16)
176e6646167SDoug Evans
177e6646167SDoug Evans #define RX_DESC_PKT_LEN(word) ((uint32_t) (word) & 0xffff)
178e6646167SDoug Evans
179e6646167SDoug Evans typedef struct EMCModule {
180e6646167SDoug Evans int rx_irq;
181e6646167SDoug Evans int tx_irq;
182e6646167SDoug Evans uint64_t base_addr;
183e6646167SDoug Evans } EMCModule;
184e6646167SDoug Evans
185e6646167SDoug Evans typedef struct TestData {
186e6646167SDoug Evans const EMCModule *module;
187e6646167SDoug Evans } TestData;
188e6646167SDoug Evans
189e6646167SDoug Evans static const EMCModule emc_module_list[] = {
190e6646167SDoug Evans {
191e6646167SDoug Evans .rx_irq = 15,
192e6646167SDoug Evans .tx_irq = 16,
193e6646167SDoug Evans .base_addr = 0xf0825000
194e6646167SDoug Evans },
195e6646167SDoug Evans {
196e6646167SDoug Evans .rx_irq = 114,
197e6646167SDoug Evans .tx_irq = 115,
198e6646167SDoug Evans .base_addr = 0xf0826000
199e6646167SDoug Evans }
200e6646167SDoug Evans };
201e6646167SDoug Evans
202e6646167SDoug Evans /* Returns the index of the EMC module. */
emc_module_index(const EMCModule * mod)203e6646167SDoug Evans static int emc_module_index(const EMCModule *mod)
204e6646167SDoug Evans {
205e6646167SDoug Evans ptrdiff_t diff = mod - emc_module_list;
206e6646167SDoug Evans
207e6646167SDoug Evans g_assert_true(diff >= 0 && diff < ARRAY_SIZE(emc_module_list));
208e6646167SDoug Evans
209e6646167SDoug Evans return diff;
210e6646167SDoug Evans }
211e6646167SDoug Evans
212bf3267e7SBin Meng #ifndef _WIN32
packet_test_clear(void * sockets)213e6646167SDoug Evans static void packet_test_clear(void *sockets)
214e6646167SDoug Evans {
215e6646167SDoug Evans int *test_sockets = sockets;
216e6646167SDoug Evans
217e6646167SDoug Evans close(test_sockets[0]);
218e6646167SDoug Evans g_free(test_sockets);
219e6646167SDoug Evans }
220e6646167SDoug Evans
packet_test_init(int module_num,GString * cmd_line)221e6646167SDoug Evans static int *packet_test_init(int module_num, GString *cmd_line)
222e6646167SDoug Evans {
223e6646167SDoug Evans int *test_sockets = g_new(int, 2);
224e6646167SDoug Evans int ret = socketpair(PF_UNIX, SOCK_STREAM, 0, test_sockets);
225e6646167SDoug Evans g_assert_cmpint(ret, != , -1);
226e6646167SDoug Evans
227e6646167SDoug Evans /*
228e6646167SDoug Evans * KISS and use -nic. We specify two nics (both emc{0,1}) because there's
229e6646167SDoug Evans * currently no way to specify only emc1: The driver implicitly relies on
230e6646167SDoug Evans * emc[i] == nd_table[i].
231e6646167SDoug Evans */
232e6646167SDoug Evans if (module_num == 0) {
233e6646167SDoug Evans g_string_append_printf(cmd_line,
234e6646167SDoug Evans " -nic socket,fd=%d,model=" TYPE_NPCM7XX_EMC " "
235e6646167SDoug Evans " -nic user,model=" TYPE_NPCM7XX_EMC " ",
236e6646167SDoug Evans test_sockets[1]);
237e6646167SDoug Evans } else {
238e6646167SDoug Evans g_string_append_printf(cmd_line,
239e6646167SDoug Evans " -nic user,model=" TYPE_NPCM7XX_EMC " "
240e6646167SDoug Evans " -nic socket,fd=%d,model=" TYPE_NPCM7XX_EMC " ",
241e6646167SDoug Evans test_sockets[1]);
242e6646167SDoug Evans }
243e6646167SDoug Evans
244e6646167SDoug Evans g_test_queue_destroy(packet_test_clear, test_sockets);
245e6646167SDoug Evans return test_sockets;
246e6646167SDoug Evans }
247bf3267e7SBin Meng #endif /* _WIN32 */
248e6646167SDoug Evans
emc_read(QTestState * qts,const EMCModule * mod,NPCM7xxPWMRegister regno)249e6646167SDoug Evans static uint32_t emc_read(QTestState *qts, const EMCModule *mod,
250e6646167SDoug Evans NPCM7xxPWMRegister regno)
251e6646167SDoug Evans {
252e6646167SDoug Evans return qtest_readl(qts, mod->base_addr + regno * sizeof(uint32_t));
253e6646167SDoug Evans }
254e6646167SDoug Evans
255bf3267e7SBin Meng #ifndef _WIN32
emc_write(QTestState * qts,const EMCModule * mod,NPCM7xxPWMRegister regno,uint32_t value)256e6646167SDoug Evans static void emc_write(QTestState *qts, const EMCModule *mod,
257e6646167SDoug Evans NPCM7xxPWMRegister regno, uint32_t value)
258e6646167SDoug Evans {
259e6646167SDoug Evans qtest_writel(qts, mod->base_addr + regno * sizeof(uint32_t), value);
260e6646167SDoug Evans }
261e6646167SDoug Evans
emc_read_tx_desc(QTestState * qts,uint32_t addr,NPCM7xxEMCTxDesc * desc)262e6646167SDoug Evans static void emc_read_tx_desc(QTestState *qts, uint32_t addr,
263e6646167SDoug Evans NPCM7xxEMCTxDesc *desc)
264e6646167SDoug Evans {
265e6646167SDoug Evans qtest_memread(qts, addr, desc, sizeof(*desc));
266e6646167SDoug Evans desc->flags = le32_to_cpu(desc->flags);
267e6646167SDoug Evans desc->txbsa = le32_to_cpu(desc->txbsa);
268e6646167SDoug Evans desc->status_and_length = le32_to_cpu(desc->status_and_length);
269e6646167SDoug Evans desc->ntxdsa = le32_to_cpu(desc->ntxdsa);
270e6646167SDoug Evans }
271e6646167SDoug Evans
emc_write_tx_desc(QTestState * qts,const NPCM7xxEMCTxDesc * desc,uint32_t addr)272e6646167SDoug Evans static void emc_write_tx_desc(QTestState *qts, const NPCM7xxEMCTxDesc *desc,
273e6646167SDoug Evans uint32_t addr)
274e6646167SDoug Evans {
275e6646167SDoug Evans NPCM7xxEMCTxDesc le_desc;
276e6646167SDoug Evans
277e6646167SDoug Evans le_desc.flags = cpu_to_le32(desc->flags);
278e6646167SDoug Evans le_desc.txbsa = cpu_to_le32(desc->txbsa);
279e6646167SDoug Evans le_desc.status_and_length = cpu_to_le32(desc->status_and_length);
280e6646167SDoug Evans le_desc.ntxdsa = cpu_to_le32(desc->ntxdsa);
281e6646167SDoug Evans qtest_memwrite(qts, addr, &le_desc, sizeof(le_desc));
282e6646167SDoug Evans }
283e6646167SDoug Evans
emc_read_rx_desc(QTestState * qts,uint32_t addr,NPCM7xxEMCRxDesc * desc)284e6646167SDoug Evans static void emc_read_rx_desc(QTestState *qts, uint32_t addr,
285e6646167SDoug Evans NPCM7xxEMCRxDesc *desc)
286e6646167SDoug Evans {
287e6646167SDoug Evans qtest_memread(qts, addr, desc, sizeof(*desc));
288e6646167SDoug Evans desc->status_and_length = le32_to_cpu(desc->status_and_length);
289e6646167SDoug Evans desc->rxbsa = le32_to_cpu(desc->rxbsa);
290e6646167SDoug Evans desc->reserved = le32_to_cpu(desc->reserved);
291e6646167SDoug Evans desc->nrxdsa = le32_to_cpu(desc->nrxdsa);
292e6646167SDoug Evans }
293e6646167SDoug Evans
emc_write_rx_desc(QTestState * qts,const NPCM7xxEMCRxDesc * desc,uint32_t addr)294e6646167SDoug Evans static void emc_write_rx_desc(QTestState *qts, const NPCM7xxEMCRxDesc *desc,
295e6646167SDoug Evans uint32_t addr)
296e6646167SDoug Evans {
297e6646167SDoug Evans NPCM7xxEMCRxDesc le_desc;
298e6646167SDoug Evans
299e6646167SDoug Evans le_desc.status_and_length = cpu_to_le32(desc->status_and_length);
300e6646167SDoug Evans le_desc.rxbsa = cpu_to_le32(desc->rxbsa);
301e6646167SDoug Evans le_desc.reserved = cpu_to_le32(desc->reserved);
302e6646167SDoug Evans le_desc.nrxdsa = cpu_to_le32(desc->nrxdsa);
303e6646167SDoug Evans qtest_memwrite(qts, addr, &le_desc, sizeof(le_desc));
304e6646167SDoug Evans }
305e6646167SDoug Evans
306e6646167SDoug Evans /*
307e6646167SDoug Evans * Reset the EMC module.
308e6646167SDoug Evans * The module must be reset before, e.g., TXDLSA,RXDLSA are changed.
309e6646167SDoug Evans */
emc_soft_reset(QTestState * qts,const EMCModule * mod)310e6646167SDoug Evans static bool emc_soft_reset(QTestState *qts, const EMCModule *mod)
311e6646167SDoug Evans {
312e6646167SDoug Evans uint32_t val;
313e6646167SDoug Evans uint64_t end_time;
314e6646167SDoug Evans
315e6646167SDoug Evans emc_write(qts, mod, REG_MCMDR, REG_MCMDR_SWR);
316e6646167SDoug Evans
317e6646167SDoug Evans /*
318e6646167SDoug Evans * Wait for device to reset as the linux driver does.
319e6646167SDoug Evans * During reset the AHB reads 0 for all registers. So first wait for
320e6646167SDoug Evans * something that resets to non-zero, and then wait for SWR becoming 0.
321e6646167SDoug Evans */
322e6646167SDoug Evans end_time = g_get_monotonic_time() + TIMEOUT_SECONDS * G_TIME_SPAN_SECOND;
323e6646167SDoug Evans
324e6646167SDoug Evans do {
325e6646167SDoug Evans qtest_clock_step(qts, 100);
326e6646167SDoug Evans val = emc_read(qts, mod, REG_FFTCR);
327e6646167SDoug Evans } while (val == 0 && g_get_monotonic_time() < end_time);
328e6646167SDoug Evans if (val != 0) {
329e6646167SDoug Evans do {
330e6646167SDoug Evans qtest_clock_step(qts, 100);
331e6646167SDoug Evans val = emc_read(qts, mod, REG_MCMDR);
332e6646167SDoug Evans if ((val & REG_MCMDR_SWR) == 0) {
333e6646167SDoug Evans /*
334e6646167SDoug Evans * N.B. The CAMs have been reset here, so macaddr matching of
335e6646167SDoug Evans * incoming packets will not work.
336e6646167SDoug Evans */
337e6646167SDoug Evans return true;
338e6646167SDoug Evans }
339e6646167SDoug Evans } while (g_get_monotonic_time() < end_time);
340e6646167SDoug Evans }
341e6646167SDoug Evans
342e6646167SDoug Evans g_message("%s: Timeout expired", __func__);
343e6646167SDoug Evans return false;
344e6646167SDoug Evans }
345bf3267e7SBin Meng #endif /* _WIN32 */
346e6646167SDoug Evans
347e6646167SDoug Evans /* Check emc registers are reset to default value. */
test_init(gconstpointer test_data)348e6646167SDoug Evans static void test_init(gconstpointer test_data)
349e6646167SDoug Evans {
350e6646167SDoug Evans const TestData *td = test_data;
351e6646167SDoug Evans const EMCModule *mod = td->module;
352e6646167SDoug Evans QTestState *qts = qtest_init("-machine quanta-gsj");
353e6646167SDoug Evans int i;
354e6646167SDoug Evans
355e6646167SDoug Evans #define CHECK_REG(regno, value) \
356e6646167SDoug Evans do { \
357e6646167SDoug Evans g_assert_cmphex(emc_read(qts, mod, (regno)), ==, (value)); \
358e6646167SDoug Evans } while (0)
359e6646167SDoug Evans
360e6646167SDoug Evans CHECK_REG(REG_CAMCMR, 0);
361e6646167SDoug Evans CHECK_REG(REG_CAMEN, 0);
362e6646167SDoug Evans CHECK_REG(REG_TXDLSA, 0xfffffffc);
363e6646167SDoug Evans CHECK_REG(REG_RXDLSA, 0xfffffffc);
364e6646167SDoug Evans CHECK_REG(REG_MCMDR, 0);
365e6646167SDoug Evans CHECK_REG(REG_MIID, 0);
366e6646167SDoug Evans CHECK_REG(REG_MIIDA, 0x00900000);
367e6646167SDoug Evans CHECK_REG(REG_FFTCR, 0x0101);
368e6646167SDoug Evans CHECK_REG(REG_DMARFC, 0x0800);
369e6646167SDoug Evans CHECK_REG(REG_MIEN, 0);
370e6646167SDoug Evans CHECK_REG(REG_MISTA, 0);
371e6646167SDoug Evans CHECK_REG(REG_MGSTA, 0);
372e6646167SDoug Evans CHECK_REG(REG_MPCNT, 0x7fff);
373e6646167SDoug Evans CHECK_REG(REG_MRPC, 0);
374e6646167SDoug Evans CHECK_REG(REG_MRPCC, 0);
375e6646167SDoug Evans CHECK_REG(REG_MREPC, 0);
376e6646167SDoug Evans CHECK_REG(REG_DMARFS, 0);
377e6646167SDoug Evans CHECK_REG(REG_CTXDSA, 0);
378e6646167SDoug Evans CHECK_REG(REG_CTXBSA, 0);
379e6646167SDoug Evans CHECK_REG(REG_CRXDSA, 0);
380e6646167SDoug Evans CHECK_REG(REG_CRXBSA, 0);
381e6646167SDoug Evans
382e6646167SDoug Evans #undef CHECK_REG
383e6646167SDoug Evans
384*d1592cbeSPatrick Venture /* Skip over the MAC address registers, which is BASE+0 */
385*d1592cbeSPatrick Venture for (i = 1; i < NUM_CAMML_REGS; ++i) {
386e6646167SDoug Evans g_assert_cmpuint(emc_read(qts, mod, REG_CAMM_BASE + i * 2), ==,
387e6646167SDoug Evans 0);
388e6646167SDoug Evans g_assert_cmpuint(emc_read(qts, mod, REG_CAML_BASE + i * 2), ==,
389e6646167SDoug Evans 0);
390e6646167SDoug Evans }
391e6646167SDoug Evans
392e6646167SDoug Evans qtest_quit(qts);
393e6646167SDoug Evans }
394e6646167SDoug Evans
395bf3267e7SBin Meng #ifndef _WIN32
emc_wait_irq(QTestState * qts,const EMCModule * mod,int step,bool is_tx)396e6646167SDoug Evans static bool emc_wait_irq(QTestState *qts, const EMCModule *mod, int step,
397e6646167SDoug Evans bool is_tx)
398e6646167SDoug Evans {
399e6646167SDoug Evans uint64_t end_time =
400e6646167SDoug Evans g_get_monotonic_time() + TIMEOUT_SECONDS * G_TIME_SPAN_SECOND;
401e6646167SDoug Evans
402e6646167SDoug Evans do {
403e6646167SDoug Evans if (qtest_get_irq(qts, is_tx ? mod->tx_irq : mod->rx_irq)) {
404e6646167SDoug Evans return true;
405e6646167SDoug Evans }
406e6646167SDoug Evans qtest_clock_step(qts, step);
407e6646167SDoug Evans } while (g_get_monotonic_time() < end_time);
408e6646167SDoug Evans
409e6646167SDoug Evans g_message("%s: Timeout expired", __func__);
410e6646167SDoug Evans return false;
411e6646167SDoug Evans }
412e6646167SDoug Evans
emc_wait_mista(QTestState * qts,const EMCModule * mod,int step,uint32_t flag)413e6646167SDoug Evans static bool emc_wait_mista(QTestState *qts, const EMCModule *mod, int step,
414e6646167SDoug Evans uint32_t flag)
415e6646167SDoug Evans {
416e6646167SDoug Evans uint64_t end_time =
417e6646167SDoug Evans g_get_monotonic_time() + TIMEOUT_SECONDS * G_TIME_SPAN_SECOND;
418e6646167SDoug Evans
419e6646167SDoug Evans do {
420e6646167SDoug Evans uint32_t mista = emc_read(qts, mod, REG_MISTA);
421e6646167SDoug Evans if (mista & flag) {
422e6646167SDoug Evans return true;
423e6646167SDoug Evans }
424e6646167SDoug Evans qtest_clock_step(qts, step);
425e6646167SDoug Evans } while (g_get_monotonic_time() < end_time);
426e6646167SDoug Evans
427e6646167SDoug Evans g_message("%s: Timeout expired", __func__);
428e6646167SDoug Evans return false;
429e6646167SDoug Evans }
430e6646167SDoug Evans
wait_socket_readable(int fd)431e6646167SDoug Evans static bool wait_socket_readable(int fd)
432e6646167SDoug Evans {
433e6646167SDoug Evans fd_set read_fds;
434e6646167SDoug Evans struct timeval tv;
435e6646167SDoug Evans int rv;
436e6646167SDoug Evans
437e6646167SDoug Evans FD_ZERO(&read_fds);
438e6646167SDoug Evans FD_SET(fd, &read_fds);
439e6646167SDoug Evans tv.tv_sec = TIMEOUT_SECONDS;
440e6646167SDoug Evans tv.tv_usec = 0;
441e6646167SDoug Evans rv = select(fd + 1, &read_fds, NULL, NULL, &tv);
442e6646167SDoug Evans if (rv == -1) {
443e6646167SDoug Evans perror("select");
444e6646167SDoug Evans } else if (rv == 0) {
445e6646167SDoug Evans g_message("%s: Timeout expired", __func__);
446e6646167SDoug Evans }
447e6646167SDoug Evans return rv == 1;
448e6646167SDoug Evans }
449e6646167SDoug Evans
450e6646167SDoug Evans /* Initialize *desc (in host endian format). */
init_tx_desc(NPCM7xxEMCTxDesc * desc,size_t count,uint32_t desc_addr)451e6646167SDoug Evans static void init_tx_desc(NPCM7xxEMCTxDesc *desc, size_t count,
452e6646167SDoug Evans uint32_t desc_addr)
453e6646167SDoug Evans {
454e6646167SDoug Evans g_assert(count >= 2);
455e6646167SDoug Evans memset(&desc[0], 0, sizeof(*desc) * count);
456e6646167SDoug Evans /* Leave the last one alone, owned by the cpu -> stops transmission. */
457e6646167SDoug Evans for (size_t i = 0; i < count - 1; ++i) {
458e6646167SDoug Evans desc[i].flags =
459e6646167SDoug Evans (TX_DESC_FLAG_OWNER_MASK | /* owner = 1: emc */
460e6646167SDoug Evans TX_DESC_FLAG_INTEN |
461e6646167SDoug Evans 0 | /* crc append = 0 */
462e6646167SDoug Evans 0 /* padding enable = 0 */);
463e6646167SDoug Evans desc[i].status_and_length =
464e6646167SDoug Evans (0 | /* collision count = 0 */
465e6646167SDoug Evans 0 | /* SQE = 0 */
466e6646167SDoug Evans 0 | /* PAU = 0 */
467e6646167SDoug Evans 0 | /* TXHA = 0 */
468e6646167SDoug Evans 0 | /* LC = 0 */
469e6646167SDoug Evans 0 | /* TXABT = 0 */
470e6646167SDoug Evans 0 | /* NCS = 0 */
471e6646167SDoug Evans 0 | /* EXDEF = 0 */
472e6646167SDoug Evans 0 | /* TXCP = 0 */
473e6646167SDoug Evans 0 | /* DEF = 0 */
474e6646167SDoug Evans 0 | /* TXINTR = 0 */
475e6646167SDoug Evans 0 /* length filled in later */);
476e6646167SDoug Evans desc[i].ntxdsa = desc_addr + (i + 1) * sizeof(*desc);
477e6646167SDoug Evans }
478e6646167SDoug Evans }
479e6646167SDoug Evans
enable_tx(QTestState * qts,const EMCModule * mod,const NPCM7xxEMCTxDesc * desc,size_t count,uint32_t desc_addr,uint32_t mien_flags)480e6646167SDoug Evans static void enable_tx(QTestState *qts, const EMCModule *mod,
481e6646167SDoug Evans const NPCM7xxEMCTxDesc *desc, size_t count,
482e6646167SDoug Evans uint32_t desc_addr, uint32_t mien_flags)
483e6646167SDoug Evans {
484e6646167SDoug Evans /* Write the descriptors to guest memory. */
485e6646167SDoug Evans for (size_t i = 0; i < count; ++i) {
486e6646167SDoug Evans emc_write_tx_desc(qts, desc + i, desc_addr + i * sizeof(*desc));
487e6646167SDoug Evans }
488e6646167SDoug Evans
489e6646167SDoug Evans /* Trigger sending the packet. */
490e6646167SDoug Evans /* The module must be reset before changing TXDLSA. */
491e6646167SDoug Evans g_assert(emc_soft_reset(qts, mod));
492e6646167SDoug Evans emc_write(qts, mod, REG_TXDLSA, desc_addr);
493e6646167SDoug Evans emc_write(qts, mod, REG_CTXDSA, ~0);
494e6646167SDoug Evans emc_write(qts, mod, REG_MIEN, REG_MIEN_ENTXCP | mien_flags);
495e6646167SDoug Evans {
496e6646167SDoug Evans uint32_t mcmdr = emc_read(qts, mod, REG_MCMDR);
497e6646167SDoug Evans mcmdr |= REG_MCMDR_TXON;
498e6646167SDoug Evans emc_write(qts, mod, REG_MCMDR, mcmdr);
499e6646167SDoug Evans }
500e6646167SDoug Evans }
501e6646167SDoug Evans
emc_send_verify1(QTestState * qts,const EMCModule * mod,int fd,bool with_irq,uint32_t desc_addr,uint32_t next_desc_addr,const char * test_data,int test_size)502e6646167SDoug Evans static void emc_send_verify1(QTestState *qts, const EMCModule *mod, int fd,
503e6646167SDoug Evans bool with_irq, uint32_t desc_addr,
504e6646167SDoug Evans uint32_t next_desc_addr,
505e6646167SDoug Evans const char *test_data, int test_size)
506e6646167SDoug Evans {
507e6646167SDoug Evans NPCM7xxEMCTxDesc result_desc;
508e6646167SDoug Evans uint32_t expected_mask, expected_value, recv_len;
509e6646167SDoug Evans int ret;
510e6646167SDoug Evans char buffer[TX_DATA_LEN];
511e6646167SDoug Evans
512e6646167SDoug Evans g_assert(wait_socket_readable(fd));
513e6646167SDoug Evans
514e6646167SDoug Evans /* Read the descriptor back. */
515e6646167SDoug Evans emc_read_tx_desc(qts, desc_addr, &result_desc);
516e6646167SDoug Evans /* Descriptor should be owned by cpu now. */
517e6646167SDoug Evans g_assert((result_desc.flags & TX_DESC_FLAG_OWNER_MASK) == 0);
518e6646167SDoug Evans /* Test the status bits, ignoring the length field. */
519e6646167SDoug Evans expected_mask = 0xffff << 16;
520e6646167SDoug Evans expected_value = TX_DESC_STATUS_TXCP;
521e6646167SDoug Evans if (with_irq) {
522e6646167SDoug Evans expected_value |= TX_DESC_STATUS_TXINTR;
523e6646167SDoug Evans }
524e6646167SDoug Evans g_assert_cmphex((result_desc.status_and_length & expected_mask), ==,
525e6646167SDoug Evans expected_value);
526e6646167SDoug Evans
527e6646167SDoug Evans /* Check data sent to the backend. */
528e6646167SDoug Evans recv_len = ~0;
529e7b79428SMarc-André Lureau ret = recv(fd, &recv_len, sizeof(recv_len), MSG_DONTWAIT);
530e6646167SDoug Evans g_assert_cmpint(ret, == , sizeof(recv_len));
531e6646167SDoug Evans
532e6646167SDoug Evans g_assert(wait_socket_readable(fd));
533e6646167SDoug Evans memset(buffer, 0xff, sizeof(buffer));
534e7b79428SMarc-André Lureau ret = recv(fd, buffer, test_size, MSG_DONTWAIT);
535e6646167SDoug Evans g_assert_cmpmem(buffer, ret, test_data, test_size);
536e6646167SDoug Evans }
537e6646167SDoug Evans
emc_send_verify(QTestState * qts,const EMCModule * mod,int fd,bool with_irq)538e6646167SDoug Evans static void emc_send_verify(QTestState *qts, const EMCModule *mod, int fd,
539e6646167SDoug Evans bool with_irq)
540e6646167SDoug Evans {
541e6646167SDoug Evans NPCM7xxEMCTxDesc desc[NUM_TX_DESCRIPTORS];
542e6646167SDoug Evans uint32_t desc_addr = DESC_ADDR;
543e6646167SDoug Evans static const char test1_data[] = "TEST1";
544e6646167SDoug Evans static const char test2_data[] = "Testing 1 2 3 ...";
545e6646167SDoug Evans uint32_t data1_addr = DATA_ADDR;
546e6646167SDoug Evans uint32_t data2_addr = data1_addr + sizeof(test1_data);
547e6646167SDoug Evans bool got_tdu;
548e6646167SDoug Evans uint32_t end_desc_addr;
549e6646167SDoug Evans
550e6646167SDoug Evans /* Prepare test data buffer. */
551e6646167SDoug Evans qtest_memwrite(qts, data1_addr, test1_data, sizeof(test1_data));
552e6646167SDoug Evans qtest_memwrite(qts, data2_addr, test2_data, sizeof(test2_data));
553e6646167SDoug Evans
554e6646167SDoug Evans init_tx_desc(&desc[0], NUM_TX_DESCRIPTORS, desc_addr);
555e6646167SDoug Evans desc[0].txbsa = data1_addr;
556e6646167SDoug Evans desc[0].status_and_length |= sizeof(test1_data);
557e6646167SDoug Evans desc[1].txbsa = data2_addr;
558e6646167SDoug Evans desc[1].status_and_length |= sizeof(test2_data);
559e6646167SDoug Evans
560e6646167SDoug Evans enable_tx(qts, mod, &desc[0], NUM_TX_DESCRIPTORS, desc_addr,
561e6646167SDoug Evans with_irq ? REG_MIEN_ENTXINTR : 0);
562e6646167SDoug Evans
563a62ee00aSDoug Evans /* Prod the device to send the packet. */
564a62ee00aSDoug Evans emc_write(qts, mod, REG_TSDR, 1);
565a62ee00aSDoug Evans
566e6646167SDoug Evans /*
567e6646167SDoug Evans * It's problematic to observe the interrupt for each packet.
568e6646167SDoug Evans * Instead just wait until all the packets go out.
569e6646167SDoug Evans */
570e6646167SDoug Evans got_tdu = false;
571e6646167SDoug Evans while (!got_tdu) {
572e6646167SDoug Evans if (with_irq) {
573e6646167SDoug Evans g_assert_true(emc_wait_irq(qts, mod, TX_STEP_COUNT,
574e6646167SDoug Evans /*is_tx=*/true));
575e6646167SDoug Evans } else {
576e6646167SDoug Evans g_assert_true(emc_wait_mista(qts, mod, TX_STEP_COUNT,
577e6646167SDoug Evans REG_MISTA_TXINTR));
578e6646167SDoug Evans }
579e6646167SDoug Evans got_tdu = !!(emc_read(qts, mod, REG_MISTA) & REG_MISTA_TDU);
580e6646167SDoug Evans /* If we don't have TDU yet, reset the interrupt. */
581e6646167SDoug Evans if (!got_tdu) {
582e6646167SDoug Evans emc_write(qts, mod, REG_MISTA,
583e6646167SDoug Evans emc_read(qts, mod, REG_MISTA) & 0xffff0000);
584e6646167SDoug Evans }
585e6646167SDoug Evans }
586e6646167SDoug Evans
587e6646167SDoug Evans end_desc_addr = desc_addr + 2 * sizeof(desc[0]);
588e6646167SDoug Evans g_assert_cmphex(emc_read(qts, mod, REG_CTXDSA), ==, end_desc_addr);
589e6646167SDoug Evans g_assert_cmphex(emc_read(qts, mod, REG_MISTA), ==,
590e6646167SDoug Evans REG_MISTA_TXCP | REG_MISTA_TXINTR | REG_MISTA_TDU);
591e6646167SDoug Evans
592e6646167SDoug Evans emc_send_verify1(qts, mod, fd, with_irq,
593e6646167SDoug Evans desc_addr, end_desc_addr,
594e6646167SDoug Evans test1_data, sizeof(test1_data));
595e6646167SDoug Evans emc_send_verify1(qts, mod, fd, with_irq,
596e6646167SDoug Evans desc_addr + sizeof(desc[0]), end_desc_addr,
597e6646167SDoug Evans test2_data, sizeof(test2_data));
598e6646167SDoug Evans }
599e6646167SDoug Evans
600e6646167SDoug Evans /* Initialize *desc (in host endian format). */
init_rx_desc(NPCM7xxEMCRxDesc * desc,size_t count,uint32_t desc_addr,uint32_t data_addr)601e6646167SDoug Evans static void init_rx_desc(NPCM7xxEMCRxDesc *desc, size_t count,
602e6646167SDoug Evans uint32_t desc_addr, uint32_t data_addr)
603e6646167SDoug Evans {
604e6646167SDoug Evans g_assert_true(count >= 2);
605e6646167SDoug Evans memset(desc, 0, sizeof(*desc) * count);
606e6646167SDoug Evans desc[0].rxbsa = data_addr;
607e6646167SDoug Evans desc[0].status_and_length =
608e6646167SDoug Evans (0b10 << RX_DESC_STATUS_OWNER_SHIFT | /* owner = 10: emc */
609e6646167SDoug Evans 0 | /* RP = 0 */
610e6646167SDoug Evans 0 | /* ALIE = 0 */
611e6646167SDoug Evans 0 | /* RXGD = 0 */
612e6646167SDoug Evans 0 | /* PTLE = 0 */
613e6646167SDoug Evans 0 | /* CRCE = 0 */
614e6646167SDoug Evans 0 | /* RXINTR = 0 */
615e6646167SDoug Evans 0 /* length (filled in later) */);
616e6646167SDoug Evans /* Leave the last one alone, owned by the cpu -> stops transmission. */
617e6646167SDoug Evans desc[0].nrxdsa = desc_addr + sizeof(*desc);
618e6646167SDoug Evans }
619e6646167SDoug Evans
enable_rx(QTestState * qts,const EMCModule * mod,const NPCM7xxEMCRxDesc * desc,size_t count,uint32_t desc_addr,uint32_t mien_flags,uint32_t mcmdr_flags)620e6646167SDoug Evans static void enable_rx(QTestState *qts, const EMCModule *mod,
621e6646167SDoug Evans const NPCM7xxEMCRxDesc *desc, size_t count,
622e6646167SDoug Evans uint32_t desc_addr, uint32_t mien_flags,
623e6646167SDoug Evans uint32_t mcmdr_flags)
624e6646167SDoug Evans {
625e6646167SDoug Evans /*
626e6646167SDoug Evans * Write the descriptor to guest memory.
627e6646167SDoug Evans * FWIW, IWBN if the docs said the buffer needs to be at least DMARFC
628e6646167SDoug Evans * bytes.
629e6646167SDoug Evans */
630e6646167SDoug Evans for (size_t i = 0; i < count; ++i) {
631e6646167SDoug Evans emc_write_rx_desc(qts, desc + i, desc_addr + i * sizeof(*desc));
632e6646167SDoug Evans }
633e6646167SDoug Evans
634e6646167SDoug Evans /* Trigger receiving the packet. */
635e6646167SDoug Evans /* The module must be reset before changing RXDLSA. */
636e6646167SDoug Evans g_assert(emc_soft_reset(qts, mod));
637e6646167SDoug Evans emc_write(qts, mod, REG_RXDLSA, desc_addr);
638e6646167SDoug Evans emc_write(qts, mod, REG_MIEN, REG_MIEN_ENRXGD | mien_flags);
639e6646167SDoug Evans
640e6646167SDoug Evans /*
641e6646167SDoug Evans * We don't know what the device's macaddr is, so just accept all
642e6646167SDoug Evans * unicast packets (AUP).
643e6646167SDoug Evans */
644e6646167SDoug Evans emc_write(qts, mod, REG_CAMCMR, REG_CAMCMR_AUP);
645e6646167SDoug Evans emc_write(qts, mod, REG_CAMEN, 1 << 0);
646e6646167SDoug Evans {
647e6646167SDoug Evans uint32_t mcmdr = emc_read(qts, mod, REG_MCMDR);
648e6646167SDoug Evans mcmdr |= REG_MCMDR_RXON | mcmdr_flags;
649e6646167SDoug Evans emc_write(qts, mod, REG_MCMDR, mcmdr);
650e6646167SDoug Evans }
651e6646167SDoug Evans }
652e6646167SDoug Evans
emc_recv_verify(QTestState * qts,const EMCModule * mod,int fd,bool with_irq,bool pump_rsdr)653e6646167SDoug Evans static void emc_recv_verify(QTestState *qts, const EMCModule *mod, int fd,
654a62ee00aSDoug Evans bool with_irq, bool pump_rsdr)
655e6646167SDoug Evans {
656e6646167SDoug Evans NPCM7xxEMCRxDesc desc[NUM_RX_DESCRIPTORS];
657e6646167SDoug Evans uint32_t desc_addr = DESC_ADDR;
658e6646167SDoug Evans uint32_t data_addr = DATA_ADDR;
659e6646167SDoug Evans int ret;
660e6646167SDoug Evans uint32_t expected_mask, expected_value;
661e6646167SDoug Evans NPCM7xxEMCRxDesc result_desc;
662e6646167SDoug Evans
663e6646167SDoug Evans /* Prepare test data buffer. */
664e6646167SDoug Evans const char test[RX_DATA_LEN] = "TEST";
665e6646167SDoug Evans int len = htonl(sizeof(test));
666e6646167SDoug Evans const struct iovec iov[] = {
667e6646167SDoug Evans {
668e6646167SDoug Evans .iov_base = &len,
669e6646167SDoug Evans .iov_len = sizeof(len),
670e6646167SDoug Evans },{
671e6646167SDoug Evans .iov_base = (char *) test,
672e6646167SDoug Evans .iov_len = sizeof(test),
673e6646167SDoug Evans },
674e6646167SDoug Evans };
675e6646167SDoug Evans
676e6646167SDoug Evans /*
677e6646167SDoug Evans * Reset the device BEFORE sending a test packet, otherwise the packet
678e6646167SDoug Evans * may get swallowed by an active device of an earlier test.
679e6646167SDoug Evans */
680e6646167SDoug Evans init_rx_desc(&desc[0], NUM_RX_DESCRIPTORS, desc_addr, data_addr);
681e6646167SDoug Evans enable_rx(qts, mod, &desc[0], NUM_RX_DESCRIPTORS, desc_addr,
682e6646167SDoug Evans with_irq ? REG_MIEN_ENRXINTR : 0, 0);
683e6646167SDoug Evans
684a62ee00aSDoug Evans /*
685a62ee00aSDoug Evans * If requested, prod the device to accept a packet.
686a62ee00aSDoug Evans * This isn't necessary, the linux driver doesn't do this.
687a62ee00aSDoug Evans * Test doing/not-doing this for robustness.
688a62ee00aSDoug Evans */
689a62ee00aSDoug Evans if (pump_rsdr) {
690a62ee00aSDoug Evans emc_write(qts, mod, REG_RSDR, 1);
691a62ee00aSDoug Evans }
692a62ee00aSDoug Evans
693e6646167SDoug Evans /* Send test packet to device's socket. */
694e6646167SDoug Evans ret = iov_send(fd, iov, 2, 0, sizeof(len) + sizeof(test));
695e6646167SDoug Evans g_assert_cmpint(ret, == , sizeof(test) + sizeof(len));
696e6646167SDoug Evans
697e6646167SDoug Evans /* Wait for RX interrupt. */
698e6646167SDoug Evans if (with_irq) {
699e6646167SDoug Evans g_assert_true(emc_wait_irq(qts, mod, RX_STEP_COUNT, /*is_tx=*/false));
700e6646167SDoug Evans } else {
701e6646167SDoug Evans g_assert_true(emc_wait_mista(qts, mod, RX_STEP_COUNT, REG_MISTA_RXGD));
702e6646167SDoug Evans }
703e6646167SDoug Evans
704e6646167SDoug Evans g_assert_cmphex(emc_read(qts, mod, REG_CRXDSA), ==,
705e6646167SDoug Evans desc_addr + sizeof(desc[0]));
706e6646167SDoug Evans
707e6646167SDoug Evans expected_mask = 0xffff;
708e6646167SDoug Evans expected_value = (REG_MISTA_DENI |
709e6646167SDoug Evans REG_MISTA_RXGD |
710e6646167SDoug Evans REG_MISTA_RXINTR);
711e6646167SDoug Evans g_assert_cmphex((emc_read(qts, mod, REG_MISTA) & expected_mask),
712e6646167SDoug Evans ==, expected_value);
713e6646167SDoug Evans
714e6646167SDoug Evans /* Read the descriptor back. */
715e6646167SDoug Evans emc_read_rx_desc(qts, desc_addr, &result_desc);
716e6646167SDoug Evans /* Descriptor should be owned by cpu now. */
717e6646167SDoug Evans g_assert((result_desc.status_and_length & RX_DESC_STATUS_OWNER_MASK) == 0);
718e6646167SDoug Evans /* Test the status bits, ignoring the length field. */
719e6646167SDoug Evans expected_mask = 0xffff << 16;
720e6646167SDoug Evans expected_value = RX_DESC_STATUS_RXGD;
721e6646167SDoug Evans if (with_irq) {
722e6646167SDoug Evans expected_value |= RX_DESC_STATUS_RXINTR;
723e6646167SDoug Evans }
724e6646167SDoug Evans g_assert_cmphex((result_desc.status_and_length & expected_mask), ==,
725e6646167SDoug Evans expected_value);
726e6646167SDoug Evans g_assert_cmpint(RX_DESC_PKT_LEN(result_desc.status_and_length), ==,
727e6646167SDoug Evans RX_DATA_LEN + CRC_LENGTH);
728e6646167SDoug Evans
729e6646167SDoug Evans {
730e6646167SDoug Evans char buffer[RX_DATA_LEN];
731e6646167SDoug Evans qtest_memread(qts, data_addr, buffer, sizeof(buffer));
732e6646167SDoug Evans g_assert_cmpstr(buffer, == , "TEST");
733e6646167SDoug Evans }
734e6646167SDoug Evans }
735e6646167SDoug Evans
emc_test_ptle(QTestState * qts,const EMCModule * mod,int fd)736e6646167SDoug Evans static void emc_test_ptle(QTestState *qts, const EMCModule *mod, int fd)
737e6646167SDoug Evans {
738e6646167SDoug Evans NPCM7xxEMCRxDesc desc[NUM_RX_DESCRIPTORS];
739e6646167SDoug Evans uint32_t desc_addr = DESC_ADDR;
740e6646167SDoug Evans uint32_t data_addr = DATA_ADDR;
741e6646167SDoug Evans int ret;
742e6646167SDoug Evans NPCM7xxEMCRxDesc result_desc;
743e6646167SDoug Evans uint32_t expected_mask, expected_value;
744e6646167SDoug Evans
745e6646167SDoug Evans /* Prepare test data buffer. */
746e6646167SDoug Evans #define PTLE_DATA_LEN 1600
747e6646167SDoug Evans char test_data[PTLE_DATA_LEN];
748e6646167SDoug Evans int len = htonl(sizeof(test_data));
749e6646167SDoug Evans const struct iovec iov[] = {
750e6646167SDoug Evans {
751e6646167SDoug Evans .iov_base = &len,
752e6646167SDoug Evans .iov_len = sizeof(len),
753e6646167SDoug Evans },{
754e6646167SDoug Evans .iov_base = (char *) test_data,
755e6646167SDoug Evans .iov_len = sizeof(test_data),
756e6646167SDoug Evans },
757e6646167SDoug Evans };
758e6646167SDoug Evans memset(test_data, 42, sizeof(test_data));
759e6646167SDoug Evans
760e6646167SDoug Evans /*
761e6646167SDoug Evans * Reset the device BEFORE sending a test packet, otherwise the packet
762e6646167SDoug Evans * may get swallowed by an active device of an earlier test.
763e6646167SDoug Evans */
764e6646167SDoug Evans init_rx_desc(&desc[0], NUM_RX_DESCRIPTORS, desc_addr, data_addr);
765e6646167SDoug Evans enable_rx(qts, mod, &desc[0], NUM_RX_DESCRIPTORS, desc_addr,
766e6646167SDoug Evans REG_MIEN_ENRXINTR, REG_MCMDR_ALP);
767e6646167SDoug Evans
768e6646167SDoug Evans /* Send test packet to device's socket. */
769e6646167SDoug Evans ret = iov_send(fd, iov, 2, 0, sizeof(len) + sizeof(test_data));
770e6646167SDoug Evans g_assert_cmpint(ret, == , sizeof(test_data) + sizeof(len));
771e6646167SDoug Evans
772e6646167SDoug Evans /* Wait for RX interrupt. */
773e6646167SDoug Evans g_assert_true(emc_wait_irq(qts, mod, RX_STEP_COUNT, /*is_tx=*/false));
774e6646167SDoug Evans
775e6646167SDoug Evans /* Read the descriptor back. */
776e6646167SDoug Evans emc_read_rx_desc(qts, desc_addr, &result_desc);
777e6646167SDoug Evans /* Descriptor should be owned by cpu now. */
778e6646167SDoug Evans g_assert((result_desc.status_and_length & RX_DESC_STATUS_OWNER_MASK) == 0);
779e6646167SDoug Evans /* Test the status bits, ignoring the length field. */
780e6646167SDoug Evans expected_mask = 0xffff << 16;
781e6646167SDoug Evans expected_value = (RX_DESC_STATUS_RXGD |
782e6646167SDoug Evans RX_DESC_STATUS_PTLE |
783e6646167SDoug Evans RX_DESC_STATUS_RXINTR);
784e6646167SDoug Evans g_assert_cmphex((result_desc.status_and_length & expected_mask), ==,
785e6646167SDoug Evans expected_value);
786e6646167SDoug Evans g_assert_cmpint(RX_DESC_PKT_LEN(result_desc.status_and_length), ==,
787e6646167SDoug Evans PTLE_DATA_LEN + CRC_LENGTH);
788e6646167SDoug Evans
789e6646167SDoug Evans {
790e6646167SDoug Evans char buffer[PTLE_DATA_LEN];
791e6646167SDoug Evans qtest_memread(qts, data_addr, buffer, sizeof(buffer));
792e6646167SDoug Evans g_assert(memcmp(buffer, test_data, PTLE_DATA_LEN) == 0);
793e6646167SDoug Evans }
794e6646167SDoug Evans }
795e6646167SDoug Evans
test_tx(gconstpointer test_data)796e6646167SDoug Evans static void test_tx(gconstpointer test_data)
797e6646167SDoug Evans {
798e6646167SDoug Evans const TestData *td = test_data;
799e6646167SDoug Evans GString *cmd_line = g_string_new("-machine quanta-gsj");
800e6646167SDoug Evans int *test_sockets = packet_test_init(emc_module_index(td->module),
801e6646167SDoug Evans cmd_line);
802e6646167SDoug Evans QTestState *qts = qtest_init(cmd_line->str);
803e6646167SDoug Evans
804e6646167SDoug Evans /*
805e6646167SDoug Evans * TODO: For pedantic correctness test_sockets[0] should be closed after
806e6646167SDoug Evans * the fork and before the exec, but that will require some harness
807e6646167SDoug Evans * improvements.
808e6646167SDoug Evans */
809e6646167SDoug Evans close(test_sockets[1]);
810e6646167SDoug Evans /* Defensive programming */
811e6646167SDoug Evans test_sockets[1] = -1;
812e6646167SDoug Evans
813e6646167SDoug Evans qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
814e6646167SDoug Evans
815e6646167SDoug Evans emc_send_verify(qts, td->module, test_sockets[0], /*with_irq=*/false);
816e6646167SDoug Evans emc_send_verify(qts, td->module, test_sockets[0], /*with_irq=*/true);
817e6646167SDoug Evans
818e6646167SDoug Evans qtest_quit(qts);
819e6646167SDoug Evans }
820e6646167SDoug Evans
test_rx(gconstpointer test_data)821e6646167SDoug Evans static void test_rx(gconstpointer test_data)
822e6646167SDoug Evans {
823e6646167SDoug Evans const TestData *td = test_data;
824e6646167SDoug Evans GString *cmd_line = g_string_new("-machine quanta-gsj");
825e6646167SDoug Evans int *test_sockets = packet_test_init(emc_module_index(td->module),
826e6646167SDoug Evans cmd_line);
827e6646167SDoug Evans QTestState *qts = qtest_init(cmd_line->str);
828e6646167SDoug Evans
829e6646167SDoug Evans /*
830e6646167SDoug Evans * TODO: For pedantic correctness test_sockets[0] should be closed after
831e6646167SDoug Evans * the fork and before the exec, but that will require some harness
832e6646167SDoug Evans * improvements.
833e6646167SDoug Evans */
834e6646167SDoug Evans close(test_sockets[1]);
835e6646167SDoug Evans /* Defensive programming */
836e6646167SDoug Evans test_sockets[1] = -1;
837e6646167SDoug Evans
838e6646167SDoug Evans qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
839e6646167SDoug Evans
840a62ee00aSDoug Evans emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=*/false,
841a62ee00aSDoug Evans /*pump_rsdr=*/false);
842a62ee00aSDoug Evans emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=*/false,
843a62ee00aSDoug Evans /*pump_rsdr=*/true);
844a62ee00aSDoug Evans emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=*/true,
845a62ee00aSDoug Evans /*pump_rsdr=*/false);
846a62ee00aSDoug Evans emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=*/true,
847a62ee00aSDoug Evans /*pump_rsdr=*/true);
848e6646167SDoug Evans emc_test_ptle(qts, td->module, test_sockets[0]);
849e6646167SDoug Evans
850e6646167SDoug Evans qtest_quit(qts);
851e6646167SDoug Evans }
852bf3267e7SBin Meng #endif /* _WIN32 */
853e6646167SDoug Evans
emc_add_test(const char * name,const TestData * td,GTestDataFunc fn)854e6646167SDoug Evans static void emc_add_test(const char *name, const TestData* td,
855e6646167SDoug Evans GTestDataFunc fn)
856e6646167SDoug Evans {
857e6646167SDoug Evans g_autofree char *full_name = g_strdup_printf(
858e6646167SDoug Evans "npcm7xx_emc/emc[%d]/%s", emc_module_index(td->module), name);
859e6646167SDoug Evans qtest_add_data_func(full_name, td, fn);
860e6646167SDoug Evans }
861e6646167SDoug Evans #define add_test(name, td) emc_add_test(#name, td, test_##name)
862e6646167SDoug Evans
main(int argc,char ** argv)863e6646167SDoug Evans int main(int argc, char **argv)
864e6646167SDoug Evans {
865e6646167SDoug Evans TestData test_data_list[ARRAY_SIZE(emc_module_list)];
866e6646167SDoug Evans
867e6646167SDoug Evans g_test_init(&argc, &argv, NULL);
868e6646167SDoug Evans
869e6646167SDoug Evans for (int i = 0; i < ARRAY_SIZE(emc_module_list); ++i) {
870e6646167SDoug Evans TestData *td = &test_data_list[i];
871e6646167SDoug Evans
872e6646167SDoug Evans td->module = &emc_module_list[i];
873e6646167SDoug Evans
874e6646167SDoug Evans add_test(init, td);
875bf3267e7SBin Meng #ifndef _WIN32
876e6646167SDoug Evans add_test(tx, td);
877e6646167SDoug Evans add_test(rx, td);
878bf3267e7SBin Meng #endif
879e6646167SDoug Evans }
880e6646167SDoug Evans
881e6646167SDoug Evans return g_test_run();
882e6646167SDoug Evans }
883