1 /* 2 * libqos driver framework 3 * 4 * Copyright (c) 2018 Emanuele Giuseppe Esposito <e.emanuelegiuseppe@gmail.com> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License version 2.1 as published by the Free Software Foundation. 9 * 10 * This library is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * Lesser General Public License for more details. 14 * 15 * You should have received a copy of the GNU Lesser General Public 16 * License along with this library; if not, see <http://www.gnu.org/licenses/> 17 */ 18 19 #include "qemu/osdep.h" 20 #include "hw/net/e1000_regs.h" 21 #include "hw/pci/pci_ids.h" 22 #include "../libqtest.h" 23 #include "pci-pc.h" 24 #include "qemu/sockets.h" 25 #include "qemu/iov.h" 26 #include "qemu/module.h" 27 #include "qemu/bitops.h" 28 #include "libqos-malloc.h" 29 #include "qgraph.h" 30 #include "e1000e.h" 31 32 #define E1000E_IVAR_TEST_CFG \ 33 (((E1000E_RX0_MSG_ID | E1000_IVAR_INT_ALLOC_VALID) << E1000_IVAR_RXQ0_SHIFT) | \ 34 ((E1000E_TX0_MSG_ID | E1000_IVAR_INT_ALLOC_VALID) << E1000_IVAR_TXQ0_SHIFT) | \ 35 E1000_IVAR_TX_INT_EVERY_WB) 36 37 #define E1000E_RING_LEN (0x1000) 38 39 static void e1000e_macreg_write(QE1000E *d, uint32_t reg, uint32_t val) 40 { 41 QE1000E_PCI *d_pci = container_of(d, QE1000E_PCI, e1000e); 42 qpci_io_writel(&d_pci->pci_dev, d_pci->mac_regs, reg, val); 43 } 44 45 static uint32_t e1000e_macreg_read(QE1000E *d, uint32_t reg) 46 { 47 QE1000E_PCI *d_pci = container_of(d, QE1000E_PCI, e1000e); 48 return qpci_io_readl(&d_pci->pci_dev, d_pci->mac_regs, reg); 49 } 50 51 void e1000e_tx_ring_push(QE1000E *d, void *descr) 52 { 53 QE1000E_PCI *d_pci = container_of(d, QE1000E_PCI, e1000e); 54 uint32_t tail = e1000e_macreg_read(d, E1000_TDT); 55 uint32_t len = e1000e_macreg_read(d, E1000_TDLEN) / E1000_RING_DESC_LEN; 56 57 qtest_memwrite(d_pci->pci_dev.bus->qts, 58 d->tx_ring + tail * E1000_RING_DESC_LEN, 59 descr, E1000_RING_DESC_LEN); 60 e1000e_macreg_write(d, E1000_TDT, (tail + 1) % len); 61 62 /* Read WB data for the packet transmitted */ 63 qtest_memread(d_pci->pci_dev.bus->qts, 64 d->tx_ring + tail * E1000_RING_DESC_LEN, 65 descr, E1000_RING_DESC_LEN); 66 } 67 68 void e1000e_rx_ring_push(QE1000E *d, void *descr) 69 { 70 QE1000E_PCI *d_pci = container_of(d, QE1000E_PCI, e1000e); 71 uint32_t tail = e1000e_macreg_read(d, E1000_RDT); 72 uint32_t len = e1000e_macreg_read(d, E1000_RDLEN) / E1000_RING_DESC_LEN; 73 74 qtest_memwrite(d_pci->pci_dev.bus->qts, 75 d->rx_ring + tail * E1000_RING_DESC_LEN, 76 descr, E1000_RING_DESC_LEN); 77 e1000e_macreg_write(d, E1000_RDT, (tail + 1) % len); 78 79 /* Read WB data for the packet received */ 80 qtest_memread(d_pci->pci_dev.bus->qts, 81 d->rx_ring + tail * E1000_RING_DESC_LEN, 82 descr, E1000_RING_DESC_LEN); 83 } 84 85 static void e1000e_foreach_callback(QPCIDevice *dev, int devfn, void *data) 86 { 87 QPCIDevice *res = data; 88 memcpy(res, dev, sizeof(QPCIDevice)); 89 g_free(dev); 90 } 91 92 void e1000e_wait_isr(QE1000E *d, uint16_t msg_id) 93 { 94 QE1000E_PCI *d_pci = container_of(d, QE1000E_PCI, e1000e); 95 guint64 end_time = g_get_monotonic_time() + 5 * G_TIME_SPAN_SECOND; 96 97 do { 98 if (qpci_msix_pending(&d_pci->pci_dev, msg_id)) { 99 return; 100 } 101 qtest_clock_step(d_pci->pci_dev.bus->qts, 10000); 102 } while (g_get_monotonic_time() < end_time); 103 104 g_error("Timeout expired"); 105 } 106 107 static void e1000e_pci_destructor(QOSGraphObject *obj) 108 { 109 QE1000E_PCI *epci = (QE1000E_PCI *) obj; 110 qpci_iounmap(&epci->pci_dev, epci->mac_regs); 111 qpci_msix_disable(&epci->pci_dev); 112 } 113 114 static void e1000e_pci_start_hw(QOSGraphObject *obj) 115 { 116 QE1000E_PCI *d = (QE1000E_PCI *) obj; 117 uint32_t val; 118 119 /* Enable the device */ 120 qpci_device_enable(&d->pci_dev); 121 122 /* Reset the device */ 123 val = e1000e_macreg_read(&d->e1000e, E1000_CTRL); 124 e1000e_macreg_write(&d->e1000e, E1000_CTRL, val | E1000_CTRL_RST | E1000_CTRL_SLU); 125 126 /* Enable and configure MSI-X */ 127 qpci_msix_enable(&d->pci_dev); 128 e1000e_macreg_write(&d->e1000e, E1000_IVAR, E1000E_IVAR_TEST_CFG); 129 130 /* Check the device status - link and speed */ 131 val = e1000e_macreg_read(&d->e1000e, E1000_STATUS); 132 g_assert_cmphex(val & (E1000_STATUS_LU | E1000_STATUS_ASDV_1000), 133 ==, E1000_STATUS_LU | E1000_STATUS_ASDV_1000); 134 135 /* Initialize TX/RX logic */ 136 e1000e_macreg_write(&d->e1000e, E1000_RCTL, 0); 137 e1000e_macreg_write(&d->e1000e, E1000_TCTL, 0); 138 139 /* Notify the device that the driver is ready */ 140 val = e1000e_macreg_read(&d->e1000e, E1000_CTRL_EXT); 141 e1000e_macreg_write(&d->e1000e, E1000_CTRL_EXT, 142 val | E1000_CTRL_EXT_DRV_LOAD); 143 144 e1000e_macreg_write(&d->e1000e, E1000_TDBAL, 145 (uint32_t) d->e1000e.tx_ring); 146 e1000e_macreg_write(&d->e1000e, E1000_TDBAH, 147 (uint32_t) (d->e1000e.tx_ring >> 32)); 148 e1000e_macreg_write(&d->e1000e, E1000_TDLEN, E1000E_RING_LEN); 149 e1000e_macreg_write(&d->e1000e, E1000_TDT, 0); 150 e1000e_macreg_write(&d->e1000e, E1000_TDH, 0); 151 152 /* Enable transmit */ 153 e1000e_macreg_write(&d->e1000e, E1000_TCTL, E1000_TCTL_EN); 154 155 e1000e_macreg_write(&d->e1000e, E1000_RDBAL, 156 (uint32_t)d->e1000e.rx_ring); 157 e1000e_macreg_write(&d->e1000e, E1000_RDBAH, 158 (uint32_t)(d->e1000e.rx_ring >> 32)); 159 e1000e_macreg_write(&d->e1000e, E1000_RDLEN, E1000E_RING_LEN); 160 e1000e_macreg_write(&d->e1000e, E1000_RDT, 0); 161 e1000e_macreg_write(&d->e1000e, E1000_RDH, 0); 162 163 /* Enable receive */ 164 e1000e_macreg_write(&d->e1000e, E1000_RFCTL, E1000_RFCTL_EXTEN); 165 e1000e_macreg_write(&d->e1000e, E1000_RCTL, E1000_RCTL_EN | 166 E1000_RCTL_UPE | 167 E1000_RCTL_MPE); 168 169 /* Enable all interrupts */ 170 e1000e_macreg_write(&d->e1000e, E1000_IMS, 0xFFFFFFFF); 171 172 } 173 174 static void *e1000e_pci_get_driver(void *obj, const char *interface) 175 { 176 QE1000E_PCI *epci = obj; 177 if (!g_strcmp0(interface, "e1000e-if")) { 178 return &epci->e1000e; 179 } 180 181 /* implicit contains */ 182 if (!g_strcmp0(interface, "pci-device")) { 183 return &epci->pci_dev; 184 } 185 186 fprintf(stderr, "%s not present in e1000e\n", interface); 187 g_assert_not_reached(); 188 } 189 190 static void *e1000e_pci_create(void *pci_bus, QGuestAllocator *alloc, 191 void *addr) 192 { 193 QE1000E_PCI *d = g_new0(QE1000E_PCI, 1); 194 QPCIBus *bus = pci_bus; 195 QPCIAddress *address = addr; 196 197 qpci_device_foreach(bus, address->vendor_id, address->device_id, 198 e1000e_foreach_callback, &d->pci_dev); 199 200 /* Map BAR0 (mac registers) */ 201 d->mac_regs = qpci_iomap(&d->pci_dev, 0, NULL); 202 203 /* Allocate and setup TX ring */ 204 d->e1000e.tx_ring = guest_alloc(alloc, E1000E_RING_LEN); 205 g_assert(d->e1000e.tx_ring != 0); 206 207 /* Allocate and setup RX ring */ 208 d->e1000e.rx_ring = guest_alloc(alloc, E1000E_RING_LEN); 209 g_assert(d->e1000e.rx_ring != 0); 210 211 d->obj.get_driver = e1000e_pci_get_driver; 212 d->obj.start_hw = e1000e_pci_start_hw; 213 d->obj.destructor = e1000e_pci_destructor; 214 215 return &d->obj; 216 } 217 218 static void e1000e_register_nodes(void) 219 { 220 QPCIAddress addr = { 221 .vendor_id = PCI_VENDOR_ID_INTEL, 222 .device_id = E1000_DEV_ID_82574L, 223 }; 224 225 /* 226 * FIXME: every test using this node needs to setup a -netdev socket,id=hs0 227 * otherwise QEMU is not going to start 228 */ 229 QOSGraphEdgeOptions opts = { 230 .extra_device_opts = "netdev=hs0", 231 }; 232 add_qpci_address(&opts, &addr); 233 234 qos_node_create_driver("e1000e", e1000e_pci_create); 235 qos_node_consumes("e1000e", "pci-bus", &opts); 236 } 237 238 libqos_init(e1000e_register_nodes); 239