1 /* 2 * IDE test cases 3 * 4 * Copyright (c) 2013 Kevin Wolf <kwolf@redhat.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 27 28 #include "libqtest.h" 29 #include "libqos/libqos.h" 30 #include "libqos/pci-pc.h" 31 #include "libqos/malloc-pc.h" 32 #include "qapi/qmp/qdict.h" 33 #include "qemu-common.h" 34 #include "qemu/bswap.h" 35 #include "hw/pci/pci_ids.h" 36 #include "hw/pci/pci_regs.h" 37 38 /* TODO actually test the results and get rid of this */ 39 #define qmp_discard_response(q, ...) qobject_unref(qtest_qmp(q, __VA_ARGS__)) 40 41 #define TEST_IMAGE_SIZE 64 * 1024 * 1024 42 43 #define IDE_PCI_DEV 1 44 #define IDE_PCI_FUNC 1 45 46 #define IDE_BASE 0x1f0 47 #define IDE_PRIMARY_IRQ 14 48 49 #define ATAPI_BLOCK_SIZE 2048 50 51 /* How many bytes to receive via ATAPI PIO at one time. 52 * Must be less than 0xFFFF. */ 53 #define BYTE_COUNT_LIMIT 5120 54 55 enum { 56 reg_data = 0x0, 57 reg_feature = 0x1, 58 reg_error = 0x1, 59 reg_nsectors = 0x2, 60 reg_lba_low = 0x3, 61 reg_lba_middle = 0x4, 62 reg_lba_high = 0x5, 63 reg_device = 0x6, 64 reg_status = 0x7, 65 reg_command = 0x7, 66 }; 67 68 enum { 69 BSY = 0x80, 70 DRDY = 0x40, 71 DF = 0x20, 72 DRQ = 0x08, 73 ERR = 0x01, 74 }; 75 76 /* Error field */ 77 enum { 78 ABRT = 0x04, 79 }; 80 81 enum { 82 DEV = 0x10, 83 LBA = 0x40, 84 }; 85 86 enum { 87 bmreg_cmd = 0x0, 88 bmreg_status = 0x2, 89 bmreg_prdt = 0x4, 90 }; 91 92 enum { 93 CMD_DSM = 0x06, 94 CMD_READ_DMA = 0xc8, 95 CMD_WRITE_DMA = 0xca, 96 CMD_FLUSH_CACHE = 0xe7, 97 CMD_IDENTIFY = 0xec, 98 CMD_PACKET = 0xa0, 99 100 CMDF_ABORT = 0x100, 101 CMDF_NO_BM = 0x200, 102 }; 103 104 enum { 105 BM_CMD_START = 0x1, 106 BM_CMD_WRITE = 0x8, /* write = from device to memory */ 107 }; 108 109 enum { 110 BM_STS_ACTIVE = 0x1, 111 BM_STS_ERROR = 0x2, 112 BM_STS_INTR = 0x4, 113 }; 114 115 enum { 116 PRDT_EOT = 0x80000000, 117 }; 118 119 #define assert_bit_set(data, mask) g_assert_cmphex((data) & (mask), ==, (mask)) 120 #define assert_bit_clear(data, mask) g_assert_cmphex((data) & (mask), ==, 0) 121 122 static QPCIBus *pcibus = NULL; 123 static QGuestAllocator guest_malloc; 124 125 static char tmp_path[] = "/tmp/qtest.XXXXXX"; 126 static char debug_path[] = "/tmp/qtest-blkdebug.XXXXXX"; 127 128 static QTestState *ide_test_start(const char *cmdline_fmt, ...) 129 { 130 QTestState *qts; 131 va_list ap; 132 133 va_start(ap, cmdline_fmt); 134 qts = qtest_vinitf(cmdline_fmt, ap); 135 va_end(ap); 136 137 pc_alloc_init(&guest_malloc, qts, 0); 138 139 return qts; 140 } 141 142 static void ide_test_quit(QTestState *qts) 143 { 144 if (pcibus) { 145 qpci_free_pc(pcibus); 146 pcibus = NULL; 147 } 148 alloc_destroy(&guest_malloc); 149 qtest_quit(qts); 150 } 151 152 static QPCIDevice *get_pci_device(QTestState *qts, QPCIBar *bmdma_bar, 153 QPCIBar *ide_bar) 154 { 155 QPCIDevice *dev; 156 uint16_t vendor_id, device_id; 157 158 if (!pcibus) { 159 pcibus = qpci_new_pc(qts, NULL); 160 } 161 162 /* Find PCI device and verify it's the right one */ 163 dev = qpci_device_find(pcibus, QPCI_DEVFN(IDE_PCI_DEV, IDE_PCI_FUNC)); 164 g_assert(dev != NULL); 165 166 vendor_id = qpci_config_readw(dev, PCI_VENDOR_ID); 167 device_id = qpci_config_readw(dev, PCI_DEVICE_ID); 168 g_assert(vendor_id == PCI_VENDOR_ID_INTEL); 169 g_assert(device_id == PCI_DEVICE_ID_INTEL_82371SB_1); 170 171 /* Map bmdma BAR */ 172 *bmdma_bar = qpci_iomap(dev, 4, NULL); 173 174 *ide_bar = qpci_legacy_iomap(dev, IDE_BASE); 175 176 qpci_device_enable(dev); 177 178 return dev; 179 } 180 181 static void free_pci_device(QPCIDevice *dev) 182 { 183 /* libqos doesn't have a function for this, so free it manually */ 184 g_free(dev); 185 } 186 187 typedef struct PrdtEntry { 188 uint32_t addr; 189 uint32_t size; 190 } QEMU_PACKED PrdtEntry; 191 192 #define assert_bit_set(data, mask) g_assert_cmphex((data) & (mask), ==, (mask)) 193 #define assert_bit_clear(data, mask) g_assert_cmphex((data) & (mask), ==, 0) 194 195 static uint64_t trim_range_le(uint64_t sector, uint16_t count) 196 { 197 /* 2-byte range, 6-byte LBA */ 198 return cpu_to_le64(((uint64_t)count << 48) + sector); 199 } 200 201 static int send_dma_request(QTestState *qts, int cmd, uint64_t sector, 202 int nb_sectors, PrdtEntry *prdt, int prdt_entries, 203 void(*post_exec)(QPCIDevice *dev, QPCIBar ide_bar, 204 uint64_t sector, int nb_sectors)) 205 { 206 QPCIDevice *dev; 207 QPCIBar bmdma_bar, ide_bar; 208 uintptr_t guest_prdt; 209 size_t len; 210 bool from_dev; 211 uint8_t status; 212 int flags; 213 214 dev = get_pci_device(qts, &bmdma_bar, &ide_bar); 215 216 flags = cmd & ~0xff; 217 cmd &= 0xff; 218 219 switch (cmd) { 220 case CMD_READ_DMA: 221 case CMD_PACKET: 222 /* Assuming we only test data reads w/ ATAPI, otherwise we need to know 223 * the SCSI command being sent in the packet, too. */ 224 from_dev = true; 225 break; 226 case CMD_DSM: 227 case CMD_WRITE_DMA: 228 from_dev = false; 229 break; 230 default: 231 g_assert_not_reached(); 232 } 233 234 if (flags & CMDF_NO_BM) { 235 qpci_config_writew(dev, PCI_COMMAND, 236 PCI_COMMAND_IO | PCI_COMMAND_MEMORY); 237 } 238 239 /* Select device 0 */ 240 qpci_io_writeb(dev, ide_bar, reg_device, 0 | LBA); 241 242 /* Stop any running transfer, clear any pending interrupt */ 243 qpci_io_writeb(dev, bmdma_bar, bmreg_cmd, 0); 244 qpci_io_writeb(dev, bmdma_bar, bmreg_status, BM_STS_INTR); 245 246 /* Setup PRDT */ 247 len = sizeof(*prdt) * prdt_entries; 248 guest_prdt = guest_alloc(&guest_malloc, len); 249 qtest_memwrite(qts, guest_prdt, prdt, len); 250 qpci_io_writel(dev, bmdma_bar, bmreg_prdt, guest_prdt); 251 252 /* ATA DMA command */ 253 if (cmd == CMD_PACKET) { 254 /* Enables ATAPI DMA; otherwise PIO is attempted */ 255 qpci_io_writeb(dev, ide_bar, reg_feature, 0x01); 256 } else { 257 if (cmd == CMD_DSM) { 258 /* trim bit */ 259 qpci_io_writeb(dev, ide_bar, reg_feature, 0x01); 260 } 261 qpci_io_writeb(dev, ide_bar, reg_nsectors, nb_sectors); 262 qpci_io_writeb(dev, ide_bar, reg_lba_low, sector & 0xff); 263 qpci_io_writeb(dev, ide_bar, reg_lba_middle, (sector >> 8) & 0xff); 264 qpci_io_writeb(dev, ide_bar, reg_lba_high, (sector >> 16) & 0xff); 265 } 266 267 qpci_io_writeb(dev, ide_bar, reg_command, cmd); 268 269 if (post_exec) { 270 post_exec(dev, ide_bar, sector, nb_sectors); 271 } 272 273 /* Start DMA transfer */ 274 qpci_io_writeb(dev, bmdma_bar, bmreg_cmd, 275 BM_CMD_START | (from_dev ? BM_CMD_WRITE : 0)); 276 277 if (flags & CMDF_ABORT) { 278 qpci_io_writeb(dev, bmdma_bar, bmreg_cmd, 0); 279 } 280 281 /* Wait for the DMA transfer to complete */ 282 do { 283 status = qpci_io_readb(dev, bmdma_bar, bmreg_status); 284 } while ((status & (BM_STS_ACTIVE | BM_STS_INTR)) == BM_STS_ACTIVE); 285 286 g_assert_cmpint(qtest_get_irq(qts, IDE_PRIMARY_IRQ), ==, 287 !!(status & BM_STS_INTR)); 288 289 /* Check IDE status code */ 290 assert_bit_set(qpci_io_readb(dev, ide_bar, reg_status), DRDY); 291 assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), BSY | DRQ); 292 293 /* Reading the status register clears the IRQ */ 294 g_assert(!qtest_get_irq(qts, IDE_PRIMARY_IRQ)); 295 296 /* Stop DMA transfer if still active */ 297 if (status & BM_STS_ACTIVE) { 298 qpci_io_writeb(dev, bmdma_bar, bmreg_cmd, 0); 299 } 300 301 free_pci_device(dev); 302 303 return status; 304 } 305 306 static QTestState *test_bmdma_setup(void) 307 { 308 QTestState *qts; 309 310 qts = ide_test_start( 311 "-drive file=%s,if=ide,cache=writeback,format=raw " 312 "-global ide-hd.serial=%s -global ide-hd.ver=%s", 313 tmp_path, "testdisk", "version"); 314 qtest_irq_intercept_in(qts, "ioapic"); 315 316 return qts; 317 } 318 319 static void test_bmdma_teardown(QTestState *qts) 320 { 321 ide_test_quit(qts); 322 } 323 324 static void test_bmdma_simple_rw(void) 325 { 326 QTestState *qts; 327 QPCIDevice *dev; 328 QPCIBar bmdma_bar, ide_bar; 329 uint8_t status; 330 uint8_t *buf; 331 uint8_t *cmpbuf; 332 size_t len = 512; 333 uintptr_t guest_buf; 334 PrdtEntry prdt[1]; 335 336 qts = test_bmdma_setup(); 337 338 guest_buf = guest_alloc(&guest_malloc, len); 339 prdt[0].addr = cpu_to_le32(guest_buf); 340 prdt[0].size = cpu_to_le32(len | PRDT_EOT); 341 342 dev = get_pci_device(qts, &bmdma_bar, &ide_bar); 343 344 buf = g_malloc(len); 345 cmpbuf = g_malloc(len); 346 347 /* Write 0x55 pattern to sector 0 */ 348 memset(buf, 0x55, len); 349 qtest_memwrite(qts, guest_buf, buf, len); 350 351 status = send_dma_request(qts, CMD_WRITE_DMA, 0, 1, prdt, 352 ARRAY_SIZE(prdt), NULL); 353 g_assert_cmphex(status, ==, BM_STS_INTR); 354 assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); 355 356 /* Write 0xaa pattern to sector 1 */ 357 memset(buf, 0xaa, len); 358 qtest_memwrite(qts, guest_buf, buf, len); 359 360 status = send_dma_request(qts, CMD_WRITE_DMA, 1, 1, prdt, 361 ARRAY_SIZE(prdt), NULL); 362 g_assert_cmphex(status, ==, BM_STS_INTR); 363 assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); 364 365 /* Read and verify 0x55 pattern in sector 0 */ 366 memset(cmpbuf, 0x55, len); 367 368 status = send_dma_request(qts, CMD_READ_DMA, 0, 1, prdt, ARRAY_SIZE(prdt), 369 NULL); 370 g_assert_cmphex(status, ==, BM_STS_INTR); 371 assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); 372 373 qtest_memread(qts, guest_buf, buf, len); 374 g_assert(memcmp(buf, cmpbuf, len) == 0); 375 376 /* Read and verify 0xaa pattern in sector 1 */ 377 memset(cmpbuf, 0xaa, len); 378 379 status = send_dma_request(qts, CMD_READ_DMA, 1, 1, prdt, ARRAY_SIZE(prdt), 380 NULL); 381 g_assert_cmphex(status, ==, BM_STS_INTR); 382 assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); 383 384 qtest_memread(qts, guest_buf, buf, len); 385 g_assert(memcmp(buf, cmpbuf, len) == 0); 386 387 free_pci_device(dev); 388 g_free(buf); 389 g_free(cmpbuf); 390 391 test_bmdma_teardown(qts); 392 } 393 394 static void test_bmdma_trim(void) 395 { 396 QTestState *qts; 397 QPCIDevice *dev; 398 QPCIBar bmdma_bar, ide_bar; 399 uint8_t status; 400 const uint64_t trim_range[] = { trim_range_le(0, 2), 401 trim_range_le(6, 8), 402 trim_range_le(10, 1), 403 }; 404 const uint64_t bad_range = trim_range_le(TEST_IMAGE_SIZE / 512 - 1, 2); 405 size_t len = 512; 406 uint8_t *buf; 407 uintptr_t guest_buf; 408 PrdtEntry prdt[1]; 409 410 qts = test_bmdma_setup(); 411 412 guest_buf = guest_alloc(&guest_malloc, len); 413 prdt[0].addr = cpu_to_le32(guest_buf), 414 prdt[0].size = cpu_to_le32(len | PRDT_EOT), 415 416 dev = get_pci_device(qts, &bmdma_bar, &ide_bar); 417 418 buf = g_malloc(len); 419 420 /* Normal request */ 421 *((uint64_t *)buf) = trim_range[0]; 422 *((uint64_t *)buf + 1) = trim_range[1]; 423 424 qtest_memwrite(qts, guest_buf, buf, 2 * sizeof(uint64_t)); 425 426 status = send_dma_request(qts, CMD_DSM, 0, 1, prdt, 427 ARRAY_SIZE(prdt), NULL); 428 g_assert_cmphex(status, ==, BM_STS_INTR); 429 assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); 430 431 /* Request contains invalid range */ 432 *((uint64_t *)buf) = trim_range[2]; 433 *((uint64_t *)buf + 1) = bad_range; 434 435 qtest_memwrite(qts, guest_buf, buf, 2 * sizeof(uint64_t)); 436 437 status = send_dma_request(qts, CMD_DSM, 0, 1, prdt, 438 ARRAY_SIZE(prdt), NULL); 439 g_assert_cmphex(status, ==, BM_STS_INTR); 440 assert_bit_set(qpci_io_readb(dev, ide_bar, reg_status), ERR); 441 assert_bit_set(qpci_io_readb(dev, ide_bar, reg_error), ABRT); 442 443 free_pci_device(dev); 444 g_free(buf); 445 test_bmdma_teardown(qts); 446 } 447 448 static void test_bmdma_short_prdt(void) 449 { 450 QTestState *qts; 451 QPCIDevice *dev; 452 QPCIBar bmdma_bar, ide_bar; 453 uint8_t status; 454 455 PrdtEntry prdt[] = { 456 { 457 .addr = 0, 458 .size = cpu_to_le32(0x10 | PRDT_EOT), 459 }, 460 }; 461 462 qts = test_bmdma_setup(); 463 464 dev = get_pci_device(qts, &bmdma_bar, &ide_bar); 465 466 /* Normal request */ 467 status = send_dma_request(qts, CMD_READ_DMA, 0, 1, 468 prdt, ARRAY_SIZE(prdt), NULL); 469 g_assert_cmphex(status, ==, 0); 470 assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); 471 472 /* Abort the request before it completes */ 473 status = send_dma_request(qts, CMD_READ_DMA | CMDF_ABORT, 0, 1, 474 prdt, ARRAY_SIZE(prdt), NULL); 475 g_assert_cmphex(status, ==, 0); 476 assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); 477 free_pci_device(dev); 478 test_bmdma_teardown(qts); 479 } 480 481 static void test_bmdma_one_sector_short_prdt(void) 482 { 483 QTestState *qts; 484 QPCIDevice *dev; 485 QPCIBar bmdma_bar, ide_bar; 486 uint8_t status; 487 488 /* Read 2 sectors but only give 1 sector in PRDT */ 489 PrdtEntry prdt[] = { 490 { 491 .addr = 0, 492 .size = cpu_to_le32(0x200 | PRDT_EOT), 493 }, 494 }; 495 496 qts = test_bmdma_setup(); 497 498 dev = get_pci_device(qts, &bmdma_bar, &ide_bar); 499 500 /* Normal request */ 501 status = send_dma_request(qts, CMD_READ_DMA, 0, 2, 502 prdt, ARRAY_SIZE(prdt), NULL); 503 g_assert_cmphex(status, ==, 0); 504 assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); 505 506 /* Abort the request before it completes */ 507 status = send_dma_request(qts, CMD_READ_DMA | CMDF_ABORT, 0, 2, 508 prdt, ARRAY_SIZE(prdt), NULL); 509 g_assert_cmphex(status, ==, 0); 510 assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); 511 free_pci_device(dev); 512 test_bmdma_teardown(qts); 513 } 514 515 static void test_bmdma_long_prdt(void) 516 { 517 QTestState *qts; 518 QPCIDevice *dev; 519 QPCIBar bmdma_bar, ide_bar; 520 uint8_t status; 521 522 PrdtEntry prdt[] = { 523 { 524 .addr = 0, 525 .size = cpu_to_le32(0x1000 | PRDT_EOT), 526 }, 527 }; 528 529 qts = test_bmdma_setup(); 530 531 dev = get_pci_device(qts, &bmdma_bar, &ide_bar); 532 533 /* Normal request */ 534 status = send_dma_request(qts, CMD_READ_DMA, 0, 1, 535 prdt, ARRAY_SIZE(prdt), NULL); 536 g_assert_cmphex(status, ==, BM_STS_ACTIVE | BM_STS_INTR); 537 assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); 538 539 /* Abort the request before it completes */ 540 status = send_dma_request(qts, CMD_READ_DMA | CMDF_ABORT, 0, 1, 541 prdt, ARRAY_SIZE(prdt), NULL); 542 g_assert_cmphex(status, ==, BM_STS_INTR); 543 assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); 544 free_pci_device(dev); 545 test_bmdma_teardown(qts); 546 } 547 548 static void test_bmdma_no_busmaster(void) 549 { 550 QTestState *qts; 551 QPCIDevice *dev; 552 QPCIBar bmdma_bar, ide_bar; 553 uint8_t status; 554 555 qts = test_bmdma_setup(); 556 557 dev = get_pci_device(qts, &bmdma_bar, &ide_bar); 558 559 /* No PRDT_EOT, each entry addr 0/size 64k, and in theory qemu shouldn't be 560 * able to access it anyway because the Bus Master bit in the PCI command 561 * register isn't set. This is complete nonsense, but it used to be pretty 562 * good at confusing and occasionally crashing qemu. */ 563 PrdtEntry prdt[4096] = { }; 564 565 status = send_dma_request(qts, CMD_READ_DMA | CMDF_NO_BM, 0, 512, 566 prdt, ARRAY_SIZE(prdt), NULL); 567 568 /* Not entirely clear what the expected result is, but this is what we get 569 * in practice. At least we want to be aware of any changes. */ 570 g_assert_cmphex(status, ==, BM_STS_ACTIVE | BM_STS_INTR); 571 assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); 572 free_pci_device(dev); 573 test_bmdma_teardown(qts); 574 } 575 576 static void string_cpu_to_be16(uint16_t *s, size_t bytes) 577 { 578 g_assert((bytes & 1) == 0); 579 bytes /= 2; 580 581 while (bytes--) { 582 *s = cpu_to_be16(*s); 583 s++; 584 } 585 } 586 587 static void test_identify(void) 588 { 589 QTestState *qts; 590 QPCIDevice *dev; 591 QPCIBar bmdma_bar, ide_bar; 592 uint8_t data; 593 uint16_t buf[256]; 594 int i; 595 int ret; 596 597 qts = ide_test_start( 598 "-drive file=%s,if=ide,cache=writeback,format=raw " 599 "-global ide-hd.serial=%s -global ide-hd.ver=%s", 600 tmp_path, "testdisk", "version"); 601 602 dev = get_pci_device(qts, &bmdma_bar, &ide_bar); 603 604 /* IDENTIFY command on device 0*/ 605 qpci_io_writeb(dev, ide_bar, reg_device, 0); 606 qpci_io_writeb(dev, ide_bar, reg_command, CMD_IDENTIFY); 607 608 /* Read in the IDENTIFY buffer and check registers */ 609 data = qpci_io_readb(dev, ide_bar, reg_device); 610 g_assert_cmpint(data & DEV, ==, 0); 611 612 for (i = 0; i < 256; i++) { 613 data = qpci_io_readb(dev, ide_bar, reg_status); 614 assert_bit_set(data, DRDY | DRQ); 615 assert_bit_clear(data, BSY | DF | ERR); 616 617 buf[i] = qpci_io_readw(dev, ide_bar, reg_data); 618 } 619 620 data = qpci_io_readb(dev, ide_bar, reg_status); 621 assert_bit_set(data, DRDY); 622 assert_bit_clear(data, BSY | DF | ERR | DRQ); 623 624 /* Check serial number/version in the buffer */ 625 string_cpu_to_be16(&buf[10], 20); 626 ret = memcmp(&buf[10], "testdisk ", 20); 627 g_assert(ret == 0); 628 629 string_cpu_to_be16(&buf[23], 8); 630 ret = memcmp(&buf[23], "version ", 8); 631 g_assert(ret == 0); 632 633 /* Write cache enabled bit */ 634 assert_bit_set(buf[85], 0x20); 635 636 ide_test_quit(qts); 637 free_pci_device(dev); 638 } 639 640 /* 641 * Write sector 1 with random data to make IDE storage dirty 642 * Needed for flush tests so that flushes actually go though the block layer 643 */ 644 static void make_dirty(QTestState *qts, uint8_t device) 645 { 646 QPCIDevice *dev; 647 QPCIBar bmdma_bar, ide_bar; 648 uint8_t status; 649 size_t len = 512; 650 uintptr_t guest_buf; 651 void* buf; 652 653 dev = get_pci_device(qts, &bmdma_bar, &ide_bar); 654 655 guest_buf = guest_alloc(&guest_malloc, len); 656 buf = g_malloc(len); 657 memset(buf, rand() % 255 + 1, len); 658 g_assert(guest_buf); 659 g_assert(buf); 660 661 qtest_memwrite(qts, guest_buf, buf, len); 662 663 PrdtEntry prdt[] = { 664 { 665 .addr = cpu_to_le32(guest_buf), 666 .size = cpu_to_le32(len | PRDT_EOT), 667 }, 668 }; 669 670 status = send_dma_request(qts, CMD_WRITE_DMA, 1, 1, prdt, 671 ARRAY_SIZE(prdt), NULL); 672 g_assert_cmphex(status, ==, BM_STS_INTR); 673 assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); 674 675 g_free(buf); 676 free_pci_device(dev); 677 } 678 679 static void test_flush(void) 680 { 681 QTestState *qts; 682 QPCIDevice *dev; 683 QPCIBar bmdma_bar, ide_bar; 684 uint8_t data; 685 686 qts = ide_test_start( 687 "-drive file=blkdebug::%s,if=ide,cache=writeback,format=raw", 688 tmp_path); 689 690 dev = get_pci_device(qts, &bmdma_bar, &ide_bar); 691 692 qtest_irq_intercept_in(qts, "ioapic"); 693 694 /* Dirty media so that CMD_FLUSH_CACHE will actually go to disk */ 695 make_dirty(qts, 0); 696 697 /* Delay the completion of the flush request until we explicitly do it */ 698 g_free(qtest_hmp(qts, "qemu-io ide0-hd0 \"break flush_to_os A\"")); 699 700 /* FLUSH CACHE command on device 0*/ 701 qpci_io_writeb(dev, ide_bar, reg_device, 0); 702 qpci_io_writeb(dev, ide_bar, reg_command, CMD_FLUSH_CACHE); 703 704 /* Check status while request is in flight*/ 705 data = qpci_io_readb(dev, ide_bar, reg_status); 706 assert_bit_set(data, BSY | DRDY); 707 assert_bit_clear(data, DF | ERR | DRQ); 708 709 /* Complete the command */ 710 g_free(qtest_hmp(qts, "qemu-io ide0-hd0 \"resume A\"")); 711 712 /* Check registers */ 713 data = qpci_io_readb(dev, ide_bar, reg_device); 714 g_assert_cmpint(data & DEV, ==, 0); 715 716 do { 717 data = qpci_io_readb(dev, ide_bar, reg_status); 718 } while (data & BSY); 719 720 assert_bit_set(data, DRDY); 721 assert_bit_clear(data, BSY | DF | ERR | DRQ); 722 723 ide_test_quit(qts); 724 free_pci_device(dev); 725 } 726 727 static void test_retry_flush(const char *machine) 728 { 729 QTestState *qts; 730 QPCIDevice *dev; 731 QPCIBar bmdma_bar, ide_bar; 732 uint8_t data; 733 734 prepare_blkdebug_script(debug_path, "flush_to_disk"); 735 736 qts = ide_test_start( 737 "-drive file=blkdebug:%s:%s,if=ide,cache=writeback,format=raw," 738 "rerror=stop,werror=stop", 739 debug_path, tmp_path); 740 741 dev = get_pci_device(qts, &bmdma_bar, &ide_bar); 742 743 qtest_irq_intercept_in(qts, "ioapic"); 744 745 /* Dirty media so that CMD_FLUSH_CACHE will actually go to disk */ 746 make_dirty(qts, 0); 747 748 /* FLUSH CACHE command on device 0*/ 749 qpci_io_writeb(dev, ide_bar, reg_device, 0); 750 qpci_io_writeb(dev, ide_bar, reg_command, CMD_FLUSH_CACHE); 751 752 /* Check status while request is in flight*/ 753 data = qpci_io_readb(dev, ide_bar, reg_status); 754 assert_bit_set(data, BSY | DRDY); 755 assert_bit_clear(data, DF | ERR | DRQ); 756 757 qtest_qmp_eventwait(qts, "STOP"); 758 759 /* Complete the command */ 760 qmp_discard_response(qts, "{'execute':'cont' }"); 761 762 /* Check registers */ 763 data = qpci_io_readb(dev, ide_bar, reg_device); 764 g_assert_cmpint(data & DEV, ==, 0); 765 766 do { 767 data = qpci_io_readb(dev, ide_bar, reg_status); 768 } while (data & BSY); 769 770 assert_bit_set(data, DRDY); 771 assert_bit_clear(data, BSY | DF | ERR | DRQ); 772 773 ide_test_quit(qts); 774 free_pci_device(dev); 775 } 776 777 static void test_flush_nodev(void) 778 { 779 QTestState *qts; 780 QPCIDevice *dev; 781 QPCIBar bmdma_bar, ide_bar; 782 783 qts = ide_test_start(""); 784 785 dev = get_pci_device(qts, &bmdma_bar, &ide_bar); 786 787 /* FLUSH CACHE command on device 0*/ 788 qpci_io_writeb(dev, ide_bar, reg_device, 0); 789 qpci_io_writeb(dev, ide_bar, reg_command, CMD_FLUSH_CACHE); 790 791 /* Just testing that qemu doesn't crash... */ 792 793 free_pci_device(dev); 794 ide_test_quit(qts); 795 } 796 797 static void test_flush_empty_drive(void) 798 { 799 QTestState *qts; 800 QPCIDevice *dev; 801 QPCIBar bmdma_bar, ide_bar; 802 803 qts = ide_test_start("-device ide-cd,bus=ide.0"); 804 dev = get_pci_device(qts, &bmdma_bar, &ide_bar); 805 806 /* FLUSH CACHE command on device 0 */ 807 qpci_io_writeb(dev, ide_bar, reg_device, 0); 808 qpci_io_writeb(dev, ide_bar, reg_command, CMD_FLUSH_CACHE); 809 810 /* Just testing that qemu doesn't crash... */ 811 812 free_pci_device(dev); 813 ide_test_quit(qts); 814 } 815 816 static void test_pci_retry_flush(void) 817 { 818 test_retry_flush("pc"); 819 } 820 821 static void test_isa_retry_flush(void) 822 { 823 test_retry_flush("isapc"); 824 } 825 826 typedef struct Read10CDB { 827 uint8_t opcode; 828 uint8_t flags; 829 uint32_t lba; 830 uint8_t reserved; 831 uint16_t nblocks; 832 uint8_t control; 833 uint16_t padding; 834 } __attribute__((__packed__)) Read10CDB; 835 836 static void send_scsi_cdb_read10(QPCIDevice *dev, QPCIBar ide_bar, 837 uint64_t lba, int nblocks) 838 { 839 Read10CDB pkt = { .padding = 0 }; 840 int i; 841 842 g_assert_cmpint(lba, <=, UINT32_MAX); 843 g_assert_cmpint(nblocks, <=, UINT16_MAX); 844 g_assert_cmpint(nblocks, >=, 0); 845 846 /* Construct SCSI CDB packet */ 847 pkt.opcode = 0x28; 848 pkt.lba = cpu_to_be32(lba); 849 pkt.nblocks = cpu_to_be16(nblocks); 850 851 /* Send Packet */ 852 for (i = 0; i < sizeof(Read10CDB)/2; i++) { 853 qpci_io_writew(dev, ide_bar, reg_data, 854 le16_to_cpu(((uint16_t *)&pkt)[i])); 855 } 856 } 857 858 static void nsleep(QTestState *qts, int64_t nsecs) 859 { 860 const struct timespec val = { .tv_nsec = nsecs }; 861 nanosleep(&val, NULL); 862 qtest_clock_set(qts, nsecs); 863 } 864 865 static uint8_t ide_wait_clear(QTestState *qts, uint8_t flag) 866 { 867 QPCIDevice *dev; 868 QPCIBar bmdma_bar, ide_bar; 869 uint8_t data; 870 time_t st; 871 872 dev = get_pci_device(qts, &bmdma_bar, &ide_bar); 873 874 /* Wait with a 5 second timeout */ 875 time(&st); 876 while (true) { 877 data = qpci_io_readb(dev, ide_bar, reg_status); 878 if (!(data & flag)) { 879 free_pci_device(dev); 880 return data; 881 } 882 if (difftime(time(NULL), st) > 5.0) { 883 break; 884 } 885 nsleep(qts, 400); 886 } 887 g_assert_not_reached(); 888 } 889 890 static void ide_wait_intr(QTestState *qts, int irq) 891 { 892 time_t st; 893 bool intr; 894 895 time(&st); 896 while (true) { 897 intr = qtest_get_irq(qts, irq); 898 if (intr) { 899 return; 900 } 901 if (difftime(time(NULL), st) > 5.0) { 902 break; 903 } 904 nsleep(qts, 400); 905 } 906 907 g_assert_not_reached(); 908 } 909 910 static void cdrom_pio_impl(int nblocks) 911 { 912 QTestState *qts; 913 QPCIDevice *dev; 914 QPCIBar bmdma_bar, ide_bar; 915 FILE *fh; 916 int patt_blocks = MAX(16, nblocks); 917 size_t patt_len = ATAPI_BLOCK_SIZE * patt_blocks; 918 char *pattern = g_malloc(patt_len); 919 size_t rxsize = ATAPI_BLOCK_SIZE * nblocks; 920 uint16_t *rx = g_malloc0(rxsize); 921 int i, j; 922 uint8_t data; 923 uint16_t limit; 924 size_t ret; 925 926 /* Prepopulate the CDROM with an interesting pattern */ 927 generate_pattern(pattern, patt_len, ATAPI_BLOCK_SIZE); 928 fh = fopen(tmp_path, "w+"); 929 ret = fwrite(pattern, ATAPI_BLOCK_SIZE, patt_blocks, fh); 930 g_assert_cmpint(ret, ==, patt_blocks); 931 fclose(fh); 932 933 qts = ide_test_start( 934 "-drive if=none,file=%s,media=cdrom,format=raw,id=sr0,index=0 " 935 "-device ide-cd,drive=sr0,bus=ide.0", tmp_path); 936 dev = get_pci_device(qts, &bmdma_bar, &ide_bar); 937 qtest_irq_intercept_in(qts, "ioapic"); 938 939 /* PACKET command on device 0 */ 940 qpci_io_writeb(dev, ide_bar, reg_device, 0); 941 qpci_io_writeb(dev, ide_bar, reg_lba_middle, BYTE_COUNT_LIMIT & 0xFF); 942 qpci_io_writeb(dev, ide_bar, reg_lba_high, (BYTE_COUNT_LIMIT >> 8 & 0xFF)); 943 qpci_io_writeb(dev, ide_bar, reg_command, CMD_PACKET); 944 /* HP0: Check_Status_A State */ 945 nsleep(qts, 400); 946 data = ide_wait_clear(qts, BSY); 947 /* HP1: Send_Packet State */ 948 assert_bit_set(data, DRQ | DRDY); 949 assert_bit_clear(data, ERR | DF | BSY); 950 951 /* SCSI CDB (READ10) -- read n*2048 bytes from block 0 */ 952 send_scsi_cdb_read10(dev, ide_bar, 0, nblocks); 953 954 /* Read data back: occurs in bursts of 'BYTE_COUNT_LIMIT' bytes. 955 * If BYTE_COUNT_LIMIT is odd, we transfer BYTE_COUNT_LIMIT - 1 bytes. 956 * We allow an odd limit only when the remaining transfer size is 957 * less than BYTE_COUNT_LIMIT. However, SCSI's read10 command can only 958 * request n blocks, so our request size is always even. 959 * For this reason, we assume there is never a hanging byte to fetch. */ 960 g_assert(!(rxsize & 1)); 961 limit = BYTE_COUNT_LIMIT & ~1; 962 for (i = 0; i < DIV_ROUND_UP(rxsize, limit); i++) { 963 size_t offset = i * (limit / 2); 964 size_t rem = (rxsize / 2) - offset; 965 966 /* HP3: INTRQ_Wait */ 967 ide_wait_intr(qts, IDE_PRIMARY_IRQ); 968 969 /* HP2: Check_Status_B (and clear IRQ) */ 970 data = ide_wait_clear(qts, BSY); 971 assert_bit_set(data, DRQ | DRDY); 972 assert_bit_clear(data, ERR | DF | BSY); 973 974 /* HP4: Transfer_Data */ 975 for (j = 0; j < MIN((limit / 2), rem); j++) { 976 rx[offset + j] = cpu_to_le16(qpci_io_readw(dev, ide_bar, 977 reg_data)); 978 } 979 } 980 981 /* Check for final completion IRQ */ 982 ide_wait_intr(qts, IDE_PRIMARY_IRQ); 983 984 /* Sanity check final state */ 985 data = ide_wait_clear(qts, DRQ); 986 assert_bit_set(data, DRDY); 987 assert_bit_clear(data, DRQ | ERR | DF | BSY); 988 989 g_assert_cmpint(memcmp(pattern, rx, rxsize), ==, 0); 990 g_free(pattern); 991 g_free(rx); 992 test_bmdma_teardown(qts); 993 free_pci_device(dev); 994 } 995 996 static void test_cdrom_pio(void) 997 { 998 cdrom_pio_impl(1); 999 } 1000 1001 static void test_cdrom_pio_large(void) 1002 { 1003 /* Test a few loops of the PIO DRQ mechanism. */ 1004 cdrom_pio_impl(BYTE_COUNT_LIMIT * 4 / ATAPI_BLOCK_SIZE); 1005 } 1006 1007 1008 static void test_cdrom_dma(void) 1009 { 1010 QTestState *qts; 1011 static const size_t len = ATAPI_BLOCK_SIZE; 1012 size_t ret; 1013 char *pattern = g_malloc(ATAPI_BLOCK_SIZE * 16); 1014 char *rx = g_malloc0(len); 1015 uintptr_t guest_buf; 1016 PrdtEntry prdt[1]; 1017 FILE *fh; 1018 1019 qts = ide_test_start( 1020 "-drive if=none,file=%s,media=cdrom,format=raw,id=sr0,index=0 " 1021 "-device ide-cd,drive=sr0,bus=ide.0", tmp_path); 1022 qtest_irq_intercept_in(qts, "ioapic"); 1023 1024 guest_buf = guest_alloc(&guest_malloc, len); 1025 prdt[0].addr = cpu_to_le32(guest_buf); 1026 prdt[0].size = cpu_to_le32(len | PRDT_EOT); 1027 1028 generate_pattern(pattern, ATAPI_BLOCK_SIZE * 16, ATAPI_BLOCK_SIZE); 1029 fh = fopen(tmp_path, "w+"); 1030 ret = fwrite(pattern, ATAPI_BLOCK_SIZE, 16, fh); 1031 g_assert_cmpint(ret, ==, 16); 1032 fclose(fh); 1033 1034 send_dma_request(qts, CMD_PACKET, 0, 1, prdt, 1, send_scsi_cdb_read10); 1035 1036 /* Read back data from guest memory into local qtest memory */ 1037 qtest_memread(qts, guest_buf, rx, len); 1038 g_assert_cmpint(memcmp(pattern, rx, len), ==, 0); 1039 1040 g_free(pattern); 1041 g_free(rx); 1042 test_bmdma_teardown(qts); 1043 } 1044 1045 int main(int argc, char **argv) 1046 { 1047 int fd; 1048 int ret; 1049 1050 /* Create temporary blkdebug instructions */ 1051 fd = mkstemp(debug_path); 1052 g_assert(fd >= 0); 1053 close(fd); 1054 1055 /* Create a temporary raw image */ 1056 fd = mkstemp(tmp_path); 1057 g_assert(fd >= 0); 1058 ret = ftruncate(fd, TEST_IMAGE_SIZE); 1059 g_assert(ret == 0); 1060 close(fd); 1061 1062 /* Run the tests */ 1063 g_test_init(&argc, &argv, NULL); 1064 1065 qtest_add_func("/ide/identify", test_identify); 1066 1067 qtest_add_func("/ide/bmdma/simple_rw", test_bmdma_simple_rw); 1068 qtest_add_func("/ide/bmdma/trim", test_bmdma_trim); 1069 qtest_add_func("/ide/bmdma/short_prdt", test_bmdma_short_prdt); 1070 qtest_add_func("/ide/bmdma/one_sector_short_prdt", 1071 test_bmdma_one_sector_short_prdt); 1072 qtest_add_func("/ide/bmdma/long_prdt", test_bmdma_long_prdt); 1073 qtest_add_func("/ide/bmdma/no_busmaster", test_bmdma_no_busmaster); 1074 1075 qtest_add_func("/ide/flush", test_flush); 1076 qtest_add_func("/ide/flush/nodev", test_flush_nodev); 1077 qtest_add_func("/ide/flush/empty_drive", test_flush_empty_drive); 1078 qtest_add_func("/ide/flush/retry_pci", test_pci_retry_flush); 1079 qtest_add_func("/ide/flush/retry_isa", test_isa_retry_flush); 1080 1081 qtest_add_func("/ide/cdrom/pio", test_cdrom_pio); 1082 qtest_add_func("/ide/cdrom/pio_large", test_cdrom_pio_large); 1083 qtest_add_func("/ide/cdrom/dma", test_cdrom_dma); 1084 1085 ret = g_test_run(); 1086 1087 /* Cleanup */ 1088 unlink(tmp_path); 1089 unlink(debug_path); 1090 1091 return ret; 1092 } 1093