1 /* 2 * QTest testcase for the ASPEED Hash and Crypto Engine 3 * 4 * SPDX-License-Identifier: GPL-2.0-or-later 5 * Copyright 2021 IBM Corp. 6 */ 7 8 #include "qemu/osdep.h" 9 10 #include "libqos/libqtest.h" 11 #include "qemu-common.h" 12 #include "qemu/bitops.h" 13 14 #define HACE_CMD 0x10 15 #define HACE_SHA_BE_EN BIT(3) 16 #define HACE_MD5_LE_EN BIT(2) 17 #define HACE_ALGO_MD5 0 18 #define HACE_ALGO_SHA1 BIT(5) 19 #define HACE_ALGO_SHA224 BIT(6) 20 #define HACE_ALGO_SHA256 (BIT(4) | BIT(6)) 21 #define HACE_ALGO_SHA512 (BIT(5) | BIT(6)) 22 #define HACE_ALGO_SHA384 (BIT(5) | BIT(6) | BIT(10)) 23 #define HACE_SG_EN BIT(18) 24 25 #define HACE_STS 0x1c 26 #define HACE_RSA_ISR BIT(13) 27 #define HACE_CRYPTO_ISR BIT(12) 28 #define HACE_HASH_ISR BIT(9) 29 #define HACE_RSA_BUSY BIT(2) 30 #define HACE_CRYPTO_BUSY BIT(1) 31 #define HACE_HASH_BUSY BIT(0) 32 #define HACE_HASH_SRC 0x20 33 #define HACE_HASH_DIGEST 0x24 34 #define HACE_HASH_KEY_BUFF 0x28 35 #define HACE_HASH_DATA_LEN 0x2c 36 #define HACE_HASH_CMD 0x30 37 /* Scatter-Gather Hash */ 38 #define SG_LIST_LEN_LAST BIT(31) 39 struct AspeedSgList { 40 uint32_t len; 41 uint32_t addr; 42 } __attribute__ ((__packed__)); 43 44 /* 45 * Test vector is the ascii "abc" 46 * 47 * Expected results were generated using command line utitiles: 48 * 49 * echo -n -e 'abc' | dd of=/tmp/test 50 * for hash in sha512sum sha256sum md5sum; do $hash /tmp/test; done 51 * 52 */ 53 static const uint8_t test_vector[] = {0x61, 0x62, 0x63}; 54 55 static const uint8_t test_result_sha512[] = { 56 0xdd, 0xaf, 0x35, 0xa1, 0x93, 0x61, 0x7a, 0xba, 0xcc, 0x41, 0x73, 0x49, 57 0xae, 0x20, 0x41, 0x31, 0x12, 0xe6, 0xfa, 0x4e, 0x89, 0xa9, 0x7e, 0xa2, 58 0x0a, 0x9e, 0xee, 0xe6, 0x4b, 0x55, 0xd3, 0x9a, 0x21, 0x92, 0x99, 0x2a, 59 0x27, 0x4f, 0xc1, 0xa8, 0x36, 0xba, 0x3c, 0x23, 0xa3, 0xfe, 0xeb, 0xbd, 60 0x45, 0x4d, 0x44, 0x23, 0x64, 0x3c, 0xe8, 0x0e, 0x2a, 0x9a, 0xc9, 0x4f, 61 0xa5, 0x4c, 0xa4, 0x9f}; 62 63 static const uint8_t test_result_sha256[] = { 64 0xba, 0x78, 0x16, 0xbf, 0x8f, 0x01, 0xcf, 0xea, 0x41, 0x41, 0x40, 0xde, 65 0x5d, 0xae, 0x22, 0x23, 0xb0, 0x03, 0x61, 0xa3, 0x96, 0x17, 0x7a, 0x9c, 66 0xb4, 0x10, 0xff, 0x61, 0xf2, 0x00, 0x15, 0xad}; 67 68 static const uint8_t test_result_md5[] = { 69 0x90, 0x01, 0x50, 0x98, 0x3c, 0xd2, 0x4f, 0xb0, 0xd6, 0x96, 0x3f, 0x7d, 70 0x28, 0xe1, 0x7f, 0x72}; 71 72 /* 73 * The Scatter-Gather Test vector is the ascii "abc" "def" "ghi", broken 74 * into blocks of 3 characters as shown 75 * 76 * Expected results were generated using command line utitiles: 77 * 78 * echo -n -e 'abcdefghijkl' | dd of=/tmp/test 79 * for hash in sha512sum sha256sum; do $hash /tmp/test; done 80 * 81 */ 82 static const uint8_t test_vector_sg1[] = {0x61, 0x62, 0x63, 0x64, 0x65, 0x66}; 83 static const uint8_t test_vector_sg2[] = {0x67, 0x68, 0x69}; 84 static const uint8_t test_vector_sg3[] = {0x6a, 0x6b, 0x6c}; 85 86 static const uint8_t test_result_sg_sha512[] = { 87 0x17, 0x80, 0x7c, 0x72, 0x8e, 0xe3, 0xba, 0x35, 0xe7, 0xcf, 0x7a, 0xf8, 88 0x23, 0x11, 0x6d, 0x26, 0xe4, 0x1e, 0x5d, 0x4d, 0x6c, 0x2f, 0xf1, 0xf3, 89 0x72, 0x0d, 0x3d, 0x96, 0xaa, 0xcb, 0x6f, 0x69, 0xde, 0x64, 0x2e, 0x63, 90 0xd5, 0xb7, 0x3f, 0xc3, 0x96, 0xc1, 0x2b, 0xe3, 0x8b, 0x2b, 0xd5, 0xd8, 91 0x84, 0x25, 0x7c, 0x32, 0xc8, 0xf6, 0xd0, 0x85, 0x4a, 0xe6, 0xb5, 0x40, 92 0xf8, 0x6d, 0xda, 0x2e}; 93 94 static const uint8_t test_result_sg_sha256[] = { 95 0xd6, 0x82, 0xed, 0x4c, 0xa4, 0xd9, 0x89, 0xc1, 0x34, 0xec, 0x94, 0xf1, 96 0x55, 0x1e, 0x1e, 0xc5, 0x80, 0xdd, 0x6d, 0x5a, 0x6e, 0xcd, 0xe9, 0xf3, 97 0xd3, 0x5e, 0x6e, 0x4a, 0x71, 0x7f, 0xbd, 0xe4}; 98 99 100 static void write_regs(QTestState *s, uint32_t base, uint32_t src, 101 uint32_t length, uint32_t out, uint32_t method) 102 { 103 qtest_writel(s, base + HACE_HASH_SRC, src); 104 qtest_writel(s, base + HACE_HASH_DIGEST, out); 105 qtest_writel(s, base + HACE_HASH_DATA_LEN, length); 106 qtest_writel(s, base + HACE_HASH_CMD, HACE_SHA_BE_EN | method); 107 } 108 109 static void test_md5(const char *machine, const uint32_t base, 110 const uint32_t src_addr) 111 112 { 113 QTestState *s = qtest_init(machine); 114 115 uint32_t digest_addr = src_addr + 0x01000000; 116 uint8_t digest[16] = {0}; 117 118 /* Check engine is idle, no busy or irq bits set */ 119 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); 120 121 /* Write test vector into memory */ 122 qtest_memwrite(s, src_addr, test_vector, sizeof(test_vector)); 123 124 write_regs(s, base, src_addr, sizeof(test_vector), digest_addr, HACE_ALGO_MD5); 125 126 /* Check hash IRQ status is asserted */ 127 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200); 128 129 /* Clear IRQ status and check status is deasserted */ 130 qtest_writel(s, base + HACE_STS, 0x00000200); 131 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); 132 133 /* Read computed digest from memory */ 134 qtest_memread(s, digest_addr, digest, sizeof(digest)); 135 136 /* Check result of computation */ 137 g_assert_cmpmem(digest, sizeof(digest), 138 test_result_md5, sizeof(digest)); 139 140 qtest_quit(s); 141 } 142 143 static void test_sha256(const char *machine, const uint32_t base, 144 const uint32_t src_addr) 145 { 146 QTestState *s = qtest_init(machine); 147 148 const uint32_t digest_addr = src_addr + 0x1000000; 149 uint8_t digest[32] = {0}; 150 151 /* Check engine is idle, no busy or irq bits set */ 152 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); 153 154 /* Write test vector into memory */ 155 qtest_memwrite(s, src_addr, test_vector, sizeof(test_vector)); 156 157 write_regs(s, base, src_addr, sizeof(test_vector), digest_addr, HACE_ALGO_SHA256); 158 159 /* Check hash IRQ status is asserted */ 160 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200); 161 162 /* Clear IRQ status and check status is deasserted */ 163 qtest_writel(s, base + HACE_STS, 0x00000200); 164 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); 165 166 /* Read computed digest from memory */ 167 qtest_memread(s, digest_addr, digest, sizeof(digest)); 168 169 /* Check result of computation */ 170 g_assert_cmpmem(digest, sizeof(digest), 171 test_result_sha256, sizeof(digest)); 172 173 qtest_quit(s); 174 } 175 176 static void test_sha512(const char *machine, const uint32_t base, 177 const uint32_t src_addr) 178 { 179 QTestState *s = qtest_init(machine); 180 181 const uint32_t digest_addr = src_addr + 0x1000000; 182 uint8_t digest[64] = {0}; 183 184 /* Check engine is idle, no busy or irq bits set */ 185 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); 186 187 /* Write test vector into memory */ 188 qtest_memwrite(s, src_addr, test_vector, sizeof(test_vector)); 189 190 write_regs(s, base, src_addr, sizeof(test_vector), digest_addr, HACE_ALGO_SHA512); 191 192 /* Check hash IRQ status is asserted */ 193 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200); 194 195 /* Clear IRQ status and check status is deasserted */ 196 qtest_writel(s, base + HACE_STS, 0x00000200); 197 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); 198 199 /* Read computed digest from memory */ 200 qtest_memread(s, digest_addr, digest, sizeof(digest)); 201 202 /* Check result of computation */ 203 g_assert_cmpmem(digest, sizeof(digest), 204 test_result_sha512, sizeof(digest)); 205 206 qtest_quit(s); 207 } 208 209 static void test_sha256_sg(const char *machine, const uint32_t base, 210 const uint32_t src_addr) 211 { 212 QTestState *s = qtest_init(machine); 213 214 const uint32_t src_addr_1 = src_addr + 0x1000000; 215 const uint32_t src_addr_2 = src_addr + 0x2000000; 216 const uint32_t src_addr_3 = src_addr + 0x3000000; 217 const uint32_t digest_addr = src_addr + 0x4000000; 218 uint8_t digest[32] = {0}; 219 struct AspeedSgList array[] = { 220 { cpu_to_le32(sizeof(test_vector_sg1)), 221 cpu_to_le32(src_addr_1) }, 222 { cpu_to_le32(sizeof(test_vector_sg2)), 223 cpu_to_le32(src_addr_2) }, 224 { cpu_to_le32(sizeof(test_vector_sg3) | SG_LIST_LEN_LAST), 225 cpu_to_le32(src_addr_3) }, 226 }; 227 228 /* Check engine is idle, no busy or irq bits set */ 229 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); 230 231 /* Write test vector into memory */ 232 qtest_memwrite(s, src_addr_1, test_vector_sg1, sizeof(test_vector_sg1)); 233 qtest_memwrite(s, src_addr_2, test_vector_sg2, sizeof(test_vector_sg2)); 234 qtest_memwrite(s, src_addr_3, test_vector_sg3, sizeof(test_vector_sg3)); 235 qtest_memwrite(s, src_addr, array, sizeof(array)); 236 237 write_regs(s, base, src_addr, 238 (sizeof(test_vector_sg1) 239 + sizeof(test_vector_sg2) 240 + sizeof(test_vector_sg3)), 241 digest_addr, HACE_ALGO_SHA256 | HACE_SG_EN); 242 243 /* Check hash IRQ status is asserted */ 244 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200); 245 246 /* Clear IRQ status and check status is deasserted */ 247 qtest_writel(s, base + HACE_STS, 0x00000200); 248 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); 249 250 /* Read computed digest from memory */ 251 qtest_memread(s, digest_addr, digest, sizeof(digest)); 252 253 /* Check result of computation */ 254 g_assert_cmpmem(digest, sizeof(digest), 255 test_result_sg_sha256, sizeof(digest)); 256 257 qtest_quit(s); 258 } 259 260 static void test_sha512_sg(const char *machine, const uint32_t base, 261 const uint32_t src_addr) 262 { 263 QTestState *s = qtest_init(machine); 264 265 const uint32_t src_addr_1 = src_addr + 0x1000000; 266 const uint32_t src_addr_2 = src_addr + 0x2000000; 267 const uint32_t src_addr_3 = src_addr + 0x3000000; 268 const uint32_t digest_addr = src_addr + 0x4000000; 269 uint8_t digest[64] = {0}; 270 struct AspeedSgList array[] = { 271 { cpu_to_le32(sizeof(test_vector_sg1)), 272 cpu_to_le32(src_addr_1) }, 273 { cpu_to_le32(sizeof(test_vector_sg2)), 274 cpu_to_le32(src_addr_2) }, 275 { cpu_to_le32(sizeof(test_vector_sg3) | SG_LIST_LEN_LAST), 276 cpu_to_le32(src_addr_3) }, 277 }; 278 279 /* Check engine is idle, no busy or irq bits set */ 280 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); 281 282 /* Write test vector into memory */ 283 qtest_memwrite(s, src_addr_1, test_vector_sg1, sizeof(test_vector_sg1)); 284 qtest_memwrite(s, src_addr_2, test_vector_sg2, sizeof(test_vector_sg2)); 285 qtest_memwrite(s, src_addr_3, test_vector_sg3, sizeof(test_vector_sg3)); 286 qtest_memwrite(s, src_addr, array, sizeof(array)); 287 288 write_regs(s, base, src_addr, 289 (sizeof(test_vector_sg1) 290 + sizeof(test_vector_sg2) 291 + sizeof(test_vector_sg3)), 292 digest_addr, HACE_ALGO_SHA512 | HACE_SG_EN); 293 294 /* Check hash IRQ status is asserted */ 295 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200); 296 297 /* Clear IRQ status and check status is deasserted */ 298 qtest_writel(s, base + HACE_STS, 0x00000200); 299 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); 300 301 /* Read computed digest from memory */ 302 qtest_memread(s, digest_addr, digest, sizeof(digest)); 303 304 /* Check result of computation */ 305 g_assert_cmpmem(digest, sizeof(digest), 306 test_result_sg_sha512, sizeof(digest)); 307 308 qtest_quit(s); 309 } 310 311 struct masks { 312 uint32_t src; 313 uint32_t dest; 314 uint32_t len; 315 }; 316 317 static const struct masks ast2600_masks = { 318 .src = 0x7fffffff, 319 .dest = 0x7ffffff8, 320 .len = 0x0fffffff, 321 }; 322 323 static const struct masks ast2500_masks = { 324 .src = 0x3fffffff, 325 .dest = 0x3ffffff8, 326 .len = 0x0fffffff, 327 }; 328 329 static const struct masks ast2400_masks = { 330 .src = 0x0fffffff, 331 .dest = 0x0ffffff8, 332 .len = 0x0fffffff, 333 }; 334 335 static void test_addresses(const char *machine, const uint32_t base, 336 const struct masks *expected) 337 { 338 QTestState *s = qtest_init(machine); 339 340 /* 341 * Check command mode is zero, meaning engine is in direct access mode, 342 * as this affects the masking behavior of the HASH_SRC register. 343 */ 344 g_assert_cmphex(qtest_readl(s, base + HACE_CMD), ==, 0); 345 g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), ==, 0); 346 g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), ==, 0); 347 g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), ==, 0); 348 349 350 /* Check that the address masking is correct */ 351 qtest_writel(s, base + HACE_HASH_SRC, 0xffffffff); 352 g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), ==, expected->src); 353 354 qtest_writel(s, base + HACE_HASH_DIGEST, 0xffffffff); 355 g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), ==, expected->dest); 356 357 qtest_writel(s, base + HACE_HASH_DATA_LEN, 0xffffffff); 358 g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), ==, expected->len); 359 360 /* Reset to zero */ 361 qtest_writel(s, base + HACE_HASH_SRC, 0); 362 qtest_writel(s, base + HACE_HASH_DIGEST, 0); 363 qtest_writel(s, base + HACE_HASH_DATA_LEN, 0); 364 365 /* Check that all bits are now zero */ 366 g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), ==, 0); 367 g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), ==, 0); 368 g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), ==, 0); 369 370 qtest_quit(s); 371 } 372 373 /* ast2600 */ 374 static void test_md5_ast2600(void) 375 { 376 test_md5("-machine ast2600-evb", 0x1e6d0000, 0x80000000); 377 } 378 379 static void test_sha256_ast2600(void) 380 { 381 test_sha256("-machine ast2600-evb", 0x1e6d0000, 0x80000000); 382 } 383 384 static void test_sha256_sg_ast2600(void) 385 { 386 test_sha256_sg("-machine ast2600-evb", 0x1e6d0000, 0x80000000); 387 } 388 389 static void test_sha512_ast2600(void) 390 { 391 test_sha512("-machine ast2600-evb", 0x1e6d0000, 0x80000000); 392 } 393 394 static void test_sha512_sg_ast2600(void) 395 { 396 test_sha512_sg("-machine ast2600-evb", 0x1e6d0000, 0x80000000); 397 } 398 399 static void test_addresses_ast2600(void) 400 { 401 test_addresses("-machine ast2600-evb", 0x1e6d0000, &ast2600_masks); 402 } 403 404 /* ast2500 */ 405 static void test_md5_ast2500(void) 406 { 407 test_md5("-machine ast2500-evb", 0x1e6e3000, 0x80000000); 408 } 409 410 static void test_sha256_ast2500(void) 411 { 412 test_sha256("-machine ast2500-evb", 0x1e6e3000, 0x80000000); 413 } 414 415 static void test_sha512_ast2500(void) 416 { 417 test_sha512("-machine ast2500-evb", 0x1e6e3000, 0x80000000); 418 } 419 420 static void test_addresses_ast2500(void) 421 { 422 test_addresses("-machine ast2500-evb", 0x1e6e3000, &ast2500_masks); 423 } 424 425 /* ast2400 */ 426 static void test_md5_ast2400(void) 427 { 428 test_md5("-machine palmetto-bmc", 0x1e6e3000, 0x40000000); 429 } 430 431 static void test_sha256_ast2400(void) 432 { 433 test_sha256("-machine palmetto-bmc", 0x1e6e3000, 0x40000000); 434 } 435 436 static void test_sha512_ast2400(void) 437 { 438 test_sha512("-machine palmetto-bmc", 0x1e6e3000, 0x40000000); 439 } 440 441 static void test_addresses_ast2400(void) 442 { 443 test_addresses("-machine palmetto-bmc", 0x1e6e3000, &ast2400_masks); 444 } 445 446 int main(int argc, char **argv) 447 { 448 g_test_init(&argc, &argv, NULL); 449 450 qtest_add_func("ast2600/hace/addresses", test_addresses_ast2600); 451 qtest_add_func("ast2600/hace/sha512", test_sha512_ast2600); 452 qtest_add_func("ast2600/hace/sha256", test_sha256_ast2600); 453 qtest_add_func("ast2600/hace/md5", test_md5_ast2600); 454 455 qtest_add_func("ast2600/hace/sha512_sg", test_sha512_sg_ast2600); 456 qtest_add_func("ast2600/hace/sha256_sg", test_sha256_sg_ast2600); 457 458 qtest_add_func("ast2500/hace/addresses", test_addresses_ast2500); 459 qtest_add_func("ast2500/hace/sha512", test_sha512_ast2500); 460 qtest_add_func("ast2500/hace/sha256", test_sha256_ast2500); 461 qtest_add_func("ast2500/hace/md5", test_md5_ast2500); 462 463 qtest_add_func("ast2400/hace/addresses", test_addresses_ast2400); 464 qtest_add_func("ast2400/hace/sha512", test_sha512_ast2400); 465 qtest_add_func("ast2400/hace/sha256", test_sha256_ast2400); 466 qtest_add_func("ast2400/hace/md5", test_md5_ast2400); 467 468 return g_test_run(); 469 } 470