1 /* 2 * QTest testcase for the M25P80 Flash (Using the Aspeed SPI 3 * Controller) 4 * 5 * Copyright (C) 2016 IBM Corp. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #ifndef TESTS_ASPEED_SMC_UTILS_H 27 #define TESTS_ASPEED_SMC_UTILS_H 28 29 #include "qemu/osdep.h" 30 #include "qemu/bswap.h" 31 #include "libqtest-single.h" 32 #include "qemu/bitops.h" 33 34 /* 35 * ASPEED SPI Controller registers 36 */ 37 #define R_CONF 0x00 38 #define CONF_ENABLE_W0 16 39 #define R_CE_CTRL 0x04 40 #define CRTL_EXTENDED0 0 /* 32 bit addressing for SPI */ 41 #define R_CTRL0 0x10 42 #define CTRL_IO_QUAD_IO BIT(31) 43 #define CTRL_CE_STOP_ACTIVE BIT(2) 44 #define CTRL_READMODE 0x0 45 #define CTRL_FREADMODE 0x1 46 #define CTRL_WRITEMODE 0x2 47 #define CTRL_USERMODE 0x3 48 #define SR_WEL BIT(1) 49 50 /* 51 * Flash commands 52 */ 53 enum { 54 JEDEC_READ = 0x9f, 55 RDSR = 0x5, 56 WRDI = 0x4, 57 BULK_ERASE = 0xc7, 58 READ = 0x03, 59 PP = 0x02, 60 WRSR = 0x1, 61 WREN = 0x6, 62 SRWD = 0x80, 63 RESET_ENABLE = 0x66, 64 RESET_MEMORY = 0x99, 65 EN_4BYTE_ADDR = 0xB7, 66 ERASE_SECTOR = 0xd8, 67 }; 68 69 #define CTRL_IO_MODE_MASK (BIT(31) | BIT(30) | BIT(29) | BIT(28)) 70 #define FLASH_PAGE_SIZE 256 71 72 typedef struct AspeedSMCTestData { 73 QTestState *s; 74 uint64_t spi_base; 75 uint64_t flash_base; 76 uint32_t jedec_id; 77 char *tmp_path; 78 uint8_t cs; 79 const char *node; 80 uint32_t page_addr; 81 } AspeedSMCTestData; 82 83 void aspeed_smc_test_read_jedec(const void *data); 84 void aspeed_smc_test_erase_sector(const void *data); 85 void aspeed_smc_test_erase_all(const void *data); 86 void aspeed_smc_test_write_page(const void *data); 87 void aspeed_smc_test_read_page_mem(const void *data); 88 void aspeed_smc_test_write_page_mem(const void *data); 89 void aspeed_smc_test_read_status_reg(const void *data); 90 void aspeed_smc_test_status_reg_write_protection(const void *data); 91 void aspeed_smc_test_write_block_protect(const void *data); 92 void aspeed_smc_test_write_block_protect_bottom_bit(const void *data); 93 void aspeed_smc_test_write_page_qpi(const void *data); 94 95 #endif /* TESTS_ASPEED_SMC_UTILS_H */ 96