1 /* 2 * AHCI test cases 3 * 4 * Copyright (c) 2014 John Snow <jsnow@redhat.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include <getopt.h> 27 28 #include "libqtest.h" 29 #include "libqos/libqos-pc.h" 30 #include "libqos/ahci.h" 31 #include "libqos/pci-pc.h" 32 33 #include "qapi/qmp/qdict.h" 34 #include "qemu/host-utils.h" 35 36 #include "hw/pci/pci_ids.h" 37 #include "hw/pci/pci_regs.h" 38 39 /* Test images sizes in MB */ 40 #define TEST_IMAGE_SIZE_MB_LARGE (200 * 1024) 41 #define TEST_IMAGE_SIZE_MB_SMALL 64 42 43 /*** Globals ***/ 44 static char *tmp_path; 45 static char *debug_path; 46 static char *mig_socket; 47 static bool ahci_pedantic; 48 static const char *imgfmt; 49 static unsigned test_image_size_mb; 50 51 /*** Function Declarations ***/ 52 static void ahci_test_port_spec(AHCIQState *ahci, uint8_t port); 53 static void ahci_test_pci_spec(AHCIQState *ahci); 54 static void ahci_test_pci_caps(AHCIQState *ahci, uint16_t header, 55 uint8_t offset); 56 static void ahci_test_satacap(AHCIQState *ahci, uint8_t offset); 57 static void ahci_test_msicap(AHCIQState *ahci, uint8_t offset); 58 static void ahci_test_pmcap(AHCIQState *ahci, uint8_t offset); 59 60 /*** Utilities ***/ 61 62 static uint64_t mb_to_sectors(uint64_t image_size_mb) 63 { 64 return (image_size_mb * 1024 * 1024) / AHCI_SECTOR_SIZE; 65 } 66 67 static void string_bswap16(uint16_t *s, size_t bytes) 68 { 69 g_assert_cmphex((bytes & 1), ==, 0); 70 bytes /= 2; 71 72 while (bytes--) { 73 *s = bswap16(*s); 74 s++; 75 } 76 } 77 78 /** 79 * Verify that the transfer did not corrupt our state at all. 80 */ 81 static void verify_state(AHCIQState *ahci, uint64_t hba_old) 82 { 83 int i, j; 84 uint32_t ahci_fingerprint; 85 uint64_t hba_base; 86 AHCICommandHeader cmd; 87 88 ahci_fingerprint = qpci_config_readl(ahci->dev, PCI_VENDOR_ID); 89 g_assert_cmphex(ahci_fingerprint, ==, ahci->fingerprint); 90 91 /* If we haven't initialized, this is as much as can be validated. */ 92 if (!ahci->enabled) { 93 return; 94 } 95 96 hba_base = (uint64_t)qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5); 97 g_assert_cmphex(hba_base, ==, hba_old); 98 99 g_assert_cmphex(ahci_rreg(ahci, AHCI_CAP), ==, ahci->cap); 100 g_assert_cmphex(ahci_rreg(ahci, AHCI_CAP2), ==, ahci->cap2); 101 102 for (i = 0; i < 32; i++) { 103 g_assert_cmphex(ahci_px_rreg(ahci, i, AHCI_PX_FB), ==, 104 ahci->port[i].fb); 105 g_assert_cmphex(ahci_px_rreg(ahci, i, AHCI_PX_CLB), ==, 106 ahci->port[i].clb); 107 for (j = 0; j < 32; j++) { 108 ahci_get_command_header(ahci, i, j, &cmd); 109 g_assert_cmphex(cmd.prdtl, ==, ahci->port[i].prdtl[j]); 110 g_assert_cmphex(cmd.ctba, ==, ahci->port[i].ctba[j]); 111 } 112 } 113 } 114 115 static void ahci_migrate(AHCIQState *from, AHCIQState *to, const char *uri) 116 { 117 QOSState *tmp = to->parent; 118 QPCIDevice *dev = to->dev; 119 char *uri_local = NULL; 120 uint64_t hba_old; 121 122 if (uri == NULL) { 123 uri_local = g_strdup_printf("%s%s", "unix:", mig_socket); 124 uri = uri_local; 125 } 126 127 hba_old = (uint64_t)qpci_config_readl(from->dev, PCI_BASE_ADDRESS_5); 128 129 /* context will be 'to' after completion. */ 130 migrate(from->parent, to->parent, uri); 131 132 /* We'd like for the AHCIState objects to still point 133 * to information specific to its specific parent 134 * instance, but otherwise just inherit the new data. */ 135 memcpy(to, from, sizeof(AHCIQState)); 136 to->parent = tmp; 137 to->dev = dev; 138 139 tmp = from->parent; 140 dev = from->dev; 141 memset(from, 0x00, sizeof(AHCIQState)); 142 from->parent = tmp; 143 from->dev = dev; 144 145 verify_state(to, hba_old); 146 g_free(uri_local); 147 } 148 149 /*** Test Setup & Teardown ***/ 150 151 /** 152 * Start a Q35 machine and bookmark a handle to the AHCI device. 153 */ 154 G_GNUC_PRINTF(1, 0) 155 static AHCIQState *ahci_vboot(const char *cli, va_list ap) 156 { 157 AHCIQState *s; 158 159 s = g_new0(AHCIQState, 1); 160 s->parent = qtest_pc_vboot(cli, ap); 161 alloc_set_flags(&s->parent->alloc, ALLOC_LEAK_ASSERT); 162 163 /* Verify that we have an AHCI device present. */ 164 s->dev = get_ahci_device(s->parent->qts, &s->fingerprint); 165 166 return s; 167 } 168 169 /** 170 * Start a Q35 machine and bookmark a handle to the AHCI device. 171 */ 172 G_GNUC_PRINTF(1, 2) 173 static AHCIQState *ahci_boot(const char *cli, ...) 174 { 175 AHCIQState *s; 176 va_list ap; 177 178 if (cli) { 179 va_start(ap, cli); 180 s = ahci_vboot(cli, ap); 181 va_end(ap); 182 } else { 183 cli = "-drive if=none,id=drive0,file=%s,cache=writeback,format=%s" 184 " -M q35 " 185 "-device ide-hd,drive=drive0 " 186 "-global ide-hd.serial=%s " 187 "-global ide-hd.ver=%s"; 188 s = ahci_boot(cli, tmp_path, imgfmt, "testdisk", "version"); 189 } 190 191 return s; 192 } 193 194 /** 195 * Clean up the PCI device, then terminate the QEMU instance. 196 */ 197 static void ahci_shutdown(AHCIQState *ahci) 198 { 199 QOSState *qs = ahci->parent; 200 201 ahci_clean_mem(ahci); 202 free_ahci_device(ahci->dev); 203 g_free(ahci); 204 qtest_shutdown(qs); 205 } 206 207 /** 208 * Boot and fully enable the HBA device. 209 * @see ahci_boot, ahci_pci_enable and ahci_hba_enable. 210 */ 211 G_GNUC_PRINTF(1, 2) 212 static AHCIQState *ahci_boot_and_enable(const char *cli, ...) 213 { 214 AHCIQState *ahci; 215 va_list ap; 216 uint16_t buff[256]; 217 uint8_t port; 218 uint8_t hello; 219 220 if (cli) { 221 va_start(ap, cli); 222 ahci = ahci_vboot(cli, ap); 223 va_end(ap); 224 } else { 225 ahci = ahci_boot(NULL); 226 } 227 228 ahci_pci_enable(ahci); 229 ahci_hba_enable(ahci); 230 /* Initialize test device */ 231 port = ahci_port_select(ahci); 232 ahci_port_clear(ahci, port); 233 if (is_atapi(ahci, port)) { 234 hello = CMD_PACKET_ID; 235 } else { 236 hello = CMD_IDENTIFY; 237 } 238 ahci_io(ahci, port, hello, &buff, sizeof(buff), 0); 239 240 return ahci; 241 } 242 243 /*** Specification Adherence Tests ***/ 244 245 /** 246 * Implementation for test_pci_spec. Ensures PCI configuration space is sane. 247 */ 248 static void ahci_test_pci_spec(AHCIQState *ahci) 249 { 250 uint8_t datab; 251 uint16_t data; 252 uint32_t datal; 253 254 /* Most of these bits should start cleared until we turn them on. */ 255 data = qpci_config_readw(ahci->dev, PCI_COMMAND); 256 ASSERT_BIT_CLEAR(data, PCI_COMMAND_MEMORY); 257 ASSERT_BIT_CLEAR(data, PCI_COMMAND_MASTER); 258 ASSERT_BIT_CLEAR(data, PCI_COMMAND_SPECIAL); /* Reserved */ 259 ASSERT_BIT_CLEAR(data, PCI_COMMAND_VGA_PALETTE); /* Reserved */ 260 ASSERT_BIT_CLEAR(data, PCI_COMMAND_PARITY); 261 ASSERT_BIT_CLEAR(data, PCI_COMMAND_WAIT); /* Reserved */ 262 ASSERT_BIT_CLEAR(data, PCI_COMMAND_SERR); 263 ASSERT_BIT_CLEAR(data, PCI_COMMAND_FAST_BACK); 264 ASSERT_BIT_CLEAR(data, PCI_COMMAND_INTX_DISABLE); 265 ASSERT_BIT_CLEAR(data, 0xF800); /* Reserved */ 266 267 data = qpci_config_readw(ahci->dev, PCI_STATUS); 268 ASSERT_BIT_CLEAR(data, 0x01 | 0x02 | 0x04); /* Reserved */ 269 ASSERT_BIT_CLEAR(data, PCI_STATUS_INTERRUPT); 270 ASSERT_BIT_SET(data, PCI_STATUS_CAP_LIST); /* must be set */ 271 ASSERT_BIT_CLEAR(data, PCI_STATUS_UDF); /* Reserved */ 272 ASSERT_BIT_CLEAR(data, PCI_STATUS_PARITY); 273 ASSERT_BIT_CLEAR(data, PCI_STATUS_SIG_TARGET_ABORT); 274 ASSERT_BIT_CLEAR(data, PCI_STATUS_REC_TARGET_ABORT); 275 ASSERT_BIT_CLEAR(data, PCI_STATUS_REC_MASTER_ABORT); 276 ASSERT_BIT_CLEAR(data, PCI_STATUS_SIG_SYSTEM_ERROR); 277 ASSERT_BIT_CLEAR(data, PCI_STATUS_DETECTED_PARITY); 278 279 /* RID occupies the low byte, CCs occupy the high three. */ 280 datal = qpci_config_readl(ahci->dev, PCI_CLASS_REVISION); 281 if (ahci_pedantic) { 282 /* AHCI 1.3 specifies that at-boot, the RID should reset to 0x00, 283 * Though in practice this is likely seldom true. */ 284 ASSERT_BIT_CLEAR(datal, 0xFF); 285 } 286 287 /* BCC *must* equal 0x01. */ 288 g_assert_cmphex(PCI_BCC(datal), ==, 0x01); 289 if (PCI_SCC(datal) == 0x01) { 290 /* IDE */ 291 ASSERT_BIT_SET(0x80000000, datal); 292 ASSERT_BIT_CLEAR(0x60000000, datal); 293 } else if (PCI_SCC(datal) == 0x04) { 294 /* RAID */ 295 g_assert_cmphex(PCI_PI(datal), ==, 0); 296 } else if (PCI_SCC(datal) == 0x06) { 297 /* AHCI */ 298 g_assert_cmphex(PCI_PI(datal), ==, 0x01); 299 } else { 300 g_assert_not_reached(); 301 } 302 303 datab = qpci_config_readb(ahci->dev, PCI_CACHE_LINE_SIZE); 304 g_assert_cmphex(datab, ==, 0); 305 306 datab = qpci_config_readb(ahci->dev, PCI_LATENCY_TIMER); 307 g_assert_cmphex(datab, ==, 0); 308 309 /* Only the bottom 7 bits must be off. */ 310 datab = qpci_config_readb(ahci->dev, PCI_HEADER_TYPE); 311 ASSERT_BIT_CLEAR(datab, 0x7F); 312 313 /* BIST is optional, but the low 7 bits must always start off regardless. */ 314 datab = qpci_config_readb(ahci->dev, PCI_BIST); 315 ASSERT_BIT_CLEAR(datab, 0x7F); 316 317 /* BARS 0-4 do not have a boot spec, but ABAR/BAR5 must be clean. */ 318 datal = qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5); 319 g_assert_cmphex(datal, ==, 0); 320 321 qpci_config_writel(ahci->dev, PCI_BASE_ADDRESS_5, 0xFFFFFFFF); 322 datal = qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5); 323 /* ABAR must be 32-bit, memory mapped, non-prefetchable and 324 * must be >= 512 bytes. To that end, bits 0-8 must be off. */ 325 ASSERT_BIT_CLEAR(datal, 0xFF); 326 327 /* Capability list MUST be present, */ 328 datal = qpci_config_readl(ahci->dev, PCI_CAPABILITY_LIST); 329 /* But these bits are reserved. */ 330 ASSERT_BIT_CLEAR(datal, ~0xFF); 331 g_assert_cmphex(datal, !=, 0); 332 333 /* Check specification adherence for capability extensions. */ 334 data = qpci_config_readw(ahci->dev, datal); 335 336 switch (ahci->fingerprint) { 337 case AHCI_INTEL_ICH9: 338 /* Intel ICH9 Family Datasheet 14.1.19 p.550 */ 339 g_assert_cmphex((data & 0xFF), ==, PCI_CAP_ID_MSI); 340 break; 341 default: 342 /* AHCI 1.3, Section 2.1.14 -- CAP must point to PMCAP. */ 343 g_assert_cmphex((data & 0xFF), ==, PCI_CAP_ID_PM); 344 } 345 346 ahci_test_pci_caps(ahci, data, (uint8_t)datal); 347 348 /* Reserved. */ 349 datal = qpci_config_readl(ahci->dev, PCI_CAPABILITY_LIST + 4); 350 g_assert_cmphex(datal, ==, 0); 351 352 /* IPIN might vary, but ILINE must be off. */ 353 datab = qpci_config_readb(ahci->dev, PCI_INTERRUPT_LINE); 354 g_assert_cmphex(datab, ==, 0); 355 } 356 357 /** 358 * Test PCI capabilities for AHCI specification adherence. 359 */ 360 static void ahci_test_pci_caps(AHCIQState *ahci, uint16_t header, 361 uint8_t offset) 362 { 363 uint8_t cid = header & 0xFF; 364 uint8_t next = header >> 8; 365 366 g_test_message("CID: %02x; next: %02x", cid, next); 367 368 switch (cid) { 369 case PCI_CAP_ID_PM: 370 ahci_test_pmcap(ahci, offset); 371 break; 372 case PCI_CAP_ID_MSI: 373 ahci_test_msicap(ahci, offset); 374 break; 375 case PCI_CAP_ID_SATA: 376 ahci_test_satacap(ahci, offset); 377 break; 378 379 default: 380 g_test_message("Unknown CAP 0x%02x", cid); 381 } 382 383 if (next) { 384 ahci_test_pci_caps(ahci, qpci_config_readw(ahci->dev, next), next); 385 } 386 } 387 388 /** 389 * Test SATA PCI capabilitity for AHCI specification adherence. 390 */ 391 static void ahci_test_satacap(AHCIQState *ahci, uint8_t offset) 392 { 393 uint16_t dataw; 394 uint32_t datal; 395 396 g_test_message("Verifying SATACAP"); 397 398 /* Assert that the SATACAP version is 1.0, And reserved bits are empty. */ 399 dataw = qpci_config_readw(ahci->dev, offset + 2); 400 g_assert_cmphex(dataw, ==, 0x10); 401 402 /* Grab the SATACR1 register. */ 403 datal = qpci_config_readw(ahci->dev, offset + 4); 404 405 switch (datal & 0x0F) { 406 case 0x04: /* BAR0 */ 407 case 0x05: /* BAR1 */ 408 case 0x06: 409 case 0x07: 410 case 0x08: 411 case 0x09: /* BAR5 */ 412 case 0x0F: /* Immediately following SATACR1 in PCI config space. */ 413 break; 414 default: 415 /* Invalid BARLOC for the Index Data Pair. */ 416 g_assert_not_reached(); 417 } 418 419 /* Reserved. */ 420 g_assert_cmphex((datal >> 24), ==, 0x00); 421 } 422 423 /** 424 * Test MSI PCI capability for AHCI specification adherence. 425 */ 426 static void ahci_test_msicap(AHCIQState *ahci, uint8_t offset) 427 { 428 uint16_t dataw; 429 uint32_t datal; 430 431 g_test_message("Verifying MSICAP"); 432 433 dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_FLAGS); 434 ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_ENABLE); 435 ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_QSIZE); 436 ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_RESERVED); 437 438 datal = qpci_config_readl(ahci->dev, offset + PCI_MSI_ADDRESS_LO); 439 g_assert_cmphex(datal, ==, 0); 440 441 if (dataw & PCI_MSI_FLAGS_64BIT) { 442 g_test_message("MSICAP is 64bit"); 443 datal = qpci_config_readl(ahci->dev, offset + PCI_MSI_ADDRESS_HI); 444 g_assert_cmphex(datal, ==, 0); 445 dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_DATA_64); 446 g_assert_cmphex(dataw, ==, 0); 447 } else { 448 g_test_message("MSICAP is 32bit"); 449 dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_DATA_32); 450 g_assert_cmphex(dataw, ==, 0); 451 } 452 } 453 454 /** 455 * Test Power Management PCI capability for AHCI specification adherence. 456 */ 457 static void ahci_test_pmcap(AHCIQState *ahci, uint8_t offset) 458 { 459 uint16_t dataw; 460 461 g_test_message("Verifying PMCAP"); 462 463 dataw = qpci_config_readw(ahci->dev, offset + PCI_PM_PMC); 464 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_PME_CLOCK); 465 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_RESERVED); 466 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_D1); 467 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_D2); 468 469 dataw = qpci_config_readw(ahci->dev, offset + PCI_PM_CTRL); 470 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_STATE_MASK); 471 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_RESERVED); 472 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_DATA_SEL_MASK); 473 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_DATA_SCALE_MASK); 474 } 475 476 static void ahci_test_hba_spec(AHCIQState *ahci) 477 { 478 unsigned i; 479 uint32_t reg; 480 uint32_t ports; 481 uint8_t nports_impl; 482 uint8_t maxports; 483 484 g_assert(ahci != NULL); 485 486 /* 487 * Note that the AHCI spec does expect the BIOS to set up a few things: 488 * CAP.SSS - Support for staggered spin-up (t/f) 489 * CAP.SMPS - Support for mechanical presence switches (t/f) 490 * PI - Ports Implemented (1-32) 491 * PxCMD.HPCP - Hot Plug Capable Port 492 * PxCMD.MPSP - Mechanical Presence Switch Present 493 * PxCMD.CPD - Cold Presence Detection support 494 * 495 * Additional items are touched if CAP.SSS is on, see AHCI 10.1.1 p.97: 496 * Foreach Port Implemented: 497 * -PxCMD.ST, PxCMD.CR, PxCMD.FRE, PxCMD.FR, PxSCTL.DET are 0 498 * -PxCLB/U and PxFB/U are set to valid regions in memory 499 * -PxSUD is set to 1. 500 * -PxSSTS.DET is polled for presence; if detected, we continue: 501 * -PxSERR is cleared with 1's. 502 * -If PxTFD.STS.BSY, PxTFD.STS.DRQ, and PxTFD.STS.ERR are all zero, 503 * the device is ready. 504 */ 505 506 /* 1 CAP - Capabilities Register */ 507 ahci->cap = ahci_rreg(ahci, AHCI_CAP); 508 ASSERT_BIT_CLEAR(ahci->cap, AHCI_CAP_RESERVED); 509 510 /* 2 GHC - Global Host Control */ 511 reg = ahci_rreg(ahci, AHCI_GHC); 512 ASSERT_BIT_CLEAR(reg, AHCI_GHC_HR); 513 ASSERT_BIT_CLEAR(reg, AHCI_GHC_IE); 514 ASSERT_BIT_CLEAR(reg, AHCI_GHC_MRSM); 515 if (BITSET(ahci->cap, AHCI_CAP_SAM)) { 516 g_test_message("Supports AHCI-Only Mode: GHC_AE is Read-Only."); 517 ASSERT_BIT_SET(reg, AHCI_GHC_AE); 518 } else { 519 g_test_message("Supports AHCI/Legacy mix."); 520 ASSERT_BIT_CLEAR(reg, AHCI_GHC_AE); 521 } 522 523 /* 3 IS - Interrupt Status */ 524 reg = ahci_rreg(ahci, AHCI_IS); 525 g_assert_cmphex(reg, ==, 0); 526 527 /* 4 PI - Ports Implemented */ 528 ports = ahci_rreg(ahci, AHCI_PI); 529 /* Ports Implemented must be non-zero. */ 530 g_assert_cmphex(ports, !=, 0); 531 /* Ports Implemented must be <= Number of Ports. */ 532 nports_impl = ctpopl(ports); 533 g_assert_cmpuint(((AHCI_CAP_NP & ahci->cap) + 1), >=, nports_impl); 534 535 /* Ports must be within the proper range. Given a mapping of SIZE, 536 * 256 bytes are used for global HBA control, and the rest is used 537 * for ports data, at 0x80 bytes each. */ 538 g_assert_cmphex(ahci->barsize, >, 0); 539 maxports = (ahci->barsize - HBA_DATA_REGION_SIZE) / HBA_PORT_DATA_SIZE; 540 /* e.g, 30 ports for 4K of memory. (4096 - 256) / 128 = 30 */ 541 g_assert_cmphex((reg >> maxports), ==, 0); 542 543 /* 5 AHCI Version */ 544 reg = ahci_rreg(ahci, AHCI_VS); 545 switch (reg) { 546 case AHCI_VERSION_0_95: 547 case AHCI_VERSION_1_0: 548 case AHCI_VERSION_1_1: 549 case AHCI_VERSION_1_2: 550 case AHCI_VERSION_1_3: 551 break; 552 default: 553 g_assert_not_reached(); 554 } 555 556 /* 6 Command Completion Coalescing Control: depends on CAP.CCCS. */ 557 reg = ahci_rreg(ahci, AHCI_CCCCTL); 558 if (BITSET(ahci->cap, AHCI_CAP_CCCS)) { 559 ASSERT_BIT_CLEAR(reg, AHCI_CCCCTL_EN); 560 ASSERT_BIT_CLEAR(reg, AHCI_CCCCTL_RESERVED); 561 ASSERT_BIT_SET(reg, AHCI_CCCCTL_CC); 562 ASSERT_BIT_SET(reg, AHCI_CCCCTL_TV); 563 } else { 564 g_assert_cmphex(reg, ==, 0); 565 } 566 567 /* 7 CCC_PORTS */ 568 reg = ahci_rreg(ahci, AHCI_CCCPORTS); 569 /* Must be zeroes initially regardless of CAP.CCCS */ 570 g_assert_cmphex(reg, ==, 0); 571 572 /* 8 EM_LOC */ 573 reg = ahci_rreg(ahci, AHCI_EMLOC); 574 if (BITCLR(ahci->cap, AHCI_CAP_EMS)) { 575 g_assert_cmphex(reg, ==, 0); 576 } 577 578 /* 9 EM_CTL */ 579 reg = ahci_rreg(ahci, AHCI_EMCTL); 580 if (BITSET(ahci->cap, AHCI_CAP_EMS)) { 581 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_STSMR); 582 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_CTLTM); 583 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_CTLRST); 584 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_RESERVED); 585 } else { 586 g_assert_cmphex(reg, ==, 0); 587 } 588 589 /* 10 CAP2 -- Capabilities Extended */ 590 ahci->cap2 = ahci_rreg(ahci, AHCI_CAP2); 591 ASSERT_BIT_CLEAR(ahci->cap2, AHCI_CAP2_RESERVED); 592 593 /* 11 BOHC -- Bios/OS Handoff Control */ 594 reg = ahci_rreg(ahci, AHCI_BOHC); 595 g_assert_cmphex(reg, ==, 0); 596 597 /* 12 -- 23: Reserved */ 598 g_test_message("Verifying HBA reserved area is empty."); 599 for (i = AHCI_RESERVED; i < AHCI_NVMHCI; ++i) { 600 reg = ahci_rreg(ahci, i); 601 g_assert_cmphex(reg, ==, 0); 602 } 603 604 /* 24 -- 39: NVMHCI */ 605 if (BITCLR(ahci->cap2, AHCI_CAP2_NVMP)) { 606 g_test_message("Verifying HBA/NVMHCI area is empty."); 607 for (i = AHCI_NVMHCI; i < AHCI_VENDOR; ++i) { 608 reg = ahci_rreg(ahci, i); 609 g_assert_cmphex(reg, ==, 0); 610 } 611 } 612 613 /* 40 -- 63: Vendor */ 614 g_test_message("Verifying HBA/Vendor area is empty."); 615 for (i = AHCI_VENDOR; i < AHCI_PORTS; ++i) { 616 reg = ahci_rreg(ahci, i); 617 g_assert_cmphex(reg, ==, 0); 618 } 619 620 /* 64 -- XX: Port Space */ 621 for (i = 0; ports || (i < maxports); ports >>= 1, ++i) { 622 if (BITSET(ports, 0x1)) { 623 g_test_message("Testing port %u for spec", i); 624 ahci_test_port_spec(ahci, i); 625 } else { 626 uint16_t j; 627 uint16_t low = AHCI_PORTS + (32 * i); 628 uint16_t high = AHCI_PORTS + (32 * (i + 1)); 629 g_test_message("Asserting unimplemented port %u " 630 "(reg [%u-%u]) is empty.", 631 i, low, high - 1); 632 for (j = low; j < high; ++j) { 633 reg = ahci_rreg(ahci, j); 634 g_assert_cmphex(reg, ==, 0); 635 } 636 } 637 } 638 } 639 640 /** 641 * Test the memory space for one port for specification adherence. 642 */ 643 static void ahci_test_port_spec(AHCIQState *ahci, uint8_t port) 644 { 645 uint32_t reg; 646 unsigned i; 647 648 /* (0) CLB */ 649 reg = ahci_px_rreg(ahci, port, AHCI_PX_CLB); 650 ASSERT_BIT_CLEAR(reg, AHCI_PX_CLB_RESERVED); 651 652 /* (1) CLBU */ 653 if (BITCLR(ahci->cap, AHCI_CAP_S64A)) { 654 reg = ahci_px_rreg(ahci, port, AHCI_PX_CLBU); 655 g_assert_cmphex(reg, ==, 0); 656 } 657 658 /* (2) FB */ 659 reg = ahci_px_rreg(ahci, port, AHCI_PX_FB); 660 ASSERT_BIT_CLEAR(reg, AHCI_PX_FB_RESERVED); 661 662 /* (3) FBU */ 663 if (BITCLR(ahci->cap, AHCI_CAP_S64A)) { 664 reg = ahci_px_rreg(ahci, port, AHCI_PX_FBU); 665 g_assert_cmphex(reg, ==, 0); 666 } 667 668 /* (4) IS */ 669 reg = ahci_px_rreg(ahci, port, AHCI_PX_IS); 670 g_assert_cmphex(reg, ==, 0); 671 672 /* (5) IE */ 673 reg = ahci_px_rreg(ahci, port, AHCI_PX_IE); 674 g_assert_cmphex(reg, ==, 0); 675 676 /* (6) CMD */ 677 reg = ahci_px_rreg(ahci, port, AHCI_PX_CMD); 678 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FRE); 679 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_RESERVED); 680 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CCS); 681 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FR); 682 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CR); 683 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_PMA); /* And RW only if CAP.SPM */ 684 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_APSTE); /* RW only if CAP2.APST */ 685 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ATAPI); 686 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_DLAE); 687 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ALPE); /* RW only if CAP.SALP */ 688 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ASP); /* RW only if CAP.SALP */ 689 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ICC); 690 /* If CPDetect support does not exist, CPState must be off. */ 691 if (BITCLR(reg, AHCI_PX_CMD_CPD)) { 692 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CPS); 693 } 694 /* If MPSPresence is not set, MPSState must be off. */ 695 if (BITCLR(reg, AHCI_PX_CMD_MPSP)) { 696 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSS); 697 } 698 /* If we do not support MPS, MPSS and MPSP must be off. */ 699 if (BITCLR(ahci->cap, AHCI_CAP_SMPS)) { 700 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSS); 701 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSP); 702 } 703 /* If, via CPD or MPSP we detect a drive, HPCP must be on. */ 704 if (BITANY(reg, AHCI_PX_CMD_CPD | AHCI_PX_CMD_MPSP)) { 705 ASSERT_BIT_SET(reg, AHCI_PX_CMD_HPCP); 706 } 707 /* HPCP and ESP cannot both be active. */ 708 g_assert(!BITSET(reg, AHCI_PX_CMD_HPCP | AHCI_PX_CMD_ESP)); 709 /* If CAP.FBSS is not set, FBSCP must not be set. */ 710 if (BITCLR(ahci->cap, AHCI_CAP_FBSS)) { 711 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FBSCP); 712 } 713 714 /* (7) RESERVED */ 715 reg = ahci_px_rreg(ahci, port, AHCI_PX_RES1); 716 g_assert_cmphex(reg, ==, 0); 717 718 /* (8) TFD */ 719 reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD); 720 /* At boot, prior to an FIS being received, the TFD register should be 0x7F, 721 * which breaks down as follows, as seen in AHCI 1.3 sec 3.3.8, p. 27. */ 722 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_ERR); 723 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_CS1); 724 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_DRQ); 725 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_CS2); 726 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_BSY); 727 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_ERR); 728 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_RESERVED); 729 730 /* (9) SIG */ 731 /* Though AHCI specifies the boot value should be 0xFFFFFFFF, 732 * Even when GHC.ST is zero, the AHCI HBA may receive the initial 733 * D2H register FIS and update the signature asynchronously, 734 * so we cannot expect a value here. AHCI 1.3, sec 3.3.9, pp 27-28 */ 735 736 /* (10) SSTS / SCR0: SStatus */ 737 reg = ahci_px_rreg(ahci, port, AHCI_PX_SSTS); 738 ASSERT_BIT_CLEAR(reg, AHCI_PX_SSTS_RESERVED); 739 /* Even though the register should be 0 at boot, it is asynchronous and 740 * prone to change, so we cannot test any well known value. */ 741 742 /* (11) SCTL / SCR2: SControl */ 743 reg = ahci_px_rreg(ahci, port, AHCI_PX_SCTL); 744 g_assert_cmphex(reg, ==, 0); 745 746 /* (12) SERR / SCR1: SError */ 747 reg = ahci_px_rreg(ahci, port, AHCI_PX_SERR); 748 g_assert_cmphex(reg, ==, 0); 749 750 /* (13) SACT / SCR3: SActive */ 751 reg = ahci_px_rreg(ahci, port, AHCI_PX_SACT); 752 g_assert_cmphex(reg, ==, 0); 753 754 /* (14) CI */ 755 reg = ahci_px_rreg(ahci, port, AHCI_PX_CI); 756 g_assert_cmphex(reg, ==, 0); 757 758 /* (15) SNTF */ 759 reg = ahci_px_rreg(ahci, port, AHCI_PX_SNTF); 760 g_assert_cmphex(reg, ==, 0); 761 762 /* (16) FBS */ 763 reg = ahci_px_rreg(ahci, port, AHCI_PX_FBS); 764 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_EN); 765 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DEC); 766 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_SDE); 767 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DEV); 768 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DWE); 769 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_RESERVED); 770 if (BITSET(ahci->cap, AHCI_CAP_FBSS)) { 771 /* if Port-Multiplier FIS-based switching avail, ADO must >= 2 */ 772 g_assert((reg & AHCI_PX_FBS_ADO) >> ctzl(AHCI_PX_FBS_ADO) >= 2); 773 } 774 775 /* [17 -- 27] RESERVED */ 776 for (i = AHCI_PX_RES2; i < AHCI_PX_VS; ++i) { 777 reg = ahci_px_rreg(ahci, port, i); 778 g_assert_cmphex(reg, ==, 0); 779 } 780 781 /* [28 -- 31] Vendor-Specific */ 782 for (i = AHCI_PX_VS; i < 32; ++i) { 783 reg = ahci_px_rreg(ahci, port, i); 784 if (reg) { 785 g_test_message("INFO: Vendor register %u non-empty", i); 786 } 787 } 788 } 789 790 /** 791 * Utilizing an initialized AHCI HBA, issue an IDENTIFY command to the first 792 * device we see, then read and check the response. 793 */ 794 static void ahci_test_identify(AHCIQState *ahci) 795 { 796 uint16_t buff[256]; 797 unsigned px; 798 int rc; 799 uint16_t sect_size; 800 const size_t buffsize = 512; 801 802 g_assert(ahci != NULL); 803 804 /** 805 * This serves as a bit of a tutorial on AHCI device programming: 806 * 807 * (1) Create a data buffer for the IDENTIFY response to be sent to 808 * (2) Create a Command Table buffer, where we will store the 809 * command and PRDT (Physical Region Descriptor Table) 810 * (3) Construct an FIS host-to-device command structure, and write it to 811 * the top of the Command Table buffer. 812 * (4) Create one or more Physical Region Descriptors (PRDs) that describe 813 * a location in memory where data may be stored/retrieved. 814 * (5) Write these PRDTs to the bottom (offset 0x80) of the Command Table. 815 * (6) Each AHCI port has up to 32 command slots. Each slot contains a 816 * header that points to a Command Table buffer. Pick an unused slot 817 * and update it to point to the Command Table we have built. 818 * (7) Now: Command #n points to our Command Table, and our Command Table 819 * contains the FIS (that describes our command) and the PRDTL, which 820 * describes our buffer. 821 * (8) We inform the HBA via PxCI (Command Issue) that the command in slot 822 * #n is ready for processing. 823 */ 824 825 /* Pick the first implemented and running port */ 826 px = ahci_port_select(ahci); 827 g_test_message("Selected port %u for test", px); 828 829 /* Clear out the FIS Receive area and any pending interrupts. */ 830 ahci_port_clear(ahci, px); 831 832 /* "Read" 512 bytes using CMD_IDENTIFY into the host buffer. */ 833 ahci_io(ahci, px, CMD_IDENTIFY, &buff, buffsize, 0); 834 835 /* Check serial number/version in the buffer */ 836 /* NB: IDENTIFY strings are packed in 16bit little endian chunks. 837 * Since we copy byte-for-byte in ahci-test, on both LE and BE, we need to 838 * unchunk this data. By contrast, ide-test copies 2 bytes at a time, and 839 * as a consequence, only needs to unchunk the data on LE machines. */ 840 string_bswap16(&buff[10], 20); 841 rc = memcmp(&buff[10], "testdisk ", 20); 842 g_assert_cmphex(rc, ==, 0); 843 844 string_bswap16(&buff[23], 8); 845 rc = memcmp(&buff[23], "version ", 8); 846 g_assert_cmphex(rc, ==, 0); 847 848 sect_size = le16_to_cpu(*((uint16_t *)(&buff[5]))); 849 g_assert_cmphex(sect_size, ==, AHCI_SECTOR_SIZE); 850 } 851 852 static void ahci_test_io_rw_simple(AHCIQState *ahci, unsigned bufsize, 853 uint64_t sector, uint8_t read_cmd, 854 uint8_t write_cmd) 855 { 856 uint64_t ptr; 857 uint8_t port; 858 unsigned char *tx = g_malloc(bufsize); 859 unsigned char *rx = g_malloc0(bufsize); 860 861 g_assert(ahci != NULL); 862 863 /* Pick the first running port and clear it. */ 864 port = ahci_port_select(ahci); 865 ahci_port_clear(ahci, port); 866 867 /*** Create pattern and transfer to guest ***/ 868 /* Data buffer in the guest */ 869 ptr = ahci_alloc(ahci, bufsize); 870 g_assert(ptr); 871 872 /* Write some indicative pattern to our buffer. */ 873 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE); 874 qtest_bufwrite(ahci->parent->qts, ptr, tx, bufsize); 875 876 /* Write this buffer to disk, then read it back to the DMA buffer. */ 877 ahci_guest_io(ahci, port, write_cmd, ptr, bufsize, sector); 878 qtest_memset(ahci->parent->qts, ptr, 0x00, bufsize); 879 ahci_guest_io(ahci, port, read_cmd, ptr, bufsize, sector); 880 881 /*** Read back the Data ***/ 882 qtest_bufread(ahci->parent->qts, ptr, rx, bufsize); 883 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0); 884 885 ahci_free(ahci, ptr); 886 g_free(tx); 887 g_free(rx); 888 } 889 890 static uint8_t ahci_test_nondata(AHCIQState *ahci, uint8_t ide_cmd) 891 { 892 uint8_t port; 893 894 /* Sanitize */ 895 port = ahci_port_select(ahci); 896 ahci_port_clear(ahci, port); 897 898 ahci_io(ahci, port, ide_cmd, NULL, 0, 0); 899 900 return port; 901 } 902 903 static void ahci_test_flush(AHCIQState *ahci) 904 { 905 ahci_test_nondata(ahci, CMD_FLUSH_CACHE); 906 } 907 908 static void ahci_test_max(AHCIQState *ahci) 909 { 910 RegD2HFIS *d2h = g_malloc0(0x20); 911 uint64_t nsect; 912 uint8_t port; 913 uint8_t cmd; 914 uint64_t config_sect = mb_to_sectors(test_image_size_mb) - 1; 915 916 if (config_sect > 0xFFFFFF) { 917 cmd = CMD_READ_MAX_EXT; 918 } else { 919 cmd = CMD_READ_MAX; 920 } 921 922 port = ahci_test_nondata(ahci, cmd); 923 qtest_memread(ahci->parent->qts, ahci->port[port].fb + 0x40, d2h, 0x20); 924 nsect = (uint64_t)d2h->lba_hi[2] << 40 | 925 (uint64_t)d2h->lba_hi[1] << 32 | 926 (uint64_t)d2h->lba_hi[0] << 24 | 927 (uint64_t)d2h->lba_lo[2] << 16 | 928 (uint64_t)d2h->lba_lo[1] << 8 | 929 (uint64_t)d2h->lba_lo[0]; 930 931 g_assert_cmphex(nsect, ==, config_sect); 932 g_free(d2h); 933 } 934 935 936 /******************************************************************************/ 937 /* Test Interfaces */ 938 /******************************************************************************/ 939 940 /** 941 * Basic sanity test to boot a machine, find an AHCI device, and shutdown. 942 */ 943 static void test_sanity(void) 944 { 945 AHCIQState *ahci; 946 ahci = ahci_boot(NULL); 947 ahci_shutdown(ahci); 948 } 949 950 /** 951 * Ensure that the PCI configuration space for the AHCI device is in-line with 952 * the AHCI 1.3 specification for initial values. 953 */ 954 static void test_pci_spec(void) 955 { 956 AHCIQState *ahci; 957 ahci = ahci_boot(NULL); 958 ahci_test_pci_spec(ahci); 959 ahci_shutdown(ahci); 960 } 961 962 /** 963 * Engage the PCI AHCI device and sanity check the response. 964 * Perform additional PCI config space bringup for the HBA. 965 */ 966 static void test_pci_enable(void) 967 { 968 AHCIQState *ahci; 969 ahci = ahci_boot(NULL); 970 ahci_pci_enable(ahci); 971 ahci_shutdown(ahci); 972 } 973 974 /** 975 * Investigate the memory mapped regions of the HBA, 976 * and test them for AHCI specification adherence. 977 */ 978 static void test_hba_spec(void) 979 { 980 AHCIQState *ahci; 981 982 ahci = ahci_boot(NULL); 983 ahci_pci_enable(ahci); 984 ahci_test_hba_spec(ahci); 985 ahci_shutdown(ahci); 986 } 987 988 /** 989 * Engage the HBA functionality of the AHCI PCI device, 990 * and bring it into a functional idle state. 991 */ 992 static void test_hba_enable(void) 993 { 994 AHCIQState *ahci; 995 996 ahci = ahci_boot(NULL); 997 ahci_pci_enable(ahci); 998 ahci_hba_enable(ahci); 999 ahci_shutdown(ahci); 1000 } 1001 1002 /** 1003 * Bring up the device and issue an IDENTIFY command. 1004 * Inspect the state of the HBA device and the data returned. 1005 */ 1006 static void test_identify(void) 1007 { 1008 AHCIQState *ahci; 1009 1010 ahci = ahci_boot_and_enable(NULL); 1011 ahci_test_identify(ahci); 1012 ahci_shutdown(ahci); 1013 } 1014 1015 /** 1016 * Fragmented DMA test: Perform a standard 4K DMA read/write 1017 * test, but make sure the physical regions are fragmented to 1018 * be very small, each just 32 bytes, to see how AHCI performs 1019 * with chunks defined to be much less than a sector. 1020 */ 1021 static void test_dma_fragmented(void) 1022 { 1023 AHCIQState *ahci; 1024 AHCICommand *cmd; 1025 uint8_t px; 1026 size_t bufsize = 4096; 1027 unsigned char *tx = g_malloc(bufsize); 1028 unsigned char *rx = g_malloc0(bufsize); 1029 uint64_t ptr; 1030 1031 ahci = ahci_boot_and_enable(NULL); 1032 px = ahci_port_select(ahci); 1033 ahci_port_clear(ahci, px); 1034 1035 /* create pattern */ 1036 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE); 1037 1038 /* Create a DMA buffer in guest memory, and write our pattern to it. */ 1039 ptr = guest_alloc(&ahci->parent->alloc, bufsize); 1040 g_assert(ptr); 1041 qtest_bufwrite(ahci->parent->qts, ptr, tx, bufsize); 1042 1043 cmd = ahci_command_create(CMD_WRITE_DMA); 1044 ahci_command_adjust(cmd, 0, ptr, bufsize, 32); 1045 ahci_command_commit(ahci, cmd, px); 1046 ahci_command_issue(ahci, cmd); 1047 ahci_command_verify(ahci, cmd); 1048 ahci_command_free(cmd); 1049 1050 cmd = ahci_command_create(CMD_READ_DMA); 1051 ahci_command_adjust(cmd, 0, ptr, bufsize, 32); 1052 ahci_command_commit(ahci, cmd, px); 1053 ahci_command_issue(ahci, cmd); 1054 ahci_command_verify(ahci, cmd); 1055 ahci_command_free(cmd); 1056 1057 /* Read back the guest's receive buffer into local memory */ 1058 qtest_bufread(ahci->parent->qts, ptr, rx, bufsize); 1059 guest_free(&ahci->parent->alloc, ptr); 1060 1061 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0); 1062 1063 ahci_shutdown(ahci); 1064 1065 g_free(rx); 1066 g_free(tx); 1067 } 1068 1069 /* 1070 * Write sector 1 with random data to make AHCI storage dirty 1071 * Needed for flush tests so that flushes actually go though the block layer 1072 */ 1073 static void make_dirty(AHCIQState* ahci, uint8_t port) 1074 { 1075 uint64_t ptr; 1076 unsigned bufsize = 512; 1077 1078 ptr = ahci_alloc(ahci, bufsize); 1079 g_assert(ptr); 1080 1081 ahci_guest_io(ahci, port, CMD_WRITE_DMA, ptr, bufsize, 1); 1082 ahci_free(ahci, ptr); 1083 } 1084 1085 static void test_flush(void) 1086 { 1087 AHCIQState *ahci; 1088 uint8_t port; 1089 1090 ahci = ahci_boot_and_enable(NULL); 1091 1092 port = ahci_port_select(ahci); 1093 ahci_port_clear(ahci, port); 1094 1095 make_dirty(ahci, port); 1096 1097 ahci_test_flush(ahci); 1098 ahci_shutdown(ahci); 1099 } 1100 1101 static void test_flush_retry(void) 1102 { 1103 AHCIQState *ahci; 1104 AHCICommand *cmd; 1105 uint8_t port; 1106 1107 prepare_blkdebug_script(debug_path, "flush_to_disk"); 1108 ahci = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0," 1109 "format=%s,cache=writeback," 1110 "rerror=stop,werror=stop " 1111 "-M q35 " 1112 "-device ide-hd,drive=drive0 ", 1113 debug_path, 1114 tmp_path, imgfmt); 1115 1116 port = ahci_port_select(ahci); 1117 ahci_port_clear(ahci, port); 1118 1119 /* Issue write so that flush actually goes to disk */ 1120 make_dirty(ahci, port); 1121 1122 /* Issue Flush Command and wait for error */ 1123 cmd = ahci_guest_io_halt(ahci, port, CMD_FLUSH_CACHE, 0, 0, 0); 1124 ahci_guest_io_resume(ahci, cmd); 1125 1126 ahci_shutdown(ahci); 1127 } 1128 1129 /** 1130 * Basic sanity test to boot a machine, find an AHCI device, and shutdown. 1131 */ 1132 static void test_migrate_sanity(void) 1133 { 1134 AHCIQState *src, *dst; 1135 char *uri = g_strdup_printf("unix:%s", mig_socket); 1136 1137 src = ahci_boot("-m 384 -M q35 " 1138 "-drive if=ide,file=%s,format=%s ", tmp_path, imgfmt); 1139 dst = ahci_boot("-m 384 -M q35 " 1140 "-drive if=ide,file=%s,format=%s " 1141 "-incoming %s", tmp_path, imgfmt, uri); 1142 1143 ahci_migrate(src, dst, uri); 1144 1145 ahci_shutdown(src); 1146 ahci_shutdown(dst); 1147 g_free(uri); 1148 } 1149 1150 /** 1151 * Simple migration test: Write a pattern, migrate, then read. 1152 */ 1153 static void ahci_migrate_simple(uint8_t cmd_read, uint8_t cmd_write) 1154 { 1155 AHCIQState *src, *dst; 1156 uint8_t px; 1157 size_t bufsize = 4096; 1158 unsigned char *tx = g_malloc(bufsize); 1159 unsigned char *rx = g_malloc0(bufsize); 1160 char *uri = g_strdup_printf("unix:%s", mig_socket); 1161 1162 src = ahci_boot_and_enable("-m 384 -M q35 " 1163 "-drive if=ide,format=%s,file=%s ", 1164 imgfmt, tmp_path); 1165 dst = ahci_boot("-m 384 -M q35 " 1166 "-drive if=ide,format=%s,file=%s " 1167 "-incoming %s", imgfmt, tmp_path, uri); 1168 1169 /* initialize */ 1170 px = ahci_port_select(src); 1171 ahci_port_clear(src, px); 1172 1173 /* create pattern */ 1174 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE); 1175 1176 /* Write, migrate, then read. */ 1177 ahci_io(src, px, cmd_write, tx, bufsize, 0); 1178 ahci_migrate(src, dst, uri); 1179 ahci_io(dst, px, cmd_read, rx, bufsize, 0); 1180 1181 /* Verify pattern */ 1182 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0); 1183 1184 ahci_shutdown(src); 1185 ahci_shutdown(dst); 1186 g_free(rx); 1187 g_free(tx); 1188 g_free(uri); 1189 } 1190 1191 static void test_migrate_dma(void) 1192 { 1193 ahci_migrate_simple(CMD_READ_DMA, CMD_WRITE_DMA); 1194 } 1195 1196 static void test_migrate_ncq(void) 1197 { 1198 ahci_migrate_simple(READ_FPDMA_QUEUED, WRITE_FPDMA_QUEUED); 1199 } 1200 1201 /** 1202 * Halted IO Error Test 1203 * 1204 * Simulate an error on first write, Try to write a pattern, 1205 * Confirm the VM has stopped, resume the VM, verify command 1206 * has completed, then read back the data and verify. 1207 */ 1208 static void ahci_halted_io_test(uint8_t cmd_read, uint8_t cmd_write) 1209 { 1210 AHCIQState *ahci; 1211 uint8_t port; 1212 size_t bufsize = 4096; 1213 unsigned char *tx = g_malloc(bufsize); 1214 unsigned char *rx = g_malloc0(bufsize); 1215 uint64_t ptr; 1216 AHCICommand *cmd; 1217 1218 prepare_blkdebug_script(debug_path, "write_aio"); 1219 1220 ahci = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0," 1221 "format=%s,cache=writeback," 1222 "rerror=stop,werror=stop " 1223 "-M q35 " 1224 "-device ide-hd,drive=drive0 ", 1225 debug_path, 1226 tmp_path, imgfmt); 1227 1228 /* Initialize and prepare */ 1229 port = ahci_port_select(ahci); 1230 ahci_port_clear(ahci, port); 1231 1232 /* create DMA source buffer and write pattern */ 1233 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE); 1234 ptr = ahci_alloc(ahci, bufsize); 1235 g_assert(ptr); 1236 qtest_memwrite(ahci->parent->qts, ptr, tx, bufsize); 1237 1238 /* Attempt to write (and fail) */ 1239 cmd = ahci_guest_io_halt(ahci, port, cmd_write, 1240 ptr, bufsize, 0); 1241 1242 /* Attempt to resume the command */ 1243 ahci_guest_io_resume(ahci, cmd); 1244 ahci_free(ahci, ptr); 1245 1246 /* Read back and verify */ 1247 ahci_io(ahci, port, cmd_read, rx, bufsize, 0); 1248 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0); 1249 1250 /* Cleanup and go home */ 1251 ahci_shutdown(ahci); 1252 g_free(rx); 1253 g_free(tx); 1254 } 1255 1256 static void test_halted_dma(void) 1257 { 1258 ahci_halted_io_test(CMD_READ_DMA, CMD_WRITE_DMA); 1259 } 1260 1261 static void test_halted_ncq(void) 1262 { 1263 ahci_halted_io_test(READ_FPDMA_QUEUED, WRITE_FPDMA_QUEUED); 1264 } 1265 1266 /** 1267 * IO Error Migration Test 1268 * 1269 * Simulate an error on first write, Try to write a pattern, 1270 * Confirm the VM has stopped, migrate, resume the VM, 1271 * verify command has completed, then read back the data and verify. 1272 */ 1273 static void ahci_migrate_halted_io(uint8_t cmd_read, uint8_t cmd_write) 1274 { 1275 AHCIQState *src, *dst; 1276 uint8_t port; 1277 size_t bufsize = 4096; 1278 unsigned char *tx = g_malloc(bufsize); 1279 unsigned char *rx = g_malloc0(bufsize); 1280 uint64_t ptr; 1281 AHCICommand *cmd; 1282 char *uri = g_strdup_printf("unix:%s", mig_socket); 1283 1284 prepare_blkdebug_script(debug_path, "write_aio"); 1285 1286 src = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0," 1287 "format=%s,cache=writeback," 1288 "rerror=stop,werror=stop " 1289 "-M q35 " 1290 "-device ide-hd,drive=drive0 ", 1291 debug_path, 1292 tmp_path, imgfmt); 1293 1294 dst = ahci_boot("-drive file=%s,if=none,id=drive0," 1295 "format=%s,cache=writeback," 1296 "rerror=stop,werror=stop " 1297 "-M q35 " 1298 "-device ide-hd,drive=drive0 " 1299 "-incoming %s", 1300 tmp_path, imgfmt, uri); 1301 1302 /* Initialize and prepare */ 1303 port = ahci_port_select(src); 1304 ahci_port_clear(src, port); 1305 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE); 1306 1307 /* create DMA source buffer and write pattern */ 1308 ptr = ahci_alloc(src, bufsize); 1309 g_assert(ptr); 1310 qtest_memwrite(src->parent->qts, ptr, tx, bufsize); 1311 1312 /* Write, trigger the VM to stop, migrate, then resume. */ 1313 cmd = ahci_guest_io_halt(src, port, cmd_write, 1314 ptr, bufsize, 0); 1315 ahci_migrate(src, dst, uri); 1316 ahci_guest_io_resume(dst, cmd); 1317 ahci_free(dst, ptr); 1318 1319 /* Read back */ 1320 ahci_io(dst, port, cmd_read, rx, bufsize, 0); 1321 1322 /* Verify TX and RX are identical */ 1323 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0); 1324 1325 /* Cleanup and go home. */ 1326 ahci_shutdown(src); 1327 ahci_shutdown(dst); 1328 g_free(rx); 1329 g_free(tx); 1330 g_free(uri); 1331 } 1332 1333 static void test_migrate_halted_dma(void) 1334 { 1335 ahci_migrate_halted_io(CMD_READ_DMA, CMD_WRITE_DMA); 1336 } 1337 1338 static void test_migrate_halted_ncq(void) 1339 { 1340 ahci_migrate_halted_io(READ_FPDMA_QUEUED, WRITE_FPDMA_QUEUED); 1341 } 1342 1343 /** 1344 * Migration test: Try to flush, migrate, then resume. 1345 */ 1346 static void test_flush_migrate(void) 1347 { 1348 AHCIQState *src, *dst; 1349 AHCICommand *cmd; 1350 uint8_t px; 1351 char *uri = g_strdup_printf("unix:%s", mig_socket); 1352 1353 prepare_blkdebug_script(debug_path, "flush_to_disk"); 1354 1355 src = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0," 1356 "cache=writeback,rerror=stop,werror=stop," 1357 "format=%s " 1358 "-M q35 " 1359 "-device ide-hd,drive=drive0 ", 1360 debug_path, tmp_path, imgfmt); 1361 dst = ahci_boot("-drive file=%s,if=none,id=drive0," 1362 "cache=writeback,rerror=stop,werror=stop," 1363 "format=%s " 1364 "-M q35 " 1365 "-device ide-hd,drive=drive0 " 1366 "-incoming %s", tmp_path, imgfmt, uri); 1367 1368 px = ahci_port_select(src); 1369 ahci_port_clear(src, px); 1370 1371 /* Dirty device so that flush reaches disk */ 1372 make_dirty(src, px); 1373 1374 /* Issue Flush Command */ 1375 cmd = ahci_command_create(CMD_FLUSH_CACHE); 1376 ahci_command_commit(src, cmd, px); 1377 ahci_command_issue_async(src, cmd); 1378 qtest_qmp_eventwait(src->parent->qts, "STOP"); 1379 1380 /* Migrate over */ 1381 ahci_migrate(src, dst, uri); 1382 1383 /* Complete the command */ 1384 qtest_qmp_send(dst->parent->qts, "{'execute':'cont' }"); 1385 qtest_qmp_eventwait(dst->parent->qts, "RESUME"); 1386 ahci_command_wait(dst, cmd); 1387 ahci_command_verify(dst, cmd); 1388 1389 ahci_command_free(cmd); 1390 ahci_shutdown(src); 1391 ahci_shutdown(dst); 1392 g_free(uri); 1393 } 1394 1395 static void test_max(void) 1396 { 1397 AHCIQState *ahci; 1398 1399 ahci = ahci_boot_and_enable(NULL); 1400 ahci_test_max(ahci); 1401 ahci_shutdown(ahci); 1402 } 1403 1404 static void test_reset(void) 1405 { 1406 AHCIQState *ahci; 1407 int i; 1408 1409 ahci = ahci_boot(NULL); 1410 ahci_test_pci_spec(ahci); 1411 ahci_pci_enable(ahci); 1412 1413 for (i = 0; i < 2; i++) { 1414 ahci_test_hba_spec(ahci); 1415 ahci_hba_enable(ahci); 1416 ahci_test_identify(ahci); 1417 ahci_test_io_rw_simple(ahci, 4096, 0, 1418 CMD_READ_DMA_EXT, 1419 CMD_WRITE_DMA_EXT); 1420 ahci_set(ahci, AHCI_GHC, AHCI_GHC_HR); 1421 ahci_clean_mem(ahci); 1422 } 1423 1424 ahci_shutdown(ahci); 1425 } 1426 1427 static void test_ncq_simple(void) 1428 { 1429 AHCIQState *ahci; 1430 1431 ahci = ahci_boot_and_enable(NULL); 1432 ahci_test_io_rw_simple(ahci, 4096, 0, 1433 READ_FPDMA_QUEUED, 1434 WRITE_FPDMA_QUEUED); 1435 ahci_shutdown(ahci); 1436 } 1437 1438 static int prepare_iso(size_t size, unsigned char **buf, char **name) 1439 { 1440 g_autofree char *cdrom_path = NULL; 1441 unsigned char *patt; 1442 ssize_t ret; 1443 int fd = g_file_open_tmp("qtest.iso.XXXXXX", &cdrom_path, NULL); 1444 1445 g_assert(fd != -1); 1446 g_assert(buf); 1447 g_assert(name); 1448 patt = g_malloc(size); 1449 1450 /* Generate a pattern and build a CDROM image to read from */ 1451 generate_pattern(patt, size, ATAPI_SECTOR_SIZE); 1452 ret = write(fd, patt, size); 1453 g_assert(ret == size); 1454 1455 *name = g_strdup(cdrom_path); 1456 *buf = patt; 1457 return fd; 1458 } 1459 1460 static void remove_iso(int fd, char *name) 1461 { 1462 unlink(name); 1463 g_free(name); 1464 close(fd); 1465 } 1466 1467 static int ahci_cb_cmp_buff(AHCIQState *ahci, AHCICommand *cmd, 1468 const AHCIOpts *opts) 1469 { 1470 unsigned char *tx = opts->opaque; 1471 unsigned char *rx; 1472 1473 if (!opts->size) { 1474 return 0; 1475 } 1476 1477 rx = g_malloc0(opts->size); 1478 qtest_bufread(ahci->parent->qts, opts->buffer, rx, opts->size); 1479 g_assert_cmphex(memcmp(tx, rx, opts->size), ==, 0); 1480 g_free(rx); 1481 1482 return 0; 1483 } 1484 1485 static void ahci_test_cdrom(int nsectors, bool dma, uint8_t cmd, 1486 bool override_bcl, uint16_t bcl) 1487 { 1488 AHCIQState *ahci; 1489 unsigned char *tx; 1490 char *iso; 1491 int fd; 1492 AHCIOpts opts = { 1493 .size = ((uint64_t)ATAPI_SECTOR_SIZE * nsectors), 1494 .atapi = true, 1495 .atapi_dma = dma, 1496 .post_cb = ahci_cb_cmp_buff, 1497 .set_bcl = override_bcl, 1498 .bcl = bcl, 1499 }; 1500 uint64_t iso_size = (uint64_t)ATAPI_SECTOR_SIZE * (nsectors + 1); 1501 1502 /* Prepare ISO and fill 'tx' buffer */ 1503 fd = prepare_iso(iso_size, &tx, &iso); 1504 opts.opaque = tx; 1505 1506 /* Standard startup wonkery, but use ide-cd and our special iso file */ 1507 ahci = ahci_boot_and_enable("-drive if=none,id=drive0,file=%s,format=raw " 1508 "-M q35 " 1509 "-device ide-cd,drive=drive0 ", iso); 1510 1511 /* Build & Send AHCI command */ 1512 ahci_exec(ahci, ahci_port_select(ahci), cmd, &opts); 1513 1514 /* Cleanup */ 1515 g_free(tx); 1516 ahci_shutdown(ahci); 1517 remove_iso(fd, iso); 1518 } 1519 1520 static void ahci_test_cdrom_read10(int nsectors, bool dma) 1521 { 1522 ahci_test_cdrom(nsectors, dma, CMD_ATAPI_READ_10, false, 0); 1523 } 1524 1525 static void test_cdrom_dma(void) 1526 { 1527 ahci_test_cdrom_read10(1, true); 1528 } 1529 1530 static void test_cdrom_dma_multi(void) 1531 { 1532 ahci_test_cdrom_read10(3, true); 1533 } 1534 1535 static void test_cdrom_pio(void) 1536 { 1537 ahci_test_cdrom_read10(1, false); 1538 } 1539 1540 static void test_cdrom_pio_multi(void) 1541 { 1542 ahci_test_cdrom_read10(3, false); 1543 } 1544 1545 /* Regression test: Test that a READ_CD command with a BCL of 0 but a size of 0 1546 * completes as a NOP instead of erroring out. */ 1547 static void test_atapi_bcl(void) 1548 { 1549 ahci_test_cdrom(0, false, CMD_ATAPI_READ_CD, true, 0); 1550 } 1551 1552 1553 static void atapi_wait_tray(AHCIQState *ahci, bool open) 1554 { 1555 QDict *rsp = qtest_qmp_eventwait_ref(ahci->parent->qts, 1556 "DEVICE_TRAY_MOVED"); 1557 QDict *data = qdict_get_qdict(rsp, "data"); 1558 if (open) { 1559 g_assert(qdict_get_bool(data, "tray-open")); 1560 } else { 1561 g_assert(!qdict_get_bool(data, "tray-open")); 1562 } 1563 qobject_unref(rsp); 1564 } 1565 1566 static void test_atapi_tray(void) 1567 { 1568 AHCIQState *ahci; 1569 unsigned char *tx; 1570 char *iso; 1571 int fd; 1572 uint8_t port, sense, asc; 1573 uint64_t iso_size = ATAPI_SECTOR_SIZE; 1574 QDict *rsp; 1575 1576 fd = prepare_iso(iso_size, &tx, &iso); 1577 ahci = ahci_boot_and_enable("-blockdev node-name=drive0,driver=file,filename=%s " 1578 "-M q35 " 1579 "-device ide-cd,id=cd0,drive=drive0 ", iso); 1580 port = ahci_port_select(ahci); 1581 1582 ahci_atapi_eject(ahci, port); 1583 atapi_wait_tray(ahci, true); 1584 1585 ahci_atapi_load(ahci, port); 1586 atapi_wait_tray(ahci, false); 1587 1588 /* Remove media */ 1589 qtest_qmp_send(ahci->parent->qts, "{'execute': 'blockdev-open-tray', " 1590 "'arguments': {'id': 'cd0'}}"); 1591 atapi_wait_tray(ahci, true); 1592 rsp = qtest_qmp_receive(ahci->parent->qts); 1593 qobject_unref(rsp); 1594 1595 qtest_qmp_assert_success(ahci->parent->qts, 1596 "{'execute': 'blockdev-remove-medium', " 1597 "'arguments': {'id': 'cd0'}}"); 1598 1599 /* Test the tray without a medium */ 1600 ahci_atapi_load(ahci, port); 1601 atapi_wait_tray(ahci, false); 1602 1603 ahci_atapi_eject(ahci, port); 1604 atapi_wait_tray(ahci, true); 1605 1606 /* Re-insert media */ 1607 qtest_qmp_assert_success( 1608 ahci->parent->qts, 1609 "{'execute': 'blockdev-add', " 1610 "'arguments': {'node-name': 'node0', " 1611 "'driver': 'raw', " 1612 "'file': { 'driver': 'file', " 1613 "'filename': %s }}}", iso); 1614 qtest_qmp_assert_success( 1615 ahci->parent->qts, 1616 "{'execute': 'blockdev-insert-medium'," 1617 "'arguments': { 'id': 'cd0', " 1618 "'node-name': 'node0' }}"); 1619 1620 /* Again, the event shows up first */ 1621 qtest_qmp_send(ahci->parent->qts, "{'execute': 'blockdev-close-tray', " 1622 "'arguments': {'id': 'cd0'}}"); 1623 atapi_wait_tray(ahci, false); 1624 rsp = qtest_qmp_receive(ahci->parent->qts); 1625 qobject_unref(rsp); 1626 1627 /* Now, to convince ATAPI we understand the media has changed... */ 1628 ahci_atapi_test_ready(ahci, port, false, SENSE_NOT_READY); 1629 ahci_atapi_get_sense(ahci, port, &sense, &asc); 1630 g_assert_cmpuint(sense, ==, SENSE_NOT_READY); 1631 g_assert_cmpuint(asc, ==, ASC_MEDIUM_NOT_PRESENT); 1632 1633 ahci_atapi_test_ready(ahci, port, false, SENSE_UNIT_ATTENTION); 1634 ahci_atapi_get_sense(ahci, port, &sense, &asc); 1635 g_assert_cmpuint(sense, ==, SENSE_UNIT_ATTENTION); 1636 g_assert_cmpuint(asc, ==, ASC_MEDIUM_MAY_HAVE_CHANGED); 1637 1638 ahci_atapi_test_ready(ahci, port, true, SENSE_NO_SENSE); 1639 ahci_atapi_get_sense(ahci, port, &sense, &asc); 1640 g_assert_cmpuint(sense, ==, SENSE_NO_SENSE); 1641 1642 /* Final tray test. */ 1643 ahci_atapi_eject(ahci, port); 1644 atapi_wait_tray(ahci, true); 1645 1646 ahci_atapi_load(ahci, port); 1647 atapi_wait_tray(ahci, false); 1648 1649 /* Cleanup */ 1650 g_free(tx); 1651 ahci_shutdown(ahci); 1652 remove_iso(fd, iso); 1653 } 1654 1655 /******************************************************************************/ 1656 /* AHCI I/O Test Matrix Definitions */ 1657 1658 enum BuffLen { 1659 LEN_BEGIN = 0, 1660 LEN_SIMPLE = LEN_BEGIN, 1661 LEN_DOUBLE, 1662 LEN_LONG, 1663 LEN_SHORT, 1664 NUM_LENGTHS 1665 }; 1666 1667 static const char *buff_len_str[NUM_LENGTHS] = { "simple", "double", 1668 "long", "short" }; 1669 1670 enum AddrMode { 1671 ADDR_MODE_BEGIN = 0, 1672 ADDR_MODE_LBA28 = ADDR_MODE_BEGIN, 1673 ADDR_MODE_LBA48, 1674 NUM_ADDR_MODES 1675 }; 1676 1677 static const char *addr_mode_str[NUM_ADDR_MODES] = { "lba28", "lba48" }; 1678 1679 enum IOMode { 1680 MODE_BEGIN = 0, 1681 MODE_PIO = MODE_BEGIN, 1682 MODE_DMA, 1683 NUM_MODES 1684 }; 1685 1686 static const char *io_mode_str[NUM_MODES] = { "pio", "dma" }; 1687 1688 enum IOOps { 1689 IO_BEGIN = 0, 1690 IO_READ = IO_BEGIN, 1691 IO_WRITE, 1692 NUM_IO_OPS 1693 }; 1694 1695 enum OffsetType { 1696 OFFSET_BEGIN = 0, 1697 OFFSET_ZERO = OFFSET_BEGIN, 1698 OFFSET_LOW, 1699 OFFSET_HIGH, 1700 NUM_OFFSETS 1701 }; 1702 1703 static const char *offset_str[NUM_OFFSETS] = { "zero", "low", "high" }; 1704 1705 typedef struct AHCIIOTestOptions { 1706 enum BuffLen length; 1707 enum AddrMode address_type; 1708 enum IOMode io_type; 1709 enum OffsetType offset; 1710 } AHCIIOTestOptions; 1711 1712 static uint64_t offset_sector(enum OffsetType ofst, 1713 enum AddrMode addr_type, 1714 uint64_t buffsize) 1715 { 1716 uint64_t ceil; 1717 uint64_t nsectors; 1718 1719 switch (ofst) { 1720 case OFFSET_ZERO: 1721 return 0; 1722 case OFFSET_LOW: 1723 return 1; 1724 case OFFSET_HIGH: 1725 ceil = (addr_type == ADDR_MODE_LBA28) ? 0xfffffff : 0xffffffffffff; 1726 ceil = MIN(ceil, mb_to_sectors(test_image_size_mb) - 1); 1727 nsectors = buffsize / AHCI_SECTOR_SIZE; 1728 return ceil - nsectors + 1; 1729 default: 1730 g_assert_not_reached(); 1731 } 1732 } 1733 1734 /** 1735 * Table of possible I/O ATA commands given a set of enumerations. 1736 */ 1737 static const uint8_t io_cmds[NUM_MODES][NUM_ADDR_MODES][NUM_IO_OPS] = { 1738 [MODE_PIO] = { 1739 [ADDR_MODE_LBA28] = { 1740 [IO_READ] = CMD_READ_PIO, 1741 [IO_WRITE] = CMD_WRITE_PIO }, 1742 [ADDR_MODE_LBA48] = { 1743 [IO_READ] = CMD_READ_PIO_EXT, 1744 [IO_WRITE] = CMD_WRITE_PIO_EXT } 1745 }, 1746 [MODE_DMA] = { 1747 [ADDR_MODE_LBA28] = { 1748 [IO_READ] = CMD_READ_DMA, 1749 [IO_WRITE] = CMD_WRITE_DMA }, 1750 [ADDR_MODE_LBA48] = { 1751 [IO_READ] = CMD_READ_DMA_EXT, 1752 [IO_WRITE] = CMD_WRITE_DMA_EXT } 1753 } 1754 }; 1755 1756 /** 1757 * Test a Read/Write pattern using various commands, addressing modes, 1758 * transfer modes, and buffer sizes. 1759 */ 1760 static void test_io_rw_interface(enum AddrMode lba48, enum IOMode dma, 1761 unsigned bufsize, uint64_t sector) 1762 { 1763 AHCIQState *ahci; 1764 1765 ahci = ahci_boot_and_enable(NULL); 1766 ahci_test_io_rw_simple(ahci, bufsize, sector, 1767 io_cmds[dma][lba48][IO_READ], 1768 io_cmds[dma][lba48][IO_WRITE]); 1769 ahci_shutdown(ahci); 1770 } 1771 1772 /** 1773 * Demultiplex the test data and invoke the actual test routine. 1774 */ 1775 static void test_io_interface(gconstpointer opaque) 1776 { 1777 AHCIIOTestOptions *opts = (AHCIIOTestOptions *)opaque; 1778 unsigned bufsize; 1779 uint64_t sector; 1780 1781 switch (opts->length) { 1782 case LEN_SIMPLE: 1783 bufsize = 4096; 1784 break; 1785 case LEN_DOUBLE: 1786 bufsize = 8192; 1787 break; 1788 case LEN_LONG: 1789 bufsize = 4096 * 64; 1790 break; 1791 case LEN_SHORT: 1792 bufsize = 512; 1793 break; 1794 default: 1795 g_assert_not_reached(); 1796 } 1797 1798 sector = offset_sector(opts->offset, opts->address_type, bufsize); 1799 test_io_rw_interface(opts->address_type, opts->io_type, bufsize, sector); 1800 g_free(opts); 1801 return; 1802 } 1803 1804 static void create_ahci_io_test(enum IOMode type, enum AddrMode addr, 1805 enum BuffLen len, enum OffsetType offset) 1806 { 1807 char *name; 1808 AHCIIOTestOptions *opts; 1809 1810 opts = g_new(AHCIIOTestOptions, 1); 1811 opts->length = len; 1812 opts->address_type = addr; 1813 opts->io_type = type; 1814 opts->offset = offset; 1815 1816 name = g_strdup_printf("ahci/io/%s/%s/%s/%s", 1817 io_mode_str[type], 1818 addr_mode_str[addr], 1819 buff_len_str[len], 1820 offset_str[offset]); 1821 1822 if ((addr == ADDR_MODE_LBA48) && (offset == OFFSET_HIGH) && 1823 (mb_to_sectors(test_image_size_mb) <= 0xFFFFFFF)) { 1824 g_test_message("%s: skipped; test image too small", name); 1825 g_free(opts); 1826 g_free(name); 1827 return; 1828 } 1829 1830 qtest_add_data_func(name, opts, test_io_interface); 1831 g_free(name); 1832 } 1833 1834 /******************************************************************************/ 1835 1836 int main(int argc, char **argv) 1837 { 1838 const char *arch, *base; 1839 int ret; 1840 int fd; 1841 int c; 1842 int i, j, k, m; 1843 1844 static struct option long_options[] = { 1845 {"pedantic", no_argument, 0, 'p' }, 1846 {0, 0, 0, 0}, 1847 }; 1848 1849 /* Should be first to utilize g_test functionality, So we can see errors. */ 1850 g_test_init(&argc, &argv, NULL); 1851 1852 while (1) { 1853 c = getopt_long(argc, argv, "", long_options, NULL); 1854 if (c == -1) { 1855 break; 1856 } 1857 switch (c) { 1858 case -1: 1859 break; 1860 case 'p': 1861 ahci_pedantic = 1; 1862 break; 1863 default: 1864 fprintf(stderr, "Unrecognized ahci_test option.\n"); 1865 g_assert_not_reached(); 1866 } 1867 } 1868 1869 /* Check architecture */ 1870 arch = qtest_get_arch(); 1871 if (strcmp(arch, "i386") && strcmp(arch, "x86_64")) { 1872 g_test_message("Skipping test for non-x86"); 1873 return 0; 1874 } 1875 1876 /* 1877 * "base" stores the starting point where we create temporary files. 1878 * 1879 * On Windows, this is set to the relative path of current working 1880 * directory, because the absolute path causes the blkdebug filename 1881 * parser fail to parse "blkdebug:path/to/config:path/to/image". 1882 */ 1883 #ifndef _WIN32 1884 base = g_get_tmp_dir(); 1885 #else 1886 base = "."; 1887 #endif 1888 1889 /* Create a temporary image */ 1890 tmp_path = g_strdup_printf("%s/qtest.XXXXXX", base); 1891 fd = g_mkstemp(tmp_path); 1892 g_assert(fd >= 0); 1893 if (have_qemu_img()) { 1894 imgfmt = "qcow2"; 1895 test_image_size_mb = TEST_IMAGE_SIZE_MB_LARGE; 1896 mkqcow2(tmp_path, TEST_IMAGE_SIZE_MB_LARGE); 1897 } else { 1898 g_test_message("QTEST_QEMU_IMG not set or qemu-img missing; " 1899 "skipping LBA48 high-sector tests"); 1900 imgfmt = "raw"; 1901 test_image_size_mb = TEST_IMAGE_SIZE_MB_SMALL; 1902 ret = ftruncate(fd, test_image_size_mb * 1024 * 1024); 1903 g_assert(ret == 0); 1904 } 1905 close(fd); 1906 1907 /* Create temporary blkdebug instructions */ 1908 debug_path = g_strdup_printf("%s/qtest-blkdebug.XXXXXX", base); 1909 fd = g_mkstemp(debug_path); 1910 g_assert(fd >= 0); 1911 close(fd); 1912 1913 /* Reserve a hollow file to use as a socket for migration tests */ 1914 fd = g_file_open_tmp("qtest-migration.XXXXXX", &mig_socket, NULL); 1915 g_assert(fd >= 0); 1916 close(fd); 1917 1918 /* Run the tests */ 1919 qtest_add_func("/ahci/sanity", test_sanity); 1920 qtest_add_func("/ahci/pci_spec", test_pci_spec); 1921 qtest_add_func("/ahci/pci_enable", test_pci_enable); 1922 qtest_add_func("/ahci/hba_spec", test_hba_spec); 1923 qtest_add_func("/ahci/hba_enable", test_hba_enable); 1924 qtest_add_func("/ahci/identify", test_identify); 1925 1926 for (i = MODE_BEGIN; i < NUM_MODES; i++) { 1927 for (j = ADDR_MODE_BEGIN; j < NUM_ADDR_MODES; j++) { 1928 for (k = LEN_BEGIN; k < NUM_LENGTHS; k++) { 1929 for (m = OFFSET_BEGIN; m < NUM_OFFSETS; m++) { 1930 create_ahci_io_test(i, j, k, m); 1931 } 1932 } 1933 } 1934 } 1935 1936 qtest_add_func("/ahci/io/dma/lba28/fragmented", test_dma_fragmented); 1937 1938 qtest_add_func("/ahci/flush/simple", test_flush); 1939 qtest_add_func("/ahci/flush/retry", test_flush_retry); 1940 qtest_add_func("/ahci/flush/migrate", test_flush_migrate); 1941 1942 qtest_add_func("/ahci/migrate/sanity", test_migrate_sanity); 1943 qtest_add_func("/ahci/migrate/dma/simple", test_migrate_dma); 1944 qtest_add_func("/ahci/io/dma/lba28/retry", test_halted_dma); 1945 qtest_add_func("/ahci/migrate/dma/halted", test_migrate_halted_dma); 1946 1947 qtest_add_func("/ahci/max", test_max); 1948 qtest_add_func("/ahci/reset", test_reset); 1949 1950 qtest_add_func("/ahci/io/ncq/simple", test_ncq_simple); 1951 qtest_add_func("/ahci/migrate/ncq/simple", test_migrate_ncq); 1952 qtest_add_func("/ahci/io/ncq/retry", test_halted_ncq); 1953 qtest_add_func("/ahci/migrate/ncq/halted", test_migrate_halted_ncq); 1954 1955 qtest_add_func("/ahci/cdrom/dma/single", test_cdrom_dma); 1956 qtest_add_func("/ahci/cdrom/dma/multi", test_cdrom_dma_multi); 1957 qtest_add_func("/ahci/cdrom/pio/single", test_cdrom_pio); 1958 qtest_add_func("/ahci/cdrom/pio/multi", test_cdrom_pio_multi); 1959 1960 qtest_add_func("/ahci/cdrom/pio/bcl", test_atapi_bcl); 1961 qtest_add_func("/ahci/cdrom/eject", test_atapi_tray); 1962 1963 ret = g_test_run(); 1964 1965 /* Cleanup */ 1966 unlink(tmp_path); 1967 g_free(tmp_path); 1968 unlink(debug_path); 1969 g_free(debug_path); 1970 unlink(mig_socket); 1971 g_free(mig_socket); 1972 1973 return ret; 1974 } 1975