1 /* 2 * AHCI test cases 3 * 4 * Copyright (c) 2014 John Snow <jsnow@redhat.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include <getopt.h> 27 28 #include "libqtest.h" 29 #include "libqos/libqos-pc.h" 30 #include "libqos/ahci.h" 31 #include "libqos/pci-pc.h" 32 33 #include "qapi/qmp/qdict.h" 34 #include "qemu/host-utils.h" 35 36 #include "hw/pci/pci_ids.h" 37 #include "hw/pci/pci_regs.h" 38 39 /* TODO actually test the results and get rid of this */ 40 #define qmp_discard_response(s, ...) qobject_unref(qtest_qmp(s, __VA_ARGS__)) 41 42 /* Test images sizes in MB */ 43 #define TEST_IMAGE_SIZE_MB_LARGE (200 * 1024) 44 #define TEST_IMAGE_SIZE_MB_SMALL 64 45 46 /*** Globals ***/ 47 static char *tmp_path; 48 static char *debug_path; 49 static char *mig_socket; 50 static bool ahci_pedantic; 51 static const char *imgfmt; 52 static unsigned test_image_size_mb; 53 54 /*** Function Declarations ***/ 55 static void ahci_test_port_spec(AHCIQState *ahci, uint8_t port); 56 static void ahci_test_pci_spec(AHCIQState *ahci); 57 static void ahci_test_pci_caps(AHCIQState *ahci, uint16_t header, 58 uint8_t offset); 59 static void ahci_test_satacap(AHCIQState *ahci, uint8_t offset); 60 static void ahci_test_msicap(AHCIQState *ahci, uint8_t offset); 61 static void ahci_test_pmcap(AHCIQState *ahci, uint8_t offset); 62 63 /*** Utilities ***/ 64 65 static uint64_t mb_to_sectors(uint64_t image_size_mb) 66 { 67 return (image_size_mb * 1024 * 1024) / AHCI_SECTOR_SIZE; 68 } 69 70 static void string_bswap16(uint16_t *s, size_t bytes) 71 { 72 g_assert_cmphex((bytes & 1), ==, 0); 73 bytes /= 2; 74 75 while (bytes--) { 76 *s = bswap16(*s); 77 s++; 78 } 79 } 80 81 /** 82 * Verify that the transfer did not corrupt our state at all. 83 */ 84 static void verify_state(AHCIQState *ahci, uint64_t hba_old) 85 { 86 int i, j; 87 uint32_t ahci_fingerprint; 88 uint64_t hba_base; 89 AHCICommandHeader cmd; 90 91 ahci_fingerprint = qpci_config_readl(ahci->dev, PCI_VENDOR_ID); 92 g_assert_cmphex(ahci_fingerprint, ==, ahci->fingerprint); 93 94 /* If we haven't initialized, this is as much as can be validated. */ 95 if (!ahci->enabled) { 96 return; 97 } 98 99 hba_base = (uint64_t)qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5); 100 g_assert_cmphex(hba_base, ==, hba_old); 101 102 g_assert_cmphex(ahci_rreg(ahci, AHCI_CAP), ==, ahci->cap); 103 g_assert_cmphex(ahci_rreg(ahci, AHCI_CAP2), ==, ahci->cap2); 104 105 for (i = 0; i < 32; i++) { 106 g_assert_cmphex(ahci_px_rreg(ahci, i, AHCI_PX_FB), ==, 107 ahci->port[i].fb); 108 g_assert_cmphex(ahci_px_rreg(ahci, i, AHCI_PX_CLB), ==, 109 ahci->port[i].clb); 110 for (j = 0; j < 32; j++) { 111 ahci_get_command_header(ahci, i, j, &cmd); 112 g_assert_cmphex(cmd.prdtl, ==, ahci->port[i].prdtl[j]); 113 g_assert_cmphex(cmd.ctba, ==, ahci->port[i].ctba[j]); 114 } 115 } 116 } 117 118 static void ahci_migrate(AHCIQState *from, AHCIQState *to, const char *uri) 119 { 120 QOSState *tmp = to->parent; 121 QPCIDevice *dev = to->dev; 122 char *uri_local = NULL; 123 uint64_t hba_old; 124 125 if (uri == NULL) { 126 uri_local = g_strdup_printf("%s%s", "unix:", mig_socket); 127 uri = uri_local; 128 } 129 130 hba_old = (uint64_t)qpci_config_readl(from->dev, PCI_BASE_ADDRESS_5); 131 132 /* context will be 'to' after completion. */ 133 migrate(from->parent, to->parent, uri); 134 135 /* We'd like for the AHCIState objects to still point 136 * to information specific to its specific parent 137 * instance, but otherwise just inherit the new data. */ 138 memcpy(to, from, sizeof(AHCIQState)); 139 to->parent = tmp; 140 to->dev = dev; 141 142 tmp = from->parent; 143 dev = from->dev; 144 memset(from, 0x00, sizeof(AHCIQState)); 145 from->parent = tmp; 146 from->dev = dev; 147 148 verify_state(to, hba_old); 149 g_free(uri_local); 150 } 151 152 /*** Test Setup & Teardown ***/ 153 154 /** 155 * Start a Q35 machine and bookmark a handle to the AHCI device. 156 */ 157 G_GNUC_PRINTF(1, 0) 158 static AHCIQState *ahci_vboot(const char *cli, va_list ap) 159 { 160 AHCIQState *s; 161 162 s = g_new0(AHCIQState, 1); 163 s->parent = qtest_pc_vboot(cli, ap); 164 alloc_set_flags(&s->parent->alloc, ALLOC_LEAK_ASSERT); 165 166 /* Verify that we have an AHCI device present. */ 167 s->dev = get_ahci_device(s->parent->qts, &s->fingerprint); 168 169 return s; 170 } 171 172 /** 173 * Start a Q35 machine and bookmark a handle to the AHCI device. 174 */ 175 G_GNUC_PRINTF(1, 2) 176 static AHCIQState *ahci_boot(const char *cli, ...) 177 { 178 AHCIQState *s; 179 va_list ap; 180 181 if (cli) { 182 va_start(ap, cli); 183 s = ahci_vboot(cli, ap); 184 va_end(ap); 185 } else { 186 cli = "-drive if=none,id=drive0,file=%s,cache=writeback,format=%s" 187 " -M q35 " 188 "-device ide-hd,drive=drive0 " 189 "-global ide-hd.serial=%s " 190 "-global ide-hd.ver=%s"; 191 s = ahci_boot(cli, tmp_path, imgfmt, "testdisk", "version"); 192 } 193 194 return s; 195 } 196 197 /** 198 * Clean up the PCI device, then terminate the QEMU instance. 199 */ 200 static void ahci_shutdown(AHCIQState *ahci) 201 { 202 QOSState *qs = ahci->parent; 203 204 ahci_clean_mem(ahci); 205 free_ahci_device(ahci->dev); 206 g_free(ahci); 207 qtest_shutdown(qs); 208 } 209 210 /** 211 * Boot and fully enable the HBA device. 212 * @see ahci_boot, ahci_pci_enable and ahci_hba_enable. 213 */ 214 G_GNUC_PRINTF(1, 2) 215 static AHCIQState *ahci_boot_and_enable(const char *cli, ...) 216 { 217 AHCIQState *ahci; 218 va_list ap; 219 uint16_t buff[256]; 220 uint8_t port; 221 uint8_t hello; 222 223 if (cli) { 224 va_start(ap, cli); 225 ahci = ahci_vboot(cli, ap); 226 va_end(ap); 227 } else { 228 ahci = ahci_boot(NULL); 229 } 230 231 ahci_pci_enable(ahci); 232 ahci_hba_enable(ahci); 233 /* Initialize test device */ 234 port = ahci_port_select(ahci); 235 ahci_port_clear(ahci, port); 236 if (is_atapi(ahci, port)) { 237 hello = CMD_PACKET_ID; 238 } else { 239 hello = CMD_IDENTIFY; 240 } 241 ahci_io(ahci, port, hello, &buff, sizeof(buff), 0); 242 243 return ahci; 244 } 245 246 /*** Specification Adherence Tests ***/ 247 248 /** 249 * Implementation for test_pci_spec. Ensures PCI configuration space is sane. 250 */ 251 static void ahci_test_pci_spec(AHCIQState *ahci) 252 { 253 uint8_t datab; 254 uint16_t data; 255 uint32_t datal; 256 257 /* Most of these bits should start cleared until we turn them on. */ 258 data = qpci_config_readw(ahci->dev, PCI_COMMAND); 259 ASSERT_BIT_CLEAR(data, PCI_COMMAND_MEMORY); 260 ASSERT_BIT_CLEAR(data, PCI_COMMAND_MASTER); 261 ASSERT_BIT_CLEAR(data, PCI_COMMAND_SPECIAL); /* Reserved */ 262 ASSERT_BIT_CLEAR(data, PCI_COMMAND_VGA_PALETTE); /* Reserved */ 263 ASSERT_BIT_CLEAR(data, PCI_COMMAND_PARITY); 264 ASSERT_BIT_CLEAR(data, PCI_COMMAND_WAIT); /* Reserved */ 265 ASSERT_BIT_CLEAR(data, PCI_COMMAND_SERR); 266 ASSERT_BIT_CLEAR(data, PCI_COMMAND_FAST_BACK); 267 ASSERT_BIT_CLEAR(data, PCI_COMMAND_INTX_DISABLE); 268 ASSERT_BIT_CLEAR(data, 0xF800); /* Reserved */ 269 270 data = qpci_config_readw(ahci->dev, PCI_STATUS); 271 ASSERT_BIT_CLEAR(data, 0x01 | 0x02 | 0x04); /* Reserved */ 272 ASSERT_BIT_CLEAR(data, PCI_STATUS_INTERRUPT); 273 ASSERT_BIT_SET(data, PCI_STATUS_CAP_LIST); /* must be set */ 274 ASSERT_BIT_CLEAR(data, PCI_STATUS_UDF); /* Reserved */ 275 ASSERT_BIT_CLEAR(data, PCI_STATUS_PARITY); 276 ASSERT_BIT_CLEAR(data, PCI_STATUS_SIG_TARGET_ABORT); 277 ASSERT_BIT_CLEAR(data, PCI_STATUS_REC_TARGET_ABORT); 278 ASSERT_BIT_CLEAR(data, PCI_STATUS_REC_MASTER_ABORT); 279 ASSERT_BIT_CLEAR(data, PCI_STATUS_SIG_SYSTEM_ERROR); 280 ASSERT_BIT_CLEAR(data, PCI_STATUS_DETECTED_PARITY); 281 282 /* RID occupies the low byte, CCs occupy the high three. */ 283 datal = qpci_config_readl(ahci->dev, PCI_CLASS_REVISION); 284 if (ahci_pedantic) { 285 /* AHCI 1.3 specifies that at-boot, the RID should reset to 0x00, 286 * Though in practice this is likely seldom true. */ 287 ASSERT_BIT_CLEAR(datal, 0xFF); 288 } 289 290 /* BCC *must* equal 0x01. */ 291 g_assert_cmphex(PCI_BCC(datal), ==, 0x01); 292 if (PCI_SCC(datal) == 0x01) { 293 /* IDE */ 294 ASSERT_BIT_SET(0x80000000, datal); 295 ASSERT_BIT_CLEAR(0x60000000, datal); 296 } else if (PCI_SCC(datal) == 0x04) { 297 /* RAID */ 298 g_assert_cmphex(PCI_PI(datal), ==, 0); 299 } else if (PCI_SCC(datal) == 0x06) { 300 /* AHCI */ 301 g_assert_cmphex(PCI_PI(datal), ==, 0x01); 302 } else { 303 g_assert_not_reached(); 304 } 305 306 datab = qpci_config_readb(ahci->dev, PCI_CACHE_LINE_SIZE); 307 g_assert_cmphex(datab, ==, 0); 308 309 datab = qpci_config_readb(ahci->dev, PCI_LATENCY_TIMER); 310 g_assert_cmphex(datab, ==, 0); 311 312 /* Only the bottom 7 bits must be off. */ 313 datab = qpci_config_readb(ahci->dev, PCI_HEADER_TYPE); 314 ASSERT_BIT_CLEAR(datab, 0x7F); 315 316 /* BIST is optional, but the low 7 bits must always start off regardless. */ 317 datab = qpci_config_readb(ahci->dev, PCI_BIST); 318 ASSERT_BIT_CLEAR(datab, 0x7F); 319 320 /* BARS 0-4 do not have a boot spec, but ABAR/BAR5 must be clean. */ 321 datal = qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5); 322 g_assert_cmphex(datal, ==, 0); 323 324 qpci_config_writel(ahci->dev, PCI_BASE_ADDRESS_5, 0xFFFFFFFF); 325 datal = qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5); 326 /* ABAR must be 32-bit, memory mapped, non-prefetchable and 327 * must be >= 512 bytes. To that end, bits 0-8 must be off. */ 328 ASSERT_BIT_CLEAR(datal, 0xFF); 329 330 /* Capability list MUST be present, */ 331 datal = qpci_config_readl(ahci->dev, PCI_CAPABILITY_LIST); 332 /* But these bits are reserved. */ 333 ASSERT_BIT_CLEAR(datal, ~0xFF); 334 g_assert_cmphex(datal, !=, 0); 335 336 /* Check specification adherence for capability extenstions. */ 337 data = qpci_config_readw(ahci->dev, datal); 338 339 switch (ahci->fingerprint) { 340 case AHCI_INTEL_ICH9: 341 /* Intel ICH9 Family Datasheet 14.1.19 p.550 */ 342 g_assert_cmphex((data & 0xFF), ==, PCI_CAP_ID_MSI); 343 break; 344 default: 345 /* AHCI 1.3, Section 2.1.14 -- CAP must point to PMCAP. */ 346 g_assert_cmphex((data & 0xFF), ==, PCI_CAP_ID_PM); 347 } 348 349 ahci_test_pci_caps(ahci, data, (uint8_t)datal); 350 351 /* Reserved. */ 352 datal = qpci_config_readl(ahci->dev, PCI_CAPABILITY_LIST + 4); 353 g_assert_cmphex(datal, ==, 0); 354 355 /* IPIN might vary, but ILINE must be off. */ 356 datab = qpci_config_readb(ahci->dev, PCI_INTERRUPT_LINE); 357 g_assert_cmphex(datab, ==, 0); 358 } 359 360 /** 361 * Test PCI capabilities for AHCI specification adherence. 362 */ 363 static void ahci_test_pci_caps(AHCIQState *ahci, uint16_t header, 364 uint8_t offset) 365 { 366 uint8_t cid = header & 0xFF; 367 uint8_t next = header >> 8; 368 369 g_test_message("CID: %02x; next: %02x", cid, next); 370 371 switch (cid) { 372 case PCI_CAP_ID_PM: 373 ahci_test_pmcap(ahci, offset); 374 break; 375 case PCI_CAP_ID_MSI: 376 ahci_test_msicap(ahci, offset); 377 break; 378 case PCI_CAP_ID_SATA: 379 ahci_test_satacap(ahci, offset); 380 break; 381 382 default: 383 g_test_message("Unknown CAP 0x%02x", cid); 384 } 385 386 if (next) { 387 ahci_test_pci_caps(ahci, qpci_config_readw(ahci->dev, next), next); 388 } 389 } 390 391 /** 392 * Test SATA PCI capabilitity for AHCI specification adherence. 393 */ 394 static void ahci_test_satacap(AHCIQState *ahci, uint8_t offset) 395 { 396 uint16_t dataw; 397 uint32_t datal; 398 399 g_test_message("Verifying SATACAP"); 400 401 /* Assert that the SATACAP version is 1.0, And reserved bits are empty. */ 402 dataw = qpci_config_readw(ahci->dev, offset + 2); 403 g_assert_cmphex(dataw, ==, 0x10); 404 405 /* Grab the SATACR1 register. */ 406 datal = qpci_config_readw(ahci->dev, offset + 4); 407 408 switch (datal & 0x0F) { 409 case 0x04: /* BAR0 */ 410 case 0x05: /* BAR1 */ 411 case 0x06: 412 case 0x07: 413 case 0x08: 414 case 0x09: /* BAR5 */ 415 case 0x0F: /* Immediately following SATACR1 in PCI config space. */ 416 break; 417 default: 418 /* Invalid BARLOC for the Index Data Pair. */ 419 g_assert_not_reached(); 420 } 421 422 /* Reserved. */ 423 g_assert_cmphex((datal >> 24), ==, 0x00); 424 } 425 426 /** 427 * Test MSI PCI capability for AHCI specification adherence. 428 */ 429 static void ahci_test_msicap(AHCIQState *ahci, uint8_t offset) 430 { 431 uint16_t dataw; 432 uint32_t datal; 433 434 g_test_message("Verifying MSICAP"); 435 436 dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_FLAGS); 437 ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_ENABLE); 438 ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_QSIZE); 439 ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_RESERVED); 440 441 datal = qpci_config_readl(ahci->dev, offset + PCI_MSI_ADDRESS_LO); 442 g_assert_cmphex(datal, ==, 0); 443 444 if (dataw & PCI_MSI_FLAGS_64BIT) { 445 g_test_message("MSICAP is 64bit"); 446 datal = qpci_config_readl(ahci->dev, offset + PCI_MSI_ADDRESS_HI); 447 g_assert_cmphex(datal, ==, 0); 448 dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_DATA_64); 449 g_assert_cmphex(dataw, ==, 0); 450 } else { 451 g_test_message("MSICAP is 32bit"); 452 dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_DATA_32); 453 g_assert_cmphex(dataw, ==, 0); 454 } 455 } 456 457 /** 458 * Test Power Management PCI capability for AHCI specification adherence. 459 */ 460 static void ahci_test_pmcap(AHCIQState *ahci, uint8_t offset) 461 { 462 uint16_t dataw; 463 464 g_test_message("Verifying PMCAP"); 465 466 dataw = qpci_config_readw(ahci->dev, offset + PCI_PM_PMC); 467 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_PME_CLOCK); 468 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_RESERVED); 469 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_D1); 470 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_D2); 471 472 dataw = qpci_config_readw(ahci->dev, offset + PCI_PM_CTRL); 473 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_STATE_MASK); 474 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_RESERVED); 475 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_DATA_SEL_MASK); 476 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_DATA_SCALE_MASK); 477 } 478 479 static void ahci_test_hba_spec(AHCIQState *ahci) 480 { 481 unsigned i; 482 uint32_t reg; 483 uint32_t ports; 484 uint8_t nports_impl; 485 uint8_t maxports; 486 487 g_assert(ahci != NULL); 488 489 /* 490 * Note that the AHCI spec does expect the BIOS to set up a few things: 491 * CAP.SSS - Support for staggered spin-up (t/f) 492 * CAP.SMPS - Support for mechanical presence switches (t/f) 493 * PI - Ports Implemented (1-32) 494 * PxCMD.HPCP - Hot Plug Capable Port 495 * PxCMD.MPSP - Mechanical Presence Switch Present 496 * PxCMD.CPD - Cold Presence Detection support 497 * 498 * Additional items are touched if CAP.SSS is on, see AHCI 10.1.1 p.97: 499 * Foreach Port Implemented: 500 * -PxCMD.ST, PxCMD.CR, PxCMD.FRE, PxCMD.FR, PxSCTL.DET are 0 501 * -PxCLB/U and PxFB/U are set to valid regions in memory 502 * -PxSUD is set to 1. 503 * -PxSSTS.DET is polled for presence; if detected, we continue: 504 * -PxSERR is cleared with 1's. 505 * -If PxTFD.STS.BSY, PxTFD.STS.DRQ, and PxTFD.STS.ERR are all zero, 506 * the device is ready. 507 */ 508 509 /* 1 CAP - Capabilities Register */ 510 ahci->cap = ahci_rreg(ahci, AHCI_CAP); 511 ASSERT_BIT_CLEAR(ahci->cap, AHCI_CAP_RESERVED); 512 513 /* 2 GHC - Global Host Control */ 514 reg = ahci_rreg(ahci, AHCI_GHC); 515 ASSERT_BIT_CLEAR(reg, AHCI_GHC_HR); 516 ASSERT_BIT_CLEAR(reg, AHCI_GHC_IE); 517 ASSERT_BIT_CLEAR(reg, AHCI_GHC_MRSM); 518 if (BITSET(ahci->cap, AHCI_CAP_SAM)) { 519 g_test_message("Supports AHCI-Only Mode: GHC_AE is Read-Only."); 520 ASSERT_BIT_SET(reg, AHCI_GHC_AE); 521 } else { 522 g_test_message("Supports AHCI/Legacy mix."); 523 ASSERT_BIT_CLEAR(reg, AHCI_GHC_AE); 524 } 525 526 /* 3 IS - Interrupt Status */ 527 reg = ahci_rreg(ahci, AHCI_IS); 528 g_assert_cmphex(reg, ==, 0); 529 530 /* 4 PI - Ports Implemented */ 531 ports = ahci_rreg(ahci, AHCI_PI); 532 /* Ports Implemented must be non-zero. */ 533 g_assert_cmphex(ports, !=, 0); 534 /* Ports Implemented must be <= Number of Ports. */ 535 nports_impl = ctpopl(ports); 536 g_assert_cmpuint(((AHCI_CAP_NP & ahci->cap) + 1), >=, nports_impl); 537 538 /* Ports must be within the proper range. Given a mapping of SIZE, 539 * 256 bytes are used for global HBA control, and the rest is used 540 * for ports data, at 0x80 bytes each. */ 541 g_assert_cmphex(ahci->barsize, >, 0); 542 maxports = (ahci->barsize - HBA_DATA_REGION_SIZE) / HBA_PORT_DATA_SIZE; 543 /* e.g, 30 ports for 4K of memory. (4096 - 256) / 128 = 30 */ 544 g_assert_cmphex((reg >> maxports), ==, 0); 545 546 /* 5 AHCI Version */ 547 reg = ahci_rreg(ahci, AHCI_VS); 548 switch (reg) { 549 case AHCI_VERSION_0_95: 550 case AHCI_VERSION_1_0: 551 case AHCI_VERSION_1_1: 552 case AHCI_VERSION_1_2: 553 case AHCI_VERSION_1_3: 554 break; 555 default: 556 g_assert_not_reached(); 557 } 558 559 /* 6 Command Completion Coalescing Control: depends on CAP.CCCS. */ 560 reg = ahci_rreg(ahci, AHCI_CCCCTL); 561 if (BITSET(ahci->cap, AHCI_CAP_CCCS)) { 562 ASSERT_BIT_CLEAR(reg, AHCI_CCCCTL_EN); 563 ASSERT_BIT_CLEAR(reg, AHCI_CCCCTL_RESERVED); 564 ASSERT_BIT_SET(reg, AHCI_CCCCTL_CC); 565 ASSERT_BIT_SET(reg, AHCI_CCCCTL_TV); 566 } else { 567 g_assert_cmphex(reg, ==, 0); 568 } 569 570 /* 7 CCC_PORTS */ 571 reg = ahci_rreg(ahci, AHCI_CCCPORTS); 572 /* Must be zeroes initially regardless of CAP.CCCS */ 573 g_assert_cmphex(reg, ==, 0); 574 575 /* 8 EM_LOC */ 576 reg = ahci_rreg(ahci, AHCI_EMLOC); 577 if (BITCLR(ahci->cap, AHCI_CAP_EMS)) { 578 g_assert_cmphex(reg, ==, 0); 579 } 580 581 /* 9 EM_CTL */ 582 reg = ahci_rreg(ahci, AHCI_EMCTL); 583 if (BITSET(ahci->cap, AHCI_CAP_EMS)) { 584 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_STSMR); 585 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_CTLTM); 586 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_CTLRST); 587 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_RESERVED); 588 } else { 589 g_assert_cmphex(reg, ==, 0); 590 } 591 592 /* 10 CAP2 -- Capabilities Extended */ 593 ahci->cap2 = ahci_rreg(ahci, AHCI_CAP2); 594 ASSERT_BIT_CLEAR(ahci->cap2, AHCI_CAP2_RESERVED); 595 596 /* 11 BOHC -- Bios/OS Handoff Control */ 597 reg = ahci_rreg(ahci, AHCI_BOHC); 598 g_assert_cmphex(reg, ==, 0); 599 600 /* 12 -- 23: Reserved */ 601 g_test_message("Verifying HBA reserved area is empty."); 602 for (i = AHCI_RESERVED; i < AHCI_NVMHCI; ++i) { 603 reg = ahci_rreg(ahci, i); 604 g_assert_cmphex(reg, ==, 0); 605 } 606 607 /* 24 -- 39: NVMHCI */ 608 if (BITCLR(ahci->cap2, AHCI_CAP2_NVMP)) { 609 g_test_message("Verifying HBA/NVMHCI area is empty."); 610 for (i = AHCI_NVMHCI; i < AHCI_VENDOR; ++i) { 611 reg = ahci_rreg(ahci, i); 612 g_assert_cmphex(reg, ==, 0); 613 } 614 } 615 616 /* 40 -- 63: Vendor */ 617 g_test_message("Verifying HBA/Vendor area is empty."); 618 for (i = AHCI_VENDOR; i < AHCI_PORTS; ++i) { 619 reg = ahci_rreg(ahci, i); 620 g_assert_cmphex(reg, ==, 0); 621 } 622 623 /* 64 -- XX: Port Space */ 624 for (i = 0; ports || (i < maxports); ports >>= 1, ++i) { 625 if (BITSET(ports, 0x1)) { 626 g_test_message("Testing port %u for spec", i); 627 ahci_test_port_spec(ahci, i); 628 } else { 629 uint16_t j; 630 uint16_t low = AHCI_PORTS + (32 * i); 631 uint16_t high = AHCI_PORTS + (32 * (i + 1)); 632 g_test_message("Asserting unimplemented port %u " 633 "(reg [%u-%u]) is empty.", 634 i, low, high - 1); 635 for (j = low; j < high; ++j) { 636 reg = ahci_rreg(ahci, j); 637 g_assert_cmphex(reg, ==, 0); 638 } 639 } 640 } 641 } 642 643 /** 644 * Test the memory space for one port for specification adherence. 645 */ 646 static void ahci_test_port_spec(AHCIQState *ahci, uint8_t port) 647 { 648 uint32_t reg; 649 unsigned i; 650 651 /* (0) CLB */ 652 reg = ahci_px_rreg(ahci, port, AHCI_PX_CLB); 653 ASSERT_BIT_CLEAR(reg, AHCI_PX_CLB_RESERVED); 654 655 /* (1) CLBU */ 656 if (BITCLR(ahci->cap, AHCI_CAP_S64A)) { 657 reg = ahci_px_rreg(ahci, port, AHCI_PX_CLBU); 658 g_assert_cmphex(reg, ==, 0); 659 } 660 661 /* (2) FB */ 662 reg = ahci_px_rreg(ahci, port, AHCI_PX_FB); 663 ASSERT_BIT_CLEAR(reg, AHCI_PX_FB_RESERVED); 664 665 /* (3) FBU */ 666 if (BITCLR(ahci->cap, AHCI_CAP_S64A)) { 667 reg = ahci_px_rreg(ahci, port, AHCI_PX_FBU); 668 g_assert_cmphex(reg, ==, 0); 669 } 670 671 /* (4) IS */ 672 reg = ahci_px_rreg(ahci, port, AHCI_PX_IS); 673 g_assert_cmphex(reg, ==, 0); 674 675 /* (5) IE */ 676 reg = ahci_px_rreg(ahci, port, AHCI_PX_IE); 677 g_assert_cmphex(reg, ==, 0); 678 679 /* (6) CMD */ 680 reg = ahci_px_rreg(ahci, port, AHCI_PX_CMD); 681 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FRE); 682 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_RESERVED); 683 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CCS); 684 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FR); 685 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CR); 686 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_PMA); /* And RW only if CAP.SPM */ 687 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_APSTE); /* RW only if CAP2.APST */ 688 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ATAPI); 689 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_DLAE); 690 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ALPE); /* RW only if CAP.SALP */ 691 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ASP); /* RW only if CAP.SALP */ 692 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ICC); 693 /* If CPDetect support does not exist, CPState must be off. */ 694 if (BITCLR(reg, AHCI_PX_CMD_CPD)) { 695 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CPS); 696 } 697 /* If MPSPresence is not set, MPSState must be off. */ 698 if (BITCLR(reg, AHCI_PX_CMD_MPSP)) { 699 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSS); 700 } 701 /* If we do not support MPS, MPSS and MPSP must be off. */ 702 if (BITCLR(ahci->cap, AHCI_CAP_SMPS)) { 703 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSS); 704 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSP); 705 } 706 /* If, via CPD or MPSP we detect a drive, HPCP must be on. */ 707 if (BITANY(reg, AHCI_PX_CMD_CPD | AHCI_PX_CMD_MPSP)) { 708 ASSERT_BIT_SET(reg, AHCI_PX_CMD_HPCP); 709 } 710 /* HPCP and ESP cannot both be active. */ 711 g_assert(!BITSET(reg, AHCI_PX_CMD_HPCP | AHCI_PX_CMD_ESP)); 712 /* If CAP.FBSS is not set, FBSCP must not be set. */ 713 if (BITCLR(ahci->cap, AHCI_CAP_FBSS)) { 714 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FBSCP); 715 } 716 717 /* (7) RESERVED */ 718 reg = ahci_px_rreg(ahci, port, AHCI_PX_RES1); 719 g_assert_cmphex(reg, ==, 0); 720 721 /* (8) TFD */ 722 reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD); 723 /* At boot, prior to an FIS being received, the TFD register should be 0x7F, 724 * which breaks down as follows, as seen in AHCI 1.3 sec 3.3.8, p. 27. */ 725 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_ERR); 726 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_CS1); 727 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_DRQ); 728 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_CS2); 729 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_BSY); 730 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_ERR); 731 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_RESERVED); 732 733 /* (9) SIG */ 734 /* Though AHCI specifies the boot value should be 0xFFFFFFFF, 735 * Even when GHC.ST is zero, the AHCI HBA may receive the initial 736 * D2H register FIS and update the signature asynchronously, 737 * so we cannot expect a value here. AHCI 1.3, sec 3.3.9, pp 27-28 */ 738 739 /* (10) SSTS / SCR0: SStatus */ 740 reg = ahci_px_rreg(ahci, port, AHCI_PX_SSTS); 741 ASSERT_BIT_CLEAR(reg, AHCI_PX_SSTS_RESERVED); 742 /* Even though the register should be 0 at boot, it is asynchronous and 743 * prone to change, so we cannot test any well known value. */ 744 745 /* (11) SCTL / SCR2: SControl */ 746 reg = ahci_px_rreg(ahci, port, AHCI_PX_SCTL); 747 g_assert_cmphex(reg, ==, 0); 748 749 /* (12) SERR / SCR1: SError */ 750 reg = ahci_px_rreg(ahci, port, AHCI_PX_SERR); 751 g_assert_cmphex(reg, ==, 0); 752 753 /* (13) SACT / SCR3: SActive */ 754 reg = ahci_px_rreg(ahci, port, AHCI_PX_SACT); 755 g_assert_cmphex(reg, ==, 0); 756 757 /* (14) CI */ 758 reg = ahci_px_rreg(ahci, port, AHCI_PX_CI); 759 g_assert_cmphex(reg, ==, 0); 760 761 /* (15) SNTF */ 762 reg = ahci_px_rreg(ahci, port, AHCI_PX_SNTF); 763 g_assert_cmphex(reg, ==, 0); 764 765 /* (16) FBS */ 766 reg = ahci_px_rreg(ahci, port, AHCI_PX_FBS); 767 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_EN); 768 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DEC); 769 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_SDE); 770 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DEV); 771 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DWE); 772 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_RESERVED); 773 if (BITSET(ahci->cap, AHCI_CAP_FBSS)) { 774 /* if Port-Multiplier FIS-based switching avail, ADO must >= 2 */ 775 g_assert((reg & AHCI_PX_FBS_ADO) >> ctzl(AHCI_PX_FBS_ADO) >= 2); 776 } 777 778 /* [17 -- 27] RESERVED */ 779 for (i = AHCI_PX_RES2; i < AHCI_PX_VS; ++i) { 780 reg = ahci_px_rreg(ahci, port, i); 781 g_assert_cmphex(reg, ==, 0); 782 } 783 784 /* [28 -- 31] Vendor-Specific */ 785 for (i = AHCI_PX_VS; i < 32; ++i) { 786 reg = ahci_px_rreg(ahci, port, i); 787 if (reg) { 788 g_test_message("INFO: Vendor register %u non-empty", i); 789 } 790 } 791 } 792 793 /** 794 * Utilizing an initialized AHCI HBA, issue an IDENTIFY command to the first 795 * device we see, then read and check the response. 796 */ 797 static void ahci_test_identify(AHCIQState *ahci) 798 { 799 uint16_t buff[256]; 800 unsigned px; 801 int rc; 802 uint16_t sect_size; 803 const size_t buffsize = 512; 804 805 g_assert(ahci != NULL); 806 807 /** 808 * This serves as a bit of a tutorial on AHCI device programming: 809 * 810 * (1) Create a data buffer for the IDENTIFY response to be sent to 811 * (2) Create a Command Table buffer, where we will store the 812 * command and PRDT (Physical Region Descriptor Table) 813 * (3) Construct an FIS host-to-device command structure, and write it to 814 * the top of the Command Table buffer. 815 * (4) Create one or more Physical Region Descriptors (PRDs) that describe 816 * a location in memory where data may be stored/retrieved. 817 * (5) Write these PRDTs to the bottom (offset 0x80) of the Command Table. 818 * (6) Each AHCI port has up to 32 command slots. Each slot contains a 819 * header that points to a Command Table buffer. Pick an unused slot 820 * and update it to point to the Command Table we have built. 821 * (7) Now: Command #n points to our Command Table, and our Command Table 822 * contains the FIS (that describes our command) and the PRDTL, which 823 * describes our buffer. 824 * (8) We inform the HBA via PxCI (Command Issue) that the command in slot 825 * #n is ready for processing. 826 */ 827 828 /* Pick the first implemented and running port */ 829 px = ahci_port_select(ahci); 830 g_test_message("Selected port %u for test", px); 831 832 /* Clear out the FIS Receive area and any pending interrupts. */ 833 ahci_port_clear(ahci, px); 834 835 /* "Read" 512 bytes using CMD_IDENTIFY into the host buffer. */ 836 ahci_io(ahci, px, CMD_IDENTIFY, &buff, buffsize, 0); 837 838 /* Check serial number/version in the buffer */ 839 /* NB: IDENTIFY strings are packed in 16bit little endian chunks. 840 * Since we copy byte-for-byte in ahci-test, on both LE and BE, we need to 841 * unchunk this data. By contrast, ide-test copies 2 bytes at a time, and 842 * as a consequence, only needs to unchunk the data on LE machines. */ 843 string_bswap16(&buff[10], 20); 844 rc = memcmp(&buff[10], "testdisk ", 20); 845 g_assert_cmphex(rc, ==, 0); 846 847 string_bswap16(&buff[23], 8); 848 rc = memcmp(&buff[23], "version ", 8); 849 g_assert_cmphex(rc, ==, 0); 850 851 sect_size = le16_to_cpu(*((uint16_t *)(&buff[5]))); 852 g_assert_cmphex(sect_size, ==, AHCI_SECTOR_SIZE); 853 } 854 855 static void ahci_test_io_rw_simple(AHCIQState *ahci, unsigned bufsize, 856 uint64_t sector, uint8_t read_cmd, 857 uint8_t write_cmd) 858 { 859 uint64_t ptr; 860 uint8_t port; 861 unsigned char *tx = g_malloc(bufsize); 862 unsigned char *rx = g_malloc0(bufsize); 863 864 g_assert(ahci != NULL); 865 866 /* Pick the first running port and clear it. */ 867 port = ahci_port_select(ahci); 868 ahci_port_clear(ahci, port); 869 870 /*** Create pattern and transfer to guest ***/ 871 /* Data buffer in the guest */ 872 ptr = ahci_alloc(ahci, bufsize); 873 g_assert(ptr); 874 875 /* Write some indicative pattern to our buffer. */ 876 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE); 877 qtest_bufwrite(ahci->parent->qts, ptr, tx, bufsize); 878 879 /* Write this buffer to disk, then read it back to the DMA buffer. */ 880 ahci_guest_io(ahci, port, write_cmd, ptr, bufsize, sector); 881 qtest_memset(ahci->parent->qts, ptr, 0x00, bufsize); 882 ahci_guest_io(ahci, port, read_cmd, ptr, bufsize, sector); 883 884 /*** Read back the Data ***/ 885 qtest_bufread(ahci->parent->qts, ptr, rx, bufsize); 886 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0); 887 888 ahci_free(ahci, ptr); 889 g_free(tx); 890 g_free(rx); 891 } 892 893 static uint8_t ahci_test_nondata(AHCIQState *ahci, uint8_t ide_cmd) 894 { 895 uint8_t port; 896 897 /* Sanitize */ 898 port = ahci_port_select(ahci); 899 ahci_port_clear(ahci, port); 900 901 ahci_io(ahci, port, ide_cmd, NULL, 0, 0); 902 903 return port; 904 } 905 906 static void ahci_test_flush(AHCIQState *ahci) 907 { 908 ahci_test_nondata(ahci, CMD_FLUSH_CACHE); 909 } 910 911 static void ahci_test_max(AHCIQState *ahci) 912 { 913 RegD2HFIS *d2h = g_malloc0(0x20); 914 uint64_t nsect; 915 uint8_t port; 916 uint8_t cmd; 917 uint64_t config_sect = mb_to_sectors(test_image_size_mb) - 1; 918 919 if (config_sect > 0xFFFFFF) { 920 cmd = CMD_READ_MAX_EXT; 921 } else { 922 cmd = CMD_READ_MAX; 923 } 924 925 port = ahci_test_nondata(ahci, cmd); 926 qtest_memread(ahci->parent->qts, ahci->port[port].fb + 0x40, d2h, 0x20); 927 nsect = (uint64_t)d2h->lba_hi[2] << 40 | 928 (uint64_t)d2h->lba_hi[1] << 32 | 929 (uint64_t)d2h->lba_hi[0] << 24 | 930 (uint64_t)d2h->lba_lo[2] << 16 | 931 (uint64_t)d2h->lba_lo[1] << 8 | 932 (uint64_t)d2h->lba_lo[0]; 933 934 g_assert_cmphex(nsect, ==, config_sect); 935 g_free(d2h); 936 } 937 938 939 /******************************************************************************/ 940 /* Test Interfaces */ 941 /******************************************************************************/ 942 943 /** 944 * Basic sanity test to boot a machine, find an AHCI device, and shutdown. 945 */ 946 static void test_sanity(void) 947 { 948 AHCIQState *ahci; 949 ahci = ahci_boot(NULL); 950 ahci_shutdown(ahci); 951 } 952 953 /** 954 * Ensure that the PCI configuration space for the AHCI device is in-line with 955 * the AHCI 1.3 specification for initial values. 956 */ 957 static void test_pci_spec(void) 958 { 959 AHCIQState *ahci; 960 ahci = ahci_boot(NULL); 961 ahci_test_pci_spec(ahci); 962 ahci_shutdown(ahci); 963 } 964 965 /** 966 * Engage the PCI AHCI device and sanity check the response. 967 * Perform additional PCI config space bringup for the HBA. 968 */ 969 static void test_pci_enable(void) 970 { 971 AHCIQState *ahci; 972 ahci = ahci_boot(NULL); 973 ahci_pci_enable(ahci); 974 ahci_shutdown(ahci); 975 } 976 977 /** 978 * Investigate the memory mapped regions of the HBA, 979 * and test them for AHCI specification adherence. 980 */ 981 static void test_hba_spec(void) 982 { 983 AHCIQState *ahci; 984 985 ahci = ahci_boot(NULL); 986 ahci_pci_enable(ahci); 987 ahci_test_hba_spec(ahci); 988 ahci_shutdown(ahci); 989 } 990 991 /** 992 * Engage the HBA functionality of the AHCI PCI device, 993 * and bring it into a functional idle state. 994 */ 995 static void test_hba_enable(void) 996 { 997 AHCIQState *ahci; 998 999 ahci = ahci_boot(NULL); 1000 ahci_pci_enable(ahci); 1001 ahci_hba_enable(ahci); 1002 ahci_shutdown(ahci); 1003 } 1004 1005 /** 1006 * Bring up the device and issue an IDENTIFY command. 1007 * Inspect the state of the HBA device and the data returned. 1008 */ 1009 static void test_identify(void) 1010 { 1011 AHCIQState *ahci; 1012 1013 ahci = ahci_boot_and_enable(NULL); 1014 ahci_test_identify(ahci); 1015 ahci_shutdown(ahci); 1016 } 1017 1018 /** 1019 * Fragmented DMA test: Perform a standard 4K DMA read/write 1020 * test, but make sure the physical regions are fragmented to 1021 * be very small, each just 32 bytes, to see how AHCI performs 1022 * with chunks defined to be much less than a sector. 1023 */ 1024 static void test_dma_fragmented(void) 1025 { 1026 AHCIQState *ahci; 1027 AHCICommand *cmd; 1028 uint8_t px; 1029 size_t bufsize = 4096; 1030 unsigned char *tx = g_malloc(bufsize); 1031 unsigned char *rx = g_malloc0(bufsize); 1032 uint64_t ptr; 1033 1034 ahci = ahci_boot_and_enable(NULL); 1035 px = ahci_port_select(ahci); 1036 ahci_port_clear(ahci, px); 1037 1038 /* create pattern */ 1039 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE); 1040 1041 /* Create a DMA buffer in guest memory, and write our pattern to it. */ 1042 ptr = guest_alloc(&ahci->parent->alloc, bufsize); 1043 g_assert(ptr); 1044 qtest_bufwrite(ahci->parent->qts, ptr, tx, bufsize); 1045 1046 cmd = ahci_command_create(CMD_WRITE_DMA); 1047 ahci_command_adjust(cmd, 0, ptr, bufsize, 32); 1048 ahci_command_commit(ahci, cmd, px); 1049 ahci_command_issue(ahci, cmd); 1050 ahci_command_verify(ahci, cmd); 1051 ahci_command_free(cmd); 1052 1053 cmd = ahci_command_create(CMD_READ_DMA); 1054 ahci_command_adjust(cmd, 0, ptr, bufsize, 32); 1055 ahci_command_commit(ahci, cmd, px); 1056 ahci_command_issue(ahci, cmd); 1057 ahci_command_verify(ahci, cmd); 1058 ahci_command_free(cmd); 1059 1060 /* Read back the guest's receive buffer into local memory */ 1061 qtest_bufread(ahci->parent->qts, ptr, rx, bufsize); 1062 guest_free(&ahci->parent->alloc, ptr); 1063 1064 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0); 1065 1066 ahci_shutdown(ahci); 1067 1068 g_free(rx); 1069 g_free(tx); 1070 } 1071 1072 /* 1073 * Write sector 1 with random data to make AHCI storage dirty 1074 * Needed for flush tests so that flushes actually go though the block layer 1075 */ 1076 static void make_dirty(AHCIQState* ahci, uint8_t port) 1077 { 1078 uint64_t ptr; 1079 unsigned bufsize = 512; 1080 1081 ptr = ahci_alloc(ahci, bufsize); 1082 g_assert(ptr); 1083 1084 ahci_guest_io(ahci, port, CMD_WRITE_DMA, ptr, bufsize, 1); 1085 ahci_free(ahci, ptr); 1086 } 1087 1088 static void test_flush(void) 1089 { 1090 AHCIQState *ahci; 1091 uint8_t port; 1092 1093 ahci = ahci_boot_and_enable(NULL); 1094 1095 port = ahci_port_select(ahci); 1096 ahci_port_clear(ahci, port); 1097 1098 make_dirty(ahci, port); 1099 1100 ahci_test_flush(ahci); 1101 ahci_shutdown(ahci); 1102 } 1103 1104 static void test_flush_retry(void) 1105 { 1106 AHCIQState *ahci; 1107 AHCICommand *cmd; 1108 uint8_t port; 1109 1110 prepare_blkdebug_script(debug_path, "flush_to_disk"); 1111 ahci = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0," 1112 "format=%s,cache=writeback," 1113 "rerror=stop,werror=stop " 1114 "-M q35 " 1115 "-device ide-hd,drive=drive0 ", 1116 debug_path, 1117 tmp_path, imgfmt); 1118 1119 port = ahci_port_select(ahci); 1120 ahci_port_clear(ahci, port); 1121 1122 /* Issue write so that flush actually goes to disk */ 1123 make_dirty(ahci, port); 1124 1125 /* Issue Flush Command and wait for error */ 1126 cmd = ahci_guest_io_halt(ahci, port, CMD_FLUSH_CACHE, 0, 0, 0); 1127 ahci_guest_io_resume(ahci, cmd); 1128 1129 ahci_shutdown(ahci); 1130 } 1131 1132 /** 1133 * Basic sanity test to boot a machine, find an AHCI device, and shutdown. 1134 */ 1135 static void test_migrate_sanity(void) 1136 { 1137 AHCIQState *src, *dst; 1138 char *uri = g_strdup_printf("unix:%s", mig_socket); 1139 1140 src = ahci_boot("-m 384 -M q35 " 1141 "-drive if=ide,file=%s,format=%s ", tmp_path, imgfmt); 1142 dst = ahci_boot("-m 384 -M q35 " 1143 "-drive if=ide,file=%s,format=%s " 1144 "-incoming %s", tmp_path, imgfmt, uri); 1145 1146 ahci_migrate(src, dst, uri); 1147 1148 ahci_shutdown(src); 1149 ahci_shutdown(dst); 1150 g_free(uri); 1151 } 1152 1153 /** 1154 * Simple migration test: Write a pattern, migrate, then read. 1155 */ 1156 static void ahci_migrate_simple(uint8_t cmd_read, uint8_t cmd_write) 1157 { 1158 AHCIQState *src, *dst; 1159 uint8_t px; 1160 size_t bufsize = 4096; 1161 unsigned char *tx = g_malloc(bufsize); 1162 unsigned char *rx = g_malloc0(bufsize); 1163 char *uri = g_strdup_printf("unix:%s", mig_socket); 1164 1165 src = ahci_boot_and_enable("-m 384 -M q35 " 1166 "-drive if=ide,format=%s,file=%s ", 1167 imgfmt, tmp_path); 1168 dst = ahci_boot("-m 384 -M q35 " 1169 "-drive if=ide,format=%s,file=%s " 1170 "-incoming %s", imgfmt, tmp_path, uri); 1171 1172 /* initialize */ 1173 px = ahci_port_select(src); 1174 ahci_port_clear(src, px); 1175 1176 /* create pattern */ 1177 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE); 1178 1179 /* Write, migrate, then read. */ 1180 ahci_io(src, px, cmd_write, tx, bufsize, 0); 1181 ahci_migrate(src, dst, uri); 1182 ahci_io(dst, px, cmd_read, rx, bufsize, 0); 1183 1184 /* Verify pattern */ 1185 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0); 1186 1187 ahci_shutdown(src); 1188 ahci_shutdown(dst); 1189 g_free(rx); 1190 g_free(tx); 1191 g_free(uri); 1192 } 1193 1194 static void test_migrate_dma(void) 1195 { 1196 ahci_migrate_simple(CMD_READ_DMA, CMD_WRITE_DMA); 1197 } 1198 1199 static void test_migrate_ncq(void) 1200 { 1201 ahci_migrate_simple(READ_FPDMA_QUEUED, WRITE_FPDMA_QUEUED); 1202 } 1203 1204 /** 1205 * Halted IO Error Test 1206 * 1207 * Simulate an error on first write, Try to write a pattern, 1208 * Confirm the VM has stopped, resume the VM, verify command 1209 * has completed, then read back the data and verify. 1210 */ 1211 static void ahci_halted_io_test(uint8_t cmd_read, uint8_t cmd_write) 1212 { 1213 AHCIQState *ahci; 1214 uint8_t port; 1215 size_t bufsize = 4096; 1216 unsigned char *tx = g_malloc(bufsize); 1217 unsigned char *rx = g_malloc0(bufsize); 1218 uint64_t ptr; 1219 AHCICommand *cmd; 1220 1221 prepare_blkdebug_script(debug_path, "write_aio"); 1222 1223 ahci = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0," 1224 "format=%s,cache=writeback," 1225 "rerror=stop,werror=stop " 1226 "-M q35 " 1227 "-device ide-hd,drive=drive0 ", 1228 debug_path, 1229 tmp_path, imgfmt); 1230 1231 /* Initialize and prepare */ 1232 port = ahci_port_select(ahci); 1233 ahci_port_clear(ahci, port); 1234 1235 /* create DMA source buffer and write pattern */ 1236 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE); 1237 ptr = ahci_alloc(ahci, bufsize); 1238 g_assert(ptr); 1239 qtest_memwrite(ahci->parent->qts, ptr, tx, bufsize); 1240 1241 /* Attempt to write (and fail) */ 1242 cmd = ahci_guest_io_halt(ahci, port, cmd_write, 1243 ptr, bufsize, 0); 1244 1245 /* Attempt to resume the command */ 1246 ahci_guest_io_resume(ahci, cmd); 1247 ahci_free(ahci, ptr); 1248 1249 /* Read back and verify */ 1250 ahci_io(ahci, port, cmd_read, rx, bufsize, 0); 1251 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0); 1252 1253 /* Cleanup and go home */ 1254 ahci_shutdown(ahci); 1255 g_free(rx); 1256 g_free(tx); 1257 } 1258 1259 static void test_halted_dma(void) 1260 { 1261 ahci_halted_io_test(CMD_READ_DMA, CMD_WRITE_DMA); 1262 } 1263 1264 static void test_halted_ncq(void) 1265 { 1266 ahci_halted_io_test(READ_FPDMA_QUEUED, WRITE_FPDMA_QUEUED); 1267 } 1268 1269 /** 1270 * IO Error Migration Test 1271 * 1272 * Simulate an error on first write, Try to write a pattern, 1273 * Confirm the VM has stopped, migrate, resume the VM, 1274 * verify command has completed, then read back the data and verify. 1275 */ 1276 static void ahci_migrate_halted_io(uint8_t cmd_read, uint8_t cmd_write) 1277 { 1278 AHCIQState *src, *dst; 1279 uint8_t port; 1280 size_t bufsize = 4096; 1281 unsigned char *tx = g_malloc(bufsize); 1282 unsigned char *rx = g_malloc0(bufsize); 1283 uint64_t ptr; 1284 AHCICommand *cmd; 1285 char *uri = g_strdup_printf("unix:%s", mig_socket); 1286 1287 prepare_blkdebug_script(debug_path, "write_aio"); 1288 1289 src = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0," 1290 "format=%s,cache=writeback," 1291 "rerror=stop,werror=stop " 1292 "-M q35 " 1293 "-device ide-hd,drive=drive0 ", 1294 debug_path, 1295 tmp_path, imgfmt); 1296 1297 dst = ahci_boot("-drive file=%s,if=none,id=drive0," 1298 "format=%s,cache=writeback," 1299 "rerror=stop,werror=stop " 1300 "-M q35 " 1301 "-device ide-hd,drive=drive0 " 1302 "-incoming %s", 1303 tmp_path, imgfmt, uri); 1304 1305 /* Initialize and prepare */ 1306 port = ahci_port_select(src); 1307 ahci_port_clear(src, port); 1308 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE); 1309 1310 /* create DMA source buffer and write pattern */ 1311 ptr = ahci_alloc(src, bufsize); 1312 g_assert(ptr); 1313 qtest_memwrite(src->parent->qts, ptr, tx, bufsize); 1314 1315 /* Write, trigger the VM to stop, migrate, then resume. */ 1316 cmd = ahci_guest_io_halt(src, port, cmd_write, 1317 ptr, bufsize, 0); 1318 ahci_migrate(src, dst, uri); 1319 ahci_guest_io_resume(dst, cmd); 1320 ahci_free(dst, ptr); 1321 1322 /* Read back */ 1323 ahci_io(dst, port, cmd_read, rx, bufsize, 0); 1324 1325 /* Verify TX and RX are identical */ 1326 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0); 1327 1328 /* Cleanup and go home. */ 1329 ahci_shutdown(src); 1330 ahci_shutdown(dst); 1331 g_free(rx); 1332 g_free(tx); 1333 g_free(uri); 1334 } 1335 1336 static void test_migrate_halted_dma(void) 1337 { 1338 ahci_migrate_halted_io(CMD_READ_DMA, CMD_WRITE_DMA); 1339 } 1340 1341 static void test_migrate_halted_ncq(void) 1342 { 1343 ahci_migrate_halted_io(READ_FPDMA_QUEUED, WRITE_FPDMA_QUEUED); 1344 } 1345 1346 /** 1347 * Migration test: Try to flush, migrate, then resume. 1348 */ 1349 static void test_flush_migrate(void) 1350 { 1351 AHCIQState *src, *dst; 1352 AHCICommand *cmd; 1353 uint8_t px; 1354 char *uri = g_strdup_printf("unix:%s", mig_socket); 1355 1356 prepare_blkdebug_script(debug_path, "flush_to_disk"); 1357 1358 src = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0," 1359 "cache=writeback,rerror=stop,werror=stop," 1360 "format=%s " 1361 "-M q35 " 1362 "-device ide-hd,drive=drive0 ", 1363 debug_path, tmp_path, imgfmt); 1364 dst = ahci_boot("-drive file=%s,if=none,id=drive0," 1365 "cache=writeback,rerror=stop,werror=stop," 1366 "format=%s " 1367 "-M q35 " 1368 "-device ide-hd,drive=drive0 " 1369 "-incoming %s", tmp_path, imgfmt, uri); 1370 1371 px = ahci_port_select(src); 1372 ahci_port_clear(src, px); 1373 1374 /* Dirty device so that flush reaches disk */ 1375 make_dirty(src, px); 1376 1377 /* Issue Flush Command */ 1378 cmd = ahci_command_create(CMD_FLUSH_CACHE); 1379 ahci_command_commit(src, cmd, px); 1380 ahci_command_issue_async(src, cmd); 1381 qtest_qmp_eventwait(src->parent->qts, "STOP"); 1382 1383 /* Migrate over */ 1384 ahci_migrate(src, dst, uri); 1385 1386 /* Complete the command */ 1387 qtest_qmp_send(dst->parent->qts, "{'execute':'cont' }"); 1388 qtest_qmp_eventwait(dst->parent->qts, "RESUME"); 1389 ahci_command_wait(dst, cmd); 1390 ahci_command_verify(dst, cmd); 1391 1392 ahci_command_free(cmd); 1393 ahci_shutdown(src); 1394 ahci_shutdown(dst); 1395 g_free(uri); 1396 } 1397 1398 static void test_max(void) 1399 { 1400 AHCIQState *ahci; 1401 1402 ahci = ahci_boot_and_enable(NULL); 1403 ahci_test_max(ahci); 1404 ahci_shutdown(ahci); 1405 } 1406 1407 static void test_reset(void) 1408 { 1409 AHCIQState *ahci; 1410 int i; 1411 1412 ahci = ahci_boot(NULL); 1413 ahci_test_pci_spec(ahci); 1414 ahci_pci_enable(ahci); 1415 1416 for (i = 0; i < 2; i++) { 1417 ahci_test_hba_spec(ahci); 1418 ahci_hba_enable(ahci); 1419 ahci_test_identify(ahci); 1420 ahci_test_io_rw_simple(ahci, 4096, 0, 1421 CMD_READ_DMA_EXT, 1422 CMD_WRITE_DMA_EXT); 1423 ahci_set(ahci, AHCI_GHC, AHCI_GHC_HR); 1424 ahci_clean_mem(ahci); 1425 } 1426 1427 ahci_shutdown(ahci); 1428 } 1429 1430 static void test_ncq_simple(void) 1431 { 1432 AHCIQState *ahci; 1433 1434 ahci = ahci_boot_and_enable(NULL); 1435 ahci_test_io_rw_simple(ahci, 4096, 0, 1436 READ_FPDMA_QUEUED, 1437 WRITE_FPDMA_QUEUED); 1438 ahci_shutdown(ahci); 1439 } 1440 1441 static int prepare_iso(size_t size, unsigned char **buf, char **name) 1442 { 1443 g_autofree char *cdrom_path = NULL; 1444 unsigned char *patt; 1445 ssize_t ret; 1446 int fd = g_file_open_tmp("qtest.iso.XXXXXX", &cdrom_path, NULL); 1447 1448 g_assert(fd != -1); 1449 g_assert(buf); 1450 g_assert(name); 1451 patt = g_malloc(size); 1452 1453 /* Generate a pattern and build a CDROM image to read from */ 1454 generate_pattern(patt, size, ATAPI_SECTOR_SIZE); 1455 ret = write(fd, patt, size); 1456 g_assert(ret == size); 1457 1458 *name = g_strdup(cdrom_path); 1459 *buf = patt; 1460 return fd; 1461 } 1462 1463 static void remove_iso(int fd, char *name) 1464 { 1465 unlink(name); 1466 g_free(name); 1467 close(fd); 1468 } 1469 1470 static int ahci_cb_cmp_buff(AHCIQState *ahci, AHCICommand *cmd, 1471 const AHCIOpts *opts) 1472 { 1473 unsigned char *tx = opts->opaque; 1474 unsigned char *rx; 1475 1476 if (!opts->size) { 1477 return 0; 1478 } 1479 1480 rx = g_malloc0(opts->size); 1481 qtest_bufread(ahci->parent->qts, opts->buffer, rx, opts->size); 1482 g_assert_cmphex(memcmp(tx, rx, opts->size), ==, 0); 1483 g_free(rx); 1484 1485 return 0; 1486 } 1487 1488 static void ahci_test_cdrom(int nsectors, bool dma, uint8_t cmd, 1489 bool override_bcl, uint16_t bcl) 1490 { 1491 AHCIQState *ahci; 1492 unsigned char *tx; 1493 char *iso; 1494 int fd; 1495 AHCIOpts opts = { 1496 .size = ((uint64_t)ATAPI_SECTOR_SIZE * nsectors), 1497 .atapi = true, 1498 .atapi_dma = dma, 1499 .post_cb = ahci_cb_cmp_buff, 1500 .set_bcl = override_bcl, 1501 .bcl = bcl, 1502 }; 1503 uint64_t iso_size = (uint64_t)ATAPI_SECTOR_SIZE * (nsectors + 1); 1504 1505 /* Prepare ISO and fill 'tx' buffer */ 1506 fd = prepare_iso(iso_size, &tx, &iso); 1507 opts.opaque = tx; 1508 1509 /* Standard startup wonkery, but use ide-cd and our special iso file */ 1510 ahci = ahci_boot_and_enable("-drive if=none,id=drive0,file=%s,format=raw " 1511 "-M q35 " 1512 "-device ide-cd,drive=drive0 ", iso); 1513 1514 /* Build & Send AHCI command */ 1515 ahci_exec(ahci, ahci_port_select(ahci), cmd, &opts); 1516 1517 /* Cleanup */ 1518 g_free(tx); 1519 ahci_shutdown(ahci); 1520 remove_iso(fd, iso); 1521 } 1522 1523 static void ahci_test_cdrom_read10(int nsectors, bool dma) 1524 { 1525 ahci_test_cdrom(nsectors, dma, CMD_ATAPI_READ_10, false, 0); 1526 } 1527 1528 static void test_cdrom_dma(void) 1529 { 1530 ahci_test_cdrom_read10(1, true); 1531 } 1532 1533 static void test_cdrom_dma_multi(void) 1534 { 1535 ahci_test_cdrom_read10(3, true); 1536 } 1537 1538 static void test_cdrom_pio(void) 1539 { 1540 ahci_test_cdrom_read10(1, false); 1541 } 1542 1543 static void test_cdrom_pio_multi(void) 1544 { 1545 ahci_test_cdrom_read10(3, false); 1546 } 1547 1548 /* Regression test: Test that a READ_CD command with a BCL of 0 but a size of 0 1549 * completes as a NOP instead of erroring out. */ 1550 static void test_atapi_bcl(void) 1551 { 1552 ahci_test_cdrom(0, false, CMD_ATAPI_READ_CD, true, 0); 1553 } 1554 1555 1556 static void atapi_wait_tray(AHCIQState *ahci, bool open) 1557 { 1558 QDict *rsp = qtest_qmp_eventwait_ref(ahci->parent->qts, 1559 "DEVICE_TRAY_MOVED"); 1560 QDict *data = qdict_get_qdict(rsp, "data"); 1561 if (open) { 1562 g_assert(qdict_get_bool(data, "tray-open")); 1563 } else { 1564 g_assert(!qdict_get_bool(data, "tray-open")); 1565 } 1566 qobject_unref(rsp); 1567 } 1568 1569 static void test_atapi_tray(void) 1570 { 1571 AHCIQState *ahci; 1572 unsigned char *tx; 1573 char *iso; 1574 int fd; 1575 uint8_t port, sense, asc; 1576 uint64_t iso_size = ATAPI_SECTOR_SIZE; 1577 QDict *rsp; 1578 1579 fd = prepare_iso(iso_size, &tx, &iso); 1580 ahci = ahci_boot_and_enable("-blockdev node-name=drive0,driver=file,filename=%s " 1581 "-M q35 " 1582 "-device ide-cd,id=cd0,drive=drive0 ", iso); 1583 port = ahci_port_select(ahci); 1584 1585 ahci_atapi_eject(ahci, port); 1586 atapi_wait_tray(ahci, true); 1587 1588 ahci_atapi_load(ahci, port); 1589 atapi_wait_tray(ahci, false); 1590 1591 /* Remove media */ 1592 qtest_qmp_send(ahci->parent->qts, "{'execute': 'blockdev-open-tray', " 1593 "'arguments': {'id': 'cd0'}}"); 1594 atapi_wait_tray(ahci, true); 1595 rsp = qtest_qmp_receive(ahci->parent->qts); 1596 qobject_unref(rsp); 1597 1598 qmp_discard_response(ahci->parent->qts, 1599 "{'execute': 'blockdev-remove-medium', " 1600 "'arguments': {'id': 'cd0'}}"); 1601 1602 /* Test the tray without a medium */ 1603 ahci_atapi_load(ahci, port); 1604 atapi_wait_tray(ahci, false); 1605 1606 ahci_atapi_eject(ahci, port); 1607 atapi_wait_tray(ahci, true); 1608 1609 /* Re-insert media */ 1610 qmp_discard_response(ahci->parent->qts, 1611 "{'execute': 'blockdev-add', " 1612 "'arguments': {'node-name': 'node0', " 1613 "'driver': 'raw', " 1614 "'file': { 'driver': 'file', " 1615 "'filename': %s }}}", iso); 1616 qmp_discard_response(ahci->parent->qts, 1617 "{'execute': 'blockdev-insert-medium'," 1618 "'arguments': { 'id': 'cd0', " 1619 "'node-name': 'node0' }}"); 1620 1621 /* Again, the event shows up first */ 1622 qtest_qmp_send(ahci->parent->qts, "{'execute': 'blockdev-close-tray', " 1623 "'arguments': {'id': 'cd0'}}"); 1624 atapi_wait_tray(ahci, false); 1625 rsp = qtest_qmp_receive(ahci->parent->qts); 1626 qobject_unref(rsp); 1627 1628 /* Now, to convince ATAPI we understand the media has changed... */ 1629 ahci_atapi_test_ready(ahci, port, false, SENSE_NOT_READY); 1630 ahci_atapi_get_sense(ahci, port, &sense, &asc); 1631 g_assert_cmpuint(sense, ==, SENSE_NOT_READY); 1632 g_assert_cmpuint(asc, ==, ASC_MEDIUM_NOT_PRESENT); 1633 1634 ahci_atapi_test_ready(ahci, port, false, SENSE_UNIT_ATTENTION); 1635 ahci_atapi_get_sense(ahci, port, &sense, &asc); 1636 g_assert_cmpuint(sense, ==, SENSE_UNIT_ATTENTION); 1637 g_assert_cmpuint(asc, ==, ASC_MEDIUM_MAY_HAVE_CHANGED); 1638 1639 ahci_atapi_test_ready(ahci, port, true, SENSE_NO_SENSE); 1640 ahci_atapi_get_sense(ahci, port, &sense, &asc); 1641 g_assert_cmpuint(sense, ==, SENSE_NO_SENSE); 1642 1643 /* Final tray test. */ 1644 ahci_atapi_eject(ahci, port); 1645 atapi_wait_tray(ahci, true); 1646 1647 ahci_atapi_load(ahci, port); 1648 atapi_wait_tray(ahci, false); 1649 1650 /* Cleanup */ 1651 g_free(tx); 1652 ahci_shutdown(ahci); 1653 remove_iso(fd, iso); 1654 } 1655 1656 /******************************************************************************/ 1657 /* AHCI I/O Test Matrix Definitions */ 1658 1659 enum BuffLen { 1660 LEN_BEGIN = 0, 1661 LEN_SIMPLE = LEN_BEGIN, 1662 LEN_DOUBLE, 1663 LEN_LONG, 1664 LEN_SHORT, 1665 NUM_LENGTHS 1666 }; 1667 1668 static const char *buff_len_str[NUM_LENGTHS] = { "simple", "double", 1669 "long", "short" }; 1670 1671 enum AddrMode { 1672 ADDR_MODE_BEGIN = 0, 1673 ADDR_MODE_LBA28 = ADDR_MODE_BEGIN, 1674 ADDR_MODE_LBA48, 1675 NUM_ADDR_MODES 1676 }; 1677 1678 static const char *addr_mode_str[NUM_ADDR_MODES] = { "lba28", "lba48" }; 1679 1680 enum IOMode { 1681 MODE_BEGIN = 0, 1682 MODE_PIO = MODE_BEGIN, 1683 MODE_DMA, 1684 NUM_MODES 1685 }; 1686 1687 static const char *io_mode_str[NUM_MODES] = { "pio", "dma" }; 1688 1689 enum IOOps { 1690 IO_BEGIN = 0, 1691 IO_READ = IO_BEGIN, 1692 IO_WRITE, 1693 NUM_IO_OPS 1694 }; 1695 1696 enum OffsetType { 1697 OFFSET_BEGIN = 0, 1698 OFFSET_ZERO = OFFSET_BEGIN, 1699 OFFSET_LOW, 1700 OFFSET_HIGH, 1701 NUM_OFFSETS 1702 }; 1703 1704 static const char *offset_str[NUM_OFFSETS] = { "zero", "low", "high" }; 1705 1706 typedef struct AHCIIOTestOptions { 1707 enum BuffLen length; 1708 enum AddrMode address_type; 1709 enum IOMode io_type; 1710 enum OffsetType offset; 1711 } AHCIIOTestOptions; 1712 1713 static uint64_t offset_sector(enum OffsetType ofst, 1714 enum AddrMode addr_type, 1715 uint64_t buffsize) 1716 { 1717 uint64_t ceil; 1718 uint64_t nsectors; 1719 1720 switch (ofst) { 1721 case OFFSET_ZERO: 1722 return 0; 1723 case OFFSET_LOW: 1724 return 1; 1725 case OFFSET_HIGH: 1726 ceil = (addr_type == ADDR_MODE_LBA28) ? 0xfffffff : 0xffffffffffff; 1727 ceil = MIN(ceil, mb_to_sectors(test_image_size_mb) - 1); 1728 nsectors = buffsize / AHCI_SECTOR_SIZE; 1729 return ceil - nsectors + 1; 1730 default: 1731 g_assert_not_reached(); 1732 } 1733 } 1734 1735 /** 1736 * Table of possible I/O ATA commands given a set of enumerations. 1737 */ 1738 static const uint8_t io_cmds[NUM_MODES][NUM_ADDR_MODES][NUM_IO_OPS] = { 1739 [MODE_PIO] = { 1740 [ADDR_MODE_LBA28] = { 1741 [IO_READ] = CMD_READ_PIO, 1742 [IO_WRITE] = CMD_WRITE_PIO }, 1743 [ADDR_MODE_LBA48] = { 1744 [IO_READ] = CMD_READ_PIO_EXT, 1745 [IO_WRITE] = CMD_WRITE_PIO_EXT } 1746 }, 1747 [MODE_DMA] = { 1748 [ADDR_MODE_LBA28] = { 1749 [IO_READ] = CMD_READ_DMA, 1750 [IO_WRITE] = CMD_WRITE_DMA }, 1751 [ADDR_MODE_LBA48] = { 1752 [IO_READ] = CMD_READ_DMA_EXT, 1753 [IO_WRITE] = CMD_WRITE_DMA_EXT } 1754 } 1755 }; 1756 1757 /** 1758 * Test a Read/Write pattern using various commands, addressing modes, 1759 * transfer modes, and buffer sizes. 1760 */ 1761 static void test_io_rw_interface(enum AddrMode lba48, enum IOMode dma, 1762 unsigned bufsize, uint64_t sector) 1763 { 1764 AHCIQState *ahci; 1765 1766 ahci = ahci_boot_and_enable(NULL); 1767 ahci_test_io_rw_simple(ahci, bufsize, sector, 1768 io_cmds[dma][lba48][IO_READ], 1769 io_cmds[dma][lba48][IO_WRITE]); 1770 ahci_shutdown(ahci); 1771 } 1772 1773 /** 1774 * Demultiplex the test data and invoke the actual test routine. 1775 */ 1776 static void test_io_interface(gconstpointer opaque) 1777 { 1778 AHCIIOTestOptions *opts = (AHCIIOTestOptions *)opaque; 1779 unsigned bufsize; 1780 uint64_t sector; 1781 1782 switch (opts->length) { 1783 case LEN_SIMPLE: 1784 bufsize = 4096; 1785 break; 1786 case LEN_DOUBLE: 1787 bufsize = 8192; 1788 break; 1789 case LEN_LONG: 1790 bufsize = 4096 * 64; 1791 break; 1792 case LEN_SHORT: 1793 bufsize = 512; 1794 break; 1795 default: 1796 g_assert_not_reached(); 1797 } 1798 1799 sector = offset_sector(opts->offset, opts->address_type, bufsize); 1800 test_io_rw_interface(opts->address_type, opts->io_type, bufsize, sector); 1801 g_free(opts); 1802 return; 1803 } 1804 1805 static void create_ahci_io_test(enum IOMode type, enum AddrMode addr, 1806 enum BuffLen len, enum OffsetType offset) 1807 { 1808 char *name; 1809 AHCIIOTestOptions *opts; 1810 1811 opts = g_new(AHCIIOTestOptions, 1); 1812 opts->length = len; 1813 opts->address_type = addr; 1814 opts->io_type = type; 1815 opts->offset = offset; 1816 1817 name = g_strdup_printf("ahci/io/%s/%s/%s/%s", 1818 io_mode_str[type], 1819 addr_mode_str[addr], 1820 buff_len_str[len], 1821 offset_str[offset]); 1822 1823 if ((addr == ADDR_MODE_LBA48) && (offset == OFFSET_HIGH) && 1824 (mb_to_sectors(test_image_size_mb) <= 0xFFFFFFF)) { 1825 g_test_message("%s: skipped; test image too small", name); 1826 g_free(opts); 1827 g_free(name); 1828 return; 1829 } 1830 1831 qtest_add_data_func(name, opts, test_io_interface); 1832 g_free(name); 1833 } 1834 1835 /******************************************************************************/ 1836 1837 int main(int argc, char **argv) 1838 { 1839 const char *arch, *base; 1840 int ret; 1841 int fd; 1842 int c; 1843 int i, j, k, m; 1844 1845 static struct option long_options[] = { 1846 {"pedantic", no_argument, 0, 'p' }, 1847 {0, 0, 0, 0}, 1848 }; 1849 1850 /* Should be first to utilize g_test functionality, So we can see errors. */ 1851 g_test_init(&argc, &argv, NULL); 1852 1853 while (1) { 1854 c = getopt_long(argc, argv, "", long_options, NULL); 1855 if (c == -1) { 1856 break; 1857 } 1858 switch (c) { 1859 case -1: 1860 break; 1861 case 'p': 1862 ahci_pedantic = 1; 1863 break; 1864 default: 1865 fprintf(stderr, "Unrecognized ahci_test option.\n"); 1866 g_assert_not_reached(); 1867 } 1868 } 1869 1870 /* Check architecture */ 1871 arch = qtest_get_arch(); 1872 if (strcmp(arch, "i386") && strcmp(arch, "x86_64")) { 1873 g_test_message("Skipping test for non-x86"); 1874 return 0; 1875 } 1876 1877 /* 1878 * "base" stores the starting point where we create temporary files. 1879 * 1880 * On Windows, this is set to the relative path of current working 1881 * directory, because the absolute path causes the blkdebug filename 1882 * parser fail to parse "blkdebug:path/to/config:path/to/image". 1883 */ 1884 #ifndef _WIN32 1885 base = g_get_tmp_dir(); 1886 #else 1887 base = "."; 1888 #endif 1889 1890 /* Create a temporary image */ 1891 tmp_path = g_strdup_printf("%s/qtest.XXXXXX", base); 1892 fd = g_mkstemp(tmp_path); 1893 g_assert(fd >= 0); 1894 if (have_qemu_img()) { 1895 imgfmt = "qcow2"; 1896 test_image_size_mb = TEST_IMAGE_SIZE_MB_LARGE; 1897 mkqcow2(tmp_path, TEST_IMAGE_SIZE_MB_LARGE); 1898 } else { 1899 g_test_message("QTEST_QEMU_IMG not set or qemu-img missing; " 1900 "skipping LBA48 high-sector tests"); 1901 imgfmt = "raw"; 1902 test_image_size_mb = TEST_IMAGE_SIZE_MB_SMALL; 1903 ret = ftruncate(fd, test_image_size_mb * 1024 * 1024); 1904 g_assert(ret == 0); 1905 } 1906 close(fd); 1907 1908 /* Create temporary blkdebug instructions */ 1909 debug_path = g_strdup_printf("%s/qtest-blkdebug.XXXXXX", base); 1910 fd = g_mkstemp(debug_path); 1911 g_assert(fd >= 0); 1912 close(fd); 1913 1914 /* Reserve a hollow file to use as a socket for migration tests */ 1915 fd = g_file_open_tmp("qtest-migration.XXXXXX", &mig_socket, NULL); 1916 g_assert(fd >= 0); 1917 close(fd); 1918 1919 /* Run the tests */ 1920 qtest_add_func("/ahci/sanity", test_sanity); 1921 qtest_add_func("/ahci/pci_spec", test_pci_spec); 1922 qtest_add_func("/ahci/pci_enable", test_pci_enable); 1923 qtest_add_func("/ahci/hba_spec", test_hba_spec); 1924 qtest_add_func("/ahci/hba_enable", test_hba_enable); 1925 qtest_add_func("/ahci/identify", test_identify); 1926 1927 for (i = MODE_BEGIN; i < NUM_MODES; i++) { 1928 for (j = ADDR_MODE_BEGIN; j < NUM_ADDR_MODES; j++) { 1929 for (k = LEN_BEGIN; k < NUM_LENGTHS; k++) { 1930 for (m = OFFSET_BEGIN; m < NUM_OFFSETS; m++) { 1931 create_ahci_io_test(i, j, k, m); 1932 } 1933 } 1934 } 1935 } 1936 1937 qtest_add_func("/ahci/io/dma/lba28/fragmented", test_dma_fragmented); 1938 1939 qtest_add_func("/ahci/flush/simple", test_flush); 1940 qtest_add_func("/ahci/flush/retry", test_flush_retry); 1941 qtest_add_func("/ahci/flush/migrate", test_flush_migrate); 1942 1943 qtest_add_func("/ahci/migrate/sanity", test_migrate_sanity); 1944 qtest_add_func("/ahci/migrate/dma/simple", test_migrate_dma); 1945 qtest_add_func("/ahci/io/dma/lba28/retry", test_halted_dma); 1946 qtest_add_func("/ahci/migrate/dma/halted", test_migrate_halted_dma); 1947 1948 qtest_add_func("/ahci/max", test_max); 1949 qtest_add_func("/ahci/reset", test_reset); 1950 1951 qtest_add_func("/ahci/io/ncq/simple", test_ncq_simple); 1952 qtest_add_func("/ahci/migrate/ncq/simple", test_migrate_ncq); 1953 qtest_add_func("/ahci/io/ncq/retry", test_halted_ncq); 1954 qtest_add_func("/ahci/migrate/ncq/halted", test_migrate_halted_ncq); 1955 1956 qtest_add_func("/ahci/cdrom/dma/single", test_cdrom_dma); 1957 qtest_add_func("/ahci/cdrom/dma/multi", test_cdrom_dma_multi); 1958 qtest_add_func("/ahci/cdrom/pio/single", test_cdrom_pio); 1959 qtest_add_func("/ahci/cdrom/pio/multi", test_cdrom_pio_multi); 1960 1961 qtest_add_func("/ahci/cdrom/pio/bcl", test_atapi_bcl); 1962 qtest_add_func("/ahci/cdrom/eject", test_atapi_tray); 1963 1964 ret = g_test_run(); 1965 1966 /* Cleanup */ 1967 unlink(tmp_path); 1968 g_free(tmp_path); 1969 unlink(debug_path); 1970 g_free(debug_path); 1971 unlink(mig_socket); 1972 g_free(mig_socket); 1973 1974 return ret; 1975 } 1976