1*6a564c8aSThomas Huth#!/usr/bin/env python3 2*6a564c8aSThomas Huth# 3*6a564c8aSThomas Huth# OpenSBI boot test for RISC-V machines 4*6a564c8aSThomas Huth# 5*6a564c8aSThomas Huth# Copyright (c) 2022, Ventana Micro 6*6a564c8aSThomas Huth# 7*6a564c8aSThomas Huth# This work is licensed under the terms of the GNU GPL, version 2 or 8*6a564c8aSThomas Huth# later. See the COPYING file in the top-level directory. 9*6a564c8aSThomas Huth 10*6a564c8aSThomas Huthfrom qemu_test import QemuSystemTest 11*6a564c8aSThomas Huthfrom qemu_test import wait_for_console_pattern 12*6a564c8aSThomas Huth 13*6a564c8aSThomas Huthclass RiscvOpenSBI(QemuSystemTest): 14*6a564c8aSThomas Huth 15*6a564c8aSThomas Huth timeout = 5 16*6a564c8aSThomas Huth 17*6a564c8aSThomas Huth def boot_opensbi(self): 18*6a564c8aSThomas Huth self.vm.set_console() 19*6a564c8aSThomas Huth self.vm.launch() 20*6a564c8aSThomas Huth wait_for_console_pattern(self, 'Platform Name') 21*6a564c8aSThomas Huth wait_for_console_pattern(self, 'Boot HART MEDELEG') 22*6a564c8aSThomas Huth 23*6a564c8aSThomas Huth def test_riscv_spike(self): 24*6a564c8aSThomas Huth self.set_machine('spike') 25*6a564c8aSThomas Huth self.boot_opensbi() 26*6a564c8aSThomas Huth 27*6a564c8aSThomas Huth def test_riscv_sifive_u(self): 28*6a564c8aSThomas Huth self.set_machine('sifive_u') 29*6a564c8aSThomas Huth self.boot_opensbi() 30*6a564c8aSThomas Huth 31*6a564c8aSThomas Huth def test_riscv_virt(self): 32*6a564c8aSThomas Huth self.set_machine('virt') 33*6a564c8aSThomas Huth self.boot_opensbi() 34*6a564c8aSThomas Huth 35*6a564c8aSThomas Huthif __name__ == '__main__': 36*6a564c8aSThomas Huth QemuSystemTest.main() 37