1 /* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2009, 2011 Stefan Weil 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 /* 26 * This code implements a TCG which does not generate machine code for some 27 * real target machine but which generates virtual machine code for an 28 * interpreter. Interpreted pseudo code is slow, but it works on any host. 29 * 30 * Some remarks might help in understanding the code: 31 * 32 * "target" or "TCG target" is the machine which runs the generated code. 33 * This is different to the usual meaning in QEMU where "target" is the 34 * emulated machine. So normally QEMU host is identical to TCG target. 35 * Here the TCG target is a virtual machine, but this virtual machine must 36 * use the same word size like the real machine. 37 * Therefore, we need both 32 and 64 bit virtual machines (interpreter). 38 */ 39 40 #ifndef TCG_TARGET_H 41 #define TCG_TARGET_H 42 43 #define TCG_TARGET_INTERPRETER 1 44 #define TCG_TARGET_INSN_UNIT_SIZE 1 45 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 32 46 47 #if UINTPTR_MAX == UINT32_MAX 48 # define TCG_TARGET_REG_BITS 32 49 #elif UINTPTR_MAX == UINT64_MAX 50 # define TCG_TARGET_REG_BITS 64 51 #else 52 # error Unknown pointer size for tci target 53 #endif 54 55 #ifdef CONFIG_DEBUG_TCG 56 /* Enable debug output. */ 57 #define CONFIG_DEBUG_TCG_INTERPRETER 58 #endif 59 60 /* Optional instructions. */ 61 62 #define TCG_TARGET_HAS_bswap16_i32 1 63 #define TCG_TARGET_HAS_bswap32_i32 1 64 #define TCG_TARGET_HAS_div_i32 1 65 #define TCG_TARGET_HAS_rem_i32 1 66 #define TCG_TARGET_HAS_ext8s_i32 1 67 #define TCG_TARGET_HAS_ext16s_i32 1 68 #define TCG_TARGET_HAS_ext8u_i32 1 69 #define TCG_TARGET_HAS_ext16u_i32 1 70 #define TCG_TARGET_HAS_andc_i32 0 71 #define TCG_TARGET_HAS_deposit_i32 1 72 #define TCG_TARGET_HAS_extract_i32 0 73 #define TCG_TARGET_HAS_sextract_i32 0 74 #define TCG_TARGET_HAS_eqv_i32 0 75 #define TCG_TARGET_HAS_nand_i32 0 76 #define TCG_TARGET_HAS_nor_i32 0 77 #define TCG_TARGET_HAS_clz_i32 0 78 #define TCG_TARGET_HAS_ctz_i32 0 79 #define TCG_TARGET_HAS_ctpop_i32 0 80 #define TCG_TARGET_HAS_neg_i32 1 81 #define TCG_TARGET_HAS_not_i32 1 82 #define TCG_TARGET_HAS_orc_i32 0 83 #define TCG_TARGET_HAS_rot_i32 1 84 #define TCG_TARGET_HAS_movcond_i32 0 85 #define TCG_TARGET_HAS_muls2_i32 0 86 #define TCG_TARGET_HAS_muluh_i32 0 87 #define TCG_TARGET_HAS_mulsh_i32 0 88 #define TCG_TARGET_HAS_goto_ptr 0 89 #define TCG_TARGET_HAS_direct_jump 1 90 91 #if TCG_TARGET_REG_BITS == 64 92 #define TCG_TARGET_HAS_extrl_i64_i32 0 93 #define TCG_TARGET_HAS_extrh_i64_i32 0 94 #define TCG_TARGET_HAS_bswap16_i64 1 95 #define TCG_TARGET_HAS_bswap32_i64 1 96 #define TCG_TARGET_HAS_bswap64_i64 1 97 #define TCG_TARGET_HAS_deposit_i64 1 98 #define TCG_TARGET_HAS_extract_i64 0 99 #define TCG_TARGET_HAS_sextract_i64 0 100 #define TCG_TARGET_HAS_div_i64 0 101 #define TCG_TARGET_HAS_rem_i64 0 102 #define TCG_TARGET_HAS_ext8s_i64 1 103 #define TCG_TARGET_HAS_ext16s_i64 1 104 #define TCG_TARGET_HAS_ext32s_i64 1 105 #define TCG_TARGET_HAS_ext8u_i64 1 106 #define TCG_TARGET_HAS_ext16u_i64 1 107 #define TCG_TARGET_HAS_ext32u_i64 1 108 #define TCG_TARGET_HAS_andc_i64 0 109 #define TCG_TARGET_HAS_eqv_i64 0 110 #define TCG_TARGET_HAS_nand_i64 0 111 #define TCG_TARGET_HAS_nor_i64 0 112 #define TCG_TARGET_HAS_clz_i64 0 113 #define TCG_TARGET_HAS_ctz_i64 0 114 #define TCG_TARGET_HAS_ctpop_i64 0 115 #define TCG_TARGET_HAS_neg_i64 1 116 #define TCG_TARGET_HAS_not_i64 1 117 #define TCG_TARGET_HAS_orc_i64 0 118 #define TCG_TARGET_HAS_rot_i64 1 119 #define TCG_TARGET_HAS_movcond_i64 0 120 #define TCG_TARGET_HAS_muls2_i64 0 121 #define TCG_TARGET_HAS_add2_i32 0 122 #define TCG_TARGET_HAS_sub2_i32 0 123 #define TCG_TARGET_HAS_mulu2_i32 0 124 #define TCG_TARGET_HAS_add2_i64 0 125 #define TCG_TARGET_HAS_sub2_i64 0 126 #define TCG_TARGET_HAS_mulu2_i64 0 127 #define TCG_TARGET_HAS_muluh_i64 0 128 #define TCG_TARGET_HAS_mulsh_i64 0 129 #else 130 #define TCG_TARGET_HAS_mulu2_i32 1 131 #endif /* TCG_TARGET_REG_BITS == 64 */ 132 133 /* Number of registers available. 134 For 32 bit hosts, we need more than 8 registers (call arguments). */ 135 /* #define TCG_TARGET_NB_REGS 8 */ 136 #define TCG_TARGET_NB_REGS 16 137 /* #define TCG_TARGET_NB_REGS 32 */ 138 139 /* List of registers which are used by TCG. */ 140 typedef enum { 141 TCG_REG_R0 = 0, 142 TCG_REG_R1, 143 TCG_REG_R2, 144 TCG_REG_R3, 145 TCG_REG_R4, 146 TCG_REG_R5, 147 TCG_REG_R6, 148 TCG_REG_R7, 149 #if TCG_TARGET_NB_REGS >= 16 150 TCG_REG_R8, 151 TCG_REG_R9, 152 TCG_REG_R10, 153 TCG_REG_R11, 154 TCG_REG_R12, 155 TCG_REG_R13, 156 TCG_REG_R14, 157 TCG_REG_R15, 158 #if TCG_TARGET_NB_REGS >= 32 159 TCG_REG_R16, 160 TCG_REG_R17, 161 TCG_REG_R18, 162 TCG_REG_R19, 163 TCG_REG_R20, 164 TCG_REG_R21, 165 TCG_REG_R22, 166 TCG_REG_R23, 167 TCG_REG_R24, 168 TCG_REG_R25, 169 TCG_REG_R26, 170 TCG_REG_R27, 171 TCG_REG_R28, 172 TCG_REG_R29, 173 TCG_REG_R30, 174 TCG_REG_R31, 175 #endif 176 #endif 177 /* Special value UINT8_MAX is used by TCI to encode constant values. */ 178 TCG_CONST = UINT8_MAX 179 } TCGReg; 180 181 #define TCG_AREG0 (TCG_TARGET_NB_REGS - 2) 182 183 /* Used for function call generation. */ 184 #define TCG_REG_CALL_STACK (TCG_TARGET_NB_REGS - 1) 185 #define TCG_TARGET_CALL_STACK_OFFSET 0 186 #define TCG_TARGET_STACK_ALIGN 16 187 188 void tci_disas(uint8_t opc); 189 190 #define HAVE_TCG_QEMU_TB_EXEC 191 192 static inline void flush_icache_range(uintptr_t start, uintptr_t stop) 193 { 194 } 195 196 /* We could notice __i386__ or __s390x__ and reduce the barriers depending 197 on the host. But if you want performance, you use the normal backend. 198 We prefer consistency across hosts on this. */ 199 #define TCG_TARGET_DEFAULT_MO (0) 200 201 static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, 202 uintptr_t jmp_addr, uintptr_t addr) 203 { 204 /* patch the branch destination */ 205 atomic_set((int32_t *)jmp_addr, addr - (jmp_addr + 4)); 206 /* no need to flush icache explicitly */ 207 } 208 209 #endif /* TCG_TARGET_H */ 210