1 /* 2 * Tiny Code Interpreter for QEMU 3 * 4 * Copyright (c) 2009, 2011, 2016 Stefan Weil 5 * 6 * This program is free software: you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation, either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "tcg/tcg.h" 22 #include "tcg/helper-info.h" 23 #include "tcg/tcg-ldst.h" 24 #include "disas/dis-asm.h" 25 #include "tcg-has.h" 26 #include <ffi.h> 27 28 29 /* 30 * Enable TCI assertions only when debugging TCG (and without NDEBUG defined). 31 * Without assertions, the interpreter runs much faster. 32 */ 33 #if defined(CONFIG_DEBUG_TCG) 34 # define tci_assert(cond) assert(cond) 35 #else 36 # define tci_assert(cond) ((void)(cond)) 37 #endif 38 39 __thread uintptr_t tci_tb_ptr; 40 41 static void tci_write_reg64(tcg_target_ulong *regs, uint32_t high_index, 42 uint32_t low_index, uint64_t value) 43 { 44 regs[low_index] = (uint32_t)value; 45 regs[high_index] = value >> 32; 46 } 47 48 /* Create a 64 bit value from two 32 bit values. */ 49 static uint64_t tci_uint64(uint32_t high, uint32_t low) 50 { 51 return ((uint64_t)high << 32) + low; 52 } 53 54 /* 55 * Load sets of arguments all at once. The naming convention is: 56 * tci_args_<arguments> 57 * where arguments is a sequence of 58 * 59 * b = immediate (bit position) 60 * c = condition (TCGCond) 61 * i = immediate (uint32_t) 62 * I = immediate (tcg_target_ulong) 63 * l = label or pointer 64 * m = immediate (MemOpIdx) 65 * n = immediate (call return length) 66 * r = register 67 * s = signed ldst offset 68 */ 69 70 static void tci_args_l(uint32_t insn, const void *tb_ptr, void **l0) 71 { 72 int diff = sextract32(insn, 12, 20); 73 *l0 = diff ? (void *)tb_ptr + diff : NULL; 74 } 75 76 static void tci_args_r(uint32_t insn, TCGReg *r0) 77 { 78 *r0 = extract32(insn, 8, 4); 79 } 80 81 static void tci_args_nl(uint32_t insn, const void *tb_ptr, 82 uint8_t *n0, void **l1) 83 { 84 *n0 = extract32(insn, 8, 4); 85 *l1 = sextract32(insn, 12, 20) + (void *)tb_ptr; 86 } 87 88 static void tci_args_rl(uint32_t insn, const void *tb_ptr, 89 TCGReg *r0, void **l1) 90 { 91 *r0 = extract32(insn, 8, 4); 92 *l1 = sextract32(insn, 12, 20) + (void *)tb_ptr; 93 } 94 95 static void tci_args_rr(uint32_t insn, TCGReg *r0, TCGReg *r1) 96 { 97 *r0 = extract32(insn, 8, 4); 98 *r1 = extract32(insn, 12, 4); 99 } 100 101 static void tci_args_ri(uint32_t insn, TCGReg *r0, tcg_target_ulong *i1) 102 { 103 *r0 = extract32(insn, 8, 4); 104 *i1 = sextract32(insn, 12, 20); 105 } 106 107 static void tci_args_rrm(uint32_t insn, TCGReg *r0, 108 TCGReg *r1, MemOpIdx *m2) 109 { 110 *r0 = extract32(insn, 8, 4); 111 *r1 = extract32(insn, 12, 4); 112 *m2 = extract32(insn, 16, 16); 113 } 114 115 static void tci_args_rrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2) 116 { 117 *r0 = extract32(insn, 8, 4); 118 *r1 = extract32(insn, 12, 4); 119 *r2 = extract32(insn, 16, 4); 120 } 121 122 static void tci_args_rrs(uint32_t insn, TCGReg *r0, TCGReg *r1, int32_t *i2) 123 { 124 *r0 = extract32(insn, 8, 4); 125 *r1 = extract32(insn, 12, 4); 126 *i2 = sextract32(insn, 16, 16); 127 } 128 129 static void tci_args_rrbb(uint32_t insn, TCGReg *r0, TCGReg *r1, 130 uint8_t *i2, uint8_t *i3) 131 { 132 *r0 = extract32(insn, 8, 4); 133 *r1 = extract32(insn, 12, 4); 134 *i2 = extract32(insn, 16, 6); 135 *i3 = extract32(insn, 22, 6); 136 } 137 138 static void tci_args_rrrc(uint32_t insn, 139 TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3) 140 { 141 *r0 = extract32(insn, 8, 4); 142 *r1 = extract32(insn, 12, 4); 143 *r2 = extract32(insn, 16, 4); 144 *c3 = extract32(insn, 20, 4); 145 } 146 147 static void tci_args_rrrbb(uint32_t insn, TCGReg *r0, TCGReg *r1, 148 TCGReg *r2, uint8_t *i3, uint8_t *i4) 149 { 150 *r0 = extract32(insn, 8, 4); 151 *r1 = extract32(insn, 12, 4); 152 *r2 = extract32(insn, 16, 4); 153 *i3 = extract32(insn, 20, 6); 154 *i4 = extract32(insn, 26, 6); 155 } 156 157 static void tci_args_rrrr(uint32_t insn, 158 TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3) 159 { 160 *r0 = extract32(insn, 8, 4); 161 *r1 = extract32(insn, 12, 4); 162 *r2 = extract32(insn, 16, 4); 163 *r3 = extract32(insn, 20, 4); 164 } 165 166 static void tci_args_rrrrrc(uint32_t insn, TCGReg *r0, TCGReg *r1, 167 TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c5) 168 { 169 *r0 = extract32(insn, 8, 4); 170 *r1 = extract32(insn, 12, 4); 171 *r2 = extract32(insn, 16, 4); 172 *r3 = extract32(insn, 20, 4); 173 *r4 = extract32(insn, 24, 4); 174 *c5 = extract32(insn, 28, 4); 175 } 176 177 static void tci_args_rrrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1, 178 TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGReg *r5) 179 { 180 *r0 = extract32(insn, 8, 4); 181 *r1 = extract32(insn, 12, 4); 182 *r2 = extract32(insn, 16, 4); 183 *r3 = extract32(insn, 20, 4); 184 *r4 = extract32(insn, 24, 4); 185 *r5 = extract32(insn, 28, 4); 186 } 187 188 static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition) 189 { 190 bool result = false; 191 int32_t i0 = u0; 192 int32_t i1 = u1; 193 switch (condition) { 194 case TCG_COND_EQ: 195 result = (u0 == u1); 196 break; 197 case TCG_COND_NE: 198 result = (u0 != u1); 199 break; 200 case TCG_COND_LT: 201 result = (i0 < i1); 202 break; 203 case TCG_COND_GE: 204 result = (i0 >= i1); 205 break; 206 case TCG_COND_LE: 207 result = (i0 <= i1); 208 break; 209 case TCG_COND_GT: 210 result = (i0 > i1); 211 break; 212 case TCG_COND_LTU: 213 result = (u0 < u1); 214 break; 215 case TCG_COND_GEU: 216 result = (u0 >= u1); 217 break; 218 case TCG_COND_LEU: 219 result = (u0 <= u1); 220 break; 221 case TCG_COND_GTU: 222 result = (u0 > u1); 223 break; 224 case TCG_COND_TSTEQ: 225 result = (u0 & u1) == 0; 226 break; 227 case TCG_COND_TSTNE: 228 result = (u0 & u1) != 0; 229 break; 230 default: 231 g_assert_not_reached(); 232 } 233 return result; 234 } 235 236 static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition) 237 { 238 bool result = false; 239 int64_t i0 = u0; 240 int64_t i1 = u1; 241 switch (condition) { 242 case TCG_COND_EQ: 243 result = (u0 == u1); 244 break; 245 case TCG_COND_NE: 246 result = (u0 != u1); 247 break; 248 case TCG_COND_LT: 249 result = (i0 < i1); 250 break; 251 case TCG_COND_GE: 252 result = (i0 >= i1); 253 break; 254 case TCG_COND_LE: 255 result = (i0 <= i1); 256 break; 257 case TCG_COND_GT: 258 result = (i0 > i1); 259 break; 260 case TCG_COND_LTU: 261 result = (u0 < u1); 262 break; 263 case TCG_COND_GEU: 264 result = (u0 >= u1); 265 break; 266 case TCG_COND_LEU: 267 result = (u0 <= u1); 268 break; 269 case TCG_COND_GTU: 270 result = (u0 > u1); 271 break; 272 case TCG_COND_TSTEQ: 273 result = (u0 & u1) == 0; 274 break; 275 case TCG_COND_TSTNE: 276 result = (u0 & u1) != 0; 277 break; 278 default: 279 g_assert_not_reached(); 280 } 281 return result; 282 } 283 284 static uint64_t tci_qemu_ld(CPUArchState *env, uint64_t taddr, 285 MemOpIdx oi, const void *tb_ptr) 286 { 287 MemOp mop = get_memop(oi); 288 uintptr_t ra = (uintptr_t)tb_ptr; 289 290 switch (mop & MO_SSIZE) { 291 case MO_UB: 292 return helper_ldub_mmu(env, taddr, oi, ra); 293 case MO_SB: 294 return helper_ldsb_mmu(env, taddr, oi, ra); 295 case MO_UW: 296 return helper_lduw_mmu(env, taddr, oi, ra); 297 case MO_SW: 298 return helper_ldsw_mmu(env, taddr, oi, ra); 299 case MO_UL: 300 return helper_ldul_mmu(env, taddr, oi, ra); 301 case MO_SL: 302 return helper_ldsl_mmu(env, taddr, oi, ra); 303 case MO_UQ: 304 return helper_ldq_mmu(env, taddr, oi, ra); 305 default: 306 g_assert_not_reached(); 307 } 308 } 309 310 static void tci_qemu_st(CPUArchState *env, uint64_t taddr, uint64_t val, 311 MemOpIdx oi, const void *tb_ptr) 312 { 313 MemOp mop = get_memop(oi); 314 uintptr_t ra = (uintptr_t)tb_ptr; 315 316 switch (mop & MO_SIZE) { 317 case MO_UB: 318 helper_stb_mmu(env, taddr, val, oi, ra); 319 break; 320 case MO_UW: 321 helper_stw_mmu(env, taddr, val, oi, ra); 322 break; 323 case MO_UL: 324 helper_stl_mmu(env, taddr, val, oi, ra); 325 break; 326 case MO_UQ: 327 helper_stq_mmu(env, taddr, val, oi, ra); 328 break; 329 default: 330 g_assert_not_reached(); 331 } 332 } 333 334 #if TCG_TARGET_REG_BITS == 64 335 # define CASE_32_64(x) \ 336 case glue(glue(INDEX_op_, x), _i64): \ 337 case glue(glue(INDEX_op_, x), _i32): 338 # define CASE_64(x) \ 339 case glue(glue(INDEX_op_, x), _i64): 340 #else 341 # define CASE_32_64(x) \ 342 case glue(glue(INDEX_op_, x), _i32): 343 # define CASE_64(x) 344 #endif 345 346 /* Interpret pseudo code in tb. */ 347 /* 348 * Disable CFI checks. 349 * One possible operation in the pseudo code is a call to binary code. 350 * Therefore, disable CFI checks in the interpreter function 351 */ 352 uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, 353 const void *v_tb_ptr) 354 { 355 const uint32_t *tb_ptr = v_tb_ptr; 356 tcg_target_ulong regs[TCG_TARGET_NB_REGS]; 357 uint64_t stack[(TCG_STATIC_CALL_ARGS_SIZE + TCG_STATIC_FRAME_SIZE) 358 / sizeof(uint64_t)]; 359 360 regs[TCG_AREG0] = (tcg_target_ulong)env; 361 regs[TCG_REG_CALL_STACK] = (uintptr_t)stack; 362 tci_assert(tb_ptr); 363 364 for (;;) { 365 uint32_t insn; 366 TCGOpcode opc; 367 TCGReg r0, r1, r2, r3, r4, r5; 368 tcg_target_ulong t1; 369 TCGCond condition; 370 uint8_t pos, len; 371 uint32_t tmp32; 372 uint64_t tmp64, taddr; 373 uint64_t T1, T2; 374 MemOpIdx oi; 375 int32_t ofs; 376 void *ptr; 377 378 insn = *tb_ptr++; 379 opc = extract32(insn, 0, 8); 380 381 switch (opc) { 382 case INDEX_op_call: 383 { 384 void *call_slots[MAX_CALL_IARGS]; 385 ffi_cif *cif; 386 void *func; 387 unsigned i, s, n; 388 389 tci_args_nl(insn, tb_ptr, &len, &ptr); 390 func = ((void **)ptr)[0]; 391 cif = ((void **)ptr)[1]; 392 393 n = cif->nargs; 394 for (i = s = 0; i < n; ++i) { 395 ffi_type *t = cif->arg_types[i]; 396 call_slots[i] = &stack[s]; 397 s += DIV_ROUND_UP(t->size, 8); 398 } 399 400 /* Helper functions may need to access the "return address" */ 401 tci_tb_ptr = (uintptr_t)tb_ptr; 402 ffi_call(cif, func, stack, call_slots); 403 } 404 405 switch (len) { 406 case 0: /* void */ 407 break; 408 case 1: /* uint32_t */ 409 /* 410 * The result winds up "left-aligned" in the stack[0] slot. 411 * Note that libffi has an odd special case in that it will 412 * always widen an integral result to ffi_arg. 413 */ 414 if (sizeof(ffi_arg) == 8) { 415 regs[TCG_REG_R0] = (uint32_t)stack[0]; 416 } else { 417 regs[TCG_REG_R0] = *(uint32_t *)stack; 418 } 419 break; 420 case 2: /* uint64_t */ 421 /* 422 * For TCG_TARGET_REG_BITS == 32, the register pair 423 * must stay in host memory order. 424 */ 425 memcpy(®s[TCG_REG_R0], stack, 8); 426 break; 427 case 3: /* Int128 */ 428 memcpy(®s[TCG_REG_R0], stack, 16); 429 break; 430 default: 431 g_assert_not_reached(); 432 } 433 break; 434 435 case INDEX_op_br: 436 tci_args_l(insn, tb_ptr, &ptr); 437 tb_ptr = ptr; 438 continue; 439 case INDEX_op_setcond_i32: 440 tci_args_rrrc(insn, &r0, &r1, &r2, &condition); 441 regs[r0] = tci_compare32(regs[r1], regs[r2], condition); 442 break; 443 case INDEX_op_movcond_i32: 444 tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition); 445 tmp32 = tci_compare32(regs[r1], regs[r2], condition); 446 regs[r0] = regs[tmp32 ? r3 : r4]; 447 break; 448 #if TCG_TARGET_REG_BITS == 32 449 case INDEX_op_setcond2_i32: 450 tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition); 451 T1 = tci_uint64(regs[r2], regs[r1]); 452 T2 = tci_uint64(regs[r4], regs[r3]); 453 regs[r0] = tci_compare64(T1, T2, condition); 454 break; 455 #elif TCG_TARGET_REG_BITS == 64 456 case INDEX_op_setcond_i64: 457 tci_args_rrrc(insn, &r0, &r1, &r2, &condition); 458 regs[r0] = tci_compare64(regs[r1], regs[r2], condition); 459 break; 460 case INDEX_op_movcond_i64: 461 tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition); 462 tmp32 = tci_compare64(regs[r1], regs[r2], condition); 463 regs[r0] = regs[tmp32 ? r3 : r4]; 464 break; 465 #endif 466 case INDEX_op_mov: 467 tci_args_rr(insn, &r0, &r1); 468 regs[r0] = regs[r1]; 469 break; 470 case INDEX_op_tci_movi: 471 tci_args_ri(insn, &r0, &t1); 472 regs[r0] = t1; 473 break; 474 case INDEX_op_tci_movl: 475 tci_args_rl(insn, tb_ptr, &r0, &ptr); 476 regs[r0] = *(tcg_target_ulong *)ptr; 477 break; 478 479 /* Load/store operations (32 bit). */ 480 481 CASE_32_64(ld8u) 482 tci_args_rrs(insn, &r0, &r1, &ofs); 483 ptr = (void *)(regs[r1] + ofs); 484 regs[r0] = *(uint8_t *)ptr; 485 break; 486 CASE_32_64(ld8s) 487 tci_args_rrs(insn, &r0, &r1, &ofs); 488 ptr = (void *)(regs[r1] + ofs); 489 regs[r0] = *(int8_t *)ptr; 490 break; 491 CASE_32_64(ld16u) 492 tci_args_rrs(insn, &r0, &r1, &ofs); 493 ptr = (void *)(regs[r1] + ofs); 494 regs[r0] = *(uint16_t *)ptr; 495 break; 496 CASE_32_64(ld16s) 497 tci_args_rrs(insn, &r0, &r1, &ofs); 498 ptr = (void *)(regs[r1] + ofs); 499 regs[r0] = *(int16_t *)ptr; 500 break; 501 case INDEX_op_ld_i32: 502 CASE_64(ld32u) 503 tci_args_rrs(insn, &r0, &r1, &ofs); 504 ptr = (void *)(regs[r1] + ofs); 505 regs[r0] = *(uint32_t *)ptr; 506 break; 507 CASE_32_64(st8) 508 tci_args_rrs(insn, &r0, &r1, &ofs); 509 ptr = (void *)(regs[r1] + ofs); 510 *(uint8_t *)ptr = regs[r0]; 511 break; 512 CASE_32_64(st16) 513 tci_args_rrs(insn, &r0, &r1, &ofs); 514 ptr = (void *)(regs[r1] + ofs); 515 *(uint16_t *)ptr = regs[r0]; 516 break; 517 case INDEX_op_st_i32: 518 CASE_64(st32) 519 tci_args_rrs(insn, &r0, &r1, &ofs); 520 ptr = (void *)(regs[r1] + ofs); 521 *(uint32_t *)ptr = regs[r0]; 522 break; 523 524 /* Arithmetic operations (mixed 32/64 bit). */ 525 526 case INDEX_op_add: 527 tci_args_rrr(insn, &r0, &r1, &r2); 528 regs[r0] = regs[r1] + regs[r2]; 529 break; 530 case INDEX_op_sub: 531 tci_args_rrr(insn, &r0, &r1, &r2); 532 regs[r0] = regs[r1] - regs[r2]; 533 break; 534 CASE_32_64(mul) 535 tci_args_rrr(insn, &r0, &r1, &r2); 536 regs[r0] = regs[r1] * regs[r2]; 537 break; 538 case INDEX_op_and: 539 tci_args_rrr(insn, &r0, &r1, &r2); 540 regs[r0] = regs[r1] & regs[r2]; 541 break; 542 case INDEX_op_or: 543 tci_args_rrr(insn, &r0, &r1, &r2); 544 regs[r0] = regs[r1] | regs[r2]; 545 break; 546 case INDEX_op_xor: 547 tci_args_rrr(insn, &r0, &r1, &r2); 548 regs[r0] = regs[r1] ^ regs[r2]; 549 break; 550 case INDEX_op_andc: 551 tci_args_rrr(insn, &r0, &r1, &r2); 552 regs[r0] = regs[r1] & ~regs[r2]; 553 break; 554 case INDEX_op_orc: 555 tci_args_rrr(insn, &r0, &r1, &r2); 556 regs[r0] = regs[r1] | ~regs[r2]; 557 break; 558 case INDEX_op_eqv: 559 tci_args_rrr(insn, &r0, &r1, &r2); 560 regs[r0] = ~(regs[r1] ^ regs[r2]); 561 break; 562 case INDEX_op_nand: 563 tci_args_rrr(insn, &r0, &r1, &r2); 564 regs[r0] = ~(regs[r1] & regs[r2]); 565 break; 566 case INDEX_op_nor: 567 tci_args_rrr(insn, &r0, &r1, &r2); 568 regs[r0] = ~(regs[r1] | regs[r2]); 569 break; 570 case INDEX_op_neg: 571 tci_args_rr(insn, &r0, &r1); 572 regs[r0] = -regs[r1]; 573 break; 574 575 /* Arithmetic operations (32 bit). */ 576 577 case INDEX_op_div_i32: 578 tci_args_rrr(insn, &r0, &r1, &r2); 579 regs[r0] = (int32_t)regs[r1] / (int32_t)regs[r2]; 580 break; 581 case INDEX_op_divu_i32: 582 tci_args_rrr(insn, &r0, &r1, &r2); 583 regs[r0] = (uint32_t)regs[r1] / (uint32_t)regs[r2]; 584 break; 585 case INDEX_op_rem_i32: 586 tci_args_rrr(insn, &r0, &r1, &r2); 587 regs[r0] = (int32_t)regs[r1] % (int32_t)regs[r2]; 588 break; 589 case INDEX_op_remu_i32: 590 tci_args_rrr(insn, &r0, &r1, &r2); 591 regs[r0] = (uint32_t)regs[r1] % (uint32_t)regs[r2]; 592 break; 593 #if TCG_TARGET_HAS_clz_i32 594 case INDEX_op_clz_i32: 595 tci_args_rrr(insn, &r0, &r1, &r2); 596 tmp32 = regs[r1]; 597 regs[r0] = tmp32 ? clz32(tmp32) : regs[r2]; 598 break; 599 #endif 600 #if TCG_TARGET_HAS_ctz_i32 601 case INDEX_op_ctz_i32: 602 tci_args_rrr(insn, &r0, &r1, &r2); 603 tmp32 = regs[r1]; 604 regs[r0] = tmp32 ? ctz32(tmp32) : regs[r2]; 605 break; 606 #endif 607 #if TCG_TARGET_HAS_ctpop_i32 608 case INDEX_op_ctpop_i32: 609 tci_args_rr(insn, &r0, &r1); 610 regs[r0] = ctpop32(regs[r1]); 611 break; 612 #endif 613 614 /* Shift/rotate operations (32 bit). */ 615 616 case INDEX_op_shl_i32: 617 tci_args_rrr(insn, &r0, &r1, &r2); 618 regs[r0] = (uint32_t)regs[r1] << (regs[r2] & 31); 619 break; 620 case INDEX_op_shr_i32: 621 tci_args_rrr(insn, &r0, &r1, &r2); 622 regs[r0] = (uint32_t)regs[r1] >> (regs[r2] & 31); 623 break; 624 case INDEX_op_sar_i32: 625 tci_args_rrr(insn, &r0, &r1, &r2); 626 regs[r0] = (int32_t)regs[r1] >> (regs[r2] & 31); 627 break; 628 #if TCG_TARGET_HAS_rot_i32 629 case INDEX_op_rotl_i32: 630 tci_args_rrr(insn, &r0, &r1, &r2); 631 regs[r0] = rol32(regs[r1], regs[r2] & 31); 632 break; 633 case INDEX_op_rotr_i32: 634 tci_args_rrr(insn, &r0, &r1, &r2); 635 regs[r0] = ror32(regs[r1], regs[r2] & 31); 636 break; 637 #endif 638 case INDEX_op_deposit_i32: 639 tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len); 640 regs[r0] = deposit32(regs[r1], pos, len, regs[r2]); 641 break; 642 case INDEX_op_extract_i32: 643 tci_args_rrbb(insn, &r0, &r1, &pos, &len); 644 regs[r0] = extract32(regs[r1], pos, len); 645 break; 646 case INDEX_op_sextract_i32: 647 tci_args_rrbb(insn, &r0, &r1, &pos, &len); 648 regs[r0] = sextract32(regs[r1], pos, len); 649 break; 650 case INDEX_op_brcond_i32: 651 tci_args_rl(insn, tb_ptr, &r0, &ptr); 652 if ((uint32_t)regs[r0]) { 653 tb_ptr = ptr; 654 } 655 break; 656 #if TCG_TARGET_REG_BITS == 32 || TCG_TARGET_HAS_add2_i32 657 case INDEX_op_add2_i32: 658 tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); 659 T1 = tci_uint64(regs[r3], regs[r2]); 660 T2 = tci_uint64(regs[r5], regs[r4]); 661 tci_write_reg64(regs, r1, r0, T1 + T2); 662 break; 663 #endif 664 #if TCG_TARGET_REG_BITS == 32 || TCG_TARGET_HAS_sub2_i32 665 case INDEX_op_sub2_i32: 666 tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); 667 T1 = tci_uint64(regs[r3], regs[r2]); 668 T2 = tci_uint64(regs[r5], regs[r4]); 669 tci_write_reg64(regs, r1, r0, T1 - T2); 670 break; 671 #endif 672 #if TCG_TARGET_HAS_mulu2_i32 673 case INDEX_op_mulu2_i32: 674 tci_args_rrrr(insn, &r0, &r1, &r2, &r3); 675 tmp64 = (uint64_t)(uint32_t)regs[r2] * (uint32_t)regs[r3]; 676 tci_write_reg64(regs, r1, r0, tmp64); 677 break; 678 #endif 679 #if TCG_TARGET_HAS_muls2_i32 680 case INDEX_op_muls2_i32: 681 tci_args_rrrr(insn, &r0, &r1, &r2, &r3); 682 tmp64 = (int64_t)(int32_t)regs[r2] * (int32_t)regs[r3]; 683 tci_write_reg64(regs, r1, r0, tmp64); 684 break; 685 #endif 686 #if TCG_TARGET_HAS_bswap16_i32 || TCG_TARGET_HAS_bswap16_i64 687 CASE_32_64(bswap16) 688 tci_args_rr(insn, &r0, &r1); 689 regs[r0] = bswap16(regs[r1]); 690 break; 691 #endif 692 #if TCG_TARGET_HAS_bswap32_i32 || TCG_TARGET_HAS_bswap32_i64 693 CASE_32_64(bswap32) 694 tci_args_rr(insn, &r0, &r1); 695 regs[r0] = bswap32(regs[r1]); 696 break; 697 #endif 698 #if TCG_TARGET_HAS_not_i32 || TCG_TARGET_HAS_not_i64 699 CASE_32_64(not) 700 tci_args_rr(insn, &r0, &r1); 701 regs[r0] = ~regs[r1]; 702 break; 703 #endif 704 #if TCG_TARGET_REG_BITS == 64 705 /* Load/store operations (64 bit). */ 706 707 case INDEX_op_ld32s_i64: 708 tci_args_rrs(insn, &r0, &r1, &ofs); 709 ptr = (void *)(regs[r1] + ofs); 710 regs[r0] = *(int32_t *)ptr; 711 break; 712 case INDEX_op_ld_i64: 713 tci_args_rrs(insn, &r0, &r1, &ofs); 714 ptr = (void *)(regs[r1] + ofs); 715 regs[r0] = *(uint64_t *)ptr; 716 break; 717 case INDEX_op_st_i64: 718 tci_args_rrs(insn, &r0, &r1, &ofs); 719 ptr = (void *)(regs[r1] + ofs); 720 *(uint64_t *)ptr = regs[r0]; 721 break; 722 723 /* Arithmetic operations (64 bit). */ 724 725 case INDEX_op_div_i64: 726 tci_args_rrr(insn, &r0, &r1, &r2); 727 regs[r0] = (int64_t)regs[r1] / (int64_t)regs[r2]; 728 break; 729 case INDEX_op_divu_i64: 730 tci_args_rrr(insn, &r0, &r1, &r2); 731 regs[r0] = (uint64_t)regs[r1] / (uint64_t)regs[r2]; 732 break; 733 case INDEX_op_rem_i64: 734 tci_args_rrr(insn, &r0, &r1, &r2); 735 regs[r0] = (int64_t)regs[r1] % (int64_t)regs[r2]; 736 break; 737 case INDEX_op_remu_i64: 738 tci_args_rrr(insn, &r0, &r1, &r2); 739 regs[r0] = (uint64_t)regs[r1] % (uint64_t)regs[r2]; 740 break; 741 #if TCG_TARGET_HAS_clz_i64 742 case INDEX_op_clz_i64: 743 tci_args_rrr(insn, &r0, &r1, &r2); 744 regs[r0] = regs[r1] ? clz64(regs[r1]) : regs[r2]; 745 break; 746 #endif 747 #if TCG_TARGET_HAS_ctz_i64 748 case INDEX_op_ctz_i64: 749 tci_args_rrr(insn, &r0, &r1, &r2); 750 regs[r0] = regs[r1] ? ctz64(regs[r1]) : regs[r2]; 751 break; 752 #endif 753 #if TCG_TARGET_HAS_ctpop_i64 754 case INDEX_op_ctpop_i64: 755 tci_args_rr(insn, &r0, &r1); 756 regs[r0] = ctpop64(regs[r1]); 757 break; 758 #endif 759 #if TCG_TARGET_HAS_mulu2_i64 760 case INDEX_op_mulu2_i64: 761 tci_args_rrrr(insn, &r0, &r1, &r2, &r3); 762 mulu64(®s[r0], ®s[r1], regs[r2], regs[r3]); 763 break; 764 #endif 765 #if TCG_TARGET_HAS_muls2_i64 766 case INDEX_op_muls2_i64: 767 tci_args_rrrr(insn, &r0, &r1, &r2, &r3); 768 muls64(®s[r0], ®s[r1], regs[r2], regs[r3]); 769 break; 770 #endif 771 #if TCG_TARGET_HAS_add2_i64 772 case INDEX_op_add2_i64: 773 tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); 774 T1 = regs[r2] + regs[r4]; 775 T2 = regs[r3] + regs[r5] + (T1 < regs[r2]); 776 regs[r0] = T1; 777 regs[r1] = T2; 778 break; 779 #endif 780 #if TCG_TARGET_HAS_add2_i64 781 case INDEX_op_sub2_i64: 782 tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); 783 T1 = regs[r2] - regs[r4]; 784 T2 = regs[r3] - regs[r5] - (regs[r2] < regs[r4]); 785 regs[r0] = T1; 786 regs[r1] = T2; 787 break; 788 #endif 789 790 /* Shift/rotate operations (64 bit). */ 791 792 case INDEX_op_shl_i64: 793 tci_args_rrr(insn, &r0, &r1, &r2); 794 regs[r0] = regs[r1] << (regs[r2] & 63); 795 break; 796 case INDEX_op_shr_i64: 797 tci_args_rrr(insn, &r0, &r1, &r2); 798 regs[r0] = regs[r1] >> (regs[r2] & 63); 799 break; 800 case INDEX_op_sar_i64: 801 tci_args_rrr(insn, &r0, &r1, &r2); 802 regs[r0] = (int64_t)regs[r1] >> (regs[r2] & 63); 803 break; 804 #if TCG_TARGET_HAS_rot_i64 805 case INDEX_op_rotl_i64: 806 tci_args_rrr(insn, &r0, &r1, &r2); 807 regs[r0] = rol64(regs[r1], regs[r2] & 63); 808 break; 809 case INDEX_op_rotr_i64: 810 tci_args_rrr(insn, &r0, &r1, &r2); 811 regs[r0] = ror64(regs[r1], regs[r2] & 63); 812 break; 813 #endif 814 case INDEX_op_deposit_i64: 815 tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len); 816 regs[r0] = deposit64(regs[r1], pos, len, regs[r2]); 817 break; 818 case INDEX_op_extract_i64: 819 tci_args_rrbb(insn, &r0, &r1, &pos, &len); 820 regs[r0] = extract64(regs[r1], pos, len); 821 break; 822 case INDEX_op_sextract_i64: 823 tci_args_rrbb(insn, &r0, &r1, &pos, &len); 824 regs[r0] = sextract64(regs[r1], pos, len); 825 break; 826 case INDEX_op_brcond_i64: 827 tci_args_rl(insn, tb_ptr, &r0, &ptr); 828 if (regs[r0]) { 829 tb_ptr = ptr; 830 } 831 break; 832 case INDEX_op_ext_i32_i64: 833 tci_args_rr(insn, &r0, &r1); 834 regs[r0] = (int32_t)regs[r1]; 835 break; 836 case INDEX_op_extu_i32_i64: 837 tci_args_rr(insn, &r0, &r1); 838 regs[r0] = (uint32_t)regs[r1]; 839 break; 840 #if TCG_TARGET_HAS_bswap64_i64 841 case INDEX_op_bswap64_i64: 842 tci_args_rr(insn, &r0, &r1); 843 regs[r0] = bswap64(regs[r1]); 844 break; 845 #endif 846 #endif /* TCG_TARGET_REG_BITS == 64 */ 847 848 /* QEMU specific operations. */ 849 850 case INDEX_op_exit_tb: 851 tci_args_l(insn, tb_ptr, &ptr); 852 return (uintptr_t)ptr; 853 854 case INDEX_op_goto_tb: 855 tci_args_l(insn, tb_ptr, &ptr); 856 tb_ptr = *(void **)ptr; 857 break; 858 859 case INDEX_op_goto_ptr: 860 tci_args_r(insn, &r0); 861 ptr = (void *)regs[r0]; 862 if (!ptr) { 863 return 0; 864 } 865 tb_ptr = ptr; 866 break; 867 868 case INDEX_op_qemu_ld_i32: 869 tci_args_rrm(insn, &r0, &r1, &oi); 870 taddr = regs[r1]; 871 regs[r0] = tci_qemu_ld(env, taddr, oi, tb_ptr); 872 break; 873 874 case INDEX_op_qemu_ld_i64: 875 if (TCG_TARGET_REG_BITS == 64) { 876 tci_args_rrm(insn, &r0, &r1, &oi); 877 taddr = regs[r1]; 878 } else { 879 tci_args_rrrr(insn, &r0, &r1, &r2, &r3); 880 taddr = regs[r2]; 881 oi = regs[r3]; 882 } 883 tmp64 = tci_qemu_ld(env, taddr, oi, tb_ptr); 884 if (TCG_TARGET_REG_BITS == 32) { 885 tci_write_reg64(regs, r1, r0, tmp64); 886 } else { 887 regs[r0] = tmp64; 888 } 889 break; 890 891 case INDEX_op_qemu_st_i32: 892 tci_args_rrm(insn, &r0, &r1, &oi); 893 taddr = regs[r1]; 894 tci_qemu_st(env, taddr, regs[r0], oi, tb_ptr); 895 break; 896 897 case INDEX_op_qemu_st_i64: 898 if (TCG_TARGET_REG_BITS == 64) { 899 tci_args_rrm(insn, &r0, &r1, &oi); 900 tmp64 = regs[r0]; 901 taddr = regs[r1]; 902 } else { 903 tci_args_rrrr(insn, &r0, &r1, &r2, &r3); 904 tmp64 = tci_uint64(regs[r1], regs[r0]); 905 taddr = regs[r2]; 906 oi = regs[r3]; 907 } 908 tci_qemu_st(env, taddr, tmp64, oi, tb_ptr); 909 break; 910 911 case INDEX_op_mb: 912 /* Ensure ordering for all kinds */ 913 smp_mb(); 914 break; 915 default: 916 g_assert_not_reached(); 917 } 918 } 919 } 920 921 /* 922 * Disassembler that matches the interpreter 923 */ 924 925 static const char *str_r(TCGReg r) 926 { 927 static const char regs[TCG_TARGET_NB_REGS][4] = { 928 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 929 "r8", "r9", "r10", "r11", "r12", "r13", "env", "sp" 930 }; 931 932 QEMU_BUILD_BUG_ON(TCG_AREG0 != TCG_REG_R14); 933 QEMU_BUILD_BUG_ON(TCG_REG_CALL_STACK != TCG_REG_R15); 934 935 assert((unsigned)r < TCG_TARGET_NB_REGS); 936 return regs[r]; 937 } 938 939 static const char *str_c(TCGCond c) 940 { 941 static const char cond[16][8] = { 942 [TCG_COND_NEVER] = "never", 943 [TCG_COND_ALWAYS] = "always", 944 [TCG_COND_EQ] = "eq", 945 [TCG_COND_NE] = "ne", 946 [TCG_COND_LT] = "lt", 947 [TCG_COND_GE] = "ge", 948 [TCG_COND_LE] = "le", 949 [TCG_COND_GT] = "gt", 950 [TCG_COND_LTU] = "ltu", 951 [TCG_COND_GEU] = "geu", 952 [TCG_COND_LEU] = "leu", 953 [TCG_COND_GTU] = "gtu", 954 [TCG_COND_TSTEQ] = "tsteq", 955 [TCG_COND_TSTNE] = "tstne", 956 }; 957 958 assert((unsigned)c < ARRAY_SIZE(cond)); 959 assert(cond[c][0] != 0); 960 return cond[c]; 961 } 962 963 /* Disassemble TCI bytecode. */ 964 int print_insn_tci(bfd_vma addr, disassemble_info *info) 965 { 966 const uint32_t *tb_ptr = (const void *)(uintptr_t)addr; 967 const TCGOpDef *def; 968 const char *op_name; 969 uint32_t insn; 970 TCGOpcode op; 971 TCGReg r0, r1, r2, r3, r4, r5; 972 tcg_target_ulong i1; 973 int32_t s2; 974 TCGCond c; 975 MemOpIdx oi; 976 uint8_t pos, len; 977 void *ptr; 978 979 /* TCI is always the host, so we don't need to load indirect. */ 980 insn = *tb_ptr++; 981 982 info->fprintf_func(info->stream, "%08x ", insn); 983 984 op = extract32(insn, 0, 8); 985 def = &tcg_op_defs[op]; 986 op_name = def->name; 987 988 switch (op) { 989 case INDEX_op_br: 990 case INDEX_op_exit_tb: 991 case INDEX_op_goto_tb: 992 tci_args_l(insn, tb_ptr, &ptr); 993 info->fprintf_func(info->stream, "%-12s %p", op_name, ptr); 994 break; 995 996 case INDEX_op_goto_ptr: 997 tci_args_r(insn, &r0); 998 info->fprintf_func(info->stream, "%-12s %s", op_name, str_r(r0)); 999 break; 1000 1001 case INDEX_op_call: 1002 tci_args_nl(insn, tb_ptr, &len, &ptr); 1003 info->fprintf_func(info->stream, "%-12s %d, %p", op_name, len, ptr); 1004 break; 1005 1006 case INDEX_op_brcond_i32: 1007 case INDEX_op_brcond_i64: 1008 tci_args_rl(insn, tb_ptr, &r0, &ptr); 1009 info->fprintf_func(info->stream, "%-12s %s, 0, ne, %p", 1010 op_name, str_r(r0), ptr); 1011 break; 1012 1013 case INDEX_op_setcond_i32: 1014 case INDEX_op_setcond_i64: 1015 tci_args_rrrc(insn, &r0, &r1, &r2, &c); 1016 info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s", 1017 op_name, str_r(r0), str_r(r1), str_r(r2), str_c(c)); 1018 break; 1019 1020 case INDEX_op_tci_movi: 1021 tci_args_ri(insn, &r0, &i1); 1022 info->fprintf_func(info->stream, "%-12s %s, 0x%" TCG_PRIlx, 1023 op_name, str_r(r0), i1); 1024 break; 1025 1026 case INDEX_op_tci_movl: 1027 tci_args_rl(insn, tb_ptr, &r0, &ptr); 1028 info->fprintf_func(info->stream, "%-12s %s, %p", 1029 op_name, str_r(r0), ptr); 1030 break; 1031 1032 case INDEX_op_ld8u_i32: 1033 case INDEX_op_ld8u_i64: 1034 case INDEX_op_ld8s_i32: 1035 case INDEX_op_ld8s_i64: 1036 case INDEX_op_ld16u_i32: 1037 case INDEX_op_ld16u_i64: 1038 case INDEX_op_ld16s_i32: 1039 case INDEX_op_ld16s_i64: 1040 case INDEX_op_ld32u_i64: 1041 case INDEX_op_ld32s_i64: 1042 case INDEX_op_ld_i32: 1043 case INDEX_op_ld_i64: 1044 case INDEX_op_st8_i32: 1045 case INDEX_op_st8_i64: 1046 case INDEX_op_st16_i32: 1047 case INDEX_op_st16_i64: 1048 case INDEX_op_st32_i64: 1049 case INDEX_op_st_i32: 1050 case INDEX_op_st_i64: 1051 tci_args_rrs(insn, &r0, &r1, &s2); 1052 info->fprintf_func(info->stream, "%-12s %s, %s, %d", 1053 op_name, str_r(r0), str_r(r1), s2); 1054 break; 1055 1056 case INDEX_op_mov: 1057 case INDEX_op_neg: 1058 case INDEX_op_ext_i32_i64: 1059 case INDEX_op_extu_i32_i64: 1060 case INDEX_op_bswap16_i32: 1061 case INDEX_op_bswap16_i64: 1062 case INDEX_op_bswap32_i32: 1063 case INDEX_op_bswap32_i64: 1064 case INDEX_op_bswap64_i64: 1065 case INDEX_op_not_i32: 1066 case INDEX_op_not_i64: 1067 case INDEX_op_ctpop_i32: 1068 case INDEX_op_ctpop_i64: 1069 tci_args_rr(insn, &r0, &r1); 1070 info->fprintf_func(info->stream, "%-12s %s, %s", 1071 op_name, str_r(r0), str_r(r1)); 1072 break; 1073 1074 case INDEX_op_add: 1075 case INDEX_op_and: 1076 case INDEX_op_andc: 1077 case INDEX_op_eqv: 1078 case INDEX_op_nand: 1079 case INDEX_op_nor: 1080 case INDEX_op_or: 1081 case INDEX_op_orc: 1082 case INDEX_op_sub: 1083 case INDEX_op_xor: 1084 case INDEX_op_mul_i32: 1085 case INDEX_op_mul_i64: 1086 case INDEX_op_div_i32: 1087 case INDEX_op_div_i64: 1088 case INDEX_op_rem_i32: 1089 case INDEX_op_rem_i64: 1090 case INDEX_op_divu_i32: 1091 case INDEX_op_divu_i64: 1092 case INDEX_op_remu_i32: 1093 case INDEX_op_remu_i64: 1094 case INDEX_op_shl_i32: 1095 case INDEX_op_shl_i64: 1096 case INDEX_op_shr_i32: 1097 case INDEX_op_shr_i64: 1098 case INDEX_op_sar_i32: 1099 case INDEX_op_sar_i64: 1100 case INDEX_op_rotl_i32: 1101 case INDEX_op_rotl_i64: 1102 case INDEX_op_rotr_i32: 1103 case INDEX_op_rotr_i64: 1104 case INDEX_op_clz_i32: 1105 case INDEX_op_clz_i64: 1106 case INDEX_op_ctz_i32: 1107 case INDEX_op_ctz_i64: 1108 tci_args_rrr(insn, &r0, &r1, &r2); 1109 info->fprintf_func(info->stream, "%-12s %s, %s, %s", 1110 op_name, str_r(r0), str_r(r1), str_r(r2)); 1111 break; 1112 1113 case INDEX_op_deposit_i32: 1114 case INDEX_op_deposit_i64: 1115 tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len); 1116 info->fprintf_func(info->stream, "%-12s %s, %s, %s, %d, %d", 1117 op_name, str_r(r0), str_r(r1), str_r(r2), pos, len); 1118 break; 1119 1120 case INDEX_op_extract_i32: 1121 case INDEX_op_extract_i64: 1122 case INDEX_op_sextract_i32: 1123 case INDEX_op_sextract_i64: 1124 tci_args_rrbb(insn, &r0, &r1, &pos, &len); 1125 info->fprintf_func(info->stream, "%-12s %s,%s,%d,%d", 1126 op_name, str_r(r0), str_r(r1), pos, len); 1127 break; 1128 1129 case INDEX_op_movcond_i32: 1130 case INDEX_op_movcond_i64: 1131 case INDEX_op_setcond2_i32: 1132 tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &c); 1133 info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s, %s, %s", 1134 op_name, str_r(r0), str_r(r1), str_r(r2), 1135 str_r(r3), str_r(r4), str_c(c)); 1136 break; 1137 1138 case INDEX_op_mulu2_i32: 1139 case INDEX_op_mulu2_i64: 1140 case INDEX_op_muls2_i32: 1141 case INDEX_op_muls2_i64: 1142 tci_args_rrrr(insn, &r0, &r1, &r2, &r3); 1143 info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s", 1144 op_name, str_r(r0), str_r(r1), 1145 str_r(r2), str_r(r3)); 1146 break; 1147 1148 case INDEX_op_add2_i32: 1149 case INDEX_op_add2_i64: 1150 case INDEX_op_sub2_i32: 1151 case INDEX_op_sub2_i64: 1152 tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); 1153 info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s, %s, %s", 1154 op_name, str_r(r0), str_r(r1), str_r(r2), 1155 str_r(r3), str_r(r4), str_r(r5)); 1156 break; 1157 1158 case INDEX_op_qemu_ld_i64: 1159 case INDEX_op_qemu_st_i64: 1160 if (TCG_TARGET_REG_BITS == 32) { 1161 tci_args_rrrr(insn, &r0, &r1, &r2, &r3); 1162 info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s", 1163 op_name, str_r(r0), str_r(r1), 1164 str_r(r2), str_r(r3)); 1165 break; 1166 } 1167 /* fall through */ 1168 case INDEX_op_qemu_ld_i32: 1169 case INDEX_op_qemu_st_i32: 1170 tci_args_rrm(insn, &r0, &r1, &oi); 1171 info->fprintf_func(info->stream, "%-12s %s, %s, %x", 1172 op_name, str_r(r0), str_r(r1), oi); 1173 break; 1174 1175 case 0: 1176 /* tcg_out_nop_fill uses zeros */ 1177 if (insn == 0) { 1178 info->fprintf_func(info->stream, "align"); 1179 break; 1180 } 1181 /* fall through */ 1182 1183 default: 1184 info->fprintf_func(info->stream, "illegal opcode %d", op); 1185 break; 1186 } 1187 1188 return sizeof(insn); 1189 } 1190