1 /* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 /* define it to use liveness analysis (better code) */ 26 #define USE_TCG_OPTIMIZATIONS 27 28 #include "qemu/osdep.h" 29 30 /* Define to jump the ELF file used to communicate with GDB. */ 31 #undef DEBUG_JIT 32 33 #include "qemu/cutils.h" 34 #include "qemu/host-utils.h" 35 #include "qemu/timer.h" 36 37 /* Note: the long term plan is to reduce the dependencies on the QEMU 38 CPU definitions. Currently they are used for qemu_ld/st 39 instructions */ 40 #define NO_CPU_IO_DEFS 41 #include "cpu.h" 42 43 #include "exec/cpu-common.h" 44 #include "exec/exec-all.h" 45 46 #include "tcg-op.h" 47 48 #if UINTPTR_MAX == UINT32_MAX 49 # define ELF_CLASS ELFCLASS32 50 #else 51 # define ELF_CLASS ELFCLASS64 52 #endif 53 #ifdef HOST_WORDS_BIGENDIAN 54 # define ELF_DATA ELFDATA2MSB 55 #else 56 # define ELF_DATA ELFDATA2LSB 57 #endif 58 59 #include "elf.h" 60 #include "exec/log.h" 61 #include "sysemu/sysemu.h" 62 63 /* Forward declarations for functions declared in tcg-target.inc.c and 64 used here. */ 65 static void tcg_target_init(TCGContext *s); 66 static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode); 67 static void tcg_target_qemu_prologue(TCGContext *s); 68 static void patch_reloc(tcg_insn_unit *code_ptr, int type, 69 intptr_t value, intptr_t addend); 70 71 /* The CIE and FDE header definitions will be common to all hosts. */ 72 typedef struct { 73 uint32_t len __attribute__((aligned((sizeof(void *))))); 74 uint32_t id; 75 uint8_t version; 76 char augmentation[1]; 77 uint8_t code_align; 78 uint8_t data_align; 79 uint8_t return_column; 80 } DebugFrameCIE; 81 82 typedef struct QEMU_PACKED { 83 uint32_t len __attribute__((aligned((sizeof(void *))))); 84 uint32_t cie_offset; 85 uintptr_t func_start; 86 uintptr_t func_len; 87 } DebugFrameFDEHeader; 88 89 typedef struct QEMU_PACKED { 90 DebugFrameCIE cie; 91 DebugFrameFDEHeader fde; 92 } DebugFrameHeader; 93 94 static void tcg_register_jit_int(void *buf, size_t size, 95 const void *debug_frame, 96 size_t debug_frame_size) 97 __attribute__((unused)); 98 99 /* Forward declarations for functions declared and used in tcg-target.inc.c. */ 100 static const char *target_parse_constraint(TCGArgConstraint *ct, 101 const char *ct_str, TCGType type); 102 static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1, 103 intptr_t arg2); 104 static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg); 105 static void tcg_out_movi(TCGContext *s, TCGType type, 106 TCGReg ret, tcg_target_long arg); 107 static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, 108 const int *const_args); 109 #if TCG_TARGET_MAYBE_vec 110 static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, 111 unsigned vece, const TCGArg *args, 112 const int *const_args); 113 #else 114 static inline void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, 115 unsigned vece, const TCGArg *args, 116 const int *const_args) 117 { 118 g_assert_not_reached(); 119 } 120 #endif 121 static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1, 122 intptr_t arg2); 123 static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 124 TCGReg base, intptr_t ofs); 125 static void tcg_out_call(TCGContext *s, tcg_insn_unit *target); 126 static int tcg_target_const_match(tcg_target_long val, TCGType type, 127 const TCGArgConstraint *arg_ct); 128 #ifdef TCG_TARGET_NEED_LDST_LABELS 129 static bool tcg_out_ldst_finalize(TCGContext *s); 130 #endif 131 132 #define TCG_HIGHWATER 1024 133 134 static TCGContext **tcg_ctxs; 135 static unsigned int n_tcg_ctxs; 136 TCGv_env cpu_env = 0; 137 138 /* 139 * We divide code_gen_buffer into equally-sized "regions" that TCG threads 140 * dynamically allocate from as demand dictates. Given appropriate region 141 * sizing, this minimizes flushes even when some TCG threads generate a lot 142 * more code than others. 143 */ 144 struct tcg_region_state { 145 QemuMutex lock; 146 147 /* fields set at init time */ 148 void *start; 149 void *start_aligned; 150 void *end; 151 size_t n; 152 size_t size; /* size of one region */ 153 size_t stride; /* .size + guard size */ 154 155 /* fields protected by the lock */ 156 size_t current; /* current region index */ 157 size_t agg_size_full; /* aggregate size of full regions */ 158 }; 159 160 static struct tcg_region_state region; 161 static TCGRegSet tcg_target_available_regs[TCG_TYPE_COUNT]; 162 static TCGRegSet tcg_target_call_clobber_regs; 163 164 #if TCG_TARGET_INSN_UNIT_SIZE == 1 165 static __attribute__((unused)) inline void tcg_out8(TCGContext *s, uint8_t v) 166 { 167 *s->code_ptr++ = v; 168 } 169 170 static __attribute__((unused)) inline void tcg_patch8(tcg_insn_unit *p, 171 uint8_t v) 172 { 173 *p = v; 174 } 175 #endif 176 177 #if TCG_TARGET_INSN_UNIT_SIZE <= 2 178 static __attribute__((unused)) inline void tcg_out16(TCGContext *s, uint16_t v) 179 { 180 if (TCG_TARGET_INSN_UNIT_SIZE == 2) { 181 *s->code_ptr++ = v; 182 } else { 183 tcg_insn_unit *p = s->code_ptr; 184 memcpy(p, &v, sizeof(v)); 185 s->code_ptr = p + (2 / TCG_TARGET_INSN_UNIT_SIZE); 186 } 187 } 188 189 static __attribute__((unused)) inline void tcg_patch16(tcg_insn_unit *p, 190 uint16_t v) 191 { 192 if (TCG_TARGET_INSN_UNIT_SIZE == 2) { 193 *p = v; 194 } else { 195 memcpy(p, &v, sizeof(v)); 196 } 197 } 198 #endif 199 200 #if TCG_TARGET_INSN_UNIT_SIZE <= 4 201 static __attribute__((unused)) inline void tcg_out32(TCGContext *s, uint32_t v) 202 { 203 if (TCG_TARGET_INSN_UNIT_SIZE == 4) { 204 *s->code_ptr++ = v; 205 } else { 206 tcg_insn_unit *p = s->code_ptr; 207 memcpy(p, &v, sizeof(v)); 208 s->code_ptr = p + (4 / TCG_TARGET_INSN_UNIT_SIZE); 209 } 210 } 211 212 static __attribute__((unused)) inline void tcg_patch32(tcg_insn_unit *p, 213 uint32_t v) 214 { 215 if (TCG_TARGET_INSN_UNIT_SIZE == 4) { 216 *p = v; 217 } else { 218 memcpy(p, &v, sizeof(v)); 219 } 220 } 221 #endif 222 223 #if TCG_TARGET_INSN_UNIT_SIZE <= 8 224 static __attribute__((unused)) inline void tcg_out64(TCGContext *s, uint64_t v) 225 { 226 if (TCG_TARGET_INSN_UNIT_SIZE == 8) { 227 *s->code_ptr++ = v; 228 } else { 229 tcg_insn_unit *p = s->code_ptr; 230 memcpy(p, &v, sizeof(v)); 231 s->code_ptr = p + (8 / TCG_TARGET_INSN_UNIT_SIZE); 232 } 233 } 234 235 static __attribute__((unused)) inline void tcg_patch64(tcg_insn_unit *p, 236 uint64_t v) 237 { 238 if (TCG_TARGET_INSN_UNIT_SIZE == 8) { 239 *p = v; 240 } else { 241 memcpy(p, &v, sizeof(v)); 242 } 243 } 244 #endif 245 246 /* label relocation processing */ 247 248 static void tcg_out_reloc(TCGContext *s, tcg_insn_unit *code_ptr, int type, 249 TCGLabel *l, intptr_t addend) 250 { 251 TCGRelocation *r; 252 253 if (l->has_value) { 254 /* FIXME: This may break relocations on RISC targets that 255 modify instruction fields in place. The caller may not have 256 written the initial value. */ 257 patch_reloc(code_ptr, type, l->u.value, addend); 258 } else { 259 /* add a new relocation entry */ 260 r = tcg_malloc(sizeof(TCGRelocation)); 261 r->type = type; 262 r->ptr = code_ptr; 263 r->addend = addend; 264 r->next = l->u.first_reloc; 265 l->u.first_reloc = r; 266 } 267 } 268 269 static void tcg_out_label(TCGContext *s, TCGLabel *l, tcg_insn_unit *ptr) 270 { 271 intptr_t value = (intptr_t)ptr; 272 TCGRelocation *r; 273 274 tcg_debug_assert(!l->has_value); 275 276 for (r = l->u.first_reloc; r != NULL; r = r->next) { 277 patch_reloc(r->ptr, r->type, value, r->addend); 278 } 279 280 l->has_value = 1; 281 l->u.value_ptr = ptr; 282 } 283 284 TCGLabel *gen_new_label(void) 285 { 286 TCGContext *s = tcg_ctx; 287 TCGLabel *l = tcg_malloc(sizeof(TCGLabel)); 288 289 *l = (TCGLabel){ 290 .id = s->nb_labels++ 291 }; 292 293 return l; 294 } 295 296 #include "tcg-target.inc.c" 297 298 static void tcg_region_bounds(size_t curr_region, void **pstart, void **pend) 299 { 300 void *start, *end; 301 302 start = region.start_aligned + curr_region * region.stride; 303 end = start + region.size; 304 305 if (curr_region == 0) { 306 start = region.start; 307 } 308 if (curr_region == region.n - 1) { 309 end = region.end; 310 } 311 312 *pstart = start; 313 *pend = end; 314 } 315 316 static void tcg_region_assign(TCGContext *s, size_t curr_region) 317 { 318 void *start, *end; 319 320 tcg_region_bounds(curr_region, &start, &end); 321 322 s->code_gen_buffer = start; 323 s->code_gen_ptr = start; 324 s->code_gen_buffer_size = end - start; 325 s->code_gen_highwater = end - TCG_HIGHWATER; 326 } 327 328 static bool tcg_region_alloc__locked(TCGContext *s) 329 { 330 if (region.current == region.n) { 331 return true; 332 } 333 tcg_region_assign(s, region.current); 334 region.current++; 335 return false; 336 } 337 338 /* 339 * Request a new region once the one in use has filled up. 340 * Returns true on error. 341 */ 342 static bool tcg_region_alloc(TCGContext *s) 343 { 344 bool err; 345 /* read the region size now; alloc__locked will overwrite it on success */ 346 size_t size_full = s->code_gen_buffer_size; 347 348 qemu_mutex_lock(®ion.lock); 349 err = tcg_region_alloc__locked(s); 350 if (!err) { 351 region.agg_size_full += size_full - TCG_HIGHWATER; 352 } 353 qemu_mutex_unlock(®ion.lock); 354 return err; 355 } 356 357 /* 358 * Perform a context's first region allocation. 359 * This function does _not_ increment region.agg_size_full. 360 */ 361 static inline bool tcg_region_initial_alloc__locked(TCGContext *s) 362 { 363 return tcg_region_alloc__locked(s); 364 } 365 366 /* Call from a safe-work context */ 367 void tcg_region_reset_all(void) 368 { 369 unsigned int n_ctxs = atomic_read(&n_tcg_ctxs); 370 unsigned int i; 371 372 qemu_mutex_lock(®ion.lock); 373 region.current = 0; 374 region.agg_size_full = 0; 375 376 for (i = 0; i < n_ctxs; i++) { 377 TCGContext *s = atomic_read(&tcg_ctxs[i]); 378 bool err = tcg_region_initial_alloc__locked(s); 379 380 g_assert(!err); 381 } 382 qemu_mutex_unlock(®ion.lock); 383 } 384 385 #ifdef CONFIG_USER_ONLY 386 static size_t tcg_n_regions(void) 387 { 388 return 1; 389 } 390 #else 391 /* 392 * It is likely that some vCPUs will translate more code than others, so we 393 * first try to set more regions than max_cpus, with those regions being of 394 * reasonable size. If that's not possible we make do by evenly dividing 395 * the code_gen_buffer among the vCPUs. 396 */ 397 static size_t tcg_n_regions(void) 398 { 399 size_t i; 400 401 /* Use a single region if all we have is one vCPU thread */ 402 if (max_cpus == 1 || !qemu_tcg_mttcg_enabled()) { 403 return 1; 404 } 405 406 /* Try to have more regions than max_cpus, with each region being >= 2 MB */ 407 for (i = 8; i > 0; i--) { 408 size_t regions_per_thread = i; 409 size_t region_size; 410 411 region_size = tcg_init_ctx.code_gen_buffer_size; 412 region_size /= max_cpus * regions_per_thread; 413 414 if (region_size >= 2 * 1024u * 1024) { 415 return max_cpus * regions_per_thread; 416 } 417 } 418 /* If we can't, then just allocate one region per vCPU thread */ 419 return max_cpus; 420 } 421 #endif 422 423 /* 424 * Initializes region partitioning. 425 * 426 * Called at init time from the parent thread (i.e. the one calling 427 * tcg_context_init), after the target's TCG globals have been set. 428 * 429 * Region partitioning works by splitting code_gen_buffer into separate regions, 430 * and then assigning regions to TCG threads so that the threads can translate 431 * code in parallel without synchronization. 432 * 433 * In softmmu the number of TCG threads is bounded by max_cpus, so we use at 434 * least max_cpus regions in MTTCG. In !MTTCG we use a single region. 435 * Note that the TCG options from the command-line (i.e. -accel accel=tcg,[...]) 436 * must have been parsed before calling this function, since it calls 437 * qemu_tcg_mttcg_enabled(). 438 * 439 * In user-mode we use a single region. Having multiple regions in user-mode 440 * is not supported, because the number of vCPU threads (recall that each thread 441 * spawned by the guest corresponds to a vCPU thread) is only bounded by the 442 * OS, and usually this number is huge (tens of thousands is not uncommon). 443 * Thus, given this large bound on the number of vCPU threads and the fact 444 * that code_gen_buffer is allocated at compile-time, we cannot guarantee 445 * that the availability of at least one region per vCPU thread. 446 * 447 * However, this user-mode limitation is unlikely to be a significant problem 448 * in practice. Multi-threaded guests share most if not all of their translated 449 * code, which makes parallel code generation less appealing than in softmmu. 450 */ 451 void tcg_region_init(void) 452 { 453 void *buf = tcg_init_ctx.code_gen_buffer; 454 void *aligned; 455 size_t size = tcg_init_ctx.code_gen_buffer_size; 456 size_t page_size = qemu_real_host_page_size; 457 size_t region_size; 458 size_t n_regions; 459 size_t i; 460 461 n_regions = tcg_n_regions(); 462 463 /* The first region will be 'aligned - buf' bytes larger than the others */ 464 aligned = QEMU_ALIGN_PTR_UP(buf, page_size); 465 g_assert(aligned < tcg_init_ctx.code_gen_buffer + size); 466 /* 467 * Make region_size a multiple of page_size, using aligned as the start. 468 * As a result of this we might end up with a few extra pages at the end of 469 * the buffer; we will assign those to the last region. 470 */ 471 region_size = (size - (aligned - buf)) / n_regions; 472 region_size = QEMU_ALIGN_DOWN(region_size, page_size); 473 474 /* A region must have at least 2 pages; one code, one guard */ 475 g_assert(region_size >= 2 * page_size); 476 477 /* init the region struct */ 478 qemu_mutex_init(®ion.lock); 479 region.n = n_regions; 480 region.size = region_size - page_size; 481 region.stride = region_size; 482 region.start = buf; 483 region.start_aligned = aligned; 484 /* page-align the end, since its last page will be a guard page */ 485 region.end = QEMU_ALIGN_PTR_DOWN(buf + size, page_size); 486 /* account for that last guard page */ 487 region.end -= page_size; 488 489 /* set guard pages */ 490 for (i = 0; i < region.n; i++) { 491 void *start, *end; 492 int rc; 493 494 tcg_region_bounds(i, &start, &end); 495 rc = qemu_mprotect_none(end, page_size); 496 g_assert(!rc); 497 } 498 499 /* In user-mode we support only one ctx, so do the initial allocation now */ 500 #ifdef CONFIG_USER_ONLY 501 { 502 bool err = tcg_region_initial_alloc__locked(tcg_ctx); 503 504 g_assert(!err); 505 } 506 #endif 507 } 508 509 /* 510 * All TCG threads except the parent (i.e. the one that called tcg_context_init 511 * and registered the target's TCG globals) must register with this function 512 * before initiating translation. 513 * 514 * In user-mode we just point tcg_ctx to tcg_init_ctx. See the documentation 515 * of tcg_region_init() for the reasoning behind this. 516 * 517 * In softmmu each caller registers its context in tcg_ctxs[]. Note that in 518 * softmmu tcg_ctxs[] does not track tcg_ctx_init, since the initial context 519 * is not used anymore for translation once this function is called. 520 * 521 * Not tracking tcg_init_ctx in tcg_ctxs[] in softmmu keeps code that iterates 522 * over the array (e.g. tcg_code_size() the same for both softmmu and user-mode. 523 */ 524 #ifdef CONFIG_USER_ONLY 525 void tcg_register_thread(void) 526 { 527 tcg_ctx = &tcg_init_ctx; 528 } 529 #else 530 void tcg_register_thread(void) 531 { 532 TCGContext *s = g_malloc(sizeof(*s)); 533 unsigned int i, n; 534 bool err; 535 536 *s = tcg_init_ctx; 537 538 /* Relink mem_base. */ 539 for (i = 0, n = tcg_init_ctx.nb_globals; i < n; ++i) { 540 if (tcg_init_ctx.temps[i].mem_base) { 541 ptrdiff_t b = tcg_init_ctx.temps[i].mem_base - tcg_init_ctx.temps; 542 tcg_debug_assert(b >= 0 && b < n); 543 s->temps[i].mem_base = &s->temps[b]; 544 } 545 } 546 547 /* Claim an entry in tcg_ctxs */ 548 n = atomic_fetch_inc(&n_tcg_ctxs); 549 g_assert(n < max_cpus); 550 atomic_set(&tcg_ctxs[n], s); 551 552 tcg_ctx = s; 553 qemu_mutex_lock(®ion.lock); 554 err = tcg_region_initial_alloc__locked(tcg_ctx); 555 g_assert(!err); 556 qemu_mutex_unlock(®ion.lock); 557 } 558 #endif /* !CONFIG_USER_ONLY */ 559 560 /* 561 * Returns the size (in bytes) of all translated code (i.e. from all regions) 562 * currently in the cache. 563 * See also: tcg_code_capacity() 564 * Do not confuse with tcg_current_code_size(); that one applies to a single 565 * TCG context. 566 */ 567 size_t tcg_code_size(void) 568 { 569 unsigned int n_ctxs = atomic_read(&n_tcg_ctxs); 570 unsigned int i; 571 size_t total; 572 573 qemu_mutex_lock(®ion.lock); 574 total = region.agg_size_full; 575 for (i = 0; i < n_ctxs; i++) { 576 const TCGContext *s = atomic_read(&tcg_ctxs[i]); 577 size_t size; 578 579 size = atomic_read(&s->code_gen_ptr) - s->code_gen_buffer; 580 g_assert(size <= s->code_gen_buffer_size); 581 total += size; 582 } 583 qemu_mutex_unlock(®ion.lock); 584 return total; 585 } 586 587 /* 588 * Returns the code capacity (in bytes) of the entire cache, i.e. including all 589 * regions. 590 * See also: tcg_code_size() 591 */ 592 size_t tcg_code_capacity(void) 593 { 594 size_t guard_size, capacity; 595 596 /* no need for synchronization; these variables are set at init time */ 597 guard_size = region.stride - region.size; 598 capacity = region.end + guard_size - region.start; 599 capacity -= region.n * (guard_size + TCG_HIGHWATER); 600 return capacity; 601 } 602 603 /* pool based memory allocation */ 604 void *tcg_malloc_internal(TCGContext *s, int size) 605 { 606 TCGPool *p; 607 int pool_size; 608 609 if (size > TCG_POOL_CHUNK_SIZE) { 610 /* big malloc: insert a new pool (XXX: could optimize) */ 611 p = g_malloc(sizeof(TCGPool) + size); 612 p->size = size; 613 p->next = s->pool_first_large; 614 s->pool_first_large = p; 615 return p->data; 616 } else { 617 p = s->pool_current; 618 if (!p) { 619 p = s->pool_first; 620 if (!p) 621 goto new_pool; 622 } else { 623 if (!p->next) { 624 new_pool: 625 pool_size = TCG_POOL_CHUNK_SIZE; 626 p = g_malloc(sizeof(TCGPool) + pool_size); 627 p->size = pool_size; 628 p->next = NULL; 629 if (s->pool_current) 630 s->pool_current->next = p; 631 else 632 s->pool_first = p; 633 } else { 634 p = p->next; 635 } 636 } 637 } 638 s->pool_current = p; 639 s->pool_cur = p->data + size; 640 s->pool_end = p->data + p->size; 641 return p->data; 642 } 643 644 void tcg_pool_reset(TCGContext *s) 645 { 646 TCGPool *p, *t; 647 for (p = s->pool_first_large; p; p = t) { 648 t = p->next; 649 g_free(p); 650 } 651 s->pool_first_large = NULL; 652 s->pool_cur = s->pool_end = NULL; 653 s->pool_current = NULL; 654 } 655 656 typedef struct TCGHelperInfo { 657 void *func; 658 const char *name; 659 unsigned flags; 660 unsigned sizemask; 661 } TCGHelperInfo; 662 663 #include "exec/helper-proto.h" 664 665 static const TCGHelperInfo all_helpers[] = { 666 #include "exec/helper-tcg.h" 667 }; 668 static GHashTable *helper_table; 669 670 static int indirect_reg_alloc_order[ARRAY_SIZE(tcg_target_reg_alloc_order)]; 671 static void process_op_defs(TCGContext *s); 672 static TCGTemp *tcg_global_reg_new_internal(TCGContext *s, TCGType type, 673 TCGReg reg, const char *name); 674 675 void tcg_context_init(TCGContext *s) 676 { 677 int op, total_args, n, i; 678 TCGOpDef *def; 679 TCGArgConstraint *args_ct; 680 int *sorted_args; 681 TCGTemp *ts; 682 683 memset(s, 0, sizeof(*s)); 684 s->nb_globals = 0; 685 686 /* Count total number of arguments and allocate the corresponding 687 space */ 688 total_args = 0; 689 for(op = 0; op < NB_OPS; op++) { 690 def = &tcg_op_defs[op]; 691 n = def->nb_iargs + def->nb_oargs; 692 total_args += n; 693 } 694 695 args_ct = g_malloc(sizeof(TCGArgConstraint) * total_args); 696 sorted_args = g_malloc(sizeof(int) * total_args); 697 698 for(op = 0; op < NB_OPS; op++) { 699 def = &tcg_op_defs[op]; 700 def->args_ct = args_ct; 701 def->sorted_args = sorted_args; 702 n = def->nb_iargs + def->nb_oargs; 703 sorted_args += n; 704 args_ct += n; 705 } 706 707 /* Register helpers. */ 708 /* Use g_direct_hash/equal for direct pointer comparisons on func. */ 709 helper_table = g_hash_table_new(NULL, NULL); 710 711 for (i = 0; i < ARRAY_SIZE(all_helpers); ++i) { 712 g_hash_table_insert(helper_table, (gpointer)all_helpers[i].func, 713 (gpointer)&all_helpers[i]); 714 } 715 716 tcg_target_init(s); 717 process_op_defs(s); 718 719 /* Reverse the order of the saved registers, assuming they're all at 720 the start of tcg_target_reg_alloc_order. */ 721 for (n = 0; n < ARRAY_SIZE(tcg_target_reg_alloc_order); ++n) { 722 int r = tcg_target_reg_alloc_order[n]; 723 if (tcg_regset_test_reg(tcg_target_call_clobber_regs, r)) { 724 break; 725 } 726 } 727 for (i = 0; i < n; ++i) { 728 indirect_reg_alloc_order[i] = tcg_target_reg_alloc_order[n - 1 - i]; 729 } 730 for (; i < ARRAY_SIZE(tcg_target_reg_alloc_order); ++i) { 731 indirect_reg_alloc_order[i] = tcg_target_reg_alloc_order[i]; 732 } 733 734 tcg_ctx = s; 735 /* 736 * In user-mode we simply share the init context among threads, since we 737 * use a single region. See the documentation tcg_region_init() for the 738 * reasoning behind this. 739 * In softmmu we will have at most max_cpus TCG threads. 740 */ 741 #ifdef CONFIG_USER_ONLY 742 tcg_ctxs = &tcg_ctx; 743 n_tcg_ctxs = 1; 744 #else 745 tcg_ctxs = g_new(TCGContext *, max_cpus); 746 #endif 747 748 tcg_debug_assert(!tcg_regset_test_reg(s->reserved_regs, TCG_AREG0)); 749 ts = tcg_global_reg_new_internal(s, TCG_TYPE_PTR, TCG_AREG0, "env"); 750 cpu_env = temp_tcgv_ptr(ts); 751 } 752 753 /* 754 * Allocate TBs right before their corresponding translated code, making 755 * sure that TBs and code are on different cache lines. 756 */ 757 TranslationBlock *tcg_tb_alloc(TCGContext *s) 758 { 759 uintptr_t align = qemu_icache_linesize; 760 TranslationBlock *tb; 761 void *next; 762 763 retry: 764 tb = (void *)ROUND_UP((uintptr_t)s->code_gen_ptr, align); 765 next = (void *)ROUND_UP((uintptr_t)(tb + 1), align); 766 767 if (unlikely(next > s->code_gen_highwater)) { 768 if (tcg_region_alloc(s)) { 769 return NULL; 770 } 771 goto retry; 772 } 773 atomic_set(&s->code_gen_ptr, next); 774 s->data_gen_ptr = NULL; 775 return tb; 776 } 777 778 void tcg_prologue_init(TCGContext *s) 779 { 780 size_t prologue_size, total_size; 781 void *buf0, *buf1; 782 783 /* Put the prologue at the beginning of code_gen_buffer. */ 784 buf0 = s->code_gen_buffer; 785 total_size = s->code_gen_buffer_size; 786 s->code_ptr = buf0; 787 s->code_buf = buf0; 788 s->data_gen_ptr = NULL; 789 s->code_gen_prologue = buf0; 790 791 /* Compute a high-water mark, at which we voluntarily flush the buffer 792 and start over. The size here is arbitrary, significantly larger 793 than we expect the code generation for any one opcode to require. */ 794 s->code_gen_highwater = s->code_gen_buffer + (total_size - TCG_HIGHWATER); 795 796 #ifdef TCG_TARGET_NEED_POOL_LABELS 797 s->pool_labels = NULL; 798 #endif 799 800 /* Generate the prologue. */ 801 tcg_target_qemu_prologue(s); 802 803 #ifdef TCG_TARGET_NEED_POOL_LABELS 804 /* Allow the prologue to put e.g. guest_base into a pool entry. */ 805 { 806 bool ok = tcg_out_pool_finalize(s); 807 tcg_debug_assert(ok); 808 } 809 #endif 810 811 buf1 = s->code_ptr; 812 flush_icache_range((uintptr_t)buf0, (uintptr_t)buf1); 813 814 /* Deduct the prologue from the buffer. */ 815 prologue_size = tcg_current_code_size(s); 816 s->code_gen_ptr = buf1; 817 s->code_gen_buffer = buf1; 818 s->code_buf = buf1; 819 total_size -= prologue_size; 820 s->code_gen_buffer_size = total_size; 821 822 tcg_register_jit(s->code_gen_buffer, total_size); 823 824 #ifdef DEBUG_DISAS 825 if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM)) { 826 qemu_log_lock(); 827 qemu_log("PROLOGUE: [size=%zu]\n", prologue_size); 828 if (s->data_gen_ptr) { 829 size_t code_size = s->data_gen_ptr - buf0; 830 size_t data_size = prologue_size - code_size; 831 size_t i; 832 833 log_disas(buf0, code_size); 834 835 for (i = 0; i < data_size; i += sizeof(tcg_target_ulong)) { 836 if (sizeof(tcg_target_ulong) == 8) { 837 qemu_log("0x%08" PRIxPTR ": .quad 0x%016" PRIx64 "\n", 838 (uintptr_t)s->data_gen_ptr + i, 839 *(uint64_t *)(s->data_gen_ptr + i)); 840 } else { 841 qemu_log("0x%08" PRIxPTR ": .long 0x%08x\n", 842 (uintptr_t)s->data_gen_ptr + i, 843 *(uint32_t *)(s->data_gen_ptr + i)); 844 } 845 } 846 } else { 847 log_disas(buf0, prologue_size); 848 } 849 qemu_log("\n"); 850 qemu_log_flush(); 851 qemu_log_unlock(); 852 } 853 #endif 854 855 /* Assert that goto_ptr is implemented completely. */ 856 if (TCG_TARGET_HAS_goto_ptr) { 857 tcg_debug_assert(s->code_gen_epilogue != NULL); 858 } 859 } 860 861 void tcg_func_start(TCGContext *s) 862 { 863 tcg_pool_reset(s); 864 s->nb_temps = s->nb_globals; 865 866 /* No temps have been previously allocated for size or locality. */ 867 memset(s->free_temps, 0, sizeof(s->free_temps)); 868 869 s->nb_labels = 0; 870 s->current_frame_offset = s->frame_start; 871 872 #ifdef CONFIG_DEBUG_TCG 873 s->goto_tb_issue_mask = 0; 874 #endif 875 876 QTAILQ_INIT(&s->ops); 877 QTAILQ_INIT(&s->free_ops); 878 } 879 880 static inline TCGTemp *tcg_temp_alloc(TCGContext *s) 881 { 882 int n = s->nb_temps++; 883 tcg_debug_assert(n < TCG_MAX_TEMPS); 884 return memset(&s->temps[n], 0, sizeof(TCGTemp)); 885 } 886 887 static inline TCGTemp *tcg_global_alloc(TCGContext *s) 888 { 889 TCGTemp *ts; 890 891 tcg_debug_assert(s->nb_globals == s->nb_temps); 892 s->nb_globals++; 893 ts = tcg_temp_alloc(s); 894 ts->temp_global = 1; 895 896 return ts; 897 } 898 899 static TCGTemp *tcg_global_reg_new_internal(TCGContext *s, TCGType type, 900 TCGReg reg, const char *name) 901 { 902 TCGTemp *ts; 903 904 if (TCG_TARGET_REG_BITS == 32 && type != TCG_TYPE_I32) { 905 tcg_abort(); 906 } 907 908 ts = tcg_global_alloc(s); 909 ts->base_type = type; 910 ts->type = type; 911 ts->fixed_reg = 1; 912 ts->reg = reg; 913 ts->name = name; 914 tcg_regset_set_reg(s->reserved_regs, reg); 915 916 return ts; 917 } 918 919 void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size) 920 { 921 s->frame_start = start; 922 s->frame_end = start + size; 923 s->frame_temp 924 = tcg_global_reg_new_internal(s, TCG_TYPE_PTR, reg, "_frame"); 925 } 926 927 TCGTemp *tcg_global_mem_new_internal(TCGType type, TCGv_ptr base, 928 intptr_t offset, const char *name) 929 { 930 TCGContext *s = tcg_ctx; 931 TCGTemp *base_ts = tcgv_ptr_temp(base); 932 TCGTemp *ts = tcg_global_alloc(s); 933 int indirect_reg = 0, bigendian = 0; 934 #ifdef HOST_WORDS_BIGENDIAN 935 bigendian = 1; 936 #endif 937 938 if (!base_ts->fixed_reg) { 939 /* We do not support double-indirect registers. */ 940 tcg_debug_assert(!base_ts->indirect_reg); 941 base_ts->indirect_base = 1; 942 s->nb_indirects += (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64 943 ? 2 : 1); 944 indirect_reg = 1; 945 } 946 947 if (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64) { 948 TCGTemp *ts2 = tcg_global_alloc(s); 949 char buf[64]; 950 951 ts->base_type = TCG_TYPE_I64; 952 ts->type = TCG_TYPE_I32; 953 ts->indirect_reg = indirect_reg; 954 ts->mem_allocated = 1; 955 ts->mem_base = base_ts; 956 ts->mem_offset = offset + bigendian * 4; 957 pstrcpy(buf, sizeof(buf), name); 958 pstrcat(buf, sizeof(buf), "_0"); 959 ts->name = strdup(buf); 960 961 tcg_debug_assert(ts2 == ts + 1); 962 ts2->base_type = TCG_TYPE_I64; 963 ts2->type = TCG_TYPE_I32; 964 ts2->indirect_reg = indirect_reg; 965 ts2->mem_allocated = 1; 966 ts2->mem_base = base_ts; 967 ts2->mem_offset = offset + (1 - bigendian) * 4; 968 pstrcpy(buf, sizeof(buf), name); 969 pstrcat(buf, sizeof(buf), "_1"); 970 ts2->name = strdup(buf); 971 } else { 972 ts->base_type = type; 973 ts->type = type; 974 ts->indirect_reg = indirect_reg; 975 ts->mem_allocated = 1; 976 ts->mem_base = base_ts; 977 ts->mem_offset = offset; 978 ts->name = name; 979 } 980 return ts; 981 } 982 983 static TCGTemp *tcg_temp_new_internal(TCGType type, int temp_local) 984 { 985 TCGContext *s = tcg_ctx; 986 TCGTemp *ts; 987 int idx, k; 988 989 k = type + (temp_local ? TCG_TYPE_COUNT : 0); 990 idx = find_first_bit(s->free_temps[k].l, TCG_MAX_TEMPS); 991 if (idx < TCG_MAX_TEMPS) { 992 /* There is already an available temp with the right type. */ 993 clear_bit(idx, s->free_temps[k].l); 994 995 ts = &s->temps[idx]; 996 ts->temp_allocated = 1; 997 tcg_debug_assert(ts->base_type == type); 998 tcg_debug_assert(ts->temp_local == temp_local); 999 } else { 1000 ts = tcg_temp_alloc(s); 1001 if (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64) { 1002 TCGTemp *ts2 = tcg_temp_alloc(s); 1003 1004 ts->base_type = type; 1005 ts->type = TCG_TYPE_I32; 1006 ts->temp_allocated = 1; 1007 ts->temp_local = temp_local; 1008 1009 tcg_debug_assert(ts2 == ts + 1); 1010 ts2->base_type = TCG_TYPE_I64; 1011 ts2->type = TCG_TYPE_I32; 1012 ts2->temp_allocated = 1; 1013 ts2->temp_local = temp_local; 1014 } else { 1015 ts->base_type = type; 1016 ts->type = type; 1017 ts->temp_allocated = 1; 1018 ts->temp_local = temp_local; 1019 } 1020 } 1021 1022 #if defined(CONFIG_DEBUG_TCG) 1023 s->temps_in_use++; 1024 #endif 1025 return ts; 1026 } 1027 1028 TCGv_i32 tcg_temp_new_internal_i32(int temp_local) 1029 { 1030 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, temp_local); 1031 return temp_tcgv_i32(t); 1032 } 1033 1034 TCGv_i64 tcg_temp_new_internal_i64(int temp_local) 1035 { 1036 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, temp_local); 1037 return temp_tcgv_i64(t); 1038 } 1039 1040 TCGv_vec tcg_temp_new_vec(TCGType type) 1041 { 1042 TCGTemp *t; 1043 1044 #ifdef CONFIG_DEBUG_TCG 1045 switch (type) { 1046 case TCG_TYPE_V64: 1047 assert(TCG_TARGET_HAS_v64); 1048 break; 1049 case TCG_TYPE_V128: 1050 assert(TCG_TARGET_HAS_v128); 1051 break; 1052 case TCG_TYPE_V256: 1053 assert(TCG_TARGET_HAS_v256); 1054 break; 1055 default: 1056 g_assert_not_reached(); 1057 } 1058 #endif 1059 1060 t = tcg_temp_new_internal(type, 0); 1061 return temp_tcgv_vec(t); 1062 } 1063 1064 /* Create a new temp of the same type as an existing temp. */ 1065 TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match) 1066 { 1067 TCGTemp *t = tcgv_vec_temp(match); 1068 1069 tcg_debug_assert(t->temp_allocated != 0); 1070 1071 t = tcg_temp_new_internal(t->base_type, 0); 1072 return temp_tcgv_vec(t); 1073 } 1074 1075 static void tcg_temp_free_internal(TCGTemp *ts) 1076 { 1077 TCGContext *s = tcg_ctx; 1078 int k, idx; 1079 1080 #if defined(CONFIG_DEBUG_TCG) 1081 s->temps_in_use--; 1082 if (s->temps_in_use < 0) { 1083 fprintf(stderr, "More temporaries freed than allocated!\n"); 1084 } 1085 #endif 1086 1087 tcg_debug_assert(ts->temp_global == 0); 1088 tcg_debug_assert(ts->temp_allocated != 0); 1089 ts->temp_allocated = 0; 1090 1091 idx = temp_idx(ts); 1092 k = ts->base_type + (ts->temp_local ? TCG_TYPE_COUNT : 0); 1093 set_bit(idx, s->free_temps[k].l); 1094 } 1095 1096 void tcg_temp_free_i32(TCGv_i32 arg) 1097 { 1098 tcg_temp_free_internal(tcgv_i32_temp(arg)); 1099 } 1100 1101 void tcg_temp_free_i64(TCGv_i64 arg) 1102 { 1103 tcg_temp_free_internal(tcgv_i64_temp(arg)); 1104 } 1105 1106 void tcg_temp_free_vec(TCGv_vec arg) 1107 { 1108 tcg_temp_free_internal(tcgv_vec_temp(arg)); 1109 } 1110 1111 TCGv_i32 tcg_const_i32(int32_t val) 1112 { 1113 TCGv_i32 t0; 1114 t0 = tcg_temp_new_i32(); 1115 tcg_gen_movi_i32(t0, val); 1116 return t0; 1117 } 1118 1119 TCGv_i64 tcg_const_i64(int64_t val) 1120 { 1121 TCGv_i64 t0; 1122 t0 = tcg_temp_new_i64(); 1123 tcg_gen_movi_i64(t0, val); 1124 return t0; 1125 } 1126 1127 TCGv_i32 tcg_const_local_i32(int32_t val) 1128 { 1129 TCGv_i32 t0; 1130 t0 = tcg_temp_local_new_i32(); 1131 tcg_gen_movi_i32(t0, val); 1132 return t0; 1133 } 1134 1135 TCGv_i64 tcg_const_local_i64(int64_t val) 1136 { 1137 TCGv_i64 t0; 1138 t0 = tcg_temp_local_new_i64(); 1139 tcg_gen_movi_i64(t0, val); 1140 return t0; 1141 } 1142 1143 #if defined(CONFIG_DEBUG_TCG) 1144 void tcg_clear_temp_count(void) 1145 { 1146 TCGContext *s = tcg_ctx; 1147 s->temps_in_use = 0; 1148 } 1149 1150 int tcg_check_temp_count(void) 1151 { 1152 TCGContext *s = tcg_ctx; 1153 if (s->temps_in_use) { 1154 /* Clear the count so that we don't give another 1155 * warning immediately next time around. 1156 */ 1157 s->temps_in_use = 0; 1158 return 1; 1159 } 1160 return 0; 1161 } 1162 #endif 1163 1164 /* Return true if OP may appear in the opcode stream. 1165 Test the runtime variable that controls each opcode. */ 1166 bool tcg_op_supported(TCGOpcode op) 1167 { 1168 const bool have_vec 1169 = TCG_TARGET_HAS_v64 | TCG_TARGET_HAS_v128 | TCG_TARGET_HAS_v256; 1170 1171 switch (op) { 1172 case INDEX_op_discard: 1173 case INDEX_op_set_label: 1174 case INDEX_op_call: 1175 case INDEX_op_br: 1176 case INDEX_op_mb: 1177 case INDEX_op_insn_start: 1178 case INDEX_op_exit_tb: 1179 case INDEX_op_goto_tb: 1180 case INDEX_op_qemu_ld_i32: 1181 case INDEX_op_qemu_st_i32: 1182 case INDEX_op_qemu_ld_i64: 1183 case INDEX_op_qemu_st_i64: 1184 return true; 1185 1186 case INDEX_op_goto_ptr: 1187 return TCG_TARGET_HAS_goto_ptr; 1188 1189 case INDEX_op_mov_i32: 1190 case INDEX_op_movi_i32: 1191 case INDEX_op_setcond_i32: 1192 case INDEX_op_brcond_i32: 1193 case INDEX_op_ld8u_i32: 1194 case INDEX_op_ld8s_i32: 1195 case INDEX_op_ld16u_i32: 1196 case INDEX_op_ld16s_i32: 1197 case INDEX_op_ld_i32: 1198 case INDEX_op_st8_i32: 1199 case INDEX_op_st16_i32: 1200 case INDEX_op_st_i32: 1201 case INDEX_op_add_i32: 1202 case INDEX_op_sub_i32: 1203 case INDEX_op_mul_i32: 1204 case INDEX_op_and_i32: 1205 case INDEX_op_or_i32: 1206 case INDEX_op_xor_i32: 1207 case INDEX_op_shl_i32: 1208 case INDEX_op_shr_i32: 1209 case INDEX_op_sar_i32: 1210 return true; 1211 1212 case INDEX_op_movcond_i32: 1213 return TCG_TARGET_HAS_movcond_i32; 1214 case INDEX_op_div_i32: 1215 case INDEX_op_divu_i32: 1216 return TCG_TARGET_HAS_div_i32; 1217 case INDEX_op_rem_i32: 1218 case INDEX_op_remu_i32: 1219 return TCG_TARGET_HAS_rem_i32; 1220 case INDEX_op_div2_i32: 1221 case INDEX_op_divu2_i32: 1222 return TCG_TARGET_HAS_div2_i32; 1223 case INDEX_op_rotl_i32: 1224 case INDEX_op_rotr_i32: 1225 return TCG_TARGET_HAS_rot_i32; 1226 case INDEX_op_deposit_i32: 1227 return TCG_TARGET_HAS_deposit_i32; 1228 case INDEX_op_extract_i32: 1229 return TCG_TARGET_HAS_extract_i32; 1230 case INDEX_op_sextract_i32: 1231 return TCG_TARGET_HAS_sextract_i32; 1232 case INDEX_op_add2_i32: 1233 return TCG_TARGET_HAS_add2_i32; 1234 case INDEX_op_sub2_i32: 1235 return TCG_TARGET_HAS_sub2_i32; 1236 case INDEX_op_mulu2_i32: 1237 return TCG_TARGET_HAS_mulu2_i32; 1238 case INDEX_op_muls2_i32: 1239 return TCG_TARGET_HAS_muls2_i32; 1240 case INDEX_op_muluh_i32: 1241 return TCG_TARGET_HAS_muluh_i32; 1242 case INDEX_op_mulsh_i32: 1243 return TCG_TARGET_HAS_mulsh_i32; 1244 case INDEX_op_ext8s_i32: 1245 return TCG_TARGET_HAS_ext8s_i32; 1246 case INDEX_op_ext16s_i32: 1247 return TCG_TARGET_HAS_ext16s_i32; 1248 case INDEX_op_ext8u_i32: 1249 return TCG_TARGET_HAS_ext8u_i32; 1250 case INDEX_op_ext16u_i32: 1251 return TCG_TARGET_HAS_ext16u_i32; 1252 case INDEX_op_bswap16_i32: 1253 return TCG_TARGET_HAS_bswap16_i32; 1254 case INDEX_op_bswap32_i32: 1255 return TCG_TARGET_HAS_bswap32_i32; 1256 case INDEX_op_not_i32: 1257 return TCG_TARGET_HAS_not_i32; 1258 case INDEX_op_neg_i32: 1259 return TCG_TARGET_HAS_neg_i32; 1260 case INDEX_op_andc_i32: 1261 return TCG_TARGET_HAS_andc_i32; 1262 case INDEX_op_orc_i32: 1263 return TCG_TARGET_HAS_orc_i32; 1264 case INDEX_op_eqv_i32: 1265 return TCG_TARGET_HAS_eqv_i32; 1266 case INDEX_op_nand_i32: 1267 return TCG_TARGET_HAS_nand_i32; 1268 case INDEX_op_nor_i32: 1269 return TCG_TARGET_HAS_nor_i32; 1270 case INDEX_op_clz_i32: 1271 return TCG_TARGET_HAS_clz_i32; 1272 case INDEX_op_ctz_i32: 1273 return TCG_TARGET_HAS_ctz_i32; 1274 case INDEX_op_ctpop_i32: 1275 return TCG_TARGET_HAS_ctpop_i32; 1276 1277 case INDEX_op_brcond2_i32: 1278 case INDEX_op_setcond2_i32: 1279 return TCG_TARGET_REG_BITS == 32; 1280 1281 case INDEX_op_mov_i64: 1282 case INDEX_op_movi_i64: 1283 case INDEX_op_setcond_i64: 1284 case INDEX_op_brcond_i64: 1285 case INDEX_op_ld8u_i64: 1286 case INDEX_op_ld8s_i64: 1287 case INDEX_op_ld16u_i64: 1288 case INDEX_op_ld16s_i64: 1289 case INDEX_op_ld32u_i64: 1290 case INDEX_op_ld32s_i64: 1291 case INDEX_op_ld_i64: 1292 case INDEX_op_st8_i64: 1293 case INDEX_op_st16_i64: 1294 case INDEX_op_st32_i64: 1295 case INDEX_op_st_i64: 1296 case INDEX_op_add_i64: 1297 case INDEX_op_sub_i64: 1298 case INDEX_op_mul_i64: 1299 case INDEX_op_and_i64: 1300 case INDEX_op_or_i64: 1301 case INDEX_op_xor_i64: 1302 case INDEX_op_shl_i64: 1303 case INDEX_op_shr_i64: 1304 case INDEX_op_sar_i64: 1305 case INDEX_op_ext_i32_i64: 1306 case INDEX_op_extu_i32_i64: 1307 return TCG_TARGET_REG_BITS == 64; 1308 1309 case INDEX_op_movcond_i64: 1310 return TCG_TARGET_HAS_movcond_i64; 1311 case INDEX_op_div_i64: 1312 case INDEX_op_divu_i64: 1313 return TCG_TARGET_HAS_div_i64; 1314 case INDEX_op_rem_i64: 1315 case INDEX_op_remu_i64: 1316 return TCG_TARGET_HAS_rem_i64; 1317 case INDEX_op_div2_i64: 1318 case INDEX_op_divu2_i64: 1319 return TCG_TARGET_HAS_div2_i64; 1320 case INDEX_op_rotl_i64: 1321 case INDEX_op_rotr_i64: 1322 return TCG_TARGET_HAS_rot_i64; 1323 case INDEX_op_deposit_i64: 1324 return TCG_TARGET_HAS_deposit_i64; 1325 case INDEX_op_extract_i64: 1326 return TCG_TARGET_HAS_extract_i64; 1327 case INDEX_op_sextract_i64: 1328 return TCG_TARGET_HAS_sextract_i64; 1329 case INDEX_op_extrl_i64_i32: 1330 return TCG_TARGET_HAS_extrl_i64_i32; 1331 case INDEX_op_extrh_i64_i32: 1332 return TCG_TARGET_HAS_extrh_i64_i32; 1333 case INDEX_op_ext8s_i64: 1334 return TCG_TARGET_HAS_ext8s_i64; 1335 case INDEX_op_ext16s_i64: 1336 return TCG_TARGET_HAS_ext16s_i64; 1337 case INDEX_op_ext32s_i64: 1338 return TCG_TARGET_HAS_ext32s_i64; 1339 case INDEX_op_ext8u_i64: 1340 return TCG_TARGET_HAS_ext8u_i64; 1341 case INDEX_op_ext16u_i64: 1342 return TCG_TARGET_HAS_ext16u_i64; 1343 case INDEX_op_ext32u_i64: 1344 return TCG_TARGET_HAS_ext32u_i64; 1345 case INDEX_op_bswap16_i64: 1346 return TCG_TARGET_HAS_bswap16_i64; 1347 case INDEX_op_bswap32_i64: 1348 return TCG_TARGET_HAS_bswap32_i64; 1349 case INDEX_op_bswap64_i64: 1350 return TCG_TARGET_HAS_bswap64_i64; 1351 case INDEX_op_not_i64: 1352 return TCG_TARGET_HAS_not_i64; 1353 case INDEX_op_neg_i64: 1354 return TCG_TARGET_HAS_neg_i64; 1355 case INDEX_op_andc_i64: 1356 return TCG_TARGET_HAS_andc_i64; 1357 case INDEX_op_orc_i64: 1358 return TCG_TARGET_HAS_orc_i64; 1359 case INDEX_op_eqv_i64: 1360 return TCG_TARGET_HAS_eqv_i64; 1361 case INDEX_op_nand_i64: 1362 return TCG_TARGET_HAS_nand_i64; 1363 case INDEX_op_nor_i64: 1364 return TCG_TARGET_HAS_nor_i64; 1365 case INDEX_op_clz_i64: 1366 return TCG_TARGET_HAS_clz_i64; 1367 case INDEX_op_ctz_i64: 1368 return TCG_TARGET_HAS_ctz_i64; 1369 case INDEX_op_ctpop_i64: 1370 return TCG_TARGET_HAS_ctpop_i64; 1371 case INDEX_op_add2_i64: 1372 return TCG_TARGET_HAS_add2_i64; 1373 case INDEX_op_sub2_i64: 1374 return TCG_TARGET_HAS_sub2_i64; 1375 case INDEX_op_mulu2_i64: 1376 return TCG_TARGET_HAS_mulu2_i64; 1377 case INDEX_op_muls2_i64: 1378 return TCG_TARGET_HAS_muls2_i64; 1379 case INDEX_op_muluh_i64: 1380 return TCG_TARGET_HAS_muluh_i64; 1381 case INDEX_op_mulsh_i64: 1382 return TCG_TARGET_HAS_mulsh_i64; 1383 1384 case INDEX_op_mov_vec: 1385 case INDEX_op_dup_vec: 1386 case INDEX_op_dupi_vec: 1387 case INDEX_op_ld_vec: 1388 case INDEX_op_st_vec: 1389 case INDEX_op_add_vec: 1390 case INDEX_op_sub_vec: 1391 case INDEX_op_and_vec: 1392 case INDEX_op_or_vec: 1393 case INDEX_op_xor_vec: 1394 return have_vec; 1395 case INDEX_op_dup2_vec: 1396 return have_vec && TCG_TARGET_REG_BITS == 32; 1397 case INDEX_op_not_vec: 1398 return have_vec && TCG_TARGET_HAS_not_vec; 1399 case INDEX_op_neg_vec: 1400 return have_vec && TCG_TARGET_HAS_neg_vec; 1401 case INDEX_op_andc_vec: 1402 return have_vec && TCG_TARGET_HAS_andc_vec; 1403 case INDEX_op_orc_vec: 1404 return have_vec && TCG_TARGET_HAS_orc_vec; 1405 case INDEX_op_shli_vec: 1406 case INDEX_op_shri_vec: 1407 case INDEX_op_sari_vec: 1408 return have_vec && TCG_TARGET_HAS_shi_vec; 1409 case INDEX_op_shls_vec: 1410 case INDEX_op_shrs_vec: 1411 case INDEX_op_sars_vec: 1412 return have_vec && TCG_TARGET_HAS_shs_vec; 1413 case INDEX_op_shlv_vec: 1414 case INDEX_op_shrv_vec: 1415 case INDEX_op_sarv_vec: 1416 return have_vec && TCG_TARGET_HAS_shv_vec; 1417 1418 default: 1419 tcg_debug_assert(op > INDEX_op_last_generic && op < NB_OPS); 1420 return true; 1421 } 1422 } 1423 1424 /* Note: we convert the 64 bit args to 32 bit and do some alignment 1425 and endian swap. Maybe it would be better to do the alignment 1426 and endian swap in tcg_reg_alloc_call(). */ 1427 void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) 1428 { 1429 int i, real_args, nb_rets, pi; 1430 unsigned sizemask, flags; 1431 TCGHelperInfo *info; 1432 TCGOp *op; 1433 1434 info = g_hash_table_lookup(helper_table, (gpointer)func); 1435 flags = info->flags; 1436 sizemask = info->sizemask; 1437 1438 #if defined(__sparc__) && !defined(__arch64__) \ 1439 && !defined(CONFIG_TCG_INTERPRETER) 1440 /* We have 64-bit values in one register, but need to pass as two 1441 separate parameters. Split them. */ 1442 int orig_sizemask = sizemask; 1443 int orig_nargs = nargs; 1444 TCGv_i64 retl, reth; 1445 TCGTemp *split_args[MAX_OPC_PARAM]; 1446 1447 retl = NULL; 1448 reth = NULL; 1449 if (sizemask != 0) { 1450 for (i = real_args = 0; i < nargs; ++i) { 1451 int is_64bit = sizemask & (1 << (i+1)*2); 1452 if (is_64bit) { 1453 TCGv_i64 orig = temp_tcgv_i64(args[i]); 1454 TCGv_i32 h = tcg_temp_new_i32(); 1455 TCGv_i32 l = tcg_temp_new_i32(); 1456 tcg_gen_extr_i64_i32(l, h, orig); 1457 split_args[real_args++] = tcgv_i32_temp(h); 1458 split_args[real_args++] = tcgv_i32_temp(l); 1459 } else { 1460 split_args[real_args++] = args[i]; 1461 } 1462 } 1463 nargs = real_args; 1464 args = split_args; 1465 sizemask = 0; 1466 } 1467 #elif defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS == 64 1468 for (i = 0; i < nargs; ++i) { 1469 int is_64bit = sizemask & (1 << (i+1)*2); 1470 int is_signed = sizemask & (2 << (i+1)*2); 1471 if (!is_64bit) { 1472 TCGv_i64 temp = tcg_temp_new_i64(); 1473 TCGv_i64 orig = temp_tcgv_i64(args[i]); 1474 if (is_signed) { 1475 tcg_gen_ext32s_i64(temp, orig); 1476 } else { 1477 tcg_gen_ext32u_i64(temp, orig); 1478 } 1479 args[i] = tcgv_i64_temp(temp); 1480 } 1481 } 1482 #endif /* TCG_TARGET_EXTEND_ARGS */ 1483 1484 op = tcg_emit_op(INDEX_op_call); 1485 1486 pi = 0; 1487 if (ret != NULL) { 1488 #if defined(__sparc__) && !defined(__arch64__) \ 1489 && !defined(CONFIG_TCG_INTERPRETER) 1490 if (orig_sizemask & 1) { 1491 /* The 32-bit ABI is going to return the 64-bit value in 1492 the %o0/%o1 register pair. Prepare for this by using 1493 two return temporaries, and reassemble below. */ 1494 retl = tcg_temp_new_i64(); 1495 reth = tcg_temp_new_i64(); 1496 op->args[pi++] = tcgv_i64_arg(reth); 1497 op->args[pi++] = tcgv_i64_arg(retl); 1498 nb_rets = 2; 1499 } else { 1500 op->args[pi++] = temp_arg(ret); 1501 nb_rets = 1; 1502 } 1503 #else 1504 if (TCG_TARGET_REG_BITS < 64 && (sizemask & 1)) { 1505 #ifdef HOST_WORDS_BIGENDIAN 1506 op->args[pi++] = temp_arg(ret + 1); 1507 op->args[pi++] = temp_arg(ret); 1508 #else 1509 op->args[pi++] = temp_arg(ret); 1510 op->args[pi++] = temp_arg(ret + 1); 1511 #endif 1512 nb_rets = 2; 1513 } else { 1514 op->args[pi++] = temp_arg(ret); 1515 nb_rets = 1; 1516 } 1517 #endif 1518 } else { 1519 nb_rets = 0; 1520 } 1521 TCGOP_CALLO(op) = nb_rets; 1522 1523 real_args = 0; 1524 for (i = 0; i < nargs; i++) { 1525 int is_64bit = sizemask & (1 << (i+1)*2); 1526 if (TCG_TARGET_REG_BITS < 64 && is_64bit) { 1527 #ifdef TCG_TARGET_CALL_ALIGN_ARGS 1528 /* some targets want aligned 64 bit args */ 1529 if (real_args & 1) { 1530 op->args[pi++] = TCG_CALL_DUMMY_ARG; 1531 real_args++; 1532 } 1533 #endif 1534 /* If stack grows up, then we will be placing successive 1535 arguments at lower addresses, which means we need to 1536 reverse the order compared to how we would normally 1537 treat either big or little-endian. For those arguments 1538 that will wind up in registers, this still works for 1539 HPPA (the only current STACK_GROWSUP target) since the 1540 argument registers are *also* allocated in decreasing 1541 order. If another such target is added, this logic may 1542 have to get more complicated to differentiate between 1543 stack arguments and register arguments. */ 1544 #if defined(HOST_WORDS_BIGENDIAN) != defined(TCG_TARGET_STACK_GROWSUP) 1545 op->args[pi++] = temp_arg(args[i] + 1); 1546 op->args[pi++] = temp_arg(args[i]); 1547 #else 1548 op->args[pi++] = temp_arg(args[i]); 1549 op->args[pi++] = temp_arg(args[i] + 1); 1550 #endif 1551 real_args += 2; 1552 continue; 1553 } 1554 1555 op->args[pi++] = temp_arg(args[i]); 1556 real_args++; 1557 } 1558 op->args[pi++] = (uintptr_t)func; 1559 op->args[pi++] = flags; 1560 TCGOP_CALLI(op) = real_args; 1561 1562 /* Make sure the fields didn't overflow. */ 1563 tcg_debug_assert(TCGOP_CALLI(op) == real_args); 1564 tcg_debug_assert(pi <= ARRAY_SIZE(op->args)); 1565 1566 #if defined(__sparc__) && !defined(__arch64__) \ 1567 && !defined(CONFIG_TCG_INTERPRETER) 1568 /* Free all of the parts we allocated above. */ 1569 for (i = real_args = 0; i < orig_nargs; ++i) { 1570 int is_64bit = orig_sizemask & (1 << (i+1)*2); 1571 if (is_64bit) { 1572 tcg_temp_free_internal(args[real_args++]); 1573 tcg_temp_free_internal(args[real_args++]); 1574 } else { 1575 real_args++; 1576 } 1577 } 1578 if (orig_sizemask & 1) { 1579 /* The 32-bit ABI returned two 32-bit pieces. Re-assemble them. 1580 Note that describing these as TCGv_i64 eliminates an unnecessary 1581 zero-extension that tcg_gen_concat_i32_i64 would create. */ 1582 tcg_gen_concat32_i64(temp_tcgv_i64(ret), retl, reth); 1583 tcg_temp_free_i64(retl); 1584 tcg_temp_free_i64(reth); 1585 } 1586 #elif defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS == 64 1587 for (i = 0; i < nargs; ++i) { 1588 int is_64bit = sizemask & (1 << (i+1)*2); 1589 if (!is_64bit) { 1590 tcg_temp_free_internal(args[i]); 1591 } 1592 } 1593 #endif /* TCG_TARGET_EXTEND_ARGS */ 1594 } 1595 1596 static void tcg_reg_alloc_start(TCGContext *s) 1597 { 1598 int i, n; 1599 TCGTemp *ts; 1600 1601 for (i = 0, n = s->nb_globals; i < n; i++) { 1602 ts = &s->temps[i]; 1603 ts->val_type = (ts->fixed_reg ? TEMP_VAL_REG : TEMP_VAL_MEM); 1604 } 1605 for (n = s->nb_temps; i < n; i++) { 1606 ts = &s->temps[i]; 1607 ts->val_type = (ts->temp_local ? TEMP_VAL_MEM : TEMP_VAL_DEAD); 1608 ts->mem_allocated = 0; 1609 ts->fixed_reg = 0; 1610 } 1611 1612 memset(s->reg_to_temp, 0, sizeof(s->reg_to_temp)); 1613 } 1614 1615 static char *tcg_get_arg_str_ptr(TCGContext *s, char *buf, int buf_size, 1616 TCGTemp *ts) 1617 { 1618 int idx = temp_idx(ts); 1619 1620 if (ts->temp_global) { 1621 pstrcpy(buf, buf_size, ts->name); 1622 } else if (ts->temp_local) { 1623 snprintf(buf, buf_size, "loc%d", idx - s->nb_globals); 1624 } else { 1625 snprintf(buf, buf_size, "tmp%d", idx - s->nb_globals); 1626 } 1627 return buf; 1628 } 1629 1630 static char *tcg_get_arg_str(TCGContext *s, char *buf, 1631 int buf_size, TCGArg arg) 1632 { 1633 return tcg_get_arg_str_ptr(s, buf, buf_size, arg_temp(arg)); 1634 } 1635 1636 /* Find helper name. */ 1637 static inline const char *tcg_find_helper(TCGContext *s, uintptr_t val) 1638 { 1639 const char *ret = NULL; 1640 if (helper_table) { 1641 TCGHelperInfo *info = g_hash_table_lookup(helper_table, (gpointer)val); 1642 if (info) { 1643 ret = info->name; 1644 } 1645 } 1646 return ret; 1647 } 1648 1649 static const char * const cond_name[] = 1650 { 1651 [TCG_COND_NEVER] = "never", 1652 [TCG_COND_ALWAYS] = "always", 1653 [TCG_COND_EQ] = "eq", 1654 [TCG_COND_NE] = "ne", 1655 [TCG_COND_LT] = "lt", 1656 [TCG_COND_GE] = "ge", 1657 [TCG_COND_LE] = "le", 1658 [TCG_COND_GT] = "gt", 1659 [TCG_COND_LTU] = "ltu", 1660 [TCG_COND_GEU] = "geu", 1661 [TCG_COND_LEU] = "leu", 1662 [TCG_COND_GTU] = "gtu" 1663 }; 1664 1665 static const char * const ldst_name[] = 1666 { 1667 [MO_UB] = "ub", 1668 [MO_SB] = "sb", 1669 [MO_LEUW] = "leuw", 1670 [MO_LESW] = "lesw", 1671 [MO_LEUL] = "leul", 1672 [MO_LESL] = "lesl", 1673 [MO_LEQ] = "leq", 1674 [MO_BEUW] = "beuw", 1675 [MO_BESW] = "besw", 1676 [MO_BEUL] = "beul", 1677 [MO_BESL] = "besl", 1678 [MO_BEQ] = "beq", 1679 }; 1680 1681 static const char * const alignment_name[(MO_AMASK >> MO_ASHIFT) + 1] = { 1682 #ifdef ALIGNED_ONLY 1683 [MO_UNALN >> MO_ASHIFT] = "un+", 1684 [MO_ALIGN >> MO_ASHIFT] = "", 1685 #else 1686 [MO_UNALN >> MO_ASHIFT] = "", 1687 [MO_ALIGN >> MO_ASHIFT] = "al+", 1688 #endif 1689 [MO_ALIGN_2 >> MO_ASHIFT] = "al2+", 1690 [MO_ALIGN_4 >> MO_ASHIFT] = "al4+", 1691 [MO_ALIGN_8 >> MO_ASHIFT] = "al8+", 1692 [MO_ALIGN_16 >> MO_ASHIFT] = "al16+", 1693 [MO_ALIGN_32 >> MO_ASHIFT] = "al32+", 1694 [MO_ALIGN_64 >> MO_ASHIFT] = "al64+", 1695 }; 1696 1697 void tcg_dump_ops(TCGContext *s) 1698 { 1699 char buf[128]; 1700 TCGOp *op; 1701 1702 QTAILQ_FOREACH(op, &s->ops, link) { 1703 int i, k, nb_oargs, nb_iargs, nb_cargs; 1704 const TCGOpDef *def; 1705 TCGOpcode c; 1706 int col = 0; 1707 1708 c = op->opc; 1709 def = &tcg_op_defs[c]; 1710 1711 if (c == INDEX_op_insn_start) { 1712 col += qemu_log("\n ----"); 1713 1714 for (i = 0; i < TARGET_INSN_START_WORDS; ++i) { 1715 target_ulong a; 1716 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS 1717 a = deposit64(op->args[i * 2], 32, 32, op->args[i * 2 + 1]); 1718 #else 1719 a = op->args[i]; 1720 #endif 1721 col += qemu_log(" " TARGET_FMT_lx, a); 1722 } 1723 } else if (c == INDEX_op_call) { 1724 /* variable number of arguments */ 1725 nb_oargs = TCGOP_CALLO(op); 1726 nb_iargs = TCGOP_CALLI(op); 1727 nb_cargs = def->nb_cargs; 1728 1729 /* function name, flags, out args */ 1730 col += qemu_log(" %s %s,$0x%" TCG_PRIlx ",$%d", def->name, 1731 tcg_find_helper(s, op->args[nb_oargs + nb_iargs]), 1732 op->args[nb_oargs + nb_iargs + 1], nb_oargs); 1733 for (i = 0; i < nb_oargs; i++) { 1734 col += qemu_log(",%s", tcg_get_arg_str(s, buf, sizeof(buf), 1735 op->args[i])); 1736 } 1737 for (i = 0; i < nb_iargs; i++) { 1738 TCGArg arg = op->args[nb_oargs + i]; 1739 const char *t = "<dummy>"; 1740 if (arg != TCG_CALL_DUMMY_ARG) { 1741 t = tcg_get_arg_str(s, buf, sizeof(buf), arg); 1742 } 1743 col += qemu_log(",%s", t); 1744 } 1745 } else { 1746 col += qemu_log(" %s ", def->name); 1747 1748 nb_oargs = def->nb_oargs; 1749 nb_iargs = def->nb_iargs; 1750 nb_cargs = def->nb_cargs; 1751 1752 if (def->flags & TCG_OPF_VECTOR) { 1753 col += qemu_log("v%d,e%d,", 64 << TCGOP_VECL(op), 1754 8 << TCGOP_VECE(op)); 1755 } 1756 1757 k = 0; 1758 for (i = 0; i < nb_oargs; i++) { 1759 if (k != 0) { 1760 col += qemu_log(","); 1761 } 1762 col += qemu_log("%s", tcg_get_arg_str(s, buf, sizeof(buf), 1763 op->args[k++])); 1764 } 1765 for (i = 0; i < nb_iargs; i++) { 1766 if (k != 0) { 1767 col += qemu_log(","); 1768 } 1769 col += qemu_log("%s", tcg_get_arg_str(s, buf, sizeof(buf), 1770 op->args[k++])); 1771 } 1772 switch (c) { 1773 case INDEX_op_brcond_i32: 1774 case INDEX_op_setcond_i32: 1775 case INDEX_op_movcond_i32: 1776 case INDEX_op_brcond2_i32: 1777 case INDEX_op_setcond2_i32: 1778 case INDEX_op_brcond_i64: 1779 case INDEX_op_setcond_i64: 1780 case INDEX_op_movcond_i64: 1781 if (op->args[k] < ARRAY_SIZE(cond_name) 1782 && cond_name[op->args[k]]) { 1783 col += qemu_log(",%s", cond_name[op->args[k++]]); 1784 } else { 1785 col += qemu_log(",$0x%" TCG_PRIlx, op->args[k++]); 1786 } 1787 i = 1; 1788 break; 1789 case INDEX_op_qemu_ld_i32: 1790 case INDEX_op_qemu_st_i32: 1791 case INDEX_op_qemu_ld_i64: 1792 case INDEX_op_qemu_st_i64: 1793 { 1794 TCGMemOpIdx oi = op->args[k++]; 1795 TCGMemOp op = get_memop(oi); 1796 unsigned ix = get_mmuidx(oi); 1797 1798 if (op & ~(MO_AMASK | MO_BSWAP | MO_SSIZE)) { 1799 col += qemu_log(",$0x%x,%u", op, ix); 1800 } else { 1801 const char *s_al, *s_op; 1802 s_al = alignment_name[(op & MO_AMASK) >> MO_ASHIFT]; 1803 s_op = ldst_name[op & (MO_BSWAP | MO_SSIZE)]; 1804 col += qemu_log(",%s%s,%u", s_al, s_op, ix); 1805 } 1806 i = 1; 1807 } 1808 break; 1809 default: 1810 i = 0; 1811 break; 1812 } 1813 switch (c) { 1814 case INDEX_op_set_label: 1815 case INDEX_op_br: 1816 case INDEX_op_brcond_i32: 1817 case INDEX_op_brcond_i64: 1818 case INDEX_op_brcond2_i32: 1819 col += qemu_log("%s$L%d", k ? "," : "", 1820 arg_label(op->args[k])->id); 1821 i++, k++; 1822 break; 1823 default: 1824 break; 1825 } 1826 for (; i < nb_cargs; i++, k++) { 1827 col += qemu_log("%s$0x%" TCG_PRIlx, k ? "," : "", op->args[k]); 1828 } 1829 } 1830 if (op->life) { 1831 unsigned life = op->life; 1832 1833 for (; col < 48; ++col) { 1834 putc(' ', qemu_logfile); 1835 } 1836 1837 if (life & (SYNC_ARG * 3)) { 1838 qemu_log(" sync:"); 1839 for (i = 0; i < 2; ++i) { 1840 if (life & (SYNC_ARG << i)) { 1841 qemu_log(" %d", i); 1842 } 1843 } 1844 } 1845 life /= DEAD_ARG; 1846 if (life) { 1847 qemu_log(" dead:"); 1848 for (i = 0; life; ++i, life >>= 1) { 1849 if (life & 1) { 1850 qemu_log(" %d", i); 1851 } 1852 } 1853 } 1854 } 1855 qemu_log("\n"); 1856 } 1857 } 1858 1859 /* we give more priority to constraints with less registers */ 1860 static int get_constraint_priority(const TCGOpDef *def, int k) 1861 { 1862 const TCGArgConstraint *arg_ct; 1863 1864 int i, n; 1865 arg_ct = &def->args_ct[k]; 1866 if (arg_ct->ct & TCG_CT_ALIAS) { 1867 /* an alias is equivalent to a single register */ 1868 n = 1; 1869 } else { 1870 if (!(arg_ct->ct & TCG_CT_REG)) 1871 return 0; 1872 n = 0; 1873 for(i = 0; i < TCG_TARGET_NB_REGS; i++) { 1874 if (tcg_regset_test_reg(arg_ct->u.regs, i)) 1875 n++; 1876 } 1877 } 1878 return TCG_TARGET_NB_REGS - n + 1; 1879 } 1880 1881 /* sort from highest priority to lowest */ 1882 static void sort_constraints(TCGOpDef *def, int start, int n) 1883 { 1884 int i, j, p1, p2, tmp; 1885 1886 for(i = 0; i < n; i++) 1887 def->sorted_args[start + i] = start + i; 1888 if (n <= 1) 1889 return; 1890 for(i = 0; i < n - 1; i++) { 1891 for(j = i + 1; j < n; j++) { 1892 p1 = get_constraint_priority(def, def->sorted_args[start + i]); 1893 p2 = get_constraint_priority(def, def->sorted_args[start + j]); 1894 if (p1 < p2) { 1895 tmp = def->sorted_args[start + i]; 1896 def->sorted_args[start + i] = def->sorted_args[start + j]; 1897 def->sorted_args[start + j] = tmp; 1898 } 1899 } 1900 } 1901 } 1902 1903 static void process_op_defs(TCGContext *s) 1904 { 1905 TCGOpcode op; 1906 1907 for (op = 0; op < NB_OPS; op++) { 1908 TCGOpDef *def = &tcg_op_defs[op]; 1909 const TCGTargetOpDef *tdefs; 1910 TCGType type; 1911 int i, nb_args; 1912 1913 if (def->flags & TCG_OPF_NOT_PRESENT) { 1914 continue; 1915 } 1916 1917 nb_args = def->nb_iargs + def->nb_oargs; 1918 if (nb_args == 0) { 1919 continue; 1920 } 1921 1922 tdefs = tcg_target_op_def(op); 1923 /* Missing TCGTargetOpDef entry. */ 1924 tcg_debug_assert(tdefs != NULL); 1925 1926 type = (def->flags & TCG_OPF_64BIT ? TCG_TYPE_I64 : TCG_TYPE_I32); 1927 for (i = 0; i < nb_args; i++) { 1928 const char *ct_str = tdefs->args_ct_str[i]; 1929 /* Incomplete TCGTargetOpDef entry. */ 1930 tcg_debug_assert(ct_str != NULL); 1931 1932 def->args_ct[i].u.regs = 0; 1933 def->args_ct[i].ct = 0; 1934 while (*ct_str != '\0') { 1935 switch(*ct_str) { 1936 case '0' ... '9': 1937 { 1938 int oarg = *ct_str - '0'; 1939 tcg_debug_assert(ct_str == tdefs->args_ct_str[i]); 1940 tcg_debug_assert(oarg < def->nb_oargs); 1941 tcg_debug_assert(def->args_ct[oarg].ct & TCG_CT_REG); 1942 /* TCG_CT_ALIAS is for the output arguments. 1943 The input is tagged with TCG_CT_IALIAS. */ 1944 def->args_ct[i] = def->args_ct[oarg]; 1945 def->args_ct[oarg].ct |= TCG_CT_ALIAS; 1946 def->args_ct[oarg].alias_index = i; 1947 def->args_ct[i].ct |= TCG_CT_IALIAS; 1948 def->args_ct[i].alias_index = oarg; 1949 } 1950 ct_str++; 1951 break; 1952 case '&': 1953 def->args_ct[i].ct |= TCG_CT_NEWREG; 1954 ct_str++; 1955 break; 1956 case 'i': 1957 def->args_ct[i].ct |= TCG_CT_CONST; 1958 ct_str++; 1959 break; 1960 default: 1961 ct_str = target_parse_constraint(&def->args_ct[i], 1962 ct_str, type); 1963 /* Typo in TCGTargetOpDef constraint. */ 1964 tcg_debug_assert(ct_str != NULL); 1965 } 1966 } 1967 } 1968 1969 /* TCGTargetOpDef entry with too much information? */ 1970 tcg_debug_assert(i == TCG_MAX_OP_ARGS || tdefs->args_ct_str[i] == NULL); 1971 1972 /* sort the constraints (XXX: this is just an heuristic) */ 1973 sort_constraints(def, 0, def->nb_oargs); 1974 sort_constraints(def, def->nb_oargs, def->nb_iargs); 1975 } 1976 } 1977 1978 void tcg_op_remove(TCGContext *s, TCGOp *op) 1979 { 1980 QTAILQ_REMOVE(&s->ops, op, link); 1981 QTAILQ_INSERT_TAIL(&s->free_ops, op, link); 1982 1983 #ifdef CONFIG_PROFILER 1984 atomic_set(&s->prof.del_op_count, s->prof.del_op_count + 1); 1985 #endif 1986 } 1987 1988 static TCGOp *tcg_op_alloc(TCGOpcode opc) 1989 { 1990 TCGContext *s = tcg_ctx; 1991 TCGOp *op; 1992 1993 if (likely(QTAILQ_EMPTY(&s->free_ops))) { 1994 op = tcg_malloc(sizeof(TCGOp)); 1995 } else { 1996 op = QTAILQ_FIRST(&s->free_ops); 1997 QTAILQ_REMOVE(&s->free_ops, op, link); 1998 } 1999 memset(op, 0, offsetof(TCGOp, link)); 2000 op->opc = opc; 2001 2002 return op; 2003 } 2004 2005 TCGOp *tcg_emit_op(TCGOpcode opc) 2006 { 2007 TCGOp *op = tcg_op_alloc(opc); 2008 QTAILQ_INSERT_TAIL(&tcg_ctx->ops, op, link); 2009 return op; 2010 } 2011 2012 TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *old_op, 2013 TCGOpcode opc, int nargs) 2014 { 2015 TCGOp *new_op = tcg_op_alloc(opc); 2016 QTAILQ_INSERT_BEFORE(old_op, new_op, link); 2017 return new_op; 2018 } 2019 2020 TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *old_op, 2021 TCGOpcode opc, int nargs) 2022 { 2023 TCGOp *new_op = tcg_op_alloc(opc); 2024 QTAILQ_INSERT_AFTER(&s->ops, old_op, new_op, link); 2025 return new_op; 2026 } 2027 2028 #define TS_DEAD 1 2029 #define TS_MEM 2 2030 2031 #define IS_DEAD_ARG(n) (arg_life & (DEAD_ARG << (n))) 2032 #define NEED_SYNC_ARG(n) (arg_life & (SYNC_ARG << (n))) 2033 2034 /* liveness analysis: end of function: all temps are dead, and globals 2035 should be in memory. */ 2036 static void tcg_la_func_end(TCGContext *s) 2037 { 2038 int ng = s->nb_globals; 2039 int nt = s->nb_temps; 2040 int i; 2041 2042 for (i = 0; i < ng; ++i) { 2043 s->temps[i].state = TS_DEAD | TS_MEM; 2044 } 2045 for (i = ng; i < nt; ++i) { 2046 s->temps[i].state = TS_DEAD; 2047 } 2048 } 2049 2050 /* liveness analysis: end of basic block: all temps are dead, globals 2051 and local temps should be in memory. */ 2052 static void tcg_la_bb_end(TCGContext *s) 2053 { 2054 int ng = s->nb_globals; 2055 int nt = s->nb_temps; 2056 int i; 2057 2058 for (i = 0; i < ng; ++i) { 2059 s->temps[i].state = TS_DEAD | TS_MEM; 2060 } 2061 for (i = ng; i < nt; ++i) { 2062 s->temps[i].state = (s->temps[i].temp_local 2063 ? TS_DEAD | TS_MEM 2064 : TS_DEAD); 2065 } 2066 } 2067 2068 /* Liveness analysis : update the opc_arg_life array to tell if a 2069 given input arguments is dead. Instructions updating dead 2070 temporaries are removed. */ 2071 static void liveness_pass_1(TCGContext *s) 2072 { 2073 int nb_globals = s->nb_globals; 2074 TCGOp *op, *op_prev; 2075 2076 tcg_la_func_end(s); 2077 2078 QTAILQ_FOREACH_REVERSE_SAFE(op, &s->ops, TCGOpHead, link, op_prev) { 2079 int i, nb_iargs, nb_oargs; 2080 TCGOpcode opc_new, opc_new2; 2081 bool have_opc_new2; 2082 TCGLifeData arg_life = 0; 2083 TCGTemp *arg_ts; 2084 TCGOpcode opc = op->opc; 2085 const TCGOpDef *def = &tcg_op_defs[opc]; 2086 2087 switch (opc) { 2088 case INDEX_op_call: 2089 { 2090 int call_flags; 2091 2092 nb_oargs = TCGOP_CALLO(op); 2093 nb_iargs = TCGOP_CALLI(op); 2094 call_flags = op->args[nb_oargs + nb_iargs + 1]; 2095 2096 /* pure functions can be removed if their result is unused */ 2097 if (call_flags & TCG_CALL_NO_SIDE_EFFECTS) { 2098 for (i = 0; i < nb_oargs; i++) { 2099 arg_ts = arg_temp(op->args[i]); 2100 if (arg_ts->state != TS_DEAD) { 2101 goto do_not_remove_call; 2102 } 2103 } 2104 goto do_remove; 2105 } else { 2106 do_not_remove_call: 2107 2108 /* output args are dead */ 2109 for (i = 0; i < nb_oargs; i++) { 2110 arg_ts = arg_temp(op->args[i]); 2111 if (arg_ts->state & TS_DEAD) { 2112 arg_life |= DEAD_ARG << i; 2113 } 2114 if (arg_ts->state & TS_MEM) { 2115 arg_life |= SYNC_ARG << i; 2116 } 2117 arg_ts->state = TS_DEAD; 2118 } 2119 2120 if (!(call_flags & (TCG_CALL_NO_WRITE_GLOBALS | 2121 TCG_CALL_NO_READ_GLOBALS))) { 2122 /* globals should go back to memory */ 2123 for (i = 0; i < nb_globals; i++) { 2124 s->temps[i].state = TS_DEAD | TS_MEM; 2125 } 2126 } else if (!(call_flags & TCG_CALL_NO_READ_GLOBALS)) { 2127 /* globals should be synced to memory */ 2128 for (i = 0; i < nb_globals; i++) { 2129 s->temps[i].state |= TS_MEM; 2130 } 2131 } 2132 2133 /* record arguments that die in this helper */ 2134 for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) { 2135 arg_ts = arg_temp(op->args[i]); 2136 if (arg_ts && arg_ts->state & TS_DEAD) { 2137 arg_life |= DEAD_ARG << i; 2138 } 2139 } 2140 /* input arguments are live for preceding opcodes */ 2141 for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) { 2142 arg_ts = arg_temp(op->args[i]); 2143 if (arg_ts) { 2144 arg_ts->state &= ~TS_DEAD; 2145 } 2146 } 2147 } 2148 } 2149 break; 2150 case INDEX_op_insn_start: 2151 break; 2152 case INDEX_op_discard: 2153 /* mark the temporary as dead */ 2154 arg_temp(op->args[0])->state = TS_DEAD; 2155 break; 2156 2157 case INDEX_op_add2_i32: 2158 opc_new = INDEX_op_add_i32; 2159 goto do_addsub2; 2160 case INDEX_op_sub2_i32: 2161 opc_new = INDEX_op_sub_i32; 2162 goto do_addsub2; 2163 case INDEX_op_add2_i64: 2164 opc_new = INDEX_op_add_i64; 2165 goto do_addsub2; 2166 case INDEX_op_sub2_i64: 2167 opc_new = INDEX_op_sub_i64; 2168 do_addsub2: 2169 nb_iargs = 4; 2170 nb_oargs = 2; 2171 /* Test if the high part of the operation is dead, but not 2172 the low part. The result can be optimized to a simple 2173 add or sub. This happens often for x86_64 guest when the 2174 cpu mode is set to 32 bit. */ 2175 if (arg_temp(op->args[1])->state == TS_DEAD) { 2176 if (arg_temp(op->args[0])->state == TS_DEAD) { 2177 goto do_remove; 2178 } 2179 /* Replace the opcode and adjust the args in place, 2180 leaving 3 unused args at the end. */ 2181 op->opc = opc = opc_new; 2182 op->args[1] = op->args[2]; 2183 op->args[2] = op->args[4]; 2184 /* Fall through and mark the single-word operation live. */ 2185 nb_iargs = 2; 2186 nb_oargs = 1; 2187 } 2188 goto do_not_remove; 2189 2190 case INDEX_op_mulu2_i32: 2191 opc_new = INDEX_op_mul_i32; 2192 opc_new2 = INDEX_op_muluh_i32; 2193 have_opc_new2 = TCG_TARGET_HAS_muluh_i32; 2194 goto do_mul2; 2195 case INDEX_op_muls2_i32: 2196 opc_new = INDEX_op_mul_i32; 2197 opc_new2 = INDEX_op_mulsh_i32; 2198 have_opc_new2 = TCG_TARGET_HAS_mulsh_i32; 2199 goto do_mul2; 2200 case INDEX_op_mulu2_i64: 2201 opc_new = INDEX_op_mul_i64; 2202 opc_new2 = INDEX_op_muluh_i64; 2203 have_opc_new2 = TCG_TARGET_HAS_muluh_i64; 2204 goto do_mul2; 2205 case INDEX_op_muls2_i64: 2206 opc_new = INDEX_op_mul_i64; 2207 opc_new2 = INDEX_op_mulsh_i64; 2208 have_opc_new2 = TCG_TARGET_HAS_mulsh_i64; 2209 goto do_mul2; 2210 do_mul2: 2211 nb_iargs = 2; 2212 nb_oargs = 2; 2213 if (arg_temp(op->args[1])->state == TS_DEAD) { 2214 if (arg_temp(op->args[0])->state == TS_DEAD) { 2215 /* Both parts of the operation are dead. */ 2216 goto do_remove; 2217 } 2218 /* The high part of the operation is dead; generate the low. */ 2219 op->opc = opc = opc_new; 2220 op->args[1] = op->args[2]; 2221 op->args[2] = op->args[3]; 2222 } else if (arg_temp(op->args[0])->state == TS_DEAD && have_opc_new2) { 2223 /* The low part of the operation is dead; generate the high. */ 2224 op->opc = opc = opc_new2; 2225 op->args[0] = op->args[1]; 2226 op->args[1] = op->args[2]; 2227 op->args[2] = op->args[3]; 2228 } else { 2229 goto do_not_remove; 2230 } 2231 /* Mark the single-word operation live. */ 2232 nb_oargs = 1; 2233 goto do_not_remove; 2234 2235 default: 2236 /* XXX: optimize by hardcoding common cases (e.g. triadic ops) */ 2237 nb_iargs = def->nb_iargs; 2238 nb_oargs = def->nb_oargs; 2239 2240 /* Test if the operation can be removed because all 2241 its outputs are dead. We assume that nb_oargs == 0 2242 implies side effects */ 2243 if (!(def->flags & TCG_OPF_SIDE_EFFECTS) && nb_oargs != 0) { 2244 for (i = 0; i < nb_oargs; i++) { 2245 if (arg_temp(op->args[i])->state != TS_DEAD) { 2246 goto do_not_remove; 2247 } 2248 } 2249 do_remove: 2250 tcg_op_remove(s, op); 2251 } else { 2252 do_not_remove: 2253 /* output args are dead */ 2254 for (i = 0; i < nb_oargs; i++) { 2255 arg_ts = arg_temp(op->args[i]); 2256 if (arg_ts->state & TS_DEAD) { 2257 arg_life |= DEAD_ARG << i; 2258 } 2259 if (arg_ts->state & TS_MEM) { 2260 arg_life |= SYNC_ARG << i; 2261 } 2262 arg_ts->state = TS_DEAD; 2263 } 2264 2265 /* if end of basic block, update */ 2266 if (def->flags & TCG_OPF_BB_END) { 2267 tcg_la_bb_end(s); 2268 } else if (def->flags & TCG_OPF_SIDE_EFFECTS) { 2269 /* globals should be synced to memory */ 2270 for (i = 0; i < nb_globals; i++) { 2271 s->temps[i].state |= TS_MEM; 2272 } 2273 } 2274 2275 /* record arguments that die in this opcode */ 2276 for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) { 2277 arg_ts = arg_temp(op->args[i]); 2278 if (arg_ts->state & TS_DEAD) { 2279 arg_life |= DEAD_ARG << i; 2280 } 2281 } 2282 /* input arguments are live for preceding opcodes */ 2283 for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) { 2284 arg_temp(op->args[i])->state &= ~TS_DEAD; 2285 } 2286 } 2287 break; 2288 } 2289 op->life = arg_life; 2290 } 2291 } 2292 2293 /* Liveness analysis: Convert indirect regs to direct temporaries. */ 2294 static bool liveness_pass_2(TCGContext *s) 2295 { 2296 int nb_globals = s->nb_globals; 2297 int nb_temps, i; 2298 bool changes = false; 2299 TCGOp *op, *op_next; 2300 2301 /* Create a temporary for each indirect global. */ 2302 for (i = 0; i < nb_globals; ++i) { 2303 TCGTemp *its = &s->temps[i]; 2304 if (its->indirect_reg) { 2305 TCGTemp *dts = tcg_temp_alloc(s); 2306 dts->type = its->type; 2307 dts->base_type = its->base_type; 2308 its->state_ptr = dts; 2309 } else { 2310 its->state_ptr = NULL; 2311 } 2312 /* All globals begin dead. */ 2313 its->state = TS_DEAD; 2314 } 2315 for (nb_temps = s->nb_temps; i < nb_temps; ++i) { 2316 TCGTemp *its = &s->temps[i]; 2317 its->state_ptr = NULL; 2318 its->state = TS_DEAD; 2319 } 2320 2321 QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) { 2322 TCGOpcode opc = op->opc; 2323 const TCGOpDef *def = &tcg_op_defs[opc]; 2324 TCGLifeData arg_life = op->life; 2325 int nb_iargs, nb_oargs, call_flags; 2326 TCGTemp *arg_ts, *dir_ts; 2327 2328 if (opc == INDEX_op_call) { 2329 nb_oargs = TCGOP_CALLO(op); 2330 nb_iargs = TCGOP_CALLI(op); 2331 call_flags = op->args[nb_oargs + nb_iargs + 1]; 2332 } else { 2333 nb_iargs = def->nb_iargs; 2334 nb_oargs = def->nb_oargs; 2335 2336 /* Set flags similar to how calls require. */ 2337 if (def->flags & TCG_OPF_BB_END) { 2338 /* Like writing globals: save_globals */ 2339 call_flags = 0; 2340 } else if (def->flags & TCG_OPF_SIDE_EFFECTS) { 2341 /* Like reading globals: sync_globals */ 2342 call_flags = TCG_CALL_NO_WRITE_GLOBALS; 2343 } else { 2344 /* No effect on globals. */ 2345 call_flags = (TCG_CALL_NO_READ_GLOBALS | 2346 TCG_CALL_NO_WRITE_GLOBALS); 2347 } 2348 } 2349 2350 /* Make sure that input arguments are available. */ 2351 for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) { 2352 arg_ts = arg_temp(op->args[i]); 2353 if (arg_ts) { 2354 dir_ts = arg_ts->state_ptr; 2355 if (dir_ts && arg_ts->state == TS_DEAD) { 2356 TCGOpcode lopc = (arg_ts->type == TCG_TYPE_I32 2357 ? INDEX_op_ld_i32 2358 : INDEX_op_ld_i64); 2359 TCGOp *lop = tcg_op_insert_before(s, op, lopc, 3); 2360 2361 lop->args[0] = temp_arg(dir_ts); 2362 lop->args[1] = temp_arg(arg_ts->mem_base); 2363 lop->args[2] = arg_ts->mem_offset; 2364 2365 /* Loaded, but synced with memory. */ 2366 arg_ts->state = TS_MEM; 2367 } 2368 } 2369 } 2370 2371 /* Perform input replacement, and mark inputs that became dead. 2372 No action is required except keeping temp_state up to date 2373 so that we reload when needed. */ 2374 for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) { 2375 arg_ts = arg_temp(op->args[i]); 2376 if (arg_ts) { 2377 dir_ts = arg_ts->state_ptr; 2378 if (dir_ts) { 2379 op->args[i] = temp_arg(dir_ts); 2380 changes = true; 2381 if (IS_DEAD_ARG(i)) { 2382 arg_ts->state = TS_DEAD; 2383 } 2384 } 2385 } 2386 } 2387 2388 /* Liveness analysis should ensure that the following are 2389 all correct, for call sites and basic block end points. */ 2390 if (call_flags & TCG_CALL_NO_READ_GLOBALS) { 2391 /* Nothing to do */ 2392 } else if (call_flags & TCG_CALL_NO_WRITE_GLOBALS) { 2393 for (i = 0; i < nb_globals; ++i) { 2394 /* Liveness should see that globals are synced back, 2395 that is, either TS_DEAD or TS_MEM. */ 2396 arg_ts = &s->temps[i]; 2397 tcg_debug_assert(arg_ts->state_ptr == 0 2398 || arg_ts->state != 0); 2399 } 2400 } else { 2401 for (i = 0; i < nb_globals; ++i) { 2402 /* Liveness should see that globals are saved back, 2403 that is, TS_DEAD, waiting to be reloaded. */ 2404 arg_ts = &s->temps[i]; 2405 tcg_debug_assert(arg_ts->state_ptr == 0 2406 || arg_ts->state == TS_DEAD); 2407 } 2408 } 2409 2410 /* Outputs become available. */ 2411 for (i = 0; i < nb_oargs; i++) { 2412 arg_ts = arg_temp(op->args[i]); 2413 dir_ts = arg_ts->state_ptr; 2414 if (!dir_ts) { 2415 continue; 2416 } 2417 op->args[i] = temp_arg(dir_ts); 2418 changes = true; 2419 2420 /* The output is now live and modified. */ 2421 arg_ts->state = 0; 2422 2423 /* Sync outputs upon their last write. */ 2424 if (NEED_SYNC_ARG(i)) { 2425 TCGOpcode sopc = (arg_ts->type == TCG_TYPE_I32 2426 ? INDEX_op_st_i32 2427 : INDEX_op_st_i64); 2428 TCGOp *sop = tcg_op_insert_after(s, op, sopc, 3); 2429 2430 sop->args[0] = temp_arg(dir_ts); 2431 sop->args[1] = temp_arg(arg_ts->mem_base); 2432 sop->args[2] = arg_ts->mem_offset; 2433 2434 arg_ts->state = TS_MEM; 2435 } 2436 /* Drop outputs that are dead. */ 2437 if (IS_DEAD_ARG(i)) { 2438 arg_ts->state = TS_DEAD; 2439 } 2440 } 2441 } 2442 2443 return changes; 2444 } 2445 2446 #ifdef CONFIG_DEBUG_TCG 2447 static void dump_regs(TCGContext *s) 2448 { 2449 TCGTemp *ts; 2450 int i; 2451 char buf[64]; 2452 2453 for(i = 0; i < s->nb_temps; i++) { 2454 ts = &s->temps[i]; 2455 printf(" %10s: ", tcg_get_arg_str_ptr(s, buf, sizeof(buf), ts)); 2456 switch(ts->val_type) { 2457 case TEMP_VAL_REG: 2458 printf("%s", tcg_target_reg_names[ts->reg]); 2459 break; 2460 case TEMP_VAL_MEM: 2461 printf("%d(%s)", (int)ts->mem_offset, 2462 tcg_target_reg_names[ts->mem_base->reg]); 2463 break; 2464 case TEMP_VAL_CONST: 2465 printf("$0x%" TCG_PRIlx, ts->val); 2466 break; 2467 case TEMP_VAL_DEAD: 2468 printf("D"); 2469 break; 2470 default: 2471 printf("???"); 2472 break; 2473 } 2474 printf("\n"); 2475 } 2476 2477 for(i = 0; i < TCG_TARGET_NB_REGS; i++) { 2478 if (s->reg_to_temp[i] != NULL) { 2479 printf("%s: %s\n", 2480 tcg_target_reg_names[i], 2481 tcg_get_arg_str_ptr(s, buf, sizeof(buf), s->reg_to_temp[i])); 2482 } 2483 } 2484 } 2485 2486 static void check_regs(TCGContext *s) 2487 { 2488 int reg; 2489 int k; 2490 TCGTemp *ts; 2491 char buf[64]; 2492 2493 for (reg = 0; reg < TCG_TARGET_NB_REGS; reg++) { 2494 ts = s->reg_to_temp[reg]; 2495 if (ts != NULL) { 2496 if (ts->val_type != TEMP_VAL_REG || ts->reg != reg) { 2497 printf("Inconsistency for register %s:\n", 2498 tcg_target_reg_names[reg]); 2499 goto fail; 2500 } 2501 } 2502 } 2503 for (k = 0; k < s->nb_temps; k++) { 2504 ts = &s->temps[k]; 2505 if (ts->val_type == TEMP_VAL_REG && !ts->fixed_reg 2506 && s->reg_to_temp[ts->reg] != ts) { 2507 printf("Inconsistency for temp %s:\n", 2508 tcg_get_arg_str_ptr(s, buf, sizeof(buf), ts)); 2509 fail: 2510 printf("reg state:\n"); 2511 dump_regs(s); 2512 tcg_abort(); 2513 } 2514 } 2515 } 2516 #endif 2517 2518 static void temp_allocate_frame(TCGContext *s, TCGTemp *ts) 2519 { 2520 #if !(defined(__sparc__) && TCG_TARGET_REG_BITS == 64) 2521 /* Sparc64 stack is accessed with offset of 2047 */ 2522 s->current_frame_offset = (s->current_frame_offset + 2523 (tcg_target_long)sizeof(tcg_target_long) - 1) & 2524 ~(sizeof(tcg_target_long) - 1); 2525 #endif 2526 if (s->current_frame_offset + (tcg_target_long)sizeof(tcg_target_long) > 2527 s->frame_end) { 2528 tcg_abort(); 2529 } 2530 ts->mem_offset = s->current_frame_offset; 2531 ts->mem_base = s->frame_temp; 2532 ts->mem_allocated = 1; 2533 s->current_frame_offset += sizeof(tcg_target_long); 2534 } 2535 2536 static void temp_load(TCGContext *, TCGTemp *, TCGRegSet, TCGRegSet); 2537 2538 /* Mark a temporary as free or dead. If 'free_or_dead' is negative, 2539 mark it free; otherwise mark it dead. */ 2540 static void temp_free_or_dead(TCGContext *s, TCGTemp *ts, int free_or_dead) 2541 { 2542 if (ts->fixed_reg) { 2543 return; 2544 } 2545 if (ts->val_type == TEMP_VAL_REG) { 2546 s->reg_to_temp[ts->reg] = NULL; 2547 } 2548 ts->val_type = (free_or_dead < 0 2549 || ts->temp_local 2550 || ts->temp_global 2551 ? TEMP_VAL_MEM : TEMP_VAL_DEAD); 2552 } 2553 2554 /* Mark a temporary as dead. */ 2555 static inline void temp_dead(TCGContext *s, TCGTemp *ts) 2556 { 2557 temp_free_or_dead(s, ts, 1); 2558 } 2559 2560 /* Sync a temporary to memory. 'allocated_regs' is used in case a temporary 2561 registers needs to be allocated to store a constant. If 'free_or_dead' 2562 is non-zero, subsequently release the temporary; if it is positive, the 2563 temp is dead; if it is negative, the temp is free. */ 2564 static void temp_sync(TCGContext *s, TCGTemp *ts, 2565 TCGRegSet allocated_regs, int free_or_dead) 2566 { 2567 if (ts->fixed_reg) { 2568 return; 2569 } 2570 if (!ts->mem_coherent) { 2571 if (!ts->mem_allocated) { 2572 temp_allocate_frame(s, ts); 2573 } 2574 switch (ts->val_type) { 2575 case TEMP_VAL_CONST: 2576 /* If we're going to free the temp immediately, then we won't 2577 require it later in a register, so attempt to store the 2578 constant to memory directly. */ 2579 if (free_or_dead 2580 && tcg_out_sti(s, ts->type, ts->val, 2581 ts->mem_base->reg, ts->mem_offset)) { 2582 break; 2583 } 2584 temp_load(s, ts, tcg_target_available_regs[ts->type], 2585 allocated_regs); 2586 /* fallthrough */ 2587 2588 case TEMP_VAL_REG: 2589 tcg_out_st(s, ts->type, ts->reg, 2590 ts->mem_base->reg, ts->mem_offset); 2591 break; 2592 2593 case TEMP_VAL_MEM: 2594 break; 2595 2596 case TEMP_VAL_DEAD: 2597 default: 2598 tcg_abort(); 2599 } 2600 ts->mem_coherent = 1; 2601 } 2602 if (free_or_dead) { 2603 temp_free_or_dead(s, ts, free_or_dead); 2604 } 2605 } 2606 2607 /* free register 'reg' by spilling the corresponding temporary if necessary */ 2608 static void tcg_reg_free(TCGContext *s, TCGReg reg, TCGRegSet allocated_regs) 2609 { 2610 TCGTemp *ts = s->reg_to_temp[reg]; 2611 if (ts != NULL) { 2612 temp_sync(s, ts, allocated_regs, -1); 2613 } 2614 } 2615 2616 /* Allocate a register belonging to reg1 & ~reg2 */ 2617 static TCGReg tcg_reg_alloc(TCGContext *s, TCGRegSet desired_regs, 2618 TCGRegSet allocated_regs, bool rev) 2619 { 2620 int i, n = ARRAY_SIZE(tcg_target_reg_alloc_order); 2621 const int *order; 2622 TCGReg reg; 2623 TCGRegSet reg_ct; 2624 2625 reg_ct = desired_regs & ~allocated_regs; 2626 order = rev ? indirect_reg_alloc_order : tcg_target_reg_alloc_order; 2627 2628 /* first try free registers */ 2629 for(i = 0; i < n; i++) { 2630 reg = order[i]; 2631 if (tcg_regset_test_reg(reg_ct, reg) && s->reg_to_temp[reg] == NULL) 2632 return reg; 2633 } 2634 2635 /* XXX: do better spill choice */ 2636 for(i = 0; i < n; i++) { 2637 reg = order[i]; 2638 if (tcg_regset_test_reg(reg_ct, reg)) { 2639 tcg_reg_free(s, reg, allocated_regs); 2640 return reg; 2641 } 2642 } 2643 2644 tcg_abort(); 2645 } 2646 2647 /* Make sure the temporary is in a register. If needed, allocate the register 2648 from DESIRED while avoiding ALLOCATED. */ 2649 static void temp_load(TCGContext *s, TCGTemp *ts, TCGRegSet desired_regs, 2650 TCGRegSet allocated_regs) 2651 { 2652 TCGReg reg; 2653 2654 switch (ts->val_type) { 2655 case TEMP_VAL_REG: 2656 return; 2657 case TEMP_VAL_CONST: 2658 reg = tcg_reg_alloc(s, desired_regs, allocated_regs, ts->indirect_base); 2659 tcg_out_movi(s, ts->type, reg, ts->val); 2660 ts->mem_coherent = 0; 2661 break; 2662 case TEMP_VAL_MEM: 2663 reg = tcg_reg_alloc(s, desired_regs, allocated_regs, ts->indirect_base); 2664 tcg_out_ld(s, ts->type, reg, ts->mem_base->reg, ts->mem_offset); 2665 ts->mem_coherent = 1; 2666 break; 2667 case TEMP_VAL_DEAD: 2668 default: 2669 tcg_abort(); 2670 } 2671 ts->reg = reg; 2672 ts->val_type = TEMP_VAL_REG; 2673 s->reg_to_temp[reg] = ts; 2674 } 2675 2676 /* Save a temporary to memory. 'allocated_regs' is used in case a 2677 temporary registers needs to be allocated to store a constant. */ 2678 static void temp_save(TCGContext *s, TCGTemp *ts, TCGRegSet allocated_regs) 2679 { 2680 /* The liveness analysis already ensures that globals are back 2681 in memory. Keep an tcg_debug_assert for safety. */ 2682 tcg_debug_assert(ts->val_type == TEMP_VAL_MEM || ts->fixed_reg); 2683 } 2684 2685 /* save globals to their canonical location and assume they can be 2686 modified be the following code. 'allocated_regs' is used in case a 2687 temporary registers needs to be allocated to store a constant. */ 2688 static void save_globals(TCGContext *s, TCGRegSet allocated_regs) 2689 { 2690 int i, n; 2691 2692 for (i = 0, n = s->nb_globals; i < n; i++) { 2693 temp_save(s, &s->temps[i], allocated_regs); 2694 } 2695 } 2696 2697 /* sync globals to their canonical location and assume they can be 2698 read by the following code. 'allocated_regs' is used in case a 2699 temporary registers needs to be allocated to store a constant. */ 2700 static void sync_globals(TCGContext *s, TCGRegSet allocated_regs) 2701 { 2702 int i, n; 2703 2704 for (i = 0, n = s->nb_globals; i < n; i++) { 2705 TCGTemp *ts = &s->temps[i]; 2706 tcg_debug_assert(ts->val_type != TEMP_VAL_REG 2707 || ts->fixed_reg 2708 || ts->mem_coherent); 2709 } 2710 } 2711 2712 /* at the end of a basic block, we assume all temporaries are dead and 2713 all globals are stored at their canonical location. */ 2714 static void tcg_reg_alloc_bb_end(TCGContext *s, TCGRegSet allocated_regs) 2715 { 2716 int i; 2717 2718 for (i = s->nb_globals; i < s->nb_temps; i++) { 2719 TCGTemp *ts = &s->temps[i]; 2720 if (ts->temp_local) { 2721 temp_save(s, ts, allocated_regs); 2722 } else { 2723 /* The liveness analysis already ensures that temps are dead. 2724 Keep an tcg_debug_assert for safety. */ 2725 tcg_debug_assert(ts->val_type == TEMP_VAL_DEAD); 2726 } 2727 } 2728 2729 save_globals(s, allocated_regs); 2730 } 2731 2732 static void tcg_reg_alloc_do_movi(TCGContext *s, TCGTemp *ots, 2733 tcg_target_ulong val, TCGLifeData arg_life) 2734 { 2735 if (ots->fixed_reg) { 2736 /* For fixed registers, we do not do any constant propagation. */ 2737 tcg_out_movi(s, ots->type, ots->reg, val); 2738 return; 2739 } 2740 2741 /* The movi is not explicitly generated here. */ 2742 if (ots->val_type == TEMP_VAL_REG) { 2743 s->reg_to_temp[ots->reg] = NULL; 2744 } 2745 ots->val_type = TEMP_VAL_CONST; 2746 ots->val = val; 2747 ots->mem_coherent = 0; 2748 if (NEED_SYNC_ARG(0)) { 2749 temp_sync(s, ots, s->reserved_regs, IS_DEAD_ARG(0)); 2750 } else if (IS_DEAD_ARG(0)) { 2751 temp_dead(s, ots); 2752 } 2753 } 2754 2755 static void tcg_reg_alloc_movi(TCGContext *s, const TCGOp *op) 2756 { 2757 TCGTemp *ots = arg_temp(op->args[0]); 2758 tcg_target_ulong val = op->args[1]; 2759 2760 tcg_reg_alloc_do_movi(s, ots, val, op->life); 2761 } 2762 2763 static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op) 2764 { 2765 const TCGLifeData arg_life = op->life; 2766 TCGRegSet allocated_regs; 2767 TCGTemp *ts, *ots; 2768 TCGType otype, itype; 2769 2770 allocated_regs = s->reserved_regs; 2771 ots = arg_temp(op->args[0]); 2772 ts = arg_temp(op->args[1]); 2773 2774 /* Note that otype != itype for no-op truncation. */ 2775 otype = ots->type; 2776 itype = ts->type; 2777 2778 if (ts->val_type == TEMP_VAL_CONST) { 2779 /* propagate constant or generate sti */ 2780 tcg_target_ulong val = ts->val; 2781 if (IS_DEAD_ARG(1)) { 2782 temp_dead(s, ts); 2783 } 2784 tcg_reg_alloc_do_movi(s, ots, val, arg_life); 2785 return; 2786 } 2787 2788 /* If the source value is in memory we're going to be forced 2789 to have it in a register in order to perform the copy. Copy 2790 the SOURCE value into its own register first, that way we 2791 don't have to reload SOURCE the next time it is used. */ 2792 if (ts->val_type == TEMP_VAL_MEM) { 2793 temp_load(s, ts, tcg_target_available_regs[itype], allocated_regs); 2794 } 2795 2796 tcg_debug_assert(ts->val_type == TEMP_VAL_REG); 2797 if (IS_DEAD_ARG(0) && !ots->fixed_reg) { 2798 /* mov to a non-saved dead register makes no sense (even with 2799 liveness analysis disabled). */ 2800 tcg_debug_assert(NEED_SYNC_ARG(0)); 2801 if (!ots->mem_allocated) { 2802 temp_allocate_frame(s, ots); 2803 } 2804 tcg_out_st(s, otype, ts->reg, ots->mem_base->reg, ots->mem_offset); 2805 if (IS_DEAD_ARG(1)) { 2806 temp_dead(s, ts); 2807 } 2808 temp_dead(s, ots); 2809 } else { 2810 if (IS_DEAD_ARG(1) && !ts->fixed_reg && !ots->fixed_reg) { 2811 /* the mov can be suppressed */ 2812 if (ots->val_type == TEMP_VAL_REG) { 2813 s->reg_to_temp[ots->reg] = NULL; 2814 } 2815 ots->reg = ts->reg; 2816 temp_dead(s, ts); 2817 } else { 2818 if (ots->val_type != TEMP_VAL_REG) { 2819 /* When allocating a new register, make sure to not spill the 2820 input one. */ 2821 tcg_regset_set_reg(allocated_regs, ts->reg); 2822 ots->reg = tcg_reg_alloc(s, tcg_target_available_regs[otype], 2823 allocated_regs, ots->indirect_base); 2824 } 2825 tcg_out_mov(s, otype, ots->reg, ts->reg); 2826 } 2827 ots->val_type = TEMP_VAL_REG; 2828 ots->mem_coherent = 0; 2829 s->reg_to_temp[ots->reg] = ots; 2830 if (NEED_SYNC_ARG(0)) { 2831 temp_sync(s, ots, allocated_regs, 0); 2832 } 2833 } 2834 } 2835 2836 static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) 2837 { 2838 const TCGLifeData arg_life = op->life; 2839 const TCGOpDef * const def = &tcg_op_defs[op->opc]; 2840 TCGRegSet i_allocated_regs; 2841 TCGRegSet o_allocated_regs; 2842 int i, k, nb_iargs, nb_oargs; 2843 TCGReg reg; 2844 TCGArg arg; 2845 const TCGArgConstraint *arg_ct; 2846 TCGTemp *ts; 2847 TCGArg new_args[TCG_MAX_OP_ARGS]; 2848 int const_args[TCG_MAX_OP_ARGS]; 2849 2850 nb_oargs = def->nb_oargs; 2851 nb_iargs = def->nb_iargs; 2852 2853 /* copy constants */ 2854 memcpy(new_args + nb_oargs + nb_iargs, 2855 op->args + nb_oargs + nb_iargs, 2856 sizeof(TCGArg) * def->nb_cargs); 2857 2858 i_allocated_regs = s->reserved_regs; 2859 o_allocated_regs = s->reserved_regs; 2860 2861 /* satisfy input constraints */ 2862 for (k = 0; k < nb_iargs; k++) { 2863 i = def->sorted_args[nb_oargs + k]; 2864 arg = op->args[i]; 2865 arg_ct = &def->args_ct[i]; 2866 ts = arg_temp(arg); 2867 2868 if (ts->val_type == TEMP_VAL_CONST 2869 && tcg_target_const_match(ts->val, ts->type, arg_ct)) { 2870 /* constant is OK for instruction */ 2871 const_args[i] = 1; 2872 new_args[i] = ts->val; 2873 goto iarg_end; 2874 } 2875 2876 temp_load(s, ts, arg_ct->u.regs, i_allocated_regs); 2877 2878 if (arg_ct->ct & TCG_CT_IALIAS) { 2879 if (ts->fixed_reg) { 2880 /* if fixed register, we must allocate a new register 2881 if the alias is not the same register */ 2882 if (arg != op->args[arg_ct->alias_index]) 2883 goto allocate_in_reg; 2884 } else { 2885 /* if the input is aliased to an output and if it is 2886 not dead after the instruction, we must allocate 2887 a new register and move it */ 2888 if (!IS_DEAD_ARG(i)) { 2889 goto allocate_in_reg; 2890 } 2891 /* check if the current register has already been allocated 2892 for another input aliased to an output */ 2893 int k2, i2; 2894 for (k2 = 0 ; k2 < k ; k2++) { 2895 i2 = def->sorted_args[nb_oargs + k2]; 2896 if ((def->args_ct[i2].ct & TCG_CT_IALIAS) && 2897 (new_args[i2] == ts->reg)) { 2898 goto allocate_in_reg; 2899 } 2900 } 2901 } 2902 } 2903 reg = ts->reg; 2904 if (tcg_regset_test_reg(arg_ct->u.regs, reg)) { 2905 /* nothing to do : the constraint is satisfied */ 2906 } else { 2907 allocate_in_reg: 2908 /* allocate a new register matching the constraint 2909 and move the temporary register into it */ 2910 reg = tcg_reg_alloc(s, arg_ct->u.regs, i_allocated_regs, 2911 ts->indirect_base); 2912 tcg_out_mov(s, ts->type, reg, ts->reg); 2913 } 2914 new_args[i] = reg; 2915 const_args[i] = 0; 2916 tcg_regset_set_reg(i_allocated_regs, reg); 2917 iarg_end: ; 2918 } 2919 2920 /* mark dead temporaries and free the associated registers */ 2921 for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) { 2922 if (IS_DEAD_ARG(i)) { 2923 temp_dead(s, arg_temp(op->args[i])); 2924 } 2925 } 2926 2927 if (def->flags & TCG_OPF_BB_END) { 2928 tcg_reg_alloc_bb_end(s, i_allocated_regs); 2929 } else { 2930 if (def->flags & TCG_OPF_CALL_CLOBBER) { 2931 /* XXX: permit generic clobber register list ? */ 2932 for (i = 0; i < TCG_TARGET_NB_REGS; i++) { 2933 if (tcg_regset_test_reg(tcg_target_call_clobber_regs, i)) { 2934 tcg_reg_free(s, i, i_allocated_regs); 2935 } 2936 } 2937 } 2938 if (def->flags & TCG_OPF_SIDE_EFFECTS) { 2939 /* sync globals if the op has side effects and might trigger 2940 an exception. */ 2941 sync_globals(s, i_allocated_regs); 2942 } 2943 2944 /* satisfy the output constraints */ 2945 for(k = 0; k < nb_oargs; k++) { 2946 i = def->sorted_args[k]; 2947 arg = op->args[i]; 2948 arg_ct = &def->args_ct[i]; 2949 ts = arg_temp(arg); 2950 if ((arg_ct->ct & TCG_CT_ALIAS) 2951 && !const_args[arg_ct->alias_index]) { 2952 reg = new_args[arg_ct->alias_index]; 2953 } else if (arg_ct->ct & TCG_CT_NEWREG) { 2954 reg = tcg_reg_alloc(s, arg_ct->u.regs, 2955 i_allocated_regs | o_allocated_regs, 2956 ts->indirect_base); 2957 } else { 2958 /* if fixed register, we try to use it */ 2959 reg = ts->reg; 2960 if (ts->fixed_reg && 2961 tcg_regset_test_reg(arg_ct->u.regs, reg)) { 2962 goto oarg_end; 2963 } 2964 reg = tcg_reg_alloc(s, arg_ct->u.regs, o_allocated_regs, 2965 ts->indirect_base); 2966 } 2967 tcg_regset_set_reg(o_allocated_regs, reg); 2968 /* if a fixed register is used, then a move will be done afterwards */ 2969 if (!ts->fixed_reg) { 2970 if (ts->val_type == TEMP_VAL_REG) { 2971 s->reg_to_temp[ts->reg] = NULL; 2972 } 2973 ts->val_type = TEMP_VAL_REG; 2974 ts->reg = reg; 2975 /* temp value is modified, so the value kept in memory is 2976 potentially not the same */ 2977 ts->mem_coherent = 0; 2978 s->reg_to_temp[reg] = ts; 2979 } 2980 oarg_end: 2981 new_args[i] = reg; 2982 } 2983 } 2984 2985 /* emit instruction */ 2986 if (def->flags & TCG_OPF_VECTOR) { 2987 tcg_out_vec_op(s, op->opc, TCGOP_VECL(op), TCGOP_VECE(op), 2988 new_args, const_args); 2989 } else { 2990 tcg_out_op(s, op->opc, new_args, const_args); 2991 } 2992 2993 /* move the outputs in the correct register if needed */ 2994 for(i = 0; i < nb_oargs; i++) { 2995 ts = arg_temp(op->args[i]); 2996 reg = new_args[i]; 2997 if (ts->fixed_reg && ts->reg != reg) { 2998 tcg_out_mov(s, ts->type, ts->reg, reg); 2999 } 3000 if (NEED_SYNC_ARG(i)) { 3001 temp_sync(s, ts, o_allocated_regs, IS_DEAD_ARG(i)); 3002 } else if (IS_DEAD_ARG(i)) { 3003 temp_dead(s, ts); 3004 } 3005 } 3006 } 3007 3008 #ifdef TCG_TARGET_STACK_GROWSUP 3009 #define STACK_DIR(x) (-(x)) 3010 #else 3011 #define STACK_DIR(x) (x) 3012 #endif 3013 3014 static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) 3015 { 3016 const int nb_oargs = TCGOP_CALLO(op); 3017 const int nb_iargs = TCGOP_CALLI(op); 3018 const TCGLifeData arg_life = op->life; 3019 int flags, nb_regs, i; 3020 TCGReg reg; 3021 TCGArg arg; 3022 TCGTemp *ts; 3023 intptr_t stack_offset; 3024 size_t call_stack_size; 3025 tcg_insn_unit *func_addr; 3026 int allocate_args; 3027 TCGRegSet allocated_regs; 3028 3029 func_addr = (tcg_insn_unit *)(intptr_t)op->args[nb_oargs + nb_iargs]; 3030 flags = op->args[nb_oargs + nb_iargs + 1]; 3031 3032 nb_regs = ARRAY_SIZE(tcg_target_call_iarg_regs); 3033 if (nb_regs > nb_iargs) { 3034 nb_regs = nb_iargs; 3035 } 3036 3037 /* assign stack slots first */ 3038 call_stack_size = (nb_iargs - nb_regs) * sizeof(tcg_target_long); 3039 call_stack_size = (call_stack_size + TCG_TARGET_STACK_ALIGN - 1) & 3040 ~(TCG_TARGET_STACK_ALIGN - 1); 3041 allocate_args = (call_stack_size > TCG_STATIC_CALL_ARGS_SIZE); 3042 if (allocate_args) { 3043 /* XXX: if more than TCG_STATIC_CALL_ARGS_SIZE is needed, 3044 preallocate call stack */ 3045 tcg_abort(); 3046 } 3047 3048 stack_offset = TCG_TARGET_CALL_STACK_OFFSET; 3049 for (i = nb_regs; i < nb_iargs; i++) { 3050 arg = op->args[nb_oargs + i]; 3051 #ifdef TCG_TARGET_STACK_GROWSUP 3052 stack_offset -= sizeof(tcg_target_long); 3053 #endif 3054 if (arg != TCG_CALL_DUMMY_ARG) { 3055 ts = arg_temp(arg); 3056 temp_load(s, ts, tcg_target_available_regs[ts->type], 3057 s->reserved_regs); 3058 tcg_out_st(s, ts->type, ts->reg, TCG_REG_CALL_STACK, stack_offset); 3059 } 3060 #ifndef TCG_TARGET_STACK_GROWSUP 3061 stack_offset += sizeof(tcg_target_long); 3062 #endif 3063 } 3064 3065 /* assign input registers */ 3066 allocated_regs = s->reserved_regs; 3067 for (i = 0; i < nb_regs; i++) { 3068 arg = op->args[nb_oargs + i]; 3069 if (arg != TCG_CALL_DUMMY_ARG) { 3070 ts = arg_temp(arg); 3071 reg = tcg_target_call_iarg_regs[i]; 3072 tcg_reg_free(s, reg, allocated_regs); 3073 3074 if (ts->val_type == TEMP_VAL_REG) { 3075 if (ts->reg != reg) { 3076 tcg_out_mov(s, ts->type, reg, ts->reg); 3077 } 3078 } else { 3079 TCGRegSet arg_set = 0; 3080 3081 tcg_regset_set_reg(arg_set, reg); 3082 temp_load(s, ts, arg_set, allocated_regs); 3083 } 3084 3085 tcg_regset_set_reg(allocated_regs, reg); 3086 } 3087 } 3088 3089 /* mark dead temporaries and free the associated registers */ 3090 for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) { 3091 if (IS_DEAD_ARG(i)) { 3092 temp_dead(s, arg_temp(op->args[i])); 3093 } 3094 } 3095 3096 /* clobber call registers */ 3097 for (i = 0; i < TCG_TARGET_NB_REGS; i++) { 3098 if (tcg_regset_test_reg(tcg_target_call_clobber_regs, i)) { 3099 tcg_reg_free(s, i, allocated_regs); 3100 } 3101 } 3102 3103 /* Save globals if they might be written by the helper, sync them if 3104 they might be read. */ 3105 if (flags & TCG_CALL_NO_READ_GLOBALS) { 3106 /* Nothing to do */ 3107 } else if (flags & TCG_CALL_NO_WRITE_GLOBALS) { 3108 sync_globals(s, allocated_regs); 3109 } else { 3110 save_globals(s, allocated_regs); 3111 } 3112 3113 tcg_out_call(s, func_addr); 3114 3115 /* assign output registers and emit moves if needed */ 3116 for(i = 0; i < nb_oargs; i++) { 3117 arg = op->args[i]; 3118 ts = arg_temp(arg); 3119 reg = tcg_target_call_oarg_regs[i]; 3120 tcg_debug_assert(s->reg_to_temp[reg] == NULL); 3121 3122 if (ts->fixed_reg) { 3123 if (ts->reg != reg) { 3124 tcg_out_mov(s, ts->type, ts->reg, reg); 3125 } 3126 } else { 3127 if (ts->val_type == TEMP_VAL_REG) { 3128 s->reg_to_temp[ts->reg] = NULL; 3129 } 3130 ts->val_type = TEMP_VAL_REG; 3131 ts->reg = reg; 3132 ts->mem_coherent = 0; 3133 s->reg_to_temp[reg] = ts; 3134 if (NEED_SYNC_ARG(i)) { 3135 temp_sync(s, ts, allocated_regs, IS_DEAD_ARG(i)); 3136 } else if (IS_DEAD_ARG(i)) { 3137 temp_dead(s, ts); 3138 } 3139 } 3140 } 3141 } 3142 3143 #ifdef CONFIG_PROFILER 3144 3145 /* avoid copy/paste errors */ 3146 #define PROF_ADD(to, from, field) \ 3147 do { \ 3148 (to)->field += atomic_read(&((from)->field)); \ 3149 } while (0) 3150 3151 #define PROF_MAX(to, from, field) \ 3152 do { \ 3153 typeof((from)->field) val__ = atomic_read(&((from)->field)); \ 3154 if (val__ > (to)->field) { \ 3155 (to)->field = val__; \ 3156 } \ 3157 } while (0) 3158 3159 /* Pass in a zero'ed @prof */ 3160 static inline 3161 void tcg_profile_snapshot(TCGProfile *prof, bool counters, bool table) 3162 { 3163 unsigned int n_ctxs = atomic_read(&n_tcg_ctxs); 3164 unsigned int i; 3165 3166 for (i = 0; i < n_ctxs; i++) { 3167 TCGContext *s = atomic_read(&tcg_ctxs[i]); 3168 const TCGProfile *orig = &s->prof; 3169 3170 if (counters) { 3171 PROF_ADD(prof, orig, tb_count1); 3172 PROF_ADD(prof, orig, tb_count); 3173 PROF_ADD(prof, orig, op_count); 3174 PROF_MAX(prof, orig, op_count_max); 3175 PROF_ADD(prof, orig, temp_count); 3176 PROF_MAX(prof, orig, temp_count_max); 3177 PROF_ADD(prof, orig, del_op_count); 3178 PROF_ADD(prof, orig, code_in_len); 3179 PROF_ADD(prof, orig, code_out_len); 3180 PROF_ADD(prof, orig, search_out_len); 3181 PROF_ADD(prof, orig, interm_time); 3182 PROF_ADD(prof, orig, code_time); 3183 PROF_ADD(prof, orig, la_time); 3184 PROF_ADD(prof, orig, opt_time); 3185 PROF_ADD(prof, orig, restore_count); 3186 PROF_ADD(prof, orig, restore_time); 3187 } 3188 if (table) { 3189 int i; 3190 3191 for (i = 0; i < NB_OPS; i++) { 3192 PROF_ADD(prof, orig, table_op_count[i]); 3193 } 3194 } 3195 } 3196 } 3197 3198 #undef PROF_ADD 3199 #undef PROF_MAX 3200 3201 static void tcg_profile_snapshot_counters(TCGProfile *prof) 3202 { 3203 tcg_profile_snapshot(prof, true, false); 3204 } 3205 3206 static void tcg_profile_snapshot_table(TCGProfile *prof) 3207 { 3208 tcg_profile_snapshot(prof, false, true); 3209 } 3210 3211 void tcg_dump_op_count(FILE *f, fprintf_function cpu_fprintf) 3212 { 3213 TCGProfile prof = {}; 3214 int i; 3215 3216 tcg_profile_snapshot_table(&prof); 3217 for (i = 0; i < NB_OPS; i++) { 3218 cpu_fprintf(f, "%s %" PRId64 "\n", tcg_op_defs[i].name, 3219 prof.table_op_count[i]); 3220 } 3221 } 3222 #else 3223 void tcg_dump_op_count(FILE *f, fprintf_function cpu_fprintf) 3224 { 3225 cpu_fprintf(f, "[TCG profiler not compiled]\n"); 3226 } 3227 #endif 3228 3229 3230 int tcg_gen_code(TCGContext *s, TranslationBlock *tb) 3231 { 3232 #ifdef CONFIG_PROFILER 3233 TCGProfile *prof = &s->prof; 3234 #endif 3235 int i, num_insns; 3236 TCGOp *op; 3237 3238 #ifdef CONFIG_PROFILER 3239 { 3240 int n; 3241 3242 QTAILQ_FOREACH(op, &s->ops, link) { 3243 n++; 3244 } 3245 atomic_set(&prof->op_count, prof->op_count + n); 3246 if (n > prof->op_count_max) { 3247 atomic_set(&prof->op_count_max, n); 3248 } 3249 3250 n = s->nb_temps; 3251 atomic_set(&prof->temp_count, prof->temp_count + n); 3252 if (n > prof->temp_count_max) { 3253 atomic_set(&prof->temp_count_max, n); 3254 } 3255 } 3256 #endif 3257 3258 #ifdef DEBUG_DISAS 3259 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP) 3260 && qemu_log_in_addr_range(tb->pc))) { 3261 qemu_log_lock(); 3262 qemu_log("OP:\n"); 3263 tcg_dump_ops(s); 3264 qemu_log("\n"); 3265 qemu_log_unlock(); 3266 } 3267 #endif 3268 3269 #ifdef CONFIG_PROFILER 3270 atomic_set(&prof->opt_time, prof->opt_time - profile_getclock()); 3271 #endif 3272 3273 #ifdef USE_TCG_OPTIMIZATIONS 3274 tcg_optimize(s); 3275 #endif 3276 3277 #ifdef CONFIG_PROFILER 3278 atomic_set(&prof->opt_time, prof->opt_time + profile_getclock()); 3279 atomic_set(&prof->la_time, prof->la_time - profile_getclock()); 3280 #endif 3281 3282 liveness_pass_1(s); 3283 3284 if (s->nb_indirects > 0) { 3285 #ifdef DEBUG_DISAS 3286 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_IND) 3287 && qemu_log_in_addr_range(tb->pc))) { 3288 qemu_log_lock(); 3289 qemu_log("OP before indirect lowering:\n"); 3290 tcg_dump_ops(s); 3291 qemu_log("\n"); 3292 qemu_log_unlock(); 3293 } 3294 #endif 3295 /* Replace indirect temps with direct temps. */ 3296 if (liveness_pass_2(s)) { 3297 /* If changes were made, re-run liveness. */ 3298 liveness_pass_1(s); 3299 } 3300 } 3301 3302 #ifdef CONFIG_PROFILER 3303 atomic_set(&prof->la_time, prof->la_time + profile_getclock()); 3304 #endif 3305 3306 #ifdef DEBUG_DISAS 3307 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT) 3308 && qemu_log_in_addr_range(tb->pc))) { 3309 qemu_log_lock(); 3310 qemu_log("OP after optimization and liveness analysis:\n"); 3311 tcg_dump_ops(s); 3312 qemu_log("\n"); 3313 qemu_log_unlock(); 3314 } 3315 #endif 3316 3317 tcg_reg_alloc_start(s); 3318 3319 s->code_buf = tb->tc.ptr; 3320 s->code_ptr = tb->tc.ptr; 3321 3322 #ifdef TCG_TARGET_NEED_LDST_LABELS 3323 s->ldst_labels = NULL; 3324 #endif 3325 #ifdef TCG_TARGET_NEED_POOL_LABELS 3326 s->pool_labels = NULL; 3327 #endif 3328 3329 num_insns = -1; 3330 QTAILQ_FOREACH(op, &s->ops, link) { 3331 TCGOpcode opc = op->opc; 3332 3333 #ifdef CONFIG_PROFILER 3334 atomic_set(&prof->table_op_count[opc], prof->table_op_count[opc] + 1); 3335 #endif 3336 3337 switch (opc) { 3338 case INDEX_op_mov_i32: 3339 case INDEX_op_mov_i64: 3340 case INDEX_op_mov_vec: 3341 tcg_reg_alloc_mov(s, op); 3342 break; 3343 case INDEX_op_movi_i32: 3344 case INDEX_op_movi_i64: 3345 case INDEX_op_dupi_vec: 3346 tcg_reg_alloc_movi(s, op); 3347 break; 3348 case INDEX_op_insn_start: 3349 if (num_insns >= 0) { 3350 s->gen_insn_end_off[num_insns] = tcg_current_code_size(s); 3351 } 3352 num_insns++; 3353 for (i = 0; i < TARGET_INSN_START_WORDS; ++i) { 3354 target_ulong a; 3355 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS 3356 a = deposit64(op->args[i * 2], 32, 32, op->args[i * 2 + 1]); 3357 #else 3358 a = op->args[i]; 3359 #endif 3360 s->gen_insn_data[num_insns][i] = a; 3361 } 3362 break; 3363 case INDEX_op_discard: 3364 temp_dead(s, arg_temp(op->args[0])); 3365 break; 3366 case INDEX_op_set_label: 3367 tcg_reg_alloc_bb_end(s, s->reserved_regs); 3368 tcg_out_label(s, arg_label(op->args[0]), s->code_ptr); 3369 break; 3370 case INDEX_op_call: 3371 tcg_reg_alloc_call(s, op); 3372 break; 3373 default: 3374 /* Sanity check that we've not introduced any unhandled opcodes. */ 3375 tcg_debug_assert(tcg_op_supported(opc)); 3376 /* Note: in order to speed up the code, it would be much 3377 faster to have specialized register allocator functions for 3378 some common argument patterns */ 3379 tcg_reg_alloc_op(s, op); 3380 break; 3381 } 3382 #ifdef CONFIG_DEBUG_TCG 3383 check_regs(s); 3384 #endif 3385 /* Test for (pending) buffer overflow. The assumption is that any 3386 one operation beginning below the high water mark cannot overrun 3387 the buffer completely. Thus we can test for overflow after 3388 generating code without having to check during generation. */ 3389 if (unlikely((void *)s->code_ptr > s->code_gen_highwater)) { 3390 return -1; 3391 } 3392 } 3393 tcg_debug_assert(num_insns >= 0); 3394 s->gen_insn_end_off[num_insns] = tcg_current_code_size(s); 3395 3396 /* Generate TB finalization at the end of block */ 3397 #ifdef TCG_TARGET_NEED_LDST_LABELS 3398 if (!tcg_out_ldst_finalize(s)) { 3399 return -1; 3400 } 3401 #endif 3402 #ifdef TCG_TARGET_NEED_POOL_LABELS 3403 if (!tcg_out_pool_finalize(s)) { 3404 return -1; 3405 } 3406 #endif 3407 3408 /* flush instruction cache */ 3409 flush_icache_range((uintptr_t)s->code_buf, (uintptr_t)s->code_ptr); 3410 3411 return tcg_current_code_size(s); 3412 } 3413 3414 #ifdef CONFIG_PROFILER 3415 void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf) 3416 { 3417 TCGProfile prof = {}; 3418 const TCGProfile *s; 3419 int64_t tb_count; 3420 int64_t tb_div_count; 3421 int64_t tot; 3422 3423 tcg_profile_snapshot_counters(&prof); 3424 s = &prof; 3425 tb_count = s->tb_count; 3426 tb_div_count = tb_count ? tb_count : 1; 3427 tot = s->interm_time + s->code_time; 3428 3429 cpu_fprintf(f, "JIT cycles %" PRId64 " (%0.3f s at 2.4 GHz)\n", 3430 tot, tot / 2.4e9); 3431 cpu_fprintf(f, "translated TBs %" PRId64 " (aborted=%" PRId64 " %0.1f%%)\n", 3432 tb_count, s->tb_count1 - tb_count, 3433 (double)(s->tb_count1 - s->tb_count) 3434 / (s->tb_count1 ? s->tb_count1 : 1) * 100.0); 3435 cpu_fprintf(f, "avg ops/TB %0.1f max=%d\n", 3436 (double)s->op_count / tb_div_count, s->op_count_max); 3437 cpu_fprintf(f, "deleted ops/TB %0.2f\n", 3438 (double)s->del_op_count / tb_div_count); 3439 cpu_fprintf(f, "avg temps/TB %0.2f max=%d\n", 3440 (double)s->temp_count / tb_div_count, s->temp_count_max); 3441 cpu_fprintf(f, "avg host code/TB %0.1f\n", 3442 (double)s->code_out_len / tb_div_count); 3443 cpu_fprintf(f, "avg search data/TB %0.1f\n", 3444 (double)s->search_out_len / tb_div_count); 3445 3446 cpu_fprintf(f, "cycles/op %0.1f\n", 3447 s->op_count ? (double)tot / s->op_count : 0); 3448 cpu_fprintf(f, "cycles/in byte %0.1f\n", 3449 s->code_in_len ? (double)tot / s->code_in_len : 0); 3450 cpu_fprintf(f, "cycles/out byte %0.1f\n", 3451 s->code_out_len ? (double)tot / s->code_out_len : 0); 3452 cpu_fprintf(f, "cycles/search byte %0.1f\n", 3453 s->search_out_len ? (double)tot / s->search_out_len : 0); 3454 if (tot == 0) { 3455 tot = 1; 3456 } 3457 cpu_fprintf(f, " gen_interm time %0.1f%%\n", 3458 (double)s->interm_time / tot * 100.0); 3459 cpu_fprintf(f, " gen_code time %0.1f%%\n", 3460 (double)s->code_time / tot * 100.0); 3461 cpu_fprintf(f, "optim./code time %0.1f%%\n", 3462 (double)s->opt_time / (s->code_time ? s->code_time : 1) 3463 * 100.0); 3464 cpu_fprintf(f, "liveness/code time %0.1f%%\n", 3465 (double)s->la_time / (s->code_time ? s->code_time : 1) * 100.0); 3466 cpu_fprintf(f, "cpu_restore count %" PRId64 "\n", 3467 s->restore_count); 3468 cpu_fprintf(f, " avg cycles %0.1f\n", 3469 s->restore_count ? (double)s->restore_time / s->restore_count : 0); 3470 } 3471 #else 3472 void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf) 3473 { 3474 cpu_fprintf(f, "[TCG profiler not compiled]\n"); 3475 } 3476 #endif 3477 3478 #ifdef ELF_HOST_MACHINE 3479 /* In order to use this feature, the backend needs to do three things: 3480 3481 (1) Define ELF_HOST_MACHINE to indicate both what value to 3482 put into the ELF image and to indicate support for the feature. 3483 3484 (2) Define tcg_register_jit. This should create a buffer containing 3485 the contents of a .debug_frame section that describes the post- 3486 prologue unwind info for the tcg machine. 3487 3488 (3) Call tcg_register_jit_int, with the constructed .debug_frame. 3489 */ 3490 3491 /* Begin GDB interface. THE FOLLOWING MUST MATCH GDB DOCS. */ 3492 typedef enum { 3493 JIT_NOACTION = 0, 3494 JIT_REGISTER_FN, 3495 JIT_UNREGISTER_FN 3496 } jit_actions_t; 3497 3498 struct jit_code_entry { 3499 struct jit_code_entry *next_entry; 3500 struct jit_code_entry *prev_entry; 3501 const void *symfile_addr; 3502 uint64_t symfile_size; 3503 }; 3504 3505 struct jit_descriptor { 3506 uint32_t version; 3507 uint32_t action_flag; 3508 struct jit_code_entry *relevant_entry; 3509 struct jit_code_entry *first_entry; 3510 }; 3511 3512 void __jit_debug_register_code(void) __attribute__((noinline)); 3513 void __jit_debug_register_code(void) 3514 { 3515 asm(""); 3516 } 3517 3518 /* Must statically initialize the version, because GDB may check 3519 the version before we can set it. */ 3520 struct jit_descriptor __jit_debug_descriptor = { 1, 0, 0, 0 }; 3521 3522 /* End GDB interface. */ 3523 3524 static int find_string(const char *strtab, const char *str) 3525 { 3526 const char *p = strtab + 1; 3527 3528 while (1) { 3529 if (strcmp(p, str) == 0) { 3530 return p - strtab; 3531 } 3532 p += strlen(p) + 1; 3533 } 3534 } 3535 3536 static void tcg_register_jit_int(void *buf_ptr, size_t buf_size, 3537 const void *debug_frame, 3538 size_t debug_frame_size) 3539 { 3540 struct __attribute__((packed)) DebugInfo { 3541 uint32_t len; 3542 uint16_t version; 3543 uint32_t abbrev; 3544 uint8_t ptr_size; 3545 uint8_t cu_die; 3546 uint16_t cu_lang; 3547 uintptr_t cu_low_pc; 3548 uintptr_t cu_high_pc; 3549 uint8_t fn_die; 3550 char fn_name[16]; 3551 uintptr_t fn_low_pc; 3552 uintptr_t fn_high_pc; 3553 uint8_t cu_eoc; 3554 }; 3555 3556 struct ElfImage { 3557 ElfW(Ehdr) ehdr; 3558 ElfW(Phdr) phdr; 3559 ElfW(Shdr) shdr[7]; 3560 ElfW(Sym) sym[2]; 3561 struct DebugInfo di; 3562 uint8_t da[24]; 3563 char str[80]; 3564 }; 3565 3566 struct ElfImage *img; 3567 3568 static const struct ElfImage img_template = { 3569 .ehdr = { 3570 .e_ident[EI_MAG0] = ELFMAG0, 3571 .e_ident[EI_MAG1] = ELFMAG1, 3572 .e_ident[EI_MAG2] = ELFMAG2, 3573 .e_ident[EI_MAG3] = ELFMAG3, 3574 .e_ident[EI_CLASS] = ELF_CLASS, 3575 .e_ident[EI_DATA] = ELF_DATA, 3576 .e_ident[EI_VERSION] = EV_CURRENT, 3577 .e_type = ET_EXEC, 3578 .e_machine = ELF_HOST_MACHINE, 3579 .e_version = EV_CURRENT, 3580 .e_phoff = offsetof(struct ElfImage, phdr), 3581 .e_shoff = offsetof(struct ElfImage, shdr), 3582 .e_ehsize = sizeof(ElfW(Shdr)), 3583 .e_phentsize = sizeof(ElfW(Phdr)), 3584 .e_phnum = 1, 3585 .e_shentsize = sizeof(ElfW(Shdr)), 3586 .e_shnum = ARRAY_SIZE(img->shdr), 3587 .e_shstrndx = ARRAY_SIZE(img->shdr) - 1, 3588 #ifdef ELF_HOST_FLAGS 3589 .e_flags = ELF_HOST_FLAGS, 3590 #endif 3591 #ifdef ELF_OSABI 3592 .e_ident[EI_OSABI] = ELF_OSABI, 3593 #endif 3594 }, 3595 .phdr = { 3596 .p_type = PT_LOAD, 3597 .p_flags = PF_X, 3598 }, 3599 .shdr = { 3600 [0] = { .sh_type = SHT_NULL }, 3601 /* Trick: The contents of code_gen_buffer are not present in 3602 this fake ELF file; that got allocated elsewhere. Therefore 3603 we mark .text as SHT_NOBITS (similar to .bss) so that readers 3604 will not look for contents. We can record any address. */ 3605 [1] = { /* .text */ 3606 .sh_type = SHT_NOBITS, 3607 .sh_flags = SHF_EXECINSTR | SHF_ALLOC, 3608 }, 3609 [2] = { /* .debug_info */ 3610 .sh_type = SHT_PROGBITS, 3611 .sh_offset = offsetof(struct ElfImage, di), 3612 .sh_size = sizeof(struct DebugInfo), 3613 }, 3614 [3] = { /* .debug_abbrev */ 3615 .sh_type = SHT_PROGBITS, 3616 .sh_offset = offsetof(struct ElfImage, da), 3617 .sh_size = sizeof(img->da), 3618 }, 3619 [4] = { /* .debug_frame */ 3620 .sh_type = SHT_PROGBITS, 3621 .sh_offset = sizeof(struct ElfImage), 3622 }, 3623 [5] = { /* .symtab */ 3624 .sh_type = SHT_SYMTAB, 3625 .sh_offset = offsetof(struct ElfImage, sym), 3626 .sh_size = sizeof(img->sym), 3627 .sh_info = 1, 3628 .sh_link = ARRAY_SIZE(img->shdr) - 1, 3629 .sh_entsize = sizeof(ElfW(Sym)), 3630 }, 3631 [6] = { /* .strtab */ 3632 .sh_type = SHT_STRTAB, 3633 .sh_offset = offsetof(struct ElfImage, str), 3634 .sh_size = sizeof(img->str), 3635 } 3636 }, 3637 .sym = { 3638 [1] = { /* code_gen_buffer */ 3639 .st_info = ELF_ST_INFO(STB_GLOBAL, STT_FUNC), 3640 .st_shndx = 1, 3641 } 3642 }, 3643 .di = { 3644 .len = sizeof(struct DebugInfo) - 4, 3645 .version = 2, 3646 .ptr_size = sizeof(void *), 3647 .cu_die = 1, 3648 .cu_lang = 0x8001, /* DW_LANG_Mips_Assembler */ 3649 .fn_die = 2, 3650 .fn_name = "code_gen_buffer" 3651 }, 3652 .da = { 3653 1, /* abbrev number (the cu) */ 3654 0x11, 1, /* DW_TAG_compile_unit, has children */ 3655 0x13, 0x5, /* DW_AT_language, DW_FORM_data2 */ 3656 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */ 3657 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */ 3658 0, 0, /* end of abbrev */ 3659 2, /* abbrev number (the fn) */ 3660 0x2e, 0, /* DW_TAG_subprogram, no children */ 3661 0x3, 0x8, /* DW_AT_name, DW_FORM_string */ 3662 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */ 3663 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */ 3664 0, 0, /* end of abbrev */ 3665 0 /* no more abbrev */ 3666 }, 3667 .str = "\0" ".text\0" ".debug_info\0" ".debug_abbrev\0" 3668 ".debug_frame\0" ".symtab\0" ".strtab\0" "code_gen_buffer", 3669 }; 3670 3671 /* We only need a single jit entry; statically allocate it. */ 3672 static struct jit_code_entry one_entry; 3673 3674 uintptr_t buf = (uintptr_t)buf_ptr; 3675 size_t img_size = sizeof(struct ElfImage) + debug_frame_size; 3676 DebugFrameHeader *dfh; 3677 3678 img = g_malloc(img_size); 3679 *img = img_template; 3680 3681 img->phdr.p_vaddr = buf; 3682 img->phdr.p_paddr = buf; 3683 img->phdr.p_memsz = buf_size; 3684 3685 img->shdr[1].sh_name = find_string(img->str, ".text"); 3686 img->shdr[1].sh_addr = buf; 3687 img->shdr[1].sh_size = buf_size; 3688 3689 img->shdr[2].sh_name = find_string(img->str, ".debug_info"); 3690 img->shdr[3].sh_name = find_string(img->str, ".debug_abbrev"); 3691 3692 img->shdr[4].sh_name = find_string(img->str, ".debug_frame"); 3693 img->shdr[4].sh_size = debug_frame_size; 3694 3695 img->shdr[5].sh_name = find_string(img->str, ".symtab"); 3696 img->shdr[6].sh_name = find_string(img->str, ".strtab"); 3697 3698 img->sym[1].st_name = find_string(img->str, "code_gen_buffer"); 3699 img->sym[1].st_value = buf; 3700 img->sym[1].st_size = buf_size; 3701 3702 img->di.cu_low_pc = buf; 3703 img->di.cu_high_pc = buf + buf_size; 3704 img->di.fn_low_pc = buf; 3705 img->di.fn_high_pc = buf + buf_size; 3706 3707 dfh = (DebugFrameHeader *)(img + 1); 3708 memcpy(dfh, debug_frame, debug_frame_size); 3709 dfh->fde.func_start = buf; 3710 dfh->fde.func_len = buf_size; 3711 3712 #ifdef DEBUG_JIT 3713 /* Enable this block to be able to debug the ELF image file creation. 3714 One can use readelf, objdump, or other inspection utilities. */ 3715 { 3716 FILE *f = fopen("/tmp/qemu.jit", "w+b"); 3717 if (f) { 3718 if (fwrite(img, img_size, 1, f) != img_size) { 3719 /* Avoid stupid unused return value warning for fwrite. */ 3720 } 3721 fclose(f); 3722 } 3723 } 3724 #endif 3725 3726 one_entry.symfile_addr = img; 3727 one_entry.symfile_size = img_size; 3728 3729 __jit_debug_descriptor.action_flag = JIT_REGISTER_FN; 3730 __jit_debug_descriptor.relevant_entry = &one_entry; 3731 __jit_debug_descriptor.first_entry = &one_entry; 3732 __jit_debug_register_code(); 3733 } 3734 #else 3735 /* No support for the feature. Provide the entry point expected by exec.c, 3736 and implement the internal function we declared earlier. */ 3737 3738 static void tcg_register_jit_int(void *buf, size_t size, 3739 const void *debug_frame, 3740 size_t debug_frame_size) 3741 { 3742 } 3743 3744 void tcg_register_jit(void *buf, size_t buf_size) 3745 { 3746 } 3747 #endif /* ELF_HOST_MACHINE */ 3748 3749 #if !TCG_TARGET_MAYBE_vec 3750 void tcg_expand_vec_op(TCGOpcode o, TCGType t, unsigned e, TCGArg a0, ...) 3751 { 3752 g_assert_not_reached(); 3753 } 3754 #endif 3755