1 /* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 27 /* Define to jump the ELF file used to communicate with GDB. */ 28 #undef DEBUG_JIT 29 30 #include "qemu/error-report.h" 31 #include "qemu/cutils.h" 32 #include "qemu/host-utils.h" 33 #include "qemu/qemu-print.h" 34 #include "qemu/cacheflush.h" 35 #include "qemu/cacheinfo.h" 36 #include "qemu/timer.h" 37 #include "exec/translation-block.h" 38 #include "exec/tlb-common.h" 39 #include "tcg/startup.h" 40 #include "tcg/tcg-op-common.h" 41 42 #if UINTPTR_MAX == UINT32_MAX 43 # define ELF_CLASS ELFCLASS32 44 #else 45 # define ELF_CLASS ELFCLASS64 46 #endif 47 #if HOST_BIG_ENDIAN 48 # define ELF_DATA ELFDATA2MSB 49 #else 50 # define ELF_DATA ELFDATA2LSB 51 #endif 52 53 #include "elf.h" 54 #include "exec/log.h" 55 #include "tcg/tcg-ldst.h" 56 #include "tcg/tcg-temp-internal.h" 57 #include "tcg-internal.h" 58 #include "tcg/perf.h" 59 #include "tcg-has.h" 60 #ifdef CONFIG_USER_ONLY 61 #include "user/guest-base.h" 62 #endif 63 64 /* Forward declarations for functions declared in tcg-target.c.inc and 65 used here. */ 66 static void tcg_target_init(TCGContext *s); 67 static void tcg_target_qemu_prologue(TCGContext *s); 68 static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 69 intptr_t value, intptr_t addend); 70 static void tcg_out_nop_fill(tcg_insn_unit *p, int count); 71 72 typedef struct TCGLabelQemuLdst TCGLabelQemuLdst; 73 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l); 74 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l); 75 76 /* The CIE and FDE header definitions will be common to all hosts. */ 77 typedef struct { 78 uint32_t len __attribute__((aligned((sizeof(void *))))); 79 uint32_t id; 80 uint8_t version; 81 char augmentation[1]; 82 uint8_t code_align; 83 uint8_t data_align; 84 uint8_t return_column; 85 } DebugFrameCIE; 86 87 typedef struct QEMU_PACKED { 88 uint32_t len __attribute__((aligned((sizeof(void *))))); 89 uint32_t cie_offset; 90 uintptr_t func_start; 91 uintptr_t func_len; 92 } DebugFrameFDEHeader; 93 94 typedef struct QEMU_PACKED { 95 DebugFrameCIE cie; 96 DebugFrameFDEHeader fde; 97 } DebugFrameHeader; 98 99 struct TCGLabelQemuLdst { 100 bool is_ld; /* qemu_ld: true, qemu_st: false */ 101 MemOpIdx oi; 102 TCGType type; /* result type of a load */ 103 TCGReg addr_reg; /* reg index for guest virtual addr */ 104 TCGReg datalo_reg; /* reg index for low word to be loaded or stored */ 105 TCGReg datahi_reg; /* reg index for high word to be loaded or stored */ 106 const tcg_insn_unit *raddr; /* addr of the next IR of qemu_ld/st IR */ 107 tcg_insn_unit *label_ptr[2]; /* label pointers to be updated */ 108 QSIMPLEQ_ENTRY(TCGLabelQemuLdst) next; 109 }; 110 111 static void tcg_register_jit_int(const void *buf, size_t size, 112 const void *debug_frame, 113 size_t debug_frame_size) 114 __attribute__((unused)); 115 116 /* Forward declarations for functions declared and used in tcg-target.c.inc. */ 117 static void tcg_out_tb_start(TCGContext *s); 118 static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1, 119 intptr_t arg2); 120 static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg); 121 static void tcg_out_movi(TCGContext *s, TCGType type, 122 TCGReg ret, tcg_target_long arg); 123 static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg); 124 static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg); 125 static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg); 126 static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg); 127 static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg); 128 static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg); 129 static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg); 130 static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg); 131 static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg ret, TCGReg arg); 132 static void tcg_out_addi_ptr(TCGContext *s, TCGReg, TCGReg, tcg_target_long); 133 static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2); 134 static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg); 135 static void tcg_out_goto_tb(TCGContext *s, int which); 136 static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, 137 const TCGArg args[TCG_MAX_OP_ARGS], 138 const int const_args[TCG_MAX_OP_ARGS]); 139 #if TCG_TARGET_MAYBE_vec 140 static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 141 TCGReg dst, TCGReg src); 142 static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 143 TCGReg dst, TCGReg base, intptr_t offset); 144 static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 145 TCGReg dst, int64_t arg); 146 static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 147 unsigned vecl, unsigned vece, 148 const TCGArg args[TCG_MAX_OP_ARGS], 149 const int const_args[TCG_MAX_OP_ARGS]); 150 #else 151 static inline bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 152 TCGReg dst, TCGReg src) 153 { 154 g_assert_not_reached(); 155 } 156 static inline bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 157 TCGReg dst, TCGReg base, intptr_t offset) 158 { 159 g_assert_not_reached(); 160 } 161 static inline void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 162 TCGReg dst, int64_t arg) 163 { 164 g_assert_not_reached(); 165 } 166 static inline void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 167 unsigned vecl, unsigned vece, 168 const TCGArg args[TCG_MAX_OP_ARGS], 169 const int const_args[TCG_MAX_OP_ARGS]) 170 { 171 g_assert_not_reached(); 172 } 173 int tcg_can_emit_vec_op(TCGOpcode o, TCGType t, unsigned ve) 174 { 175 return 0; 176 } 177 #endif 178 static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1, 179 intptr_t arg2); 180 static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 181 TCGReg base, intptr_t ofs); 182 static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target, 183 const TCGHelperInfo *info); 184 static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot); 185 static bool tcg_target_const_match(int64_t val, int ct, 186 TCGType type, TCGCond cond, int vece); 187 188 #ifndef CONFIG_USER_ONLY 189 #define guest_base ({ qemu_build_not_reached(); (uintptr_t)0; }) 190 #endif 191 192 typedef struct TCGLdstHelperParam { 193 TCGReg (*ra_gen)(TCGContext *s, const TCGLabelQemuLdst *l, int arg_reg); 194 unsigned ntmp; 195 int tmp[3]; 196 } TCGLdstHelperParam; 197 198 static void tcg_out_ld_helper_args(TCGContext *s, const TCGLabelQemuLdst *l, 199 const TCGLdstHelperParam *p) 200 __attribute__((unused)); 201 static void tcg_out_ld_helper_ret(TCGContext *s, const TCGLabelQemuLdst *l, 202 bool load_sign, const TCGLdstHelperParam *p) 203 __attribute__((unused)); 204 static void tcg_out_st_helper_args(TCGContext *s, const TCGLabelQemuLdst *l, 205 const TCGLdstHelperParam *p) 206 __attribute__((unused)); 207 208 static void * const qemu_ld_helpers[MO_SSIZE + 1] __attribute__((unused)) = { 209 [MO_UB] = helper_ldub_mmu, 210 [MO_SB] = helper_ldsb_mmu, 211 [MO_UW] = helper_lduw_mmu, 212 [MO_SW] = helper_ldsw_mmu, 213 [MO_UL] = helper_ldul_mmu, 214 [MO_UQ] = helper_ldq_mmu, 215 #if TCG_TARGET_REG_BITS == 64 216 [MO_SL] = helper_ldsl_mmu, 217 [MO_128] = helper_ld16_mmu, 218 #endif 219 }; 220 221 static void * const qemu_st_helpers[MO_SIZE + 1] __attribute__((unused)) = { 222 [MO_8] = helper_stb_mmu, 223 [MO_16] = helper_stw_mmu, 224 [MO_32] = helper_stl_mmu, 225 [MO_64] = helper_stq_mmu, 226 #if TCG_TARGET_REG_BITS == 64 227 [MO_128] = helper_st16_mmu, 228 #endif 229 }; 230 231 typedef struct { 232 MemOp atom; /* lg2 bits of atomicity required */ 233 MemOp align; /* lg2 bits of alignment to use */ 234 } TCGAtomAlign; 235 236 static TCGAtomAlign atom_and_align_for_opc(TCGContext *s, MemOp opc, 237 MemOp host_atom, bool allow_two_ops) 238 __attribute__((unused)); 239 240 #ifdef CONFIG_USER_ONLY 241 bool tcg_use_softmmu; 242 #endif 243 244 TCGContext tcg_init_ctx; 245 __thread TCGContext *tcg_ctx; 246 247 TCGContext **tcg_ctxs; 248 unsigned int tcg_cur_ctxs; 249 unsigned int tcg_max_ctxs; 250 TCGv_env tcg_env; 251 const void *tcg_code_gen_epilogue; 252 uintptr_t tcg_splitwx_diff; 253 254 #ifndef CONFIG_TCG_INTERPRETER 255 tcg_prologue_fn *tcg_qemu_tb_exec; 256 #endif 257 258 static TCGRegSet tcg_target_available_regs[TCG_TYPE_COUNT]; 259 static TCGRegSet tcg_target_call_clobber_regs; 260 261 #if TCG_TARGET_INSN_UNIT_SIZE == 1 262 static __attribute__((unused)) inline void tcg_out8(TCGContext *s, uint8_t v) 263 { 264 *s->code_ptr++ = v; 265 } 266 267 static __attribute__((unused)) inline void tcg_patch8(tcg_insn_unit *p, 268 uint8_t v) 269 { 270 *p = v; 271 } 272 #endif 273 274 #if TCG_TARGET_INSN_UNIT_SIZE <= 2 275 static __attribute__((unused)) inline void tcg_out16(TCGContext *s, uint16_t v) 276 { 277 if (TCG_TARGET_INSN_UNIT_SIZE == 2) { 278 *s->code_ptr++ = v; 279 } else { 280 tcg_insn_unit *p = s->code_ptr; 281 memcpy(p, &v, sizeof(v)); 282 s->code_ptr = p + (2 / TCG_TARGET_INSN_UNIT_SIZE); 283 } 284 } 285 286 static __attribute__((unused)) inline void tcg_patch16(tcg_insn_unit *p, 287 uint16_t v) 288 { 289 if (TCG_TARGET_INSN_UNIT_SIZE == 2) { 290 *p = v; 291 } else { 292 memcpy(p, &v, sizeof(v)); 293 } 294 } 295 #endif 296 297 #if TCG_TARGET_INSN_UNIT_SIZE <= 4 298 static __attribute__((unused)) inline void tcg_out32(TCGContext *s, uint32_t v) 299 { 300 if (TCG_TARGET_INSN_UNIT_SIZE == 4) { 301 *s->code_ptr++ = v; 302 } else { 303 tcg_insn_unit *p = s->code_ptr; 304 memcpy(p, &v, sizeof(v)); 305 s->code_ptr = p + (4 / TCG_TARGET_INSN_UNIT_SIZE); 306 } 307 } 308 309 static __attribute__((unused)) inline void tcg_patch32(tcg_insn_unit *p, 310 uint32_t v) 311 { 312 if (TCG_TARGET_INSN_UNIT_SIZE == 4) { 313 *p = v; 314 } else { 315 memcpy(p, &v, sizeof(v)); 316 } 317 } 318 #endif 319 320 #if TCG_TARGET_INSN_UNIT_SIZE <= 8 321 static __attribute__((unused)) inline void tcg_out64(TCGContext *s, uint64_t v) 322 { 323 if (TCG_TARGET_INSN_UNIT_SIZE == 8) { 324 *s->code_ptr++ = v; 325 } else { 326 tcg_insn_unit *p = s->code_ptr; 327 memcpy(p, &v, sizeof(v)); 328 s->code_ptr = p + (8 / TCG_TARGET_INSN_UNIT_SIZE); 329 } 330 } 331 332 static __attribute__((unused)) inline void tcg_patch64(tcg_insn_unit *p, 333 uint64_t v) 334 { 335 if (TCG_TARGET_INSN_UNIT_SIZE == 8) { 336 *p = v; 337 } else { 338 memcpy(p, &v, sizeof(v)); 339 } 340 } 341 #endif 342 343 /* label relocation processing */ 344 345 static void tcg_out_reloc(TCGContext *s, tcg_insn_unit *code_ptr, int type, 346 TCGLabel *l, intptr_t addend) 347 { 348 TCGRelocation *r = tcg_malloc(sizeof(TCGRelocation)); 349 350 r->type = type; 351 r->ptr = code_ptr; 352 r->addend = addend; 353 QSIMPLEQ_INSERT_TAIL(&l->relocs, r, next); 354 } 355 356 static void tcg_out_label(TCGContext *s, TCGLabel *l) 357 { 358 tcg_debug_assert(!l->has_value); 359 l->has_value = 1; 360 l->u.value_ptr = tcg_splitwx_to_rx(s->code_ptr); 361 } 362 363 TCGLabel *gen_new_label(void) 364 { 365 TCGContext *s = tcg_ctx; 366 TCGLabel *l = tcg_malloc(sizeof(TCGLabel)); 367 368 memset(l, 0, sizeof(TCGLabel)); 369 l->id = s->nb_labels++; 370 QSIMPLEQ_INIT(&l->branches); 371 QSIMPLEQ_INIT(&l->relocs); 372 373 QSIMPLEQ_INSERT_TAIL(&s->labels, l, next); 374 375 return l; 376 } 377 378 static bool tcg_resolve_relocs(TCGContext *s) 379 { 380 TCGLabel *l; 381 382 QSIMPLEQ_FOREACH(l, &s->labels, next) { 383 TCGRelocation *r; 384 uintptr_t value = l->u.value; 385 386 QSIMPLEQ_FOREACH(r, &l->relocs, next) { 387 if (!patch_reloc(r->ptr, r->type, value, r->addend)) { 388 return false; 389 } 390 } 391 } 392 return true; 393 } 394 395 static void set_jmp_reset_offset(TCGContext *s, int which) 396 { 397 /* 398 * We will check for overflow at the end of the opcode loop in 399 * tcg_gen_code, where we bound tcg_current_code_size to UINT16_MAX. 400 */ 401 s->gen_tb->jmp_reset_offset[which] = tcg_current_code_size(s); 402 } 403 404 static void G_GNUC_UNUSED set_jmp_insn_offset(TCGContext *s, int which) 405 { 406 /* 407 * We will check for overflow at the end of the opcode loop in 408 * tcg_gen_code, where we bound tcg_current_code_size to UINT16_MAX. 409 */ 410 s->gen_tb->jmp_insn_offset[which] = tcg_current_code_size(s); 411 } 412 413 static uintptr_t G_GNUC_UNUSED get_jmp_target_addr(TCGContext *s, int which) 414 { 415 /* 416 * Return the read-execute version of the pointer, for the benefit 417 * of any pc-relative addressing mode. 418 */ 419 return (uintptr_t)tcg_splitwx_to_rx(&s->gen_tb->jmp_target_addr[which]); 420 } 421 422 static int __attribute__((unused)) 423 tlb_mask_table_ofs(TCGContext *s, int which) 424 { 425 return (offsetof(CPUNegativeOffsetState, tlb.f[which]) - 426 sizeof(CPUNegativeOffsetState)); 427 } 428 429 /* Signal overflow, starting over with fewer guest insns. */ 430 static G_NORETURN 431 void tcg_raise_tb_overflow(TCGContext *s) 432 { 433 siglongjmp(s->jmp_trans, -2); 434 } 435 436 /* 437 * Used by tcg_out_movext{1,2} to hold the arguments for tcg_out_movext. 438 * By the time we arrive at tcg_out_movext1, @dst is always a TCGReg. 439 * 440 * However, tcg_out_helper_load_slots reuses this field to hold an 441 * argument slot number (which may designate a argument register or an 442 * argument stack slot), converting to TCGReg once all arguments that 443 * are destined for the stack are processed. 444 */ 445 typedef struct TCGMovExtend { 446 unsigned dst; 447 TCGReg src; 448 TCGType dst_type; 449 TCGType src_type; 450 MemOp src_ext; 451 } TCGMovExtend; 452 453 /** 454 * tcg_out_movext -- move and extend 455 * @s: tcg context 456 * @dst_type: integral type for destination 457 * @dst: destination register 458 * @src_type: integral type for source 459 * @src_ext: extension to apply to source 460 * @src: source register 461 * 462 * Move or extend @src into @dst, depending on @src_ext and the types. 463 */ 464 static void tcg_out_movext(TCGContext *s, TCGType dst_type, TCGReg dst, 465 TCGType src_type, MemOp src_ext, TCGReg src) 466 { 467 switch (src_ext) { 468 case MO_UB: 469 tcg_out_ext8u(s, dst, src); 470 break; 471 case MO_SB: 472 tcg_out_ext8s(s, dst_type, dst, src); 473 break; 474 case MO_UW: 475 tcg_out_ext16u(s, dst, src); 476 break; 477 case MO_SW: 478 tcg_out_ext16s(s, dst_type, dst, src); 479 break; 480 case MO_UL: 481 case MO_SL: 482 if (dst_type == TCG_TYPE_I32) { 483 if (src_type == TCG_TYPE_I32) { 484 tcg_out_mov(s, TCG_TYPE_I32, dst, src); 485 } else { 486 tcg_out_extrl_i64_i32(s, dst, src); 487 } 488 } else if (src_type == TCG_TYPE_I32) { 489 if (src_ext & MO_SIGN) { 490 tcg_out_exts_i32_i64(s, dst, src); 491 } else { 492 tcg_out_extu_i32_i64(s, dst, src); 493 } 494 } else { 495 if (src_ext & MO_SIGN) { 496 tcg_out_ext32s(s, dst, src); 497 } else { 498 tcg_out_ext32u(s, dst, src); 499 } 500 } 501 break; 502 case MO_UQ: 503 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 504 if (dst_type == TCG_TYPE_I32) { 505 tcg_out_extrl_i64_i32(s, dst, src); 506 } else { 507 tcg_out_mov(s, TCG_TYPE_I64, dst, src); 508 } 509 break; 510 default: 511 g_assert_not_reached(); 512 } 513 } 514 515 /* Minor variations on a theme, using a structure. */ 516 static void tcg_out_movext1_new_src(TCGContext *s, const TCGMovExtend *i, 517 TCGReg src) 518 { 519 tcg_out_movext(s, i->dst_type, i->dst, i->src_type, i->src_ext, src); 520 } 521 522 static void tcg_out_movext1(TCGContext *s, const TCGMovExtend *i) 523 { 524 tcg_out_movext1_new_src(s, i, i->src); 525 } 526 527 /** 528 * tcg_out_movext2 -- move and extend two pair 529 * @s: tcg context 530 * @i1: first move description 531 * @i2: second move description 532 * @scratch: temporary register, or -1 for none 533 * 534 * As tcg_out_movext, for both @i1 and @i2, caring for overlap 535 * between the sources and destinations. 536 */ 537 538 static void tcg_out_movext2(TCGContext *s, const TCGMovExtend *i1, 539 const TCGMovExtend *i2, int scratch) 540 { 541 TCGReg src1 = i1->src; 542 TCGReg src2 = i2->src; 543 544 if (i1->dst != src2) { 545 tcg_out_movext1(s, i1); 546 tcg_out_movext1(s, i2); 547 return; 548 } 549 if (i2->dst == src1) { 550 TCGType src1_type = i1->src_type; 551 TCGType src2_type = i2->src_type; 552 553 if (tcg_out_xchg(s, MAX(src1_type, src2_type), src1, src2)) { 554 /* The data is now in the correct registers, now extend. */ 555 src1 = i2->src; 556 src2 = i1->src; 557 } else { 558 tcg_debug_assert(scratch >= 0); 559 tcg_out_mov(s, src1_type, scratch, src1); 560 src1 = scratch; 561 } 562 } 563 tcg_out_movext1_new_src(s, i2, src2); 564 tcg_out_movext1_new_src(s, i1, src1); 565 } 566 567 /** 568 * tcg_out_movext3 -- move and extend three pair 569 * @s: tcg context 570 * @i1: first move description 571 * @i2: second move description 572 * @i3: third move description 573 * @scratch: temporary register, or -1 for none 574 * 575 * As tcg_out_movext, for all of @i1, @i2 and @i3, caring for overlap 576 * between the sources and destinations. 577 */ 578 579 static void tcg_out_movext3(TCGContext *s, const TCGMovExtend *i1, 580 const TCGMovExtend *i2, const TCGMovExtend *i3, 581 int scratch) 582 { 583 TCGReg src1 = i1->src; 584 TCGReg src2 = i2->src; 585 TCGReg src3 = i3->src; 586 587 if (i1->dst != src2 && i1->dst != src3) { 588 tcg_out_movext1(s, i1); 589 tcg_out_movext2(s, i2, i3, scratch); 590 return; 591 } 592 if (i2->dst != src1 && i2->dst != src3) { 593 tcg_out_movext1(s, i2); 594 tcg_out_movext2(s, i1, i3, scratch); 595 return; 596 } 597 if (i3->dst != src1 && i3->dst != src2) { 598 tcg_out_movext1(s, i3); 599 tcg_out_movext2(s, i1, i2, scratch); 600 return; 601 } 602 603 /* 604 * There is a cycle. Since there are only 3 nodes, the cycle is 605 * either "clockwise" or "anti-clockwise", and can be solved with 606 * a single scratch or two xchg. 607 */ 608 if (i1->dst == src2 && i2->dst == src3 && i3->dst == src1) { 609 /* "Clockwise" */ 610 if (tcg_out_xchg(s, MAX(i1->src_type, i2->src_type), src1, src2)) { 611 tcg_out_xchg(s, MAX(i2->src_type, i3->src_type), src2, src3); 612 /* The data is now in the correct registers, now extend. */ 613 tcg_out_movext1_new_src(s, i1, i1->dst); 614 tcg_out_movext1_new_src(s, i2, i2->dst); 615 tcg_out_movext1_new_src(s, i3, i3->dst); 616 } else { 617 tcg_debug_assert(scratch >= 0); 618 tcg_out_mov(s, i1->src_type, scratch, src1); 619 tcg_out_movext1(s, i3); 620 tcg_out_movext1(s, i2); 621 tcg_out_movext1_new_src(s, i1, scratch); 622 } 623 } else if (i1->dst == src3 && i2->dst == src1 && i3->dst == src2) { 624 /* "Anti-clockwise" */ 625 if (tcg_out_xchg(s, MAX(i2->src_type, i3->src_type), src2, src3)) { 626 tcg_out_xchg(s, MAX(i1->src_type, i2->src_type), src1, src2); 627 /* The data is now in the correct registers, now extend. */ 628 tcg_out_movext1_new_src(s, i1, i1->dst); 629 tcg_out_movext1_new_src(s, i2, i2->dst); 630 tcg_out_movext1_new_src(s, i3, i3->dst); 631 } else { 632 tcg_debug_assert(scratch >= 0); 633 tcg_out_mov(s, i1->src_type, scratch, src1); 634 tcg_out_movext1(s, i2); 635 tcg_out_movext1(s, i3); 636 tcg_out_movext1_new_src(s, i1, scratch); 637 } 638 } else { 639 g_assert_not_reached(); 640 } 641 } 642 643 /* 644 * Allocate a new TCGLabelQemuLdst entry. 645 */ 646 647 __attribute__((unused)) 648 static TCGLabelQemuLdst *new_ldst_label(TCGContext *s) 649 { 650 TCGLabelQemuLdst *l = tcg_malloc(sizeof(*l)); 651 652 memset(l, 0, sizeof(*l)); 653 QSIMPLEQ_INSERT_TAIL(&s->ldst_labels, l, next); 654 655 return l; 656 } 657 658 /* 659 * Allocate new constant pool entries. 660 */ 661 662 typedef struct TCGLabelPoolData { 663 struct TCGLabelPoolData *next; 664 tcg_insn_unit *label; 665 intptr_t addend; 666 int rtype; 667 unsigned nlong; 668 tcg_target_ulong data[]; 669 } TCGLabelPoolData; 670 671 static TCGLabelPoolData *new_pool_alloc(TCGContext *s, int nlong, int rtype, 672 tcg_insn_unit *label, intptr_t addend) 673 { 674 TCGLabelPoolData *n = tcg_malloc(sizeof(TCGLabelPoolData) 675 + sizeof(tcg_target_ulong) * nlong); 676 677 n->label = label; 678 n->addend = addend; 679 n->rtype = rtype; 680 n->nlong = nlong; 681 return n; 682 } 683 684 static void new_pool_insert(TCGContext *s, TCGLabelPoolData *n) 685 { 686 TCGLabelPoolData *i, **pp; 687 int nlong = n->nlong; 688 689 /* Insertion sort on the pool. */ 690 for (pp = &s->pool_labels; (i = *pp) != NULL; pp = &i->next) { 691 if (nlong > i->nlong) { 692 break; 693 } 694 if (nlong < i->nlong) { 695 continue; 696 } 697 if (memcmp(n->data, i->data, sizeof(tcg_target_ulong) * nlong) >= 0) { 698 break; 699 } 700 } 701 n->next = *pp; 702 *pp = n; 703 } 704 705 /* The "usual" for generic integer code. */ 706 __attribute__((unused)) 707 static void new_pool_label(TCGContext *s, tcg_target_ulong d, int rtype, 708 tcg_insn_unit *label, intptr_t addend) 709 { 710 TCGLabelPoolData *n = new_pool_alloc(s, 1, rtype, label, addend); 711 n->data[0] = d; 712 new_pool_insert(s, n); 713 } 714 715 /* For v64 or v128, depending on the host. */ 716 __attribute__((unused)) 717 static void new_pool_l2(TCGContext *s, int rtype, tcg_insn_unit *label, 718 intptr_t addend, tcg_target_ulong d0, 719 tcg_target_ulong d1) 720 { 721 TCGLabelPoolData *n = new_pool_alloc(s, 2, rtype, label, addend); 722 n->data[0] = d0; 723 n->data[1] = d1; 724 new_pool_insert(s, n); 725 } 726 727 /* For v128 or v256, depending on the host. */ 728 __attribute__((unused)) 729 static void new_pool_l4(TCGContext *s, int rtype, tcg_insn_unit *label, 730 intptr_t addend, tcg_target_ulong d0, 731 tcg_target_ulong d1, tcg_target_ulong d2, 732 tcg_target_ulong d3) 733 { 734 TCGLabelPoolData *n = new_pool_alloc(s, 4, rtype, label, addend); 735 n->data[0] = d0; 736 n->data[1] = d1; 737 n->data[2] = d2; 738 n->data[3] = d3; 739 new_pool_insert(s, n); 740 } 741 742 /* For v256, for 32-bit host. */ 743 __attribute__((unused)) 744 static void new_pool_l8(TCGContext *s, int rtype, tcg_insn_unit *label, 745 intptr_t addend, tcg_target_ulong d0, 746 tcg_target_ulong d1, tcg_target_ulong d2, 747 tcg_target_ulong d3, tcg_target_ulong d4, 748 tcg_target_ulong d5, tcg_target_ulong d6, 749 tcg_target_ulong d7) 750 { 751 TCGLabelPoolData *n = new_pool_alloc(s, 8, rtype, label, addend); 752 n->data[0] = d0; 753 n->data[1] = d1; 754 n->data[2] = d2; 755 n->data[3] = d3; 756 n->data[4] = d4; 757 n->data[5] = d5; 758 n->data[6] = d6; 759 n->data[7] = d7; 760 new_pool_insert(s, n); 761 } 762 763 /* 764 * Generate TB finalization at the end of block 765 */ 766 767 static int tcg_out_ldst_finalize(TCGContext *s) 768 { 769 TCGLabelQemuLdst *lb; 770 771 /* qemu_ld/st slow paths */ 772 QSIMPLEQ_FOREACH(lb, &s->ldst_labels, next) { 773 if (lb->is_ld 774 ? !tcg_out_qemu_ld_slow_path(s, lb) 775 : !tcg_out_qemu_st_slow_path(s, lb)) { 776 return -2; 777 } 778 779 /* 780 * Test for (pending) buffer overflow. The assumption is that any 781 * one operation beginning below the high water mark cannot overrun 782 * the buffer completely. Thus we can test for overflow after 783 * generating code without having to check during generation. 784 */ 785 if (unlikely((void *)s->code_ptr > s->code_gen_highwater)) { 786 return -1; 787 } 788 } 789 return 0; 790 } 791 792 static int tcg_out_pool_finalize(TCGContext *s) 793 { 794 TCGLabelPoolData *p = s->pool_labels; 795 TCGLabelPoolData *l = NULL; 796 void *a; 797 798 if (p == NULL) { 799 return 0; 800 } 801 802 /* 803 * ??? Round up to qemu_icache_linesize, but then do not round 804 * again when allocating the next TranslationBlock structure. 805 */ 806 a = (void *)ROUND_UP((uintptr_t)s->code_ptr, 807 sizeof(tcg_target_ulong) * p->nlong); 808 tcg_out_nop_fill(s->code_ptr, (tcg_insn_unit *)a - s->code_ptr); 809 s->data_gen_ptr = a; 810 811 for (; p != NULL; p = p->next) { 812 size_t size = sizeof(tcg_target_ulong) * p->nlong; 813 uintptr_t value; 814 815 if (!l || l->nlong != p->nlong || memcmp(l->data, p->data, size)) { 816 if (unlikely(a > s->code_gen_highwater)) { 817 return -1; 818 } 819 memcpy(a, p->data, size); 820 a += size; 821 l = p; 822 } 823 824 value = (uintptr_t)tcg_splitwx_to_rx(a) - size; 825 if (!patch_reloc(p->label, p->rtype, value, p->addend)) { 826 return -2; 827 } 828 } 829 830 s->code_ptr = a; 831 return 0; 832 } 833 834 #define C_PFX1(P, A) P##A 835 #define C_PFX2(P, A, B) P##A##_##B 836 #define C_PFX3(P, A, B, C) P##A##_##B##_##C 837 #define C_PFX4(P, A, B, C, D) P##A##_##B##_##C##_##D 838 #define C_PFX5(P, A, B, C, D, E) P##A##_##B##_##C##_##D##_##E 839 #define C_PFX6(P, A, B, C, D, E, F) P##A##_##B##_##C##_##D##_##E##_##F 840 841 /* Define an enumeration for the various combinations. */ 842 843 #define C_O0_I1(I1) C_PFX1(c_o0_i1_, I1), 844 #define C_O0_I2(I1, I2) C_PFX2(c_o0_i2_, I1, I2), 845 #define C_O0_I3(I1, I2, I3) C_PFX3(c_o0_i3_, I1, I2, I3), 846 #define C_O0_I4(I1, I2, I3, I4) C_PFX4(c_o0_i4_, I1, I2, I3, I4), 847 848 #define C_O1_I1(O1, I1) C_PFX2(c_o1_i1_, O1, I1), 849 #define C_O1_I2(O1, I1, I2) C_PFX3(c_o1_i2_, O1, I1, I2), 850 #define C_O1_I3(O1, I1, I2, I3) C_PFX4(c_o1_i3_, O1, I1, I2, I3), 851 #define C_O1_I4(O1, I1, I2, I3, I4) C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4), 852 853 #define C_N1_I2(O1, I1, I2) C_PFX3(c_n1_i2_, O1, I1, I2), 854 #define C_N1O1_I1(O1, O2, I1) C_PFX3(c_n1o1_i1_, O1, O2, I1), 855 #define C_N2_I1(O1, O2, I1) C_PFX3(c_n2_i1_, O1, O2, I1), 856 857 #define C_O2_I1(O1, O2, I1) C_PFX3(c_o2_i1_, O1, O2, I1), 858 #define C_O2_I2(O1, O2, I1, I2) C_PFX4(c_o2_i2_, O1, O2, I1, I2), 859 #define C_O2_I3(O1, O2, I1, I2, I3) C_PFX5(c_o2_i3_, O1, O2, I1, I2, I3), 860 #define C_O2_I4(O1, O2, I1, I2, I3, I4) C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, I4), 861 #define C_N1_O1_I4(O1, O2, I1, I2, I3, I4) C_PFX6(c_n1_o1_i4_, O1, O2, I1, I2, I3, I4), 862 863 typedef enum { 864 C_Dynamic = -2, 865 C_NotImplemented = -1, 866 #include "tcg-target-con-set.h" 867 } TCGConstraintSetIndex; 868 869 static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode, TCGType, unsigned); 870 871 #undef C_O0_I1 872 #undef C_O0_I2 873 #undef C_O0_I3 874 #undef C_O0_I4 875 #undef C_O1_I1 876 #undef C_O1_I2 877 #undef C_O1_I3 878 #undef C_O1_I4 879 #undef C_N1_I2 880 #undef C_N1O1_I1 881 #undef C_N2_I1 882 #undef C_O2_I1 883 #undef C_O2_I2 884 #undef C_O2_I3 885 #undef C_O2_I4 886 #undef C_N1_O1_I4 887 888 /* Put all of the constraint sets into an array, indexed by the enum. */ 889 890 typedef struct TCGConstraintSet { 891 uint8_t nb_oargs, nb_iargs; 892 const char *args_ct_str[TCG_MAX_OP_ARGS]; 893 } TCGConstraintSet; 894 895 #define C_O0_I1(I1) { 0, 1, { #I1 } }, 896 #define C_O0_I2(I1, I2) { 0, 2, { #I1, #I2 } }, 897 #define C_O0_I3(I1, I2, I3) { 0, 3, { #I1, #I2, #I3 } }, 898 #define C_O0_I4(I1, I2, I3, I4) { 0, 4, { #I1, #I2, #I3, #I4 } }, 899 900 #define C_O1_I1(O1, I1) { 1, 1, { #O1, #I1 } }, 901 #define C_O1_I2(O1, I1, I2) { 1, 2, { #O1, #I1, #I2 } }, 902 #define C_O1_I3(O1, I1, I2, I3) { 1, 3, { #O1, #I1, #I2, #I3 } }, 903 #define C_O1_I4(O1, I1, I2, I3, I4) { 1, 4, { #O1, #I1, #I2, #I3, #I4 } }, 904 905 #define C_N1_I2(O1, I1, I2) { 1, 2, { "&" #O1, #I1, #I2 } }, 906 #define C_N1O1_I1(O1, O2, I1) { 2, 1, { "&" #O1, #O2, #I1 } }, 907 #define C_N2_I1(O1, O2, I1) { 2, 1, { "&" #O1, "&" #O2, #I1 } }, 908 909 #define C_O2_I1(O1, O2, I1) { 2, 1, { #O1, #O2, #I1 } }, 910 #define C_O2_I2(O1, O2, I1, I2) { 2, 2, { #O1, #O2, #I1, #I2 } }, 911 #define C_O2_I3(O1, O2, I1, I2, I3) { 2, 3, { #O1, #O2, #I1, #I2, #I3 } }, 912 #define C_O2_I4(O1, O2, I1, I2, I3, I4) { 2, 4, { #O1, #O2, #I1, #I2, #I3, #I4 } }, 913 #define C_N1_O1_I4(O1, O2, I1, I2, I3, I4) { 2, 4, { "&" #O1, #O2, #I1, #I2, #I3, #I4 } }, 914 915 static const TCGConstraintSet constraint_sets[] = { 916 #include "tcg-target-con-set.h" 917 }; 918 919 #undef C_O0_I1 920 #undef C_O0_I2 921 #undef C_O0_I3 922 #undef C_O0_I4 923 #undef C_O1_I1 924 #undef C_O1_I2 925 #undef C_O1_I3 926 #undef C_O1_I4 927 #undef C_N1_I2 928 #undef C_N1O1_I1 929 #undef C_N2_I1 930 #undef C_O2_I1 931 #undef C_O2_I2 932 #undef C_O2_I3 933 #undef C_O2_I4 934 #undef C_N1_O1_I4 935 936 /* Expand the enumerator to be returned from tcg_target_op_def(). */ 937 938 #define C_O0_I1(I1) C_PFX1(c_o0_i1_, I1) 939 #define C_O0_I2(I1, I2) C_PFX2(c_o0_i2_, I1, I2) 940 #define C_O0_I3(I1, I2, I3) C_PFX3(c_o0_i3_, I1, I2, I3) 941 #define C_O0_I4(I1, I2, I3, I4) C_PFX4(c_o0_i4_, I1, I2, I3, I4) 942 943 #define C_O1_I1(O1, I1) C_PFX2(c_o1_i1_, O1, I1) 944 #define C_O1_I2(O1, I1, I2) C_PFX3(c_o1_i2_, O1, I1, I2) 945 #define C_O1_I3(O1, I1, I2, I3) C_PFX4(c_o1_i3_, O1, I1, I2, I3) 946 #define C_O1_I4(O1, I1, I2, I3, I4) C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4) 947 948 #define C_N1_I2(O1, I1, I2) C_PFX3(c_n1_i2_, O1, I1, I2) 949 #define C_N1O1_I1(O1, O2, I1) C_PFX3(c_n1o1_i1_, O1, O2, I1) 950 #define C_N2_I1(O1, O2, I1) C_PFX3(c_n2_i1_, O1, O2, I1) 951 952 #define C_O2_I1(O1, O2, I1) C_PFX3(c_o2_i1_, O1, O2, I1) 953 #define C_O2_I2(O1, O2, I1, I2) C_PFX4(c_o2_i2_, O1, O2, I1, I2) 954 #define C_O2_I3(O1, O2, I1, I2, I3) C_PFX5(c_o2_i3_, O1, O2, I1, I2, I3) 955 #define C_O2_I4(O1, O2, I1, I2, I3, I4) C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, I4) 956 #define C_N1_O1_I4(O1, O2, I1, I2, I3, I4) C_PFX6(c_n1_o1_i4_, O1, O2, I1, I2, I3, I4) 957 958 /* 959 * TCGOutOp is the base class for a set of structures that describe how 960 * to generate code for a given TCGOpcode. 961 * 962 * @static_constraint: 963 * C_NotImplemented: The TCGOpcode is not supported by the backend. 964 * C_Dynamic: Use @dynamic_constraint to select a constraint set 965 * based on any of @type, @flags, or host isa. 966 * Otherwise: The register allocation constrains for the TCGOpcode. 967 * 968 * Subclasses of TCGOutOp will define a set of output routines that may 969 * be used. Such routines will often be selected by the set of registers 970 * and constants that come out of register allocation. The set of 971 * routines that are provided will guide the set of constraints that are 972 * legal. In particular, assume that tcg_optimize() has done its job in 973 * swapping commutative operands and folding operations for which all 974 * operands are constant. 975 */ 976 typedef struct TCGOutOp { 977 TCGConstraintSetIndex static_constraint; 978 TCGConstraintSetIndex (*dynamic_constraint)(TCGType type, unsigned flags); 979 } TCGOutOp; 980 981 typedef struct TCGOutOpBinary { 982 TCGOutOp base; 983 void (*out_rrr)(TCGContext *s, TCGType type, 984 TCGReg a0, TCGReg a1, TCGReg a2); 985 void (*out_rri)(TCGContext *s, TCGType type, 986 TCGReg a0, TCGReg a1, tcg_target_long a2); 987 } TCGOutOpBinary; 988 989 typedef struct TCGOutOpDivRem { 990 TCGOutOp base; 991 void (*out_rr01r)(TCGContext *s, TCGType type, 992 TCGReg a0, TCGReg a1, TCGReg a4); 993 } TCGOutOpDivRem; 994 995 typedef struct TCGOutOpUnary { 996 TCGOutOp base; 997 void (*out_rr)(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1); 998 } TCGOutOpUnary; 999 1000 typedef struct TCGOutOpSubtract { 1001 TCGOutOp base; 1002 void (*out_rrr)(TCGContext *s, TCGType type, 1003 TCGReg a0, TCGReg a1, TCGReg a2); 1004 void (*out_rir)(TCGContext *s, TCGType type, 1005 TCGReg a0, tcg_target_long a1, TCGReg a2); 1006 } TCGOutOpSubtract; 1007 1008 #include "tcg-target.c.inc" 1009 1010 #ifndef CONFIG_TCG_INTERPRETER 1011 /* Validate CPUTLBDescFast placement. */ 1012 QEMU_BUILD_BUG_ON((int)(offsetof(CPUNegativeOffsetState, tlb.f[0]) - 1013 sizeof(CPUNegativeOffsetState)) 1014 < MIN_TLB_MASK_TABLE_OFS); 1015 #endif 1016 1017 /* 1018 * Register V as the TCGOutOp for O. 1019 * This verifies that V is of type T, otherwise give a nice compiler error. 1020 * This prevents trivial mistakes within each arch/tcg-target.c.inc. 1021 */ 1022 #define OUTOP(O, T, V) [O] = _Generic(V, T: &V.base) 1023 1024 /* Register allocation descriptions for every TCGOpcode. */ 1025 static const TCGOutOp * const all_outop[NB_OPS] = { 1026 OUTOP(INDEX_op_add, TCGOutOpBinary, outop_add), 1027 OUTOP(INDEX_op_and, TCGOutOpBinary, outop_and), 1028 OUTOP(INDEX_op_andc, TCGOutOpBinary, outop_andc), 1029 OUTOP(INDEX_op_divs, TCGOutOpBinary, outop_divs), 1030 OUTOP(INDEX_op_divu, TCGOutOpBinary, outop_divu), 1031 OUTOP(INDEX_op_divs2, TCGOutOpDivRem, outop_divs2), 1032 OUTOP(INDEX_op_divu2, TCGOutOpDivRem, outop_divu2), 1033 OUTOP(INDEX_op_eqv, TCGOutOpBinary, outop_eqv), 1034 OUTOP(INDEX_op_mul, TCGOutOpBinary, outop_mul), 1035 OUTOP(INDEX_op_mulsh, TCGOutOpBinary, outop_mulsh), 1036 OUTOP(INDEX_op_muluh, TCGOutOpBinary, outop_muluh), 1037 OUTOP(INDEX_op_nand, TCGOutOpBinary, outop_nand), 1038 OUTOP(INDEX_op_neg, TCGOutOpUnary, outop_neg), 1039 OUTOP(INDEX_op_nor, TCGOutOpBinary, outop_nor), 1040 OUTOP(INDEX_op_not, TCGOutOpUnary, outop_not), 1041 OUTOP(INDEX_op_or, TCGOutOpBinary, outop_or), 1042 OUTOP(INDEX_op_orc, TCGOutOpBinary, outop_orc), 1043 OUTOP(INDEX_op_rems, TCGOutOpBinary, outop_rems), 1044 OUTOP(INDEX_op_remu, TCGOutOpBinary, outop_remu), 1045 OUTOP(INDEX_op_sub, TCGOutOpSubtract, outop_sub), 1046 OUTOP(INDEX_op_xor, TCGOutOpBinary, outop_xor), 1047 }; 1048 1049 #undef OUTOP 1050 1051 /* 1052 * All TCG threads except the parent (i.e. the one that called tcg_context_init 1053 * and registered the target's TCG globals) must register with this function 1054 * before initiating translation. 1055 * 1056 * In user-mode we just point tcg_ctx to tcg_init_ctx. See the documentation 1057 * of tcg_region_init() for the reasoning behind this. 1058 * 1059 * In system-mode each caller registers its context in tcg_ctxs[]. Note that in 1060 * system-mode tcg_ctxs[] does not track tcg_ctx_init, since the initial context 1061 * is not used anymore for translation once this function is called. 1062 * 1063 * Not tracking tcg_init_ctx in tcg_ctxs[] in system-mode keeps code that 1064 * iterates over the array (e.g. tcg_code_size() the same for both system/user 1065 * modes. 1066 */ 1067 #ifdef CONFIG_USER_ONLY 1068 void tcg_register_thread(void) 1069 { 1070 tcg_ctx = &tcg_init_ctx; 1071 } 1072 #else 1073 void tcg_register_thread(void) 1074 { 1075 TCGContext *s = g_malloc(sizeof(*s)); 1076 unsigned int i, n; 1077 1078 *s = tcg_init_ctx; 1079 1080 /* Relink mem_base. */ 1081 for (i = 0, n = tcg_init_ctx.nb_globals; i < n; ++i) { 1082 if (tcg_init_ctx.temps[i].mem_base) { 1083 ptrdiff_t b = tcg_init_ctx.temps[i].mem_base - tcg_init_ctx.temps; 1084 tcg_debug_assert(b >= 0 && b < n); 1085 s->temps[i].mem_base = &s->temps[b]; 1086 } 1087 } 1088 1089 /* Claim an entry in tcg_ctxs */ 1090 n = qatomic_fetch_inc(&tcg_cur_ctxs); 1091 g_assert(n < tcg_max_ctxs); 1092 qatomic_set(&tcg_ctxs[n], s); 1093 1094 if (n > 0) { 1095 tcg_region_initial_alloc(s); 1096 } 1097 1098 tcg_ctx = s; 1099 } 1100 #endif /* !CONFIG_USER_ONLY */ 1101 1102 /* pool based memory allocation */ 1103 void *tcg_malloc_internal(TCGContext *s, int size) 1104 { 1105 TCGPool *p; 1106 int pool_size; 1107 1108 if (size > TCG_POOL_CHUNK_SIZE) { 1109 /* big malloc: insert a new pool (XXX: could optimize) */ 1110 p = g_malloc(sizeof(TCGPool) + size); 1111 p->size = size; 1112 p->next = s->pool_first_large; 1113 s->pool_first_large = p; 1114 return p->data; 1115 } else { 1116 p = s->pool_current; 1117 if (!p) { 1118 p = s->pool_first; 1119 if (!p) 1120 goto new_pool; 1121 } else { 1122 if (!p->next) { 1123 new_pool: 1124 pool_size = TCG_POOL_CHUNK_SIZE; 1125 p = g_malloc(sizeof(TCGPool) + pool_size); 1126 p->size = pool_size; 1127 p->next = NULL; 1128 if (s->pool_current) { 1129 s->pool_current->next = p; 1130 } else { 1131 s->pool_first = p; 1132 } 1133 } else { 1134 p = p->next; 1135 } 1136 } 1137 } 1138 s->pool_current = p; 1139 s->pool_cur = p->data + size; 1140 s->pool_end = p->data + p->size; 1141 return p->data; 1142 } 1143 1144 void tcg_pool_reset(TCGContext *s) 1145 { 1146 TCGPool *p, *t; 1147 for (p = s->pool_first_large; p; p = t) { 1148 t = p->next; 1149 g_free(p); 1150 } 1151 s->pool_first_large = NULL; 1152 s->pool_cur = s->pool_end = NULL; 1153 s->pool_current = NULL; 1154 } 1155 1156 /* 1157 * Create TCGHelperInfo structures for "tcg/tcg-ldst.h" functions, 1158 * akin to what "exec/helper-tcg.h" does with DEF_HELPER_FLAGS_N. 1159 * We only use these for layout in tcg_out_ld_helper_ret and 1160 * tcg_out_st_helper_args, and share them between several of 1161 * the helpers, with the end result that it's easier to build manually. 1162 */ 1163 1164 #if TCG_TARGET_REG_BITS == 32 1165 # define dh_typecode_ttl dh_typecode_i32 1166 #else 1167 # define dh_typecode_ttl dh_typecode_i64 1168 #endif 1169 1170 static TCGHelperInfo info_helper_ld32_mmu = { 1171 .flags = TCG_CALL_NO_WG, 1172 .typemask = dh_typemask(ttl, 0) /* return tcg_target_ulong */ 1173 | dh_typemask(env, 1) 1174 | dh_typemask(i64, 2) /* uint64_t addr */ 1175 | dh_typemask(i32, 3) /* unsigned oi */ 1176 | dh_typemask(ptr, 4) /* uintptr_t ra */ 1177 }; 1178 1179 static TCGHelperInfo info_helper_ld64_mmu = { 1180 .flags = TCG_CALL_NO_WG, 1181 .typemask = dh_typemask(i64, 0) /* return uint64_t */ 1182 | dh_typemask(env, 1) 1183 | dh_typemask(i64, 2) /* uint64_t addr */ 1184 | dh_typemask(i32, 3) /* unsigned oi */ 1185 | dh_typemask(ptr, 4) /* uintptr_t ra */ 1186 }; 1187 1188 static TCGHelperInfo info_helper_ld128_mmu = { 1189 .flags = TCG_CALL_NO_WG, 1190 .typemask = dh_typemask(i128, 0) /* return Int128 */ 1191 | dh_typemask(env, 1) 1192 | dh_typemask(i64, 2) /* uint64_t addr */ 1193 | dh_typemask(i32, 3) /* unsigned oi */ 1194 | dh_typemask(ptr, 4) /* uintptr_t ra */ 1195 }; 1196 1197 static TCGHelperInfo info_helper_st32_mmu = { 1198 .flags = TCG_CALL_NO_WG, 1199 .typemask = dh_typemask(void, 0) 1200 | dh_typemask(env, 1) 1201 | dh_typemask(i64, 2) /* uint64_t addr */ 1202 | dh_typemask(i32, 3) /* uint32_t data */ 1203 | dh_typemask(i32, 4) /* unsigned oi */ 1204 | dh_typemask(ptr, 5) /* uintptr_t ra */ 1205 }; 1206 1207 static TCGHelperInfo info_helper_st64_mmu = { 1208 .flags = TCG_CALL_NO_WG, 1209 .typemask = dh_typemask(void, 0) 1210 | dh_typemask(env, 1) 1211 | dh_typemask(i64, 2) /* uint64_t addr */ 1212 | dh_typemask(i64, 3) /* uint64_t data */ 1213 | dh_typemask(i32, 4) /* unsigned oi */ 1214 | dh_typemask(ptr, 5) /* uintptr_t ra */ 1215 }; 1216 1217 static TCGHelperInfo info_helper_st128_mmu = { 1218 .flags = TCG_CALL_NO_WG, 1219 .typemask = dh_typemask(void, 0) 1220 | dh_typemask(env, 1) 1221 | dh_typemask(i64, 2) /* uint64_t addr */ 1222 | dh_typemask(i128, 3) /* Int128 data */ 1223 | dh_typemask(i32, 4) /* unsigned oi */ 1224 | dh_typemask(ptr, 5) /* uintptr_t ra */ 1225 }; 1226 1227 #ifdef CONFIG_TCG_INTERPRETER 1228 static ffi_type *typecode_to_ffi(int argmask) 1229 { 1230 /* 1231 * libffi does not support __int128_t, so we have forced Int128 1232 * to use the structure definition instead of the builtin type. 1233 */ 1234 static ffi_type *ffi_type_i128_elements[3] = { 1235 &ffi_type_uint64, 1236 &ffi_type_uint64, 1237 NULL 1238 }; 1239 static ffi_type ffi_type_i128 = { 1240 .size = 16, 1241 .alignment = __alignof__(Int128), 1242 .type = FFI_TYPE_STRUCT, 1243 .elements = ffi_type_i128_elements, 1244 }; 1245 1246 switch (argmask) { 1247 case dh_typecode_void: 1248 return &ffi_type_void; 1249 case dh_typecode_i32: 1250 return &ffi_type_uint32; 1251 case dh_typecode_s32: 1252 return &ffi_type_sint32; 1253 case dh_typecode_i64: 1254 return &ffi_type_uint64; 1255 case dh_typecode_s64: 1256 return &ffi_type_sint64; 1257 case dh_typecode_ptr: 1258 return &ffi_type_pointer; 1259 case dh_typecode_i128: 1260 return &ffi_type_i128; 1261 } 1262 g_assert_not_reached(); 1263 } 1264 1265 static ffi_cif *init_ffi_layout(TCGHelperInfo *info) 1266 { 1267 unsigned typemask = info->typemask; 1268 struct { 1269 ffi_cif cif; 1270 ffi_type *args[]; 1271 } *ca; 1272 ffi_status status; 1273 int nargs; 1274 1275 /* Ignoring the return type, find the last non-zero field. */ 1276 nargs = 32 - clz32(typemask >> 3); 1277 nargs = DIV_ROUND_UP(nargs, 3); 1278 assert(nargs <= MAX_CALL_IARGS); 1279 1280 ca = g_malloc0(sizeof(*ca) + nargs * sizeof(ffi_type *)); 1281 ca->cif.rtype = typecode_to_ffi(typemask & 7); 1282 ca->cif.nargs = nargs; 1283 1284 if (nargs != 0) { 1285 ca->cif.arg_types = ca->args; 1286 for (int j = 0; j < nargs; ++j) { 1287 int typecode = extract32(typemask, (j + 1) * 3, 3); 1288 ca->args[j] = typecode_to_ffi(typecode); 1289 } 1290 } 1291 1292 status = ffi_prep_cif(&ca->cif, FFI_DEFAULT_ABI, nargs, 1293 ca->cif.rtype, ca->cif.arg_types); 1294 assert(status == FFI_OK); 1295 1296 return &ca->cif; 1297 } 1298 1299 #define HELPER_INFO_INIT(I) (&(I)->cif) 1300 #define HELPER_INFO_INIT_VAL(I) init_ffi_layout(I) 1301 #else 1302 #define HELPER_INFO_INIT(I) (&(I)->init) 1303 #define HELPER_INFO_INIT_VAL(I) 1 1304 #endif /* CONFIG_TCG_INTERPRETER */ 1305 1306 static inline bool arg_slot_reg_p(unsigned arg_slot) 1307 { 1308 /* 1309 * Split the sizeof away from the comparison to avoid Werror from 1310 * "unsigned < 0 is always false", when iarg_regs is empty. 1311 */ 1312 unsigned nreg = ARRAY_SIZE(tcg_target_call_iarg_regs); 1313 return arg_slot < nreg; 1314 } 1315 1316 static inline int arg_slot_stk_ofs(unsigned arg_slot) 1317 { 1318 unsigned max = TCG_STATIC_CALL_ARGS_SIZE / sizeof(tcg_target_long); 1319 unsigned stk_slot = arg_slot - ARRAY_SIZE(tcg_target_call_iarg_regs); 1320 1321 tcg_debug_assert(stk_slot < max); 1322 return TCG_TARGET_CALL_STACK_OFFSET + stk_slot * sizeof(tcg_target_long); 1323 } 1324 1325 typedef struct TCGCumulativeArgs { 1326 int arg_idx; /* tcg_gen_callN args[] */ 1327 int info_in_idx; /* TCGHelperInfo in[] */ 1328 int arg_slot; /* regs+stack slot */ 1329 int ref_slot; /* stack slots for references */ 1330 } TCGCumulativeArgs; 1331 1332 static void layout_arg_even(TCGCumulativeArgs *cum) 1333 { 1334 cum->arg_slot += cum->arg_slot & 1; 1335 } 1336 1337 static void layout_arg_1(TCGCumulativeArgs *cum, TCGHelperInfo *info, 1338 TCGCallArgumentKind kind) 1339 { 1340 TCGCallArgumentLoc *loc = &info->in[cum->info_in_idx]; 1341 1342 *loc = (TCGCallArgumentLoc){ 1343 .kind = kind, 1344 .arg_idx = cum->arg_idx, 1345 .arg_slot = cum->arg_slot, 1346 }; 1347 cum->info_in_idx++; 1348 cum->arg_slot++; 1349 } 1350 1351 static void layout_arg_normal_n(TCGCumulativeArgs *cum, 1352 TCGHelperInfo *info, int n) 1353 { 1354 TCGCallArgumentLoc *loc = &info->in[cum->info_in_idx]; 1355 1356 for (int i = 0; i < n; ++i) { 1357 /* Layout all using the same arg_idx, adjusting the subindex. */ 1358 loc[i] = (TCGCallArgumentLoc){ 1359 .kind = TCG_CALL_ARG_NORMAL, 1360 .arg_idx = cum->arg_idx, 1361 .tmp_subindex = i, 1362 .arg_slot = cum->arg_slot + i, 1363 }; 1364 } 1365 cum->info_in_idx += n; 1366 cum->arg_slot += n; 1367 } 1368 1369 static void layout_arg_by_ref(TCGCumulativeArgs *cum, TCGHelperInfo *info) 1370 { 1371 TCGCallArgumentLoc *loc = &info->in[cum->info_in_idx]; 1372 int n = 128 / TCG_TARGET_REG_BITS; 1373 1374 /* The first subindex carries the pointer. */ 1375 layout_arg_1(cum, info, TCG_CALL_ARG_BY_REF); 1376 1377 /* 1378 * The callee is allowed to clobber memory associated with 1379 * structure pass by-reference. Therefore we must make copies. 1380 * Allocate space from "ref_slot", which will be adjusted to 1381 * follow the parameters on the stack. 1382 */ 1383 loc[0].ref_slot = cum->ref_slot; 1384 1385 /* 1386 * Subsequent words also go into the reference slot, but 1387 * do not accumulate into the regular arguments. 1388 */ 1389 for (int i = 1; i < n; ++i) { 1390 loc[i] = (TCGCallArgumentLoc){ 1391 .kind = TCG_CALL_ARG_BY_REF_N, 1392 .arg_idx = cum->arg_idx, 1393 .tmp_subindex = i, 1394 .ref_slot = cum->ref_slot + i, 1395 }; 1396 } 1397 cum->info_in_idx += n - 1; /* i=0 accounted for in layout_arg_1 */ 1398 cum->ref_slot += n; 1399 } 1400 1401 static void init_call_layout(TCGHelperInfo *info) 1402 { 1403 int max_reg_slots = ARRAY_SIZE(tcg_target_call_iarg_regs); 1404 int max_stk_slots = TCG_STATIC_CALL_ARGS_SIZE / sizeof(tcg_target_long); 1405 unsigned typemask = info->typemask; 1406 unsigned typecode; 1407 TCGCumulativeArgs cum = { }; 1408 1409 /* 1410 * Parse and place any function return value. 1411 */ 1412 typecode = typemask & 7; 1413 switch (typecode) { 1414 case dh_typecode_void: 1415 info->nr_out = 0; 1416 break; 1417 case dh_typecode_i32: 1418 case dh_typecode_s32: 1419 case dh_typecode_ptr: 1420 info->nr_out = 1; 1421 info->out_kind = TCG_CALL_RET_NORMAL; 1422 break; 1423 case dh_typecode_i64: 1424 case dh_typecode_s64: 1425 info->nr_out = 64 / TCG_TARGET_REG_BITS; 1426 info->out_kind = TCG_CALL_RET_NORMAL; 1427 /* Query the last register now to trigger any assert early. */ 1428 tcg_target_call_oarg_reg(info->out_kind, info->nr_out - 1); 1429 break; 1430 case dh_typecode_i128: 1431 info->nr_out = 128 / TCG_TARGET_REG_BITS; 1432 info->out_kind = TCG_TARGET_CALL_RET_I128; 1433 switch (TCG_TARGET_CALL_RET_I128) { 1434 case TCG_CALL_RET_NORMAL: 1435 /* Query the last register now to trigger any assert early. */ 1436 tcg_target_call_oarg_reg(info->out_kind, info->nr_out - 1); 1437 break; 1438 case TCG_CALL_RET_BY_VEC: 1439 /* Query the single register now to trigger any assert early. */ 1440 tcg_target_call_oarg_reg(TCG_CALL_RET_BY_VEC, 0); 1441 break; 1442 case TCG_CALL_RET_BY_REF: 1443 /* 1444 * Allocate the first argument to the output. 1445 * We don't need to store this anywhere, just make it 1446 * unavailable for use in the input loop below. 1447 */ 1448 cum.arg_slot = 1; 1449 break; 1450 default: 1451 qemu_build_not_reached(); 1452 } 1453 break; 1454 default: 1455 g_assert_not_reached(); 1456 } 1457 1458 /* 1459 * Parse and place function arguments. 1460 */ 1461 for (typemask >>= 3; typemask; typemask >>= 3, cum.arg_idx++) { 1462 TCGCallArgumentKind kind; 1463 TCGType type; 1464 1465 typecode = typemask & 7; 1466 switch (typecode) { 1467 case dh_typecode_i32: 1468 case dh_typecode_s32: 1469 type = TCG_TYPE_I32; 1470 break; 1471 case dh_typecode_i64: 1472 case dh_typecode_s64: 1473 type = TCG_TYPE_I64; 1474 break; 1475 case dh_typecode_ptr: 1476 type = TCG_TYPE_PTR; 1477 break; 1478 case dh_typecode_i128: 1479 type = TCG_TYPE_I128; 1480 break; 1481 default: 1482 g_assert_not_reached(); 1483 } 1484 1485 switch (type) { 1486 case TCG_TYPE_I32: 1487 switch (TCG_TARGET_CALL_ARG_I32) { 1488 case TCG_CALL_ARG_EVEN: 1489 layout_arg_even(&cum); 1490 /* fall through */ 1491 case TCG_CALL_ARG_NORMAL: 1492 layout_arg_1(&cum, info, TCG_CALL_ARG_NORMAL); 1493 break; 1494 case TCG_CALL_ARG_EXTEND: 1495 kind = TCG_CALL_ARG_EXTEND_U + (typecode & 1); 1496 layout_arg_1(&cum, info, kind); 1497 break; 1498 default: 1499 qemu_build_not_reached(); 1500 } 1501 break; 1502 1503 case TCG_TYPE_I64: 1504 switch (TCG_TARGET_CALL_ARG_I64) { 1505 case TCG_CALL_ARG_EVEN: 1506 layout_arg_even(&cum); 1507 /* fall through */ 1508 case TCG_CALL_ARG_NORMAL: 1509 if (TCG_TARGET_REG_BITS == 32) { 1510 layout_arg_normal_n(&cum, info, 2); 1511 } else { 1512 layout_arg_1(&cum, info, TCG_CALL_ARG_NORMAL); 1513 } 1514 break; 1515 default: 1516 qemu_build_not_reached(); 1517 } 1518 break; 1519 1520 case TCG_TYPE_I128: 1521 switch (TCG_TARGET_CALL_ARG_I128) { 1522 case TCG_CALL_ARG_EVEN: 1523 layout_arg_even(&cum); 1524 /* fall through */ 1525 case TCG_CALL_ARG_NORMAL: 1526 layout_arg_normal_n(&cum, info, 128 / TCG_TARGET_REG_BITS); 1527 break; 1528 case TCG_CALL_ARG_BY_REF: 1529 layout_arg_by_ref(&cum, info); 1530 break; 1531 default: 1532 qemu_build_not_reached(); 1533 } 1534 break; 1535 1536 default: 1537 g_assert_not_reached(); 1538 } 1539 } 1540 info->nr_in = cum.info_in_idx; 1541 1542 /* Validate that we didn't overrun the input array. */ 1543 assert(cum.info_in_idx <= ARRAY_SIZE(info->in)); 1544 /* Validate the backend has enough argument space. */ 1545 assert(cum.arg_slot <= max_reg_slots + max_stk_slots); 1546 1547 /* 1548 * Relocate the "ref_slot" area to the end of the parameters. 1549 * Minimizing this stack offset helps code size for x86, 1550 * which has a signed 8-bit offset encoding. 1551 */ 1552 if (cum.ref_slot != 0) { 1553 int ref_base = 0; 1554 1555 if (cum.arg_slot > max_reg_slots) { 1556 int align = __alignof(Int128) / sizeof(tcg_target_long); 1557 1558 ref_base = cum.arg_slot - max_reg_slots; 1559 if (align > 1) { 1560 ref_base = ROUND_UP(ref_base, align); 1561 } 1562 } 1563 assert(ref_base + cum.ref_slot <= max_stk_slots); 1564 ref_base += max_reg_slots; 1565 1566 if (ref_base != 0) { 1567 for (int i = cum.info_in_idx - 1; i >= 0; --i) { 1568 TCGCallArgumentLoc *loc = &info->in[i]; 1569 switch (loc->kind) { 1570 case TCG_CALL_ARG_BY_REF: 1571 case TCG_CALL_ARG_BY_REF_N: 1572 loc->ref_slot += ref_base; 1573 break; 1574 default: 1575 break; 1576 } 1577 } 1578 } 1579 } 1580 } 1581 1582 static int indirect_reg_alloc_order[ARRAY_SIZE(tcg_target_reg_alloc_order)]; 1583 static void process_constraint_sets(void); 1584 static TCGTemp *tcg_global_reg_new_internal(TCGContext *s, TCGType type, 1585 TCGReg reg, const char *name); 1586 1587 static void tcg_context_init(unsigned max_threads) 1588 { 1589 TCGContext *s = &tcg_init_ctx; 1590 int n, i; 1591 TCGTemp *ts; 1592 1593 memset(s, 0, sizeof(*s)); 1594 s->nb_globals = 0; 1595 1596 init_call_layout(&info_helper_ld32_mmu); 1597 init_call_layout(&info_helper_ld64_mmu); 1598 init_call_layout(&info_helper_ld128_mmu); 1599 init_call_layout(&info_helper_st32_mmu); 1600 init_call_layout(&info_helper_st64_mmu); 1601 init_call_layout(&info_helper_st128_mmu); 1602 1603 tcg_target_init(s); 1604 process_constraint_sets(); 1605 1606 /* Reverse the order of the saved registers, assuming they're all at 1607 the start of tcg_target_reg_alloc_order. */ 1608 for (n = 0; n < ARRAY_SIZE(tcg_target_reg_alloc_order); ++n) { 1609 int r = tcg_target_reg_alloc_order[n]; 1610 if (tcg_regset_test_reg(tcg_target_call_clobber_regs, r)) { 1611 break; 1612 } 1613 } 1614 for (i = 0; i < n; ++i) { 1615 indirect_reg_alloc_order[i] = tcg_target_reg_alloc_order[n - 1 - i]; 1616 } 1617 for (; i < ARRAY_SIZE(tcg_target_reg_alloc_order); ++i) { 1618 indirect_reg_alloc_order[i] = tcg_target_reg_alloc_order[i]; 1619 } 1620 1621 tcg_ctx = s; 1622 /* 1623 * In user-mode we simply share the init context among threads, since we 1624 * use a single region. See the documentation tcg_region_init() for the 1625 * reasoning behind this. 1626 * In system-mode we will have at most max_threads TCG threads. 1627 */ 1628 #ifdef CONFIG_USER_ONLY 1629 tcg_ctxs = &tcg_ctx; 1630 tcg_cur_ctxs = 1; 1631 tcg_max_ctxs = 1; 1632 #else 1633 tcg_max_ctxs = max_threads; 1634 tcg_ctxs = g_new0(TCGContext *, max_threads); 1635 #endif 1636 1637 tcg_debug_assert(!tcg_regset_test_reg(s->reserved_regs, TCG_AREG0)); 1638 ts = tcg_global_reg_new_internal(s, TCG_TYPE_PTR, TCG_AREG0, "env"); 1639 tcg_env = temp_tcgv_ptr(ts); 1640 } 1641 1642 void tcg_init(size_t tb_size, int splitwx, unsigned max_threads) 1643 { 1644 tcg_context_init(max_threads); 1645 tcg_region_init(tb_size, splitwx, max_threads); 1646 } 1647 1648 /* 1649 * Allocate TBs right before their corresponding translated code, making 1650 * sure that TBs and code are on different cache lines. 1651 */ 1652 TranslationBlock *tcg_tb_alloc(TCGContext *s) 1653 { 1654 uintptr_t align = qemu_icache_linesize; 1655 TranslationBlock *tb; 1656 void *next; 1657 1658 retry: 1659 tb = (void *)ROUND_UP((uintptr_t)s->code_gen_ptr, align); 1660 next = (void *)ROUND_UP((uintptr_t)(tb + 1), align); 1661 1662 if (unlikely(next > s->code_gen_highwater)) { 1663 if (tcg_region_alloc(s)) { 1664 return NULL; 1665 } 1666 goto retry; 1667 } 1668 qatomic_set(&s->code_gen_ptr, next); 1669 return tb; 1670 } 1671 1672 void tcg_prologue_init(void) 1673 { 1674 TCGContext *s = tcg_ctx; 1675 size_t prologue_size; 1676 1677 s->code_ptr = s->code_gen_ptr; 1678 s->code_buf = s->code_gen_ptr; 1679 s->data_gen_ptr = NULL; 1680 1681 #ifndef CONFIG_TCG_INTERPRETER 1682 tcg_qemu_tb_exec = (tcg_prologue_fn *)tcg_splitwx_to_rx(s->code_ptr); 1683 #endif 1684 1685 s->pool_labels = NULL; 1686 1687 qemu_thread_jit_write(); 1688 /* Generate the prologue. */ 1689 tcg_target_qemu_prologue(s); 1690 1691 /* Allow the prologue to put e.g. guest_base into a pool entry. */ 1692 { 1693 int result = tcg_out_pool_finalize(s); 1694 tcg_debug_assert(result == 0); 1695 } 1696 1697 prologue_size = tcg_current_code_size(s); 1698 perf_report_prologue(s->code_gen_ptr, prologue_size); 1699 1700 #ifndef CONFIG_TCG_INTERPRETER 1701 flush_idcache_range((uintptr_t)tcg_splitwx_to_rx(s->code_buf), 1702 (uintptr_t)s->code_buf, prologue_size); 1703 #endif 1704 1705 if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM)) { 1706 FILE *logfile = qemu_log_trylock(); 1707 if (logfile) { 1708 fprintf(logfile, "PROLOGUE: [size=%zu]\n", prologue_size); 1709 if (s->data_gen_ptr) { 1710 size_t code_size = s->data_gen_ptr - s->code_gen_ptr; 1711 size_t data_size = prologue_size - code_size; 1712 size_t i; 1713 1714 disas(logfile, s->code_gen_ptr, code_size); 1715 1716 for (i = 0; i < data_size; i += sizeof(tcg_target_ulong)) { 1717 if (sizeof(tcg_target_ulong) == 8) { 1718 fprintf(logfile, 1719 "0x%08" PRIxPTR ": .quad 0x%016" PRIx64 "\n", 1720 (uintptr_t)s->data_gen_ptr + i, 1721 *(uint64_t *)(s->data_gen_ptr + i)); 1722 } else { 1723 fprintf(logfile, 1724 "0x%08" PRIxPTR ": .long 0x%08x\n", 1725 (uintptr_t)s->data_gen_ptr + i, 1726 *(uint32_t *)(s->data_gen_ptr + i)); 1727 } 1728 } 1729 } else { 1730 disas(logfile, s->code_gen_ptr, prologue_size); 1731 } 1732 fprintf(logfile, "\n"); 1733 qemu_log_unlock(logfile); 1734 } 1735 } 1736 1737 #ifndef CONFIG_TCG_INTERPRETER 1738 /* 1739 * Assert that goto_ptr is implemented completely, setting an epilogue. 1740 * For tci, we use NULL as the signal to return from the interpreter, 1741 * so skip this check. 1742 */ 1743 tcg_debug_assert(tcg_code_gen_epilogue != NULL); 1744 #endif 1745 1746 tcg_region_prologue_set(s); 1747 } 1748 1749 void tcg_func_start(TCGContext *s) 1750 { 1751 tcg_pool_reset(s); 1752 s->nb_temps = s->nb_globals; 1753 1754 /* No temps have been previously allocated for size or locality. */ 1755 tcg_temp_ebb_reset_freed(s); 1756 1757 /* No constant temps have been previously allocated. */ 1758 for (int i = 0; i < TCG_TYPE_COUNT; ++i) { 1759 if (s->const_table[i]) { 1760 g_hash_table_remove_all(s->const_table[i]); 1761 } 1762 } 1763 1764 s->nb_ops = 0; 1765 s->nb_labels = 0; 1766 s->current_frame_offset = s->frame_start; 1767 1768 #ifdef CONFIG_DEBUG_TCG 1769 s->goto_tb_issue_mask = 0; 1770 #endif 1771 1772 QTAILQ_INIT(&s->ops); 1773 QTAILQ_INIT(&s->free_ops); 1774 s->emit_before_op = NULL; 1775 QSIMPLEQ_INIT(&s->labels); 1776 1777 tcg_debug_assert(s->addr_type <= TCG_TYPE_REG); 1778 tcg_debug_assert(s->insn_start_words > 0); 1779 } 1780 1781 static TCGTemp *tcg_temp_alloc(TCGContext *s) 1782 { 1783 int n = s->nb_temps++; 1784 1785 if (n >= TCG_MAX_TEMPS) { 1786 tcg_raise_tb_overflow(s); 1787 } 1788 return memset(&s->temps[n], 0, sizeof(TCGTemp)); 1789 } 1790 1791 static TCGTemp *tcg_global_alloc(TCGContext *s) 1792 { 1793 TCGTemp *ts; 1794 1795 tcg_debug_assert(s->nb_globals == s->nb_temps); 1796 tcg_debug_assert(s->nb_globals < TCG_MAX_TEMPS); 1797 s->nb_globals++; 1798 ts = tcg_temp_alloc(s); 1799 ts->kind = TEMP_GLOBAL; 1800 1801 return ts; 1802 } 1803 1804 static TCGTemp *tcg_global_reg_new_internal(TCGContext *s, TCGType type, 1805 TCGReg reg, const char *name) 1806 { 1807 TCGTemp *ts; 1808 1809 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32); 1810 1811 ts = tcg_global_alloc(s); 1812 ts->base_type = type; 1813 ts->type = type; 1814 ts->kind = TEMP_FIXED; 1815 ts->reg = reg; 1816 ts->name = name; 1817 tcg_regset_set_reg(s->reserved_regs, reg); 1818 1819 return ts; 1820 } 1821 1822 void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size) 1823 { 1824 s->frame_start = start; 1825 s->frame_end = start + size; 1826 s->frame_temp 1827 = tcg_global_reg_new_internal(s, TCG_TYPE_PTR, reg, "_frame"); 1828 } 1829 1830 static TCGTemp *tcg_global_mem_new_internal(TCGv_ptr base, intptr_t offset, 1831 const char *name, TCGType type) 1832 { 1833 TCGContext *s = tcg_ctx; 1834 TCGTemp *base_ts = tcgv_ptr_temp(base); 1835 TCGTemp *ts = tcg_global_alloc(s); 1836 int indirect_reg = 0; 1837 1838 switch (base_ts->kind) { 1839 case TEMP_FIXED: 1840 break; 1841 case TEMP_GLOBAL: 1842 /* We do not support double-indirect registers. */ 1843 tcg_debug_assert(!base_ts->indirect_reg); 1844 base_ts->indirect_base = 1; 1845 s->nb_indirects += (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64 1846 ? 2 : 1); 1847 indirect_reg = 1; 1848 break; 1849 default: 1850 g_assert_not_reached(); 1851 } 1852 1853 if (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64) { 1854 TCGTemp *ts2 = tcg_global_alloc(s); 1855 char buf[64]; 1856 1857 ts->base_type = TCG_TYPE_I64; 1858 ts->type = TCG_TYPE_I32; 1859 ts->indirect_reg = indirect_reg; 1860 ts->mem_allocated = 1; 1861 ts->mem_base = base_ts; 1862 ts->mem_offset = offset; 1863 pstrcpy(buf, sizeof(buf), name); 1864 pstrcat(buf, sizeof(buf), "_0"); 1865 ts->name = strdup(buf); 1866 1867 tcg_debug_assert(ts2 == ts + 1); 1868 ts2->base_type = TCG_TYPE_I64; 1869 ts2->type = TCG_TYPE_I32; 1870 ts2->indirect_reg = indirect_reg; 1871 ts2->mem_allocated = 1; 1872 ts2->mem_base = base_ts; 1873 ts2->mem_offset = offset + 4; 1874 ts2->temp_subindex = 1; 1875 pstrcpy(buf, sizeof(buf), name); 1876 pstrcat(buf, sizeof(buf), "_1"); 1877 ts2->name = strdup(buf); 1878 } else { 1879 ts->base_type = type; 1880 ts->type = type; 1881 ts->indirect_reg = indirect_reg; 1882 ts->mem_allocated = 1; 1883 ts->mem_base = base_ts; 1884 ts->mem_offset = offset; 1885 ts->name = name; 1886 } 1887 return ts; 1888 } 1889 1890 TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t off, const char *name) 1891 { 1892 TCGTemp *ts = tcg_global_mem_new_internal(reg, off, name, TCG_TYPE_I32); 1893 return temp_tcgv_i32(ts); 1894 } 1895 1896 TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t off, const char *name) 1897 { 1898 TCGTemp *ts = tcg_global_mem_new_internal(reg, off, name, TCG_TYPE_I64); 1899 return temp_tcgv_i64(ts); 1900 } 1901 1902 TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t off, const char *name) 1903 { 1904 TCGTemp *ts = tcg_global_mem_new_internal(reg, off, name, TCG_TYPE_PTR); 1905 return temp_tcgv_ptr(ts); 1906 } 1907 1908 TCGTemp *tcg_temp_new_internal(TCGType type, TCGTempKind kind) 1909 { 1910 TCGContext *s = tcg_ctx; 1911 TCGTemp *ts; 1912 int n; 1913 1914 if (kind == TEMP_EBB) { 1915 int idx = find_first_bit(s->free_temps[type].l, TCG_MAX_TEMPS); 1916 1917 if (idx < TCG_MAX_TEMPS) { 1918 /* There is already an available temp with the right type. */ 1919 clear_bit(idx, s->free_temps[type].l); 1920 1921 ts = &s->temps[idx]; 1922 ts->temp_allocated = 1; 1923 tcg_debug_assert(ts->base_type == type); 1924 tcg_debug_assert(ts->kind == kind); 1925 return ts; 1926 } 1927 } else { 1928 tcg_debug_assert(kind == TEMP_TB); 1929 } 1930 1931 switch (type) { 1932 case TCG_TYPE_I32: 1933 case TCG_TYPE_V64: 1934 case TCG_TYPE_V128: 1935 case TCG_TYPE_V256: 1936 n = 1; 1937 break; 1938 case TCG_TYPE_I64: 1939 n = 64 / TCG_TARGET_REG_BITS; 1940 break; 1941 case TCG_TYPE_I128: 1942 n = 128 / TCG_TARGET_REG_BITS; 1943 break; 1944 default: 1945 g_assert_not_reached(); 1946 } 1947 1948 ts = tcg_temp_alloc(s); 1949 ts->base_type = type; 1950 ts->temp_allocated = 1; 1951 ts->kind = kind; 1952 1953 if (n == 1) { 1954 ts->type = type; 1955 } else { 1956 ts->type = TCG_TYPE_REG; 1957 1958 for (int i = 1; i < n; ++i) { 1959 TCGTemp *ts2 = tcg_temp_alloc(s); 1960 1961 tcg_debug_assert(ts2 == ts + i); 1962 ts2->base_type = type; 1963 ts2->type = TCG_TYPE_REG; 1964 ts2->temp_allocated = 1; 1965 ts2->temp_subindex = i; 1966 ts2->kind = kind; 1967 } 1968 } 1969 return ts; 1970 } 1971 1972 TCGv_i32 tcg_temp_new_i32(void) 1973 { 1974 return temp_tcgv_i32(tcg_temp_new_internal(TCG_TYPE_I32, TEMP_TB)); 1975 } 1976 1977 TCGv_i32 tcg_temp_ebb_new_i32(void) 1978 { 1979 return temp_tcgv_i32(tcg_temp_new_internal(TCG_TYPE_I32, TEMP_EBB)); 1980 } 1981 1982 TCGv_i64 tcg_temp_new_i64(void) 1983 { 1984 return temp_tcgv_i64(tcg_temp_new_internal(TCG_TYPE_I64, TEMP_TB)); 1985 } 1986 1987 TCGv_i64 tcg_temp_ebb_new_i64(void) 1988 { 1989 return temp_tcgv_i64(tcg_temp_new_internal(TCG_TYPE_I64, TEMP_EBB)); 1990 } 1991 1992 TCGv_ptr tcg_temp_new_ptr(void) 1993 { 1994 return temp_tcgv_ptr(tcg_temp_new_internal(TCG_TYPE_PTR, TEMP_TB)); 1995 } 1996 1997 TCGv_ptr tcg_temp_ebb_new_ptr(void) 1998 { 1999 return temp_tcgv_ptr(tcg_temp_new_internal(TCG_TYPE_PTR, TEMP_EBB)); 2000 } 2001 2002 TCGv_i128 tcg_temp_new_i128(void) 2003 { 2004 return temp_tcgv_i128(tcg_temp_new_internal(TCG_TYPE_I128, TEMP_TB)); 2005 } 2006 2007 TCGv_i128 tcg_temp_ebb_new_i128(void) 2008 { 2009 return temp_tcgv_i128(tcg_temp_new_internal(TCG_TYPE_I128, TEMP_EBB)); 2010 } 2011 2012 TCGv_vec tcg_temp_new_vec(TCGType type) 2013 { 2014 TCGTemp *t; 2015 2016 #ifdef CONFIG_DEBUG_TCG 2017 switch (type) { 2018 case TCG_TYPE_V64: 2019 assert(TCG_TARGET_HAS_v64); 2020 break; 2021 case TCG_TYPE_V128: 2022 assert(TCG_TARGET_HAS_v128); 2023 break; 2024 case TCG_TYPE_V256: 2025 assert(TCG_TARGET_HAS_v256); 2026 break; 2027 default: 2028 g_assert_not_reached(); 2029 } 2030 #endif 2031 2032 t = tcg_temp_new_internal(type, TEMP_EBB); 2033 return temp_tcgv_vec(t); 2034 } 2035 2036 /* Create a new temp of the same type as an existing temp. */ 2037 TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match) 2038 { 2039 TCGTemp *t = tcgv_vec_temp(match); 2040 2041 tcg_debug_assert(t->temp_allocated != 0); 2042 2043 t = tcg_temp_new_internal(t->base_type, TEMP_EBB); 2044 return temp_tcgv_vec(t); 2045 } 2046 2047 void tcg_temp_free_internal(TCGTemp *ts) 2048 { 2049 TCGContext *s = tcg_ctx; 2050 2051 switch (ts->kind) { 2052 case TEMP_CONST: 2053 case TEMP_TB: 2054 /* Silently ignore free. */ 2055 break; 2056 case TEMP_EBB: 2057 tcg_debug_assert(ts->temp_allocated != 0); 2058 ts->temp_allocated = 0; 2059 set_bit(temp_idx(ts), s->free_temps[ts->base_type].l); 2060 break; 2061 default: 2062 /* It never made sense to free TEMP_FIXED or TEMP_GLOBAL. */ 2063 g_assert_not_reached(); 2064 } 2065 } 2066 2067 void tcg_temp_free_i32(TCGv_i32 arg) 2068 { 2069 tcg_temp_free_internal(tcgv_i32_temp(arg)); 2070 } 2071 2072 void tcg_temp_free_i64(TCGv_i64 arg) 2073 { 2074 tcg_temp_free_internal(tcgv_i64_temp(arg)); 2075 } 2076 2077 void tcg_temp_free_i128(TCGv_i128 arg) 2078 { 2079 tcg_temp_free_internal(tcgv_i128_temp(arg)); 2080 } 2081 2082 void tcg_temp_free_ptr(TCGv_ptr arg) 2083 { 2084 tcg_temp_free_internal(tcgv_ptr_temp(arg)); 2085 } 2086 2087 void tcg_temp_free_vec(TCGv_vec arg) 2088 { 2089 tcg_temp_free_internal(tcgv_vec_temp(arg)); 2090 } 2091 2092 TCGTemp *tcg_constant_internal(TCGType type, int64_t val) 2093 { 2094 TCGContext *s = tcg_ctx; 2095 GHashTable *h = s->const_table[type]; 2096 TCGTemp *ts; 2097 2098 if (h == NULL) { 2099 h = g_hash_table_new(g_int64_hash, g_int64_equal); 2100 s->const_table[type] = h; 2101 } 2102 2103 ts = g_hash_table_lookup(h, &val); 2104 if (ts == NULL) { 2105 int64_t *val_ptr; 2106 2107 ts = tcg_temp_alloc(s); 2108 2109 if (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64) { 2110 TCGTemp *ts2 = tcg_temp_alloc(s); 2111 2112 tcg_debug_assert(ts2 == ts + 1); 2113 2114 ts->base_type = TCG_TYPE_I64; 2115 ts->type = TCG_TYPE_I32; 2116 ts->kind = TEMP_CONST; 2117 ts->temp_allocated = 1; 2118 2119 ts2->base_type = TCG_TYPE_I64; 2120 ts2->type = TCG_TYPE_I32; 2121 ts2->kind = TEMP_CONST; 2122 ts2->temp_allocated = 1; 2123 ts2->temp_subindex = 1; 2124 2125 /* 2126 * Retain the full value of the 64-bit constant in the low 2127 * part, so that the hash table works. Actual uses will 2128 * truncate the value to the low part. 2129 */ 2130 ts[HOST_BIG_ENDIAN].val = val; 2131 ts[!HOST_BIG_ENDIAN].val = val >> 32; 2132 val_ptr = &ts[HOST_BIG_ENDIAN].val; 2133 } else { 2134 ts->base_type = type; 2135 ts->type = type; 2136 ts->kind = TEMP_CONST; 2137 ts->temp_allocated = 1; 2138 ts->val = val; 2139 val_ptr = &ts->val; 2140 } 2141 g_hash_table_insert(h, val_ptr, ts); 2142 } 2143 2144 return ts; 2145 } 2146 2147 TCGv_i32 tcg_constant_i32(int32_t val) 2148 { 2149 return temp_tcgv_i32(tcg_constant_internal(TCG_TYPE_I32, val)); 2150 } 2151 2152 TCGv_i64 tcg_constant_i64(int64_t val) 2153 { 2154 return temp_tcgv_i64(tcg_constant_internal(TCG_TYPE_I64, val)); 2155 } 2156 2157 TCGv_ptr tcg_constant_ptr_int(intptr_t val) 2158 { 2159 return temp_tcgv_ptr(tcg_constant_internal(TCG_TYPE_PTR, val)); 2160 } 2161 2162 TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val) 2163 { 2164 val = dup_const(vece, val); 2165 return temp_tcgv_vec(tcg_constant_internal(type, val)); 2166 } 2167 2168 TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t val) 2169 { 2170 TCGTemp *t = tcgv_vec_temp(match); 2171 2172 tcg_debug_assert(t->temp_allocated != 0); 2173 return tcg_constant_vec(t->base_type, vece, val); 2174 } 2175 2176 #ifdef CONFIG_DEBUG_TCG 2177 size_t temp_idx(TCGTemp *ts) 2178 { 2179 ptrdiff_t n = ts - tcg_ctx->temps; 2180 assert(n >= 0 && n < tcg_ctx->nb_temps); 2181 return n; 2182 } 2183 2184 TCGTemp *tcgv_i32_temp(TCGv_i32 v) 2185 { 2186 uintptr_t o = (uintptr_t)v - offsetof(TCGContext, temps); 2187 2188 assert(o < sizeof(TCGTemp) * tcg_ctx->nb_temps); 2189 assert(o % sizeof(TCGTemp) == 0); 2190 2191 return (void *)tcg_ctx + (uintptr_t)v; 2192 } 2193 #endif /* CONFIG_DEBUG_TCG */ 2194 2195 /* 2196 * Return true if OP may appear in the opcode stream with TYPE. 2197 * Test the runtime variable that controls each opcode. 2198 */ 2199 bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags) 2200 { 2201 bool has_type; 2202 2203 switch (type) { 2204 case TCG_TYPE_I32: 2205 has_type = true; 2206 break; 2207 case TCG_TYPE_I64: 2208 has_type = TCG_TARGET_REG_BITS == 64; 2209 break; 2210 case TCG_TYPE_V64: 2211 has_type = TCG_TARGET_HAS_v64; 2212 break; 2213 case TCG_TYPE_V128: 2214 has_type = TCG_TARGET_HAS_v128; 2215 break; 2216 case TCG_TYPE_V256: 2217 has_type = TCG_TARGET_HAS_v256; 2218 break; 2219 default: 2220 has_type = false; 2221 break; 2222 } 2223 2224 switch (op) { 2225 case INDEX_op_discard: 2226 case INDEX_op_set_label: 2227 case INDEX_op_call: 2228 case INDEX_op_br: 2229 case INDEX_op_mb: 2230 case INDEX_op_insn_start: 2231 case INDEX_op_exit_tb: 2232 case INDEX_op_goto_tb: 2233 case INDEX_op_goto_ptr: 2234 case INDEX_op_qemu_ld_i32: 2235 case INDEX_op_qemu_st_i32: 2236 case INDEX_op_qemu_ld_i64: 2237 case INDEX_op_qemu_st_i64: 2238 return true; 2239 2240 case INDEX_op_qemu_st8_i32: 2241 return TCG_TARGET_HAS_qemu_st8_i32; 2242 2243 case INDEX_op_qemu_ld_i128: 2244 case INDEX_op_qemu_st_i128: 2245 return TCG_TARGET_HAS_qemu_ldst_i128; 2246 2247 case INDEX_op_add: 2248 case INDEX_op_and: 2249 case INDEX_op_mov: 2250 case INDEX_op_or: 2251 case INDEX_op_xor: 2252 return has_type; 2253 2254 case INDEX_op_setcond_i32: 2255 case INDEX_op_brcond_i32: 2256 case INDEX_op_movcond_i32: 2257 case INDEX_op_ld8u_i32: 2258 case INDEX_op_ld8s_i32: 2259 case INDEX_op_ld16u_i32: 2260 case INDEX_op_ld16s_i32: 2261 case INDEX_op_ld_i32: 2262 case INDEX_op_st8_i32: 2263 case INDEX_op_st16_i32: 2264 case INDEX_op_st_i32: 2265 case INDEX_op_shl_i32: 2266 case INDEX_op_shr_i32: 2267 case INDEX_op_sar_i32: 2268 case INDEX_op_extract_i32: 2269 case INDEX_op_sextract_i32: 2270 case INDEX_op_deposit_i32: 2271 return true; 2272 2273 case INDEX_op_negsetcond_i32: 2274 return TCG_TARGET_HAS_negsetcond_i32; 2275 case INDEX_op_rotl_i32: 2276 case INDEX_op_rotr_i32: 2277 return TCG_TARGET_HAS_rot_i32; 2278 case INDEX_op_extract2_i32: 2279 return TCG_TARGET_HAS_extract2_i32; 2280 case INDEX_op_add2_i32: 2281 return TCG_TARGET_HAS_add2_i32; 2282 case INDEX_op_sub2_i32: 2283 return TCG_TARGET_HAS_sub2_i32; 2284 case INDEX_op_mulu2_i32: 2285 return TCG_TARGET_HAS_mulu2_i32; 2286 case INDEX_op_muls2_i32: 2287 return TCG_TARGET_HAS_muls2_i32; 2288 case INDEX_op_bswap16_i32: 2289 return TCG_TARGET_HAS_bswap16_i32; 2290 case INDEX_op_bswap32_i32: 2291 return TCG_TARGET_HAS_bswap32_i32; 2292 case INDEX_op_clz_i32: 2293 return TCG_TARGET_HAS_clz_i32; 2294 case INDEX_op_ctz_i32: 2295 return TCG_TARGET_HAS_ctz_i32; 2296 case INDEX_op_ctpop_i32: 2297 return TCG_TARGET_HAS_ctpop_i32; 2298 2299 case INDEX_op_brcond2_i32: 2300 case INDEX_op_setcond2_i32: 2301 return TCG_TARGET_REG_BITS == 32; 2302 2303 case INDEX_op_setcond_i64: 2304 case INDEX_op_brcond_i64: 2305 case INDEX_op_movcond_i64: 2306 case INDEX_op_ld8u_i64: 2307 case INDEX_op_ld8s_i64: 2308 case INDEX_op_ld16u_i64: 2309 case INDEX_op_ld16s_i64: 2310 case INDEX_op_ld32u_i64: 2311 case INDEX_op_ld32s_i64: 2312 case INDEX_op_ld_i64: 2313 case INDEX_op_st8_i64: 2314 case INDEX_op_st16_i64: 2315 case INDEX_op_st32_i64: 2316 case INDEX_op_st_i64: 2317 case INDEX_op_shl_i64: 2318 case INDEX_op_shr_i64: 2319 case INDEX_op_sar_i64: 2320 case INDEX_op_ext_i32_i64: 2321 case INDEX_op_extu_i32_i64: 2322 case INDEX_op_extract_i64: 2323 case INDEX_op_sextract_i64: 2324 case INDEX_op_deposit_i64: 2325 return TCG_TARGET_REG_BITS == 64; 2326 2327 case INDEX_op_negsetcond_i64: 2328 return TCG_TARGET_HAS_negsetcond_i64; 2329 case INDEX_op_rotl_i64: 2330 case INDEX_op_rotr_i64: 2331 return TCG_TARGET_HAS_rot_i64; 2332 case INDEX_op_extract2_i64: 2333 return TCG_TARGET_HAS_extract2_i64; 2334 case INDEX_op_extrl_i64_i32: 2335 case INDEX_op_extrh_i64_i32: 2336 return TCG_TARGET_HAS_extr_i64_i32; 2337 case INDEX_op_bswap16_i64: 2338 return TCG_TARGET_HAS_bswap16_i64; 2339 case INDEX_op_bswap32_i64: 2340 return TCG_TARGET_HAS_bswap32_i64; 2341 case INDEX_op_bswap64_i64: 2342 return TCG_TARGET_HAS_bswap64_i64; 2343 case INDEX_op_clz_i64: 2344 return TCG_TARGET_HAS_clz_i64; 2345 case INDEX_op_ctz_i64: 2346 return TCG_TARGET_HAS_ctz_i64; 2347 case INDEX_op_ctpop_i64: 2348 return TCG_TARGET_HAS_ctpop_i64; 2349 case INDEX_op_add2_i64: 2350 return TCG_TARGET_HAS_add2_i64; 2351 case INDEX_op_sub2_i64: 2352 return TCG_TARGET_HAS_sub2_i64; 2353 case INDEX_op_mulu2_i64: 2354 return TCG_TARGET_HAS_mulu2_i64; 2355 case INDEX_op_muls2_i64: 2356 return TCG_TARGET_HAS_muls2_i64; 2357 2358 case INDEX_op_mov_vec: 2359 case INDEX_op_dup_vec: 2360 case INDEX_op_dupm_vec: 2361 case INDEX_op_ld_vec: 2362 case INDEX_op_st_vec: 2363 case INDEX_op_add_vec: 2364 case INDEX_op_sub_vec: 2365 case INDEX_op_and_vec: 2366 case INDEX_op_or_vec: 2367 case INDEX_op_xor_vec: 2368 case INDEX_op_cmp_vec: 2369 return has_type; 2370 case INDEX_op_dup2_vec: 2371 return has_type && TCG_TARGET_REG_BITS == 32; 2372 case INDEX_op_not_vec: 2373 return has_type && TCG_TARGET_HAS_not_vec; 2374 case INDEX_op_neg_vec: 2375 return has_type && TCG_TARGET_HAS_neg_vec; 2376 case INDEX_op_abs_vec: 2377 return has_type && TCG_TARGET_HAS_abs_vec; 2378 case INDEX_op_andc_vec: 2379 return has_type && TCG_TARGET_HAS_andc_vec; 2380 case INDEX_op_orc_vec: 2381 return has_type && TCG_TARGET_HAS_orc_vec; 2382 case INDEX_op_nand_vec: 2383 return has_type && TCG_TARGET_HAS_nand_vec; 2384 case INDEX_op_nor_vec: 2385 return has_type && TCG_TARGET_HAS_nor_vec; 2386 case INDEX_op_eqv_vec: 2387 return has_type && TCG_TARGET_HAS_eqv_vec; 2388 case INDEX_op_mul_vec: 2389 return has_type && TCG_TARGET_HAS_mul_vec; 2390 case INDEX_op_shli_vec: 2391 case INDEX_op_shri_vec: 2392 case INDEX_op_sari_vec: 2393 return has_type && TCG_TARGET_HAS_shi_vec; 2394 case INDEX_op_shls_vec: 2395 case INDEX_op_shrs_vec: 2396 case INDEX_op_sars_vec: 2397 return has_type && TCG_TARGET_HAS_shs_vec; 2398 case INDEX_op_shlv_vec: 2399 case INDEX_op_shrv_vec: 2400 case INDEX_op_sarv_vec: 2401 return has_type && TCG_TARGET_HAS_shv_vec; 2402 case INDEX_op_rotli_vec: 2403 return has_type && TCG_TARGET_HAS_roti_vec; 2404 case INDEX_op_rotls_vec: 2405 return has_type && TCG_TARGET_HAS_rots_vec; 2406 case INDEX_op_rotlv_vec: 2407 case INDEX_op_rotrv_vec: 2408 return has_type && TCG_TARGET_HAS_rotv_vec; 2409 case INDEX_op_ssadd_vec: 2410 case INDEX_op_usadd_vec: 2411 case INDEX_op_sssub_vec: 2412 case INDEX_op_ussub_vec: 2413 return has_type && TCG_TARGET_HAS_sat_vec; 2414 case INDEX_op_smin_vec: 2415 case INDEX_op_umin_vec: 2416 case INDEX_op_smax_vec: 2417 case INDEX_op_umax_vec: 2418 return has_type && TCG_TARGET_HAS_minmax_vec; 2419 case INDEX_op_bitsel_vec: 2420 return has_type && TCG_TARGET_HAS_bitsel_vec; 2421 case INDEX_op_cmpsel_vec: 2422 return has_type && TCG_TARGET_HAS_cmpsel_vec; 2423 2424 default: 2425 if (op < INDEX_op_last_generic) { 2426 const TCGOutOp *outop; 2427 TCGConstraintSetIndex con_set; 2428 2429 if (!has_type) { 2430 return false; 2431 } 2432 2433 outop = all_outop[op]; 2434 tcg_debug_assert(outop != NULL); 2435 2436 con_set = outop->static_constraint; 2437 if (con_set == C_Dynamic) { 2438 con_set = outop->dynamic_constraint(type, flags); 2439 } 2440 if (con_set >= 0) { 2441 return true; 2442 } 2443 tcg_debug_assert(con_set == C_NotImplemented); 2444 return false; 2445 } 2446 tcg_debug_assert(op < NB_OPS); 2447 return true; 2448 2449 case INDEX_op_last_generic: 2450 g_assert_not_reached(); 2451 } 2452 } 2453 2454 bool tcg_op_deposit_valid(TCGType type, unsigned ofs, unsigned len) 2455 { 2456 unsigned width; 2457 2458 tcg_debug_assert(type == TCG_TYPE_I32 || type == TCG_TYPE_I64); 2459 width = (type == TCG_TYPE_I32 ? 32 : 64); 2460 2461 tcg_debug_assert(ofs < width); 2462 tcg_debug_assert(len > 0); 2463 tcg_debug_assert(len <= width - ofs); 2464 2465 return TCG_TARGET_deposit_valid(type, ofs, len); 2466 } 2467 2468 static TCGOp *tcg_op_alloc(TCGOpcode opc, unsigned nargs); 2469 2470 static void tcg_gen_callN(void *func, TCGHelperInfo *info, 2471 TCGTemp *ret, TCGTemp **args) 2472 { 2473 TCGv_i64 extend_free[MAX_CALL_IARGS]; 2474 int n_extend = 0; 2475 TCGOp *op; 2476 int i, n, pi = 0, total_args; 2477 2478 if (unlikely(g_once_init_enter(HELPER_INFO_INIT(info)))) { 2479 init_call_layout(info); 2480 g_once_init_leave(HELPER_INFO_INIT(info), HELPER_INFO_INIT_VAL(info)); 2481 } 2482 2483 total_args = info->nr_out + info->nr_in + 2; 2484 op = tcg_op_alloc(INDEX_op_call, total_args); 2485 2486 #ifdef CONFIG_PLUGIN 2487 /* Flag helpers that may affect guest state */ 2488 if (tcg_ctx->plugin_insn && !(info->flags & TCG_CALL_NO_SIDE_EFFECTS)) { 2489 tcg_ctx->plugin_insn->calls_helpers = true; 2490 } 2491 #endif 2492 2493 TCGOP_CALLO(op) = n = info->nr_out; 2494 switch (n) { 2495 case 0: 2496 tcg_debug_assert(ret == NULL); 2497 break; 2498 case 1: 2499 tcg_debug_assert(ret != NULL); 2500 op->args[pi++] = temp_arg(ret); 2501 break; 2502 case 2: 2503 case 4: 2504 tcg_debug_assert(ret != NULL); 2505 tcg_debug_assert(ret->base_type == ret->type + ctz32(n)); 2506 tcg_debug_assert(ret->temp_subindex == 0); 2507 for (i = 0; i < n; ++i) { 2508 op->args[pi++] = temp_arg(ret + i); 2509 } 2510 break; 2511 default: 2512 g_assert_not_reached(); 2513 } 2514 2515 TCGOP_CALLI(op) = n = info->nr_in; 2516 for (i = 0; i < n; i++) { 2517 const TCGCallArgumentLoc *loc = &info->in[i]; 2518 TCGTemp *ts = args[loc->arg_idx] + loc->tmp_subindex; 2519 2520 switch (loc->kind) { 2521 case TCG_CALL_ARG_NORMAL: 2522 case TCG_CALL_ARG_BY_REF: 2523 case TCG_CALL_ARG_BY_REF_N: 2524 op->args[pi++] = temp_arg(ts); 2525 break; 2526 2527 case TCG_CALL_ARG_EXTEND_U: 2528 case TCG_CALL_ARG_EXTEND_S: 2529 { 2530 TCGv_i64 temp = tcg_temp_ebb_new_i64(); 2531 TCGv_i32 orig = temp_tcgv_i32(ts); 2532 2533 if (loc->kind == TCG_CALL_ARG_EXTEND_S) { 2534 tcg_gen_ext_i32_i64(temp, orig); 2535 } else { 2536 tcg_gen_extu_i32_i64(temp, orig); 2537 } 2538 op->args[pi++] = tcgv_i64_arg(temp); 2539 extend_free[n_extend++] = temp; 2540 } 2541 break; 2542 2543 default: 2544 g_assert_not_reached(); 2545 } 2546 } 2547 op->args[pi++] = (uintptr_t)func; 2548 op->args[pi++] = (uintptr_t)info; 2549 tcg_debug_assert(pi == total_args); 2550 2551 if (tcg_ctx->emit_before_op) { 2552 QTAILQ_INSERT_BEFORE(tcg_ctx->emit_before_op, op, link); 2553 } else { 2554 QTAILQ_INSERT_TAIL(&tcg_ctx->ops, op, link); 2555 } 2556 2557 tcg_debug_assert(n_extend < ARRAY_SIZE(extend_free)); 2558 for (i = 0; i < n_extend; ++i) { 2559 tcg_temp_free_i64(extend_free[i]); 2560 } 2561 } 2562 2563 void tcg_gen_call0(void *func, TCGHelperInfo *info, TCGTemp *ret) 2564 { 2565 tcg_gen_callN(func, info, ret, NULL); 2566 } 2567 2568 void tcg_gen_call1(void *func, TCGHelperInfo *info, TCGTemp *ret, TCGTemp *t1) 2569 { 2570 tcg_gen_callN(func, info, ret, &t1); 2571 } 2572 2573 void tcg_gen_call2(void *func, TCGHelperInfo *info, TCGTemp *ret, 2574 TCGTemp *t1, TCGTemp *t2) 2575 { 2576 TCGTemp *args[2] = { t1, t2 }; 2577 tcg_gen_callN(func, info, ret, args); 2578 } 2579 2580 void tcg_gen_call3(void *func, TCGHelperInfo *info, TCGTemp *ret, 2581 TCGTemp *t1, TCGTemp *t2, TCGTemp *t3) 2582 { 2583 TCGTemp *args[3] = { t1, t2, t3 }; 2584 tcg_gen_callN(func, info, ret, args); 2585 } 2586 2587 void tcg_gen_call4(void *func, TCGHelperInfo *info, TCGTemp *ret, 2588 TCGTemp *t1, TCGTemp *t2, TCGTemp *t3, TCGTemp *t4) 2589 { 2590 TCGTemp *args[4] = { t1, t2, t3, t4 }; 2591 tcg_gen_callN(func, info, ret, args); 2592 } 2593 2594 void tcg_gen_call5(void *func, TCGHelperInfo *info, TCGTemp *ret, TCGTemp *t1, 2595 TCGTemp *t2, TCGTemp *t3, TCGTemp *t4, TCGTemp *t5) 2596 { 2597 TCGTemp *args[5] = { t1, t2, t3, t4, t5 }; 2598 tcg_gen_callN(func, info, ret, args); 2599 } 2600 2601 void tcg_gen_call6(void *func, TCGHelperInfo *info, TCGTemp *ret, 2602 TCGTemp *t1, TCGTemp *t2, TCGTemp *t3, 2603 TCGTemp *t4, TCGTemp *t5, TCGTemp *t6) 2604 { 2605 TCGTemp *args[6] = { t1, t2, t3, t4, t5, t6 }; 2606 tcg_gen_callN(func, info, ret, args); 2607 } 2608 2609 void tcg_gen_call7(void *func, TCGHelperInfo *info, TCGTemp *ret, TCGTemp *t1, 2610 TCGTemp *t2, TCGTemp *t3, TCGTemp *t4, 2611 TCGTemp *t5, TCGTemp *t6, TCGTemp *t7) 2612 { 2613 TCGTemp *args[7] = { t1, t2, t3, t4, t5, t6, t7 }; 2614 tcg_gen_callN(func, info, ret, args); 2615 } 2616 2617 static void tcg_reg_alloc_start(TCGContext *s) 2618 { 2619 int i, n; 2620 2621 for (i = 0, n = s->nb_temps; i < n; i++) { 2622 TCGTemp *ts = &s->temps[i]; 2623 TCGTempVal val = TEMP_VAL_MEM; 2624 2625 switch (ts->kind) { 2626 case TEMP_CONST: 2627 val = TEMP_VAL_CONST; 2628 break; 2629 case TEMP_FIXED: 2630 val = TEMP_VAL_REG; 2631 break; 2632 case TEMP_GLOBAL: 2633 break; 2634 case TEMP_EBB: 2635 val = TEMP_VAL_DEAD; 2636 /* fall through */ 2637 case TEMP_TB: 2638 ts->mem_allocated = 0; 2639 break; 2640 default: 2641 g_assert_not_reached(); 2642 } 2643 ts->val_type = val; 2644 } 2645 2646 memset(s->reg_to_temp, 0, sizeof(s->reg_to_temp)); 2647 } 2648 2649 static char *tcg_get_arg_str_ptr(TCGContext *s, char *buf, int buf_size, 2650 TCGTemp *ts) 2651 { 2652 int idx = temp_idx(ts); 2653 2654 switch (ts->kind) { 2655 case TEMP_FIXED: 2656 case TEMP_GLOBAL: 2657 pstrcpy(buf, buf_size, ts->name); 2658 break; 2659 case TEMP_TB: 2660 snprintf(buf, buf_size, "loc%d", idx - s->nb_globals); 2661 break; 2662 case TEMP_EBB: 2663 snprintf(buf, buf_size, "tmp%d", idx - s->nb_globals); 2664 break; 2665 case TEMP_CONST: 2666 switch (ts->type) { 2667 case TCG_TYPE_I32: 2668 snprintf(buf, buf_size, "$0x%x", (int32_t)ts->val); 2669 break; 2670 #if TCG_TARGET_REG_BITS > 32 2671 case TCG_TYPE_I64: 2672 snprintf(buf, buf_size, "$0x%" PRIx64, ts->val); 2673 break; 2674 #endif 2675 case TCG_TYPE_V64: 2676 case TCG_TYPE_V128: 2677 case TCG_TYPE_V256: 2678 snprintf(buf, buf_size, "v%d$0x%" PRIx64, 2679 64 << (ts->type - TCG_TYPE_V64), ts->val); 2680 break; 2681 default: 2682 g_assert_not_reached(); 2683 } 2684 break; 2685 } 2686 return buf; 2687 } 2688 2689 static char *tcg_get_arg_str(TCGContext *s, char *buf, 2690 int buf_size, TCGArg arg) 2691 { 2692 return tcg_get_arg_str_ptr(s, buf, buf_size, arg_temp(arg)); 2693 } 2694 2695 static const char * const cond_name[] = 2696 { 2697 [TCG_COND_NEVER] = "never", 2698 [TCG_COND_ALWAYS] = "always", 2699 [TCG_COND_EQ] = "eq", 2700 [TCG_COND_NE] = "ne", 2701 [TCG_COND_LT] = "lt", 2702 [TCG_COND_GE] = "ge", 2703 [TCG_COND_LE] = "le", 2704 [TCG_COND_GT] = "gt", 2705 [TCG_COND_LTU] = "ltu", 2706 [TCG_COND_GEU] = "geu", 2707 [TCG_COND_LEU] = "leu", 2708 [TCG_COND_GTU] = "gtu", 2709 [TCG_COND_TSTEQ] = "tsteq", 2710 [TCG_COND_TSTNE] = "tstne", 2711 }; 2712 2713 static const char * const ldst_name[(MO_BSWAP | MO_SSIZE) + 1] = 2714 { 2715 [MO_UB] = "ub", 2716 [MO_SB] = "sb", 2717 [MO_LEUW] = "leuw", 2718 [MO_LESW] = "lesw", 2719 [MO_LEUL] = "leul", 2720 [MO_LESL] = "lesl", 2721 [MO_LEUQ] = "leq", 2722 [MO_BEUW] = "beuw", 2723 [MO_BESW] = "besw", 2724 [MO_BEUL] = "beul", 2725 [MO_BESL] = "besl", 2726 [MO_BEUQ] = "beq", 2727 [MO_128 + MO_BE] = "beo", 2728 [MO_128 + MO_LE] = "leo", 2729 }; 2730 2731 static const char * const alignment_name[(MO_AMASK >> MO_ASHIFT) + 1] = { 2732 [MO_UNALN >> MO_ASHIFT] = "un+", 2733 [MO_ALIGN >> MO_ASHIFT] = "al+", 2734 [MO_ALIGN_2 >> MO_ASHIFT] = "al2+", 2735 [MO_ALIGN_4 >> MO_ASHIFT] = "al4+", 2736 [MO_ALIGN_8 >> MO_ASHIFT] = "al8+", 2737 [MO_ALIGN_16 >> MO_ASHIFT] = "al16+", 2738 [MO_ALIGN_32 >> MO_ASHIFT] = "al32+", 2739 [MO_ALIGN_64 >> MO_ASHIFT] = "al64+", 2740 }; 2741 2742 static const char * const atom_name[(MO_ATOM_MASK >> MO_ATOM_SHIFT) + 1] = { 2743 [MO_ATOM_IFALIGN >> MO_ATOM_SHIFT] = "", 2744 [MO_ATOM_IFALIGN_PAIR >> MO_ATOM_SHIFT] = "pair+", 2745 [MO_ATOM_WITHIN16 >> MO_ATOM_SHIFT] = "w16+", 2746 [MO_ATOM_WITHIN16_PAIR >> MO_ATOM_SHIFT] = "w16p+", 2747 [MO_ATOM_SUBALIGN >> MO_ATOM_SHIFT] = "sub+", 2748 [MO_ATOM_NONE >> MO_ATOM_SHIFT] = "noat+", 2749 }; 2750 2751 static const char bswap_flag_name[][6] = { 2752 [TCG_BSWAP_IZ] = "iz", 2753 [TCG_BSWAP_OZ] = "oz", 2754 [TCG_BSWAP_OS] = "os", 2755 [TCG_BSWAP_IZ | TCG_BSWAP_OZ] = "iz,oz", 2756 [TCG_BSWAP_IZ | TCG_BSWAP_OS] = "iz,os", 2757 }; 2758 2759 #ifdef CONFIG_PLUGIN 2760 static const char * const plugin_from_name[] = { 2761 "from-tb", 2762 "from-insn", 2763 "after-insn", 2764 "after-tb", 2765 }; 2766 #endif 2767 2768 static inline bool tcg_regset_single(TCGRegSet d) 2769 { 2770 return (d & (d - 1)) == 0; 2771 } 2772 2773 static inline TCGReg tcg_regset_first(TCGRegSet d) 2774 { 2775 if (TCG_TARGET_NB_REGS <= 32) { 2776 return ctz32(d); 2777 } else { 2778 return ctz64(d); 2779 } 2780 } 2781 2782 /* Return only the number of characters output -- no error return. */ 2783 #define ne_fprintf(...) \ 2784 ({ int ret_ = fprintf(__VA_ARGS__); ret_ >= 0 ? ret_ : 0; }) 2785 2786 void tcg_dump_ops(TCGContext *s, FILE *f, bool have_prefs) 2787 { 2788 char buf[128]; 2789 TCGOp *op; 2790 2791 QTAILQ_FOREACH(op, &s->ops, link) { 2792 int i, k, nb_oargs, nb_iargs, nb_cargs; 2793 const TCGOpDef *def; 2794 TCGOpcode c; 2795 int col = 0; 2796 2797 c = op->opc; 2798 def = &tcg_op_defs[c]; 2799 2800 if (c == INDEX_op_insn_start) { 2801 nb_oargs = 0; 2802 col += ne_fprintf(f, "\n ----"); 2803 2804 for (i = 0, k = s->insn_start_words; i < k; ++i) { 2805 col += ne_fprintf(f, " %016" PRIx64, 2806 tcg_get_insn_start_param(op, i)); 2807 } 2808 } else if (c == INDEX_op_call) { 2809 const TCGHelperInfo *info = tcg_call_info(op); 2810 void *func = tcg_call_func(op); 2811 2812 /* variable number of arguments */ 2813 nb_oargs = TCGOP_CALLO(op); 2814 nb_iargs = TCGOP_CALLI(op); 2815 nb_cargs = def->nb_cargs; 2816 2817 col += ne_fprintf(f, " %s ", def->name); 2818 2819 /* 2820 * Print the function name from TCGHelperInfo, if available. 2821 * Note that plugins have a template function for the info, 2822 * but the actual function pointer comes from the plugin. 2823 */ 2824 if (func == info->func) { 2825 col += ne_fprintf(f, "%s", info->name); 2826 } else { 2827 col += ne_fprintf(f, "plugin(%p)", func); 2828 } 2829 2830 col += ne_fprintf(f, ",$0x%x,$%d", info->flags, nb_oargs); 2831 for (i = 0; i < nb_oargs; i++) { 2832 col += ne_fprintf(f, ",%s", tcg_get_arg_str(s, buf, sizeof(buf), 2833 op->args[i])); 2834 } 2835 for (i = 0; i < nb_iargs; i++) { 2836 TCGArg arg = op->args[nb_oargs + i]; 2837 const char *t = tcg_get_arg_str(s, buf, sizeof(buf), arg); 2838 col += ne_fprintf(f, ",%s", t); 2839 } 2840 } else { 2841 if (def->flags & TCG_OPF_INT) { 2842 col += ne_fprintf(f, " %s_i%d ", 2843 def->name, 2844 8 * tcg_type_size(TCGOP_TYPE(op))); 2845 } else if (def->flags & TCG_OPF_VECTOR) { 2846 col += ne_fprintf(f, "%s v%d,e%d,", 2847 def->name, 2848 8 * tcg_type_size(TCGOP_TYPE(op)), 2849 8 << TCGOP_VECE(op)); 2850 } else { 2851 col += ne_fprintf(f, " %s ", def->name); 2852 } 2853 2854 nb_oargs = def->nb_oargs; 2855 nb_iargs = def->nb_iargs; 2856 nb_cargs = def->nb_cargs; 2857 2858 k = 0; 2859 for (i = 0; i < nb_oargs; i++) { 2860 const char *sep = k ? "," : ""; 2861 col += ne_fprintf(f, "%s%s", sep, 2862 tcg_get_arg_str(s, buf, sizeof(buf), 2863 op->args[k++])); 2864 } 2865 for (i = 0; i < nb_iargs; i++) { 2866 const char *sep = k ? "," : ""; 2867 col += ne_fprintf(f, "%s%s", sep, 2868 tcg_get_arg_str(s, buf, sizeof(buf), 2869 op->args[k++])); 2870 } 2871 switch (c) { 2872 case INDEX_op_brcond_i32: 2873 case INDEX_op_setcond_i32: 2874 case INDEX_op_negsetcond_i32: 2875 case INDEX_op_movcond_i32: 2876 case INDEX_op_brcond2_i32: 2877 case INDEX_op_setcond2_i32: 2878 case INDEX_op_brcond_i64: 2879 case INDEX_op_setcond_i64: 2880 case INDEX_op_negsetcond_i64: 2881 case INDEX_op_movcond_i64: 2882 case INDEX_op_cmp_vec: 2883 case INDEX_op_cmpsel_vec: 2884 if (op->args[k] < ARRAY_SIZE(cond_name) 2885 && cond_name[op->args[k]]) { 2886 col += ne_fprintf(f, ",%s", cond_name[op->args[k++]]); 2887 } else { 2888 col += ne_fprintf(f, ",$0x%" TCG_PRIlx, op->args[k++]); 2889 } 2890 i = 1; 2891 break; 2892 case INDEX_op_qemu_ld_i32: 2893 case INDEX_op_qemu_st_i32: 2894 case INDEX_op_qemu_st8_i32: 2895 case INDEX_op_qemu_ld_i64: 2896 case INDEX_op_qemu_st_i64: 2897 case INDEX_op_qemu_ld_i128: 2898 case INDEX_op_qemu_st_i128: 2899 { 2900 const char *s_al, *s_op, *s_at; 2901 MemOpIdx oi = op->args[k++]; 2902 MemOp mop = get_memop(oi); 2903 unsigned ix = get_mmuidx(oi); 2904 2905 s_al = alignment_name[(mop & MO_AMASK) >> MO_ASHIFT]; 2906 s_op = ldst_name[mop & (MO_BSWAP | MO_SSIZE)]; 2907 s_at = atom_name[(mop & MO_ATOM_MASK) >> MO_ATOM_SHIFT]; 2908 mop &= ~(MO_AMASK | MO_BSWAP | MO_SSIZE | MO_ATOM_MASK); 2909 2910 /* If all fields are accounted for, print symbolically. */ 2911 if (!mop && s_al && s_op && s_at) { 2912 col += ne_fprintf(f, ",%s%s%s,%u", 2913 s_at, s_al, s_op, ix); 2914 } else { 2915 mop = get_memop(oi); 2916 col += ne_fprintf(f, ",$0x%x,%u", mop, ix); 2917 } 2918 i = 1; 2919 } 2920 break; 2921 case INDEX_op_bswap16_i32: 2922 case INDEX_op_bswap16_i64: 2923 case INDEX_op_bswap32_i32: 2924 case INDEX_op_bswap32_i64: 2925 case INDEX_op_bswap64_i64: 2926 { 2927 TCGArg flags = op->args[k]; 2928 const char *name = NULL; 2929 2930 if (flags < ARRAY_SIZE(bswap_flag_name)) { 2931 name = bswap_flag_name[flags]; 2932 } 2933 if (name) { 2934 col += ne_fprintf(f, ",%s", name); 2935 } else { 2936 col += ne_fprintf(f, ",$0x%" TCG_PRIlx, flags); 2937 } 2938 i = k = 1; 2939 } 2940 break; 2941 #ifdef CONFIG_PLUGIN 2942 case INDEX_op_plugin_cb: 2943 { 2944 TCGArg from = op->args[k++]; 2945 const char *name = NULL; 2946 2947 if (from < ARRAY_SIZE(plugin_from_name)) { 2948 name = plugin_from_name[from]; 2949 } 2950 if (name) { 2951 col += ne_fprintf(f, "%s", name); 2952 } else { 2953 col += ne_fprintf(f, "$0x%" TCG_PRIlx, from); 2954 } 2955 i = 1; 2956 } 2957 break; 2958 #endif 2959 default: 2960 i = 0; 2961 break; 2962 } 2963 switch (c) { 2964 case INDEX_op_set_label: 2965 case INDEX_op_br: 2966 case INDEX_op_brcond_i32: 2967 case INDEX_op_brcond_i64: 2968 case INDEX_op_brcond2_i32: 2969 col += ne_fprintf(f, "%s$L%d", k ? "," : "", 2970 arg_label(op->args[k])->id); 2971 i++, k++; 2972 break; 2973 case INDEX_op_mb: 2974 { 2975 TCGBar membar = op->args[k]; 2976 const char *b_op, *m_op; 2977 2978 switch (membar & TCG_BAR_SC) { 2979 case 0: 2980 b_op = "none"; 2981 break; 2982 case TCG_BAR_LDAQ: 2983 b_op = "acq"; 2984 break; 2985 case TCG_BAR_STRL: 2986 b_op = "rel"; 2987 break; 2988 case TCG_BAR_SC: 2989 b_op = "seq"; 2990 break; 2991 default: 2992 g_assert_not_reached(); 2993 } 2994 2995 switch (membar & TCG_MO_ALL) { 2996 case 0: 2997 m_op = "none"; 2998 break; 2999 case TCG_MO_LD_LD: 3000 m_op = "rr"; 3001 break; 3002 case TCG_MO_LD_ST: 3003 m_op = "rw"; 3004 break; 3005 case TCG_MO_ST_LD: 3006 m_op = "wr"; 3007 break; 3008 case TCG_MO_ST_ST: 3009 m_op = "ww"; 3010 break; 3011 case TCG_MO_LD_LD | TCG_MO_LD_ST: 3012 m_op = "rr+rw"; 3013 break; 3014 case TCG_MO_LD_LD | TCG_MO_ST_LD: 3015 m_op = "rr+wr"; 3016 break; 3017 case TCG_MO_LD_LD | TCG_MO_ST_ST: 3018 m_op = "rr+ww"; 3019 break; 3020 case TCG_MO_LD_ST | TCG_MO_ST_LD: 3021 m_op = "rw+wr"; 3022 break; 3023 case TCG_MO_LD_ST | TCG_MO_ST_ST: 3024 m_op = "rw+ww"; 3025 break; 3026 case TCG_MO_ST_LD | TCG_MO_ST_ST: 3027 m_op = "wr+ww"; 3028 break; 3029 case TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_LD: 3030 m_op = "rr+rw+wr"; 3031 break; 3032 case TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST: 3033 m_op = "rr+rw+ww"; 3034 break; 3035 case TCG_MO_LD_LD | TCG_MO_ST_LD | TCG_MO_ST_ST: 3036 m_op = "rr+wr+ww"; 3037 break; 3038 case TCG_MO_LD_ST | TCG_MO_ST_LD | TCG_MO_ST_ST: 3039 m_op = "rw+wr+ww"; 3040 break; 3041 case TCG_MO_ALL: 3042 m_op = "all"; 3043 break; 3044 default: 3045 g_assert_not_reached(); 3046 } 3047 3048 col += ne_fprintf(f, "%s%s:%s", (k ? "," : ""), b_op, m_op); 3049 i++, k++; 3050 } 3051 break; 3052 default: 3053 break; 3054 } 3055 for (; i < nb_cargs; i++, k++) { 3056 col += ne_fprintf(f, "%s$0x%" TCG_PRIlx, k ? "," : "", 3057 op->args[k]); 3058 } 3059 } 3060 3061 if (have_prefs || op->life) { 3062 for (; col < 40; ++col) { 3063 putc(' ', f); 3064 } 3065 } 3066 3067 if (op->life) { 3068 unsigned life = op->life; 3069 3070 if (life & (SYNC_ARG * 3)) { 3071 ne_fprintf(f, " sync:"); 3072 for (i = 0; i < 2; ++i) { 3073 if (life & (SYNC_ARG << i)) { 3074 ne_fprintf(f, " %d", i); 3075 } 3076 } 3077 } 3078 life /= DEAD_ARG; 3079 if (life) { 3080 ne_fprintf(f, " dead:"); 3081 for (i = 0; life; ++i, life >>= 1) { 3082 if (life & 1) { 3083 ne_fprintf(f, " %d", i); 3084 } 3085 } 3086 } 3087 } 3088 3089 if (have_prefs) { 3090 for (i = 0; i < nb_oargs; ++i) { 3091 TCGRegSet set = output_pref(op, i); 3092 3093 if (i == 0) { 3094 ne_fprintf(f, " pref="); 3095 } else { 3096 ne_fprintf(f, ","); 3097 } 3098 if (set == 0) { 3099 ne_fprintf(f, "none"); 3100 } else if (set == MAKE_64BIT_MASK(0, TCG_TARGET_NB_REGS)) { 3101 ne_fprintf(f, "all"); 3102 #ifdef CONFIG_DEBUG_TCG 3103 } else if (tcg_regset_single(set)) { 3104 TCGReg reg = tcg_regset_first(set); 3105 ne_fprintf(f, "%s", tcg_target_reg_names[reg]); 3106 #endif 3107 } else if (TCG_TARGET_NB_REGS <= 32) { 3108 ne_fprintf(f, "0x%x", (uint32_t)set); 3109 } else { 3110 ne_fprintf(f, "0x%" PRIx64, (uint64_t)set); 3111 } 3112 } 3113 } 3114 3115 putc('\n', f); 3116 } 3117 } 3118 3119 /* we give more priority to constraints with less registers */ 3120 static int get_constraint_priority(const TCGArgConstraint *arg_ct, int k) 3121 { 3122 int n; 3123 3124 arg_ct += k; 3125 n = ctpop64(arg_ct->regs); 3126 3127 /* 3128 * Sort constraints of a single register first, which includes output 3129 * aliases (which must exactly match the input already allocated). 3130 */ 3131 if (n == 1 || arg_ct->oalias) { 3132 return INT_MAX; 3133 } 3134 3135 /* 3136 * Sort register pairs next, first then second immediately after. 3137 * Arbitrarily sort multiple pairs by the index of the first reg; 3138 * there shouldn't be many pairs. 3139 */ 3140 switch (arg_ct->pair) { 3141 case 1: 3142 case 3: 3143 return (k + 1) * 2; 3144 case 2: 3145 return (arg_ct->pair_index + 1) * 2 - 1; 3146 } 3147 3148 /* Finally, sort by decreasing register count. */ 3149 assert(n > 1); 3150 return -n; 3151 } 3152 3153 /* sort from highest priority to lowest */ 3154 static void sort_constraints(TCGArgConstraint *a, int start, int n) 3155 { 3156 int i, j; 3157 3158 for (i = 0; i < n; i++) { 3159 a[start + i].sort_index = start + i; 3160 } 3161 if (n <= 1) { 3162 return; 3163 } 3164 for (i = 0; i < n - 1; i++) { 3165 for (j = i + 1; j < n; j++) { 3166 int p1 = get_constraint_priority(a, a[start + i].sort_index); 3167 int p2 = get_constraint_priority(a, a[start + j].sort_index); 3168 if (p1 < p2) { 3169 int tmp = a[start + i].sort_index; 3170 a[start + i].sort_index = a[start + j].sort_index; 3171 a[start + j].sort_index = tmp; 3172 } 3173 } 3174 } 3175 } 3176 3177 static const TCGArgConstraint empty_cts[TCG_MAX_OP_ARGS]; 3178 static TCGArgConstraint all_cts[ARRAY_SIZE(constraint_sets)][TCG_MAX_OP_ARGS]; 3179 3180 static void process_constraint_sets(void) 3181 { 3182 for (size_t c = 0; c < ARRAY_SIZE(constraint_sets); ++c) { 3183 const TCGConstraintSet *tdefs = &constraint_sets[c]; 3184 TCGArgConstraint *args_ct = all_cts[c]; 3185 int nb_oargs = tdefs->nb_oargs; 3186 int nb_iargs = tdefs->nb_iargs; 3187 int nb_args = nb_oargs + nb_iargs; 3188 bool saw_alias_pair = false; 3189 3190 for (int i = 0; i < nb_args; i++) { 3191 const char *ct_str = tdefs->args_ct_str[i]; 3192 bool input_p = i >= nb_oargs; 3193 int o; 3194 3195 switch (*ct_str) { 3196 case '0' ... '9': 3197 o = *ct_str - '0'; 3198 tcg_debug_assert(input_p); 3199 tcg_debug_assert(o < nb_oargs); 3200 tcg_debug_assert(args_ct[o].regs != 0); 3201 tcg_debug_assert(!args_ct[o].oalias); 3202 args_ct[i] = args_ct[o]; 3203 /* The output sets oalias. */ 3204 args_ct[o].oalias = 1; 3205 args_ct[o].alias_index = i; 3206 /* The input sets ialias. */ 3207 args_ct[i].ialias = 1; 3208 args_ct[i].alias_index = o; 3209 if (args_ct[i].pair) { 3210 saw_alias_pair = true; 3211 } 3212 tcg_debug_assert(ct_str[1] == '\0'); 3213 continue; 3214 3215 case '&': 3216 tcg_debug_assert(!input_p); 3217 args_ct[i].newreg = true; 3218 ct_str++; 3219 break; 3220 3221 case 'p': /* plus */ 3222 /* Allocate to the register after the previous. */ 3223 tcg_debug_assert(i > (input_p ? nb_oargs : 0)); 3224 o = i - 1; 3225 tcg_debug_assert(!args_ct[o].pair); 3226 tcg_debug_assert(!args_ct[o].ct); 3227 args_ct[i] = (TCGArgConstraint){ 3228 .pair = 2, 3229 .pair_index = o, 3230 .regs = args_ct[o].regs << 1, 3231 .newreg = args_ct[o].newreg, 3232 }; 3233 args_ct[o].pair = 1; 3234 args_ct[o].pair_index = i; 3235 tcg_debug_assert(ct_str[1] == '\0'); 3236 continue; 3237 3238 case 'm': /* minus */ 3239 /* Allocate to the register before the previous. */ 3240 tcg_debug_assert(i > (input_p ? nb_oargs : 0)); 3241 o = i - 1; 3242 tcg_debug_assert(!args_ct[o].pair); 3243 tcg_debug_assert(!args_ct[o].ct); 3244 args_ct[i] = (TCGArgConstraint){ 3245 .pair = 1, 3246 .pair_index = o, 3247 .regs = args_ct[o].regs >> 1, 3248 .newreg = args_ct[o].newreg, 3249 }; 3250 args_ct[o].pair = 2; 3251 args_ct[o].pair_index = i; 3252 tcg_debug_assert(ct_str[1] == '\0'); 3253 continue; 3254 } 3255 3256 do { 3257 switch (*ct_str) { 3258 case 'i': 3259 args_ct[i].ct |= TCG_CT_CONST; 3260 break; 3261 #ifdef TCG_REG_ZERO 3262 case 'z': 3263 args_ct[i].ct |= TCG_CT_REG_ZERO; 3264 break; 3265 #endif 3266 3267 /* Include all of the target-specific constraints. */ 3268 3269 #undef CONST 3270 #define CONST(CASE, MASK) \ 3271 case CASE: args_ct[i].ct |= MASK; break; 3272 #define REGS(CASE, MASK) \ 3273 case CASE: args_ct[i].regs |= MASK; break; 3274 3275 #include "tcg-target-con-str.h" 3276 3277 #undef REGS 3278 #undef CONST 3279 default: 3280 case '0' ... '9': 3281 case '&': 3282 case 'p': 3283 case 'm': 3284 /* Typo in TCGConstraintSet constraint. */ 3285 g_assert_not_reached(); 3286 } 3287 } while (*++ct_str != '\0'); 3288 } 3289 3290 /* 3291 * Fix up output pairs that are aliased with inputs. 3292 * When we created the alias, we copied pair from the output. 3293 * There are three cases: 3294 * (1a) Pairs of inputs alias pairs of outputs. 3295 * (1b) One input aliases the first of a pair of outputs. 3296 * (2) One input aliases the second of a pair of outputs. 3297 * 3298 * Case 1a is handled by making sure that the pair_index'es are 3299 * properly updated so that they appear the same as a pair of inputs. 3300 * 3301 * Case 1b is handled by setting the pair_index of the input to 3302 * itself, simply so it doesn't point to an unrelated argument. 3303 * Since we don't encounter the "second" during the input allocation 3304 * phase, nothing happens with the second half of the input pair. 3305 * 3306 * Case 2 is handled by setting the second input to pair=3, the 3307 * first output to pair=3, and the pair_index'es to match. 3308 */ 3309 if (saw_alias_pair) { 3310 for (int i = nb_oargs; i < nb_args; i++) { 3311 int o, o2, i2; 3312 3313 /* 3314 * Since [0-9pm] must be alone in the constraint string, 3315 * the only way they can both be set is if the pair comes 3316 * from the output alias. 3317 */ 3318 if (!args_ct[i].ialias) { 3319 continue; 3320 } 3321 switch (args_ct[i].pair) { 3322 case 0: 3323 break; 3324 case 1: 3325 o = args_ct[i].alias_index; 3326 o2 = args_ct[o].pair_index; 3327 tcg_debug_assert(args_ct[o].pair == 1); 3328 tcg_debug_assert(args_ct[o2].pair == 2); 3329 if (args_ct[o2].oalias) { 3330 /* Case 1a */ 3331 i2 = args_ct[o2].alias_index; 3332 tcg_debug_assert(args_ct[i2].pair == 2); 3333 args_ct[i2].pair_index = i; 3334 args_ct[i].pair_index = i2; 3335 } else { 3336 /* Case 1b */ 3337 args_ct[i].pair_index = i; 3338 } 3339 break; 3340 case 2: 3341 o = args_ct[i].alias_index; 3342 o2 = args_ct[o].pair_index; 3343 tcg_debug_assert(args_ct[o].pair == 2); 3344 tcg_debug_assert(args_ct[o2].pair == 1); 3345 if (args_ct[o2].oalias) { 3346 /* Case 1a */ 3347 i2 = args_ct[o2].alias_index; 3348 tcg_debug_assert(args_ct[i2].pair == 1); 3349 args_ct[i2].pair_index = i; 3350 args_ct[i].pair_index = i2; 3351 } else { 3352 /* Case 2 */ 3353 args_ct[i].pair = 3; 3354 args_ct[o2].pair = 3; 3355 args_ct[i].pair_index = o2; 3356 args_ct[o2].pair_index = i; 3357 } 3358 break; 3359 default: 3360 g_assert_not_reached(); 3361 } 3362 } 3363 } 3364 3365 /* sort the constraints (XXX: this is just an heuristic) */ 3366 sort_constraints(args_ct, 0, nb_oargs); 3367 sort_constraints(args_ct, nb_oargs, nb_iargs); 3368 } 3369 } 3370 3371 static const TCGArgConstraint *opcode_args_ct(const TCGOp *op) 3372 { 3373 TCGOpcode opc = op->opc; 3374 TCGType type = TCGOP_TYPE(op); 3375 unsigned flags = TCGOP_FLAGS(op); 3376 const TCGOpDef *def = &tcg_op_defs[opc]; 3377 const TCGOutOp *outop = all_outop[opc]; 3378 TCGConstraintSetIndex con_set; 3379 3380 if (def->flags & TCG_OPF_NOT_PRESENT) { 3381 return empty_cts; 3382 } 3383 3384 if (outop) { 3385 con_set = outop->static_constraint; 3386 if (con_set == C_Dynamic) { 3387 con_set = outop->dynamic_constraint(type, flags); 3388 } 3389 } else { 3390 con_set = tcg_target_op_def(opc, type, flags); 3391 } 3392 tcg_debug_assert(con_set >= 0); 3393 tcg_debug_assert(con_set < ARRAY_SIZE(constraint_sets)); 3394 3395 /* The constraint arguments must match TCGOpcode arguments. */ 3396 tcg_debug_assert(constraint_sets[con_set].nb_oargs == def->nb_oargs); 3397 tcg_debug_assert(constraint_sets[con_set].nb_iargs == def->nb_iargs); 3398 3399 return all_cts[con_set]; 3400 } 3401 3402 static void remove_label_use(TCGOp *op, int idx) 3403 { 3404 TCGLabel *label = arg_label(op->args[idx]); 3405 TCGLabelUse *use; 3406 3407 QSIMPLEQ_FOREACH(use, &label->branches, next) { 3408 if (use->op == op) { 3409 QSIMPLEQ_REMOVE(&label->branches, use, TCGLabelUse, next); 3410 return; 3411 } 3412 } 3413 g_assert_not_reached(); 3414 } 3415 3416 void tcg_op_remove(TCGContext *s, TCGOp *op) 3417 { 3418 switch (op->opc) { 3419 case INDEX_op_br: 3420 remove_label_use(op, 0); 3421 break; 3422 case INDEX_op_brcond_i32: 3423 case INDEX_op_brcond_i64: 3424 remove_label_use(op, 3); 3425 break; 3426 case INDEX_op_brcond2_i32: 3427 remove_label_use(op, 5); 3428 break; 3429 default: 3430 break; 3431 } 3432 3433 QTAILQ_REMOVE(&s->ops, op, link); 3434 QTAILQ_INSERT_TAIL(&s->free_ops, op, link); 3435 s->nb_ops--; 3436 } 3437 3438 void tcg_remove_ops_after(TCGOp *op) 3439 { 3440 TCGContext *s = tcg_ctx; 3441 3442 while (true) { 3443 TCGOp *last = tcg_last_op(); 3444 if (last == op) { 3445 return; 3446 } 3447 tcg_op_remove(s, last); 3448 } 3449 } 3450 3451 static TCGOp *tcg_op_alloc(TCGOpcode opc, unsigned nargs) 3452 { 3453 TCGContext *s = tcg_ctx; 3454 TCGOp *op = NULL; 3455 3456 if (unlikely(!QTAILQ_EMPTY(&s->free_ops))) { 3457 QTAILQ_FOREACH(op, &s->free_ops, link) { 3458 if (nargs <= op->nargs) { 3459 QTAILQ_REMOVE(&s->free_ops, op, link); 3460 nargs = op->nargs; 3461 goto found; 3462 } 3463 } 3464 } 3465 3466 /* Most opcodes have 3 or 4 operands: reduce fragmentation. */ 3467 nargs = MAX(4, nargs); 3468 op = tcg_malloc(sizeof(TCGOp) + sizeof(TCGArg) * nargs); 3469 3470 found: 3471 memset(op, 0, offsetof(TCGOp, link)); 3472 op->opc = opc; 3473 op->nargs = nargs; 3474 3475 /* Check for bitfield overflow. */ 3476 tcg_debug_assert(op->nargs == nargs); 3477 3478 s->nb_ops++; 3479 return op; 3480 } 3481 3482 TCGOp *tcg_emit_op(TCGOpcode opc, unsigned nargs) 3483 { 3484 TCGOp *op = tcg_op_alloc(opc, nargs); 3485 3486 if (tcg_ctx->emit_before_op) { 3487 QTAILQ_INSERT_BEFORE(tcg_ctx->emit_before_op, op, link); 3488 } else { 3489 QTAILQ_INSERT_TAIL(&tcg_ctx->ops, op, link); 3490 } 3491 return op; 3492 } 3493 3494 TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *old_op, 3495 TCGOpcode opc, TCGType type, unsigned nargs) 3496 { 3497 TCGOp *new_op = tcg_op_alloc(opc, nargs); 3498 3499 TCGOP_TYPE(new_op) = type; 3500 QTAILQ_INSERT_BEFORE(old_op, new_op, link); 3501 return new_op; 3502 } 3503 3504 TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *old_op, 3505 TCGOpcode opc, TCGType type, unsigned nargs) 3506 { 3507 TCGOp *new_op = tcg_op_alloc(opc, nargs); 3508 3509 TCGOP_TYPE(new_op) = type; 3510 QTAILQ_INSERT_AFTER(&s->ops, old_op, new_op, link); 3511 return new_op; 3512 } 3513 3514 static void move_label_uses(TCGLabel *to, TCGLabel *from) 3515 { 3516 TCGLabelUse *u; 3517 3518 QSIMPLEQ_FOREACH(u, &from->branches, next) { 3519 TCGOp *op = u->op; 3520 switch (op->opc) { 3521 case INDEX_op_br: 3522 op->args[0] = label_arg(to); 3523 break; 3524 case INDEX_op_brcond_i32: 3525 case INDEX_op_brcond_i64: 3526 op->args[3] = label_arg(to); 3527 break; 3528 case INDEX_op_brcond2_i32: 3529 op->args[5] = label_arg(to); 3530 break; 3531 default: 3532 g_assert_not_reached(); 3533 } 3534 } 3535 3536 QSIMPLEQ_CONCAT(&to->branches, &from->branches); 3537 } 3538 3539 /* Reachable analysis : remove unreachable code. */ 3540 static void __attribute__((noinline)) 3541 reachable_code_pass(TCGContext *s) 3542 { 3543 TCGOp *op, *op_next, *op_prev; 3544 bool dead = false; 3545 3546 QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) { 3547 bool remove = dead; 3548 TCGLabel *label; 3549 3550 switch (op->opc) { 3551 case INDEX_op_set_label: 3552 label = arg_label(op->args[0]); 3553 3554 /* 3555 * Note that the first op in the TB is always a load, 3556 * so there is always something before a label. 3557 */ 3558 op_prev = QTAILQ_PREV(op, link); 3559 3560 /* 3561 * If we find two sequential labels, move all branches to 3562 * reference the second label and remove the first label. 3563 * Do this before branch to next optimization, so that the 3564 * middle label is out of the way. 3565 */ 3566 if (op_prev->opc == INDEX_op_set_label) { 3567 move_label_uses(label, arg_label(op_prev->args[0])); 3568 tcg_op_remove(s, op_prev); 3569 op_prev = QTAILQ_PREV(op, link); 3570 } 3571 3572 /* 3573 * Optimization can fold conditional branches to unconditional. 3574 * If we find a label which is preceded by an unconditional 3575 * branch to next, remove the branch. We couldn't do this when 3576 * processing the branch because any dead code between the branch 3577 * and label had not yet been removed. 3578 */ 3579 if (op_prev->opc == INDEX_op_br && 3580 label == arg_label(op_prev->args[0])) { 3581 tcg_op_remove(s, op_prev); 3582 /* Fall through means insns become live again. */ 3583 dead = false; 3584 } 3585 3586 if (QSIMPLEQ_EMPTY(&label->branches)) { 3587 /* 3588 * While there is an occasional backward branch, virtually 3589 * all branches generated by the translators are forward. 3590 * Which means that generally we will have already removed 3591 * all references to the label that will be, and there is 3592 * little to be gained by iterating. 3593 */ 3594 remove = true; 3595 } else { 3596 /* Once we see a label, insns become live again. */ 3597 dead = false; 3598 remove = false; 3599 } 3600 break; 3601 3602 case INDEX_op_br: 3603 case INDEX_op_exit_tb: 3604 case INDEX_op_goto_ptr: 3605 /* Unconditional branches; everything following is dead. */ 3606 dead = true; 3607 break; 3608 3609 case INDEX_op_call: 3610 /* Notice noreturn helper calls, raising exceptions. */ 3611 if (tcg_call_flags(op) & TCG_CALL_NO_RETURN) { 3612 dead = true; 3613 } 3614 break; 3615 3616 case INDEX_op_insn_start: 3617 /* Never remove -- we need to keep these for unwind. */ 3618 remove = false; 3619 break; 3620 3621 default: 3622 break; 3623 } 3624 3625 if (remove) { 3626 tcg_op_remove(s, op); 3627 } 3628 } 3629 } 3630 3631 #define TS_DEAD 1 3632 #define TS_MEM 2 3633 3634 #define IS_DEAD_ARG(n) (arg_life & (DEAD_ARG << (n))) 3635 #define NEED_SYNC_ARG(n) (arg_life & (SYNC_ARG << (n))) 3636 3637 /* For liveness_pass_1, the register preferences for a given temp. */ 3638 static inline TCGRegSet *la_temp_pref(TCGTemp *ts) 3639 { 3640 return ts->state_ptr; 3641 } 3642 3643 /* For liveness_pass_1, reset the preferences for a given temp to the 3644 * maximal regset for its type. 3645 */ 3646 static inline void la_reset_pref(TCGTemp *ts) 3647 { 3648 *la_temp_pref(ts) 3649 = (ts->state == TS_DEAD ? 0 : tcg_target_available_regs[ts->type]); 3650 } 3651 3652 /* liveness analysis: end of function: all temps are dead, and globals 3653 should be in memory. */ 3654 static void la_func_end(TCGContext *s, int ng, int nt) 3655 { 3656 int i; 3657 3658 for (i = 0; i < ng; ++i) { 3659 s->temps[i].state = TS_DEAD | TS_MEM; 3660 la_reset_pref(&s->temps[i]); 3661 } 3662 for (i = ng; i < nt; ++i) { 3663 s->temps[i].state = TS_DEAD; 3664 la_reset_pref(&s->temps[i]); 3665 } 3666 } 3667 3668 /* liveness analysis: end of basic block: all temps are dead, globals 3669 and local temps should be in memory. */ 3670 static void la_bb_end(TCGContext *s, int ng, int nt) 3671 { 3672 int i; 3673 3674 for (i = 0; i < nt; ++i) { 3675 TCGTemp *ts = &s->temps[i]; 3676 int state; 3677 3678 switch (ts->kind) { 3679 case TEMP_FIXED: 3680 case TEMP_GLOBAL: 3681 case TEMP_TB: 3682 state = TS_DEAD | TS_MEM; 3683 break; 3684 case TEMP_EBB: 3685 case TEMP_CONST: 3686 state = TS_DEAD; 3687 break; 3688 default: 3689 g_assert_not_reached(); 3690 } 3691 ts->state = state; 3692 la_reset_pref(ts); 3693 } 3694 } 3695 3696 /* liveness analysis: sync globals back to memory. */ 3697 static void la_global_sync(TCGContext *s, int ng) 3698 { 3699 int i; 3700 3701 for (i = 0; i < ng; ++i) { 3702 int state = s->temps[i].state; 3703 s->temps[i].state = state | TS_MEM; 3704 if (state == TS_DEAD) { 3705 /* If the global was previously dead, reset prefs. */ 3706 la_reset_pref(&s->temps[i]); 3707 } 3708 } 3709 } 3710 3711 /* 3712 * liveness analysis: conditional branch: all temps are dead unless 3713 * explicitly live-across-conditional-branch, globals and local temps 3714 * should be synced. 3715 */ 3716 static void la_bb_sync(TCGContext *s, int ng, int nt) 3717 { 3718 la_global_sync(s, ng); 3719 3720 for (int i = ng; i < nt; ++i) { 3721 TCGTemp *ts = &s->temps[i]; 3722 int state; 3723 3724 switch (ts->kind) { 3725 case TEMP_TB: 3726 state = ts->state; 3727 ts->state = state | TS_MEM; 3728 if (state != TS_DEAD) { 3729 continue; 3730 } 3731 break; 3732 case TEMP_EBB: 3733 case TEMP_CONST: 3734 continue; 3735 default: 3736 g_assert_not_reached(); 3737 } 3738 la_reset_pref(&s->temps[i]); 3739 } 3740 } 3741 3742 /* liveness analysis: sync globals back to memory and kill. */ 3743 static void la_global_kill(TCGContext *s, int ng) 3744 { 3745 int i; 3746 3747 for (i = 0; i < ng; i++) { 3748 s->temps[i].state = TS_DEAD | TS_MEM; 3749 la_reset_pref(&s->temps[i]); 3750 } 3751 } 3752 3753 /* liveness analysis: note live globals crossing calls. */ 3754 static void la_cross_call(TCGContext *s, int nt) 3755 { 3756 TCGRegSet mask = ~tcg_target_call_clobber_regs; 3757 int i; 3758 3759 for (i = 0; i < nt; i++) { 3760 TCGTemp *ts = &s->temps[i]; 3761 if (!(ts->state & TS_DEAD)) { 3762 TCGRegSet *pset = la_temp_pref(ts); 3763 TCGRegSet set = *pset; 3764 3765 set &= mask; 3766 /* If the combination is not possible, restart. */ 3767 if (set == 0) { 3768 set = tcg_target_available_regs[ts->type] & mask; 3769 } 3770 *pset = set; 3771 } 3772 } 3773 } 3774 3775 /* 3776 * Liveness analysis: Verify the lifetime of TEMP_TB, and reduce 3777 * to TEMP_EBB, if possible. 3778 */ 3779 static void __attribute__((noinline)) 3780 liveness_pass_0(TCGContext *s) 3781 { 3782 void * const multiple_ebb = (void *)(uintptr_t)-1; 3783 int nb_temps = s->nb_temps; 3784 TCGOp *op, *ebb; 3785 3786 for (int i = s->nb_globals; i < nb_temps; ++i) { 3787 s->temps[i].state_ptr = NULL; 3788 } 3789 3790 /* 3791 * Represent each EBB by the op at which it begins. In the case of 3792 * the first EBB, this is the first op, otherwise it is a label. 3793 * Collect the uses of each TEMP_TB: NULL for unused, EBB for use 3794 * within a single EBB, else MULTIPLE_EBB. 3795 */ 3796 ebb = QTAILQ_FIRST(&s->ops); 3797 QTAILQ_FOREACH(op, &s->ops, link) { 3798 const TCGOpDef *def; 3799 int nb_oargs, nb_iargs; 3800 3801 switch (op->opc) { 3802 case INDEX_op_set_label: 3803 ebb = op; 3804 continue; 3805 case INDEX_op_discard: 3806 continue; 3807 case INDEX_op_call: 3808 nb_oargs = TCGOP_CALLO(op); 3809 nb_iargs = TCGOP_CALLI(op); 3810 break; 3811 default: 3812 def = &tcg_op_defs[op->opc]; 3813 nb_oargs = def->nb_oargs; 3814 nb_iargs = def->nb_iargs; 3815 break; 3816 } 3817 3818 for (int i = 0; i < nb_oargs + nb_iargs; ++i) { 3819 TCGTemp *ts = arg_temp(op->args[i]); 3820 3821 if (ts->kind != TEMP_TB) { 3822 continue; 3823 } 3824 if (ts->state_ptr == NULL) { 3825 ts->state_ptr = ebb; 3826 } else if (ts->state_ptr != ebb) { 3827 ts->state_ptr = multiple_ebb; 3828 } 3829 } 3830 } 3831 3832 /* 3833 * For TEMP_TB that turned out not to be used beyond one EBB, 3834 * reduce the liveness to TEMP_EBB. 3835 */ 3836 for (int i = s->nb_globals; i < nb_temps; ++i) { 3837 TCGTemp *ts = &s->temps[i]; 3838 if (ts->kind == TEMP_TB && ts->state_ptr != multiple_ebb) { 3839 ts->kind = TEMP_EBB; 3840 } 3841 } 3842 } 3843 3844 /* Liveness analysis : update the opc_arg_life array to tell if a 3845 given input arguments is dead. Instructions updating dead 3846 temporaries are removed. */ 3847 static void __attribute__((noinline)) 3848 liveness_pass_1(TCGContext *s) 3849 { 3850 int nb_globals = s->nb_globals; 3851 int nb_temps = s->nb_temps; 3852 TCGOp *op, *op_prev; 3853 TCGRegSet *prefs; 3854 int i; 3855 3856 prefs = tcg_malloc(sizeof(TCGRegSet) * nb_temps); 3857 for (i = 0; i < nb_temps; ++i) { 3858 s->temps[i].state_ptr = prefs + i; 3859 } 3860 3861 /* ??? Should be redundant with the exit_tb that ends the TB. */ 3862 la_func_end(s, nb_globals, nb_temps); 3863 3864 QTAILQ_FOREACH_REVERSE_SAFE(op, &s->ops, link, op_prev) { 3865 int nb_iargs, nb_oargs; 3866 TCGOpcode opc_new, opc_new2; 3867 TCGLifeData arg_life = 0; 3868 TCGTemp *ts; 3869 TCGOpcode opc = op->opc; 3870 const TCGOpDef *def = &tcg_op_defs[opc]; 3871 const TCGArgConstraint *args_ct; 3872 3873 switch (opc) { 3874 case INDEX_op_call: 3875 { 3876 const TCGHelperInfo *info = tcg_call_info(op); 3877 int call_flags = tcg_call_flags(op); 3878 3879 nb_oargs = TCGOP_CALLO(op); 3880 nb_iargs = TCGOP_CALLI(op); 3881 3882 /* pure functions can be removed if their result is unused */ 3883 if (call_flags & TCG_CALL_NO_SIDE_EFFECTS) { 3884 for (i = 0; i < nb_oargs; i++) { 3885 ts = arg_temp(op->args[i]); 3886 if (ts->state != TS_DEAD) { 3887 goto do_not_remove_call; 3888 } 3889 } 3890 goto do_remove; 3891 } 3892 do_not_remove_call: 3893 3894 /* Output args are dead. */ 3895 for (i = 0; i < nb_oargs; i++) { 3896 ts = arg_temp(op->args[i]); 3897 if (ts->state & TS_DEAD) { 3898 arg_life |= DEAD_ARG << i; 3899 } 3900 if (ts->state & TS_MEM) { 3901 arg_life |= SYNC_ARG << i; 3902 } 3903 ts->state = TS_DEAD; 3904 la_reset_pref(ts); 3905 } 3906 3907 /* Not used -- it will be tcg_target_call_oarg_reg(). */ 3908 memset(op->output_pref, 0, sizeof(op->output_pref)); 3909 3910 if (!(call_flags & (TCG_CALL_NO_WRITE_GLOBALS | 3911 TCG_CALL_NO_READ_GLOBALS))) { 3912 la_global_kill(s, nb_globals); 3913 } else if (!(call_flags & TCG_CALL_NO_READ_GLOBALS)) { 3914 la_global_sync(s, nb_globals); 3915 } 3916 3917 /* Record arguments that die in this helper. */ 3918 for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) { 3919 ts = arg_temp(op->args[i]); 3920 if (ts->state & TS_DEAD) { 3921 arg_life |= DEAD_ARG << i; 3922 } 3923 } 3924 3925 /* For all live registers, remove call-clobbered prefs. */ 3926 la_cross_call(s, nb_temps); 3927 3928 /* 3929 * Input arguments are live for preceding opcodes. 3930 * 3931 * For those arguments that die, and will be allocated in 3932 * registers, clear the register set for that arg, to be 3933 * filled in below. For args that will be on the stack, 3934 * reset to any available reg. Process arguments in reverse 3935 * order so that if a temp is used more than once, the stack 3936 * reset to max happens before the register reset to 0. 3937 */ 3938 for (i = nb_iargs - 1; i >= 0; i--) { 3939 const TCGCallArgumentLoc *loc = &info->in[i]; 3940 ts = arg_temp(op->args[nb_oargs + i]); 3941 3942 if (ts->state & TS_DEAD) { 3943 switch (loc->kind) { 3944 case TCG_CALL_ARG_NORMAL: 3945 case TCG_CALL_ARG_EXTEND_U: 3946 case TCG_CALL_ARG_EXTEND_S: 3947 if (arg_slot_reg_p(loc->arg_slot)) { 3948 *la_temp_pref(ts) = 0; 3949 break; 3950 } 3951 /* fall through */ 3952 default: 3953 *la_temp_pref(ts) = 3954 tcg_target_available_regs[ts->type]; 3955 break; 3956 } 3957 ts->state &= ~TS_DEAD; 3958 } 3959 } 3960 3961 /* 3962 * For each input argument, add its input register to prefs. 3963 * If a temp is used once, this produces a single set bit; 3964 * if a temp is used multiple times, this produces a set. 3965 */ 3966 for (i = 0; i < nb_iargs; i++) { 3967 const TCGCallArgumentLoc *loc = &info->in[i]; 3968 ts = arg_temp(op->args[nb_oargs + i]); 3969 3970 switch (loc->kind) { 3971 case TCG_CALL_ARG_NORMAL: 3972 case TCG_CALL_ARG_EXTEND_U: 3973 case TCG_CALL_ARG_EXTEND_S: 3974 if (arg_slot_reg_p(loc->arg_slot)) { 3975 tcg_regset_set_reg(*la_temp_pref(ts), 3976 tcg_target_call_iarg_regs[loc->arg_slot]); 3977 } 3978 break; 3979 default: 3980 break; 3981 } 3982 } 3983 } 3984 break; 3985 case INDEX_op_insn_start: 3986 break; 3987 case INDEX_op_discard: 3988 /* mark the temporary as dead */ 3989 ts = arg_temp(op->args[0]); 3990 ts->state = TS_DEAD; 3991 la_reset_pref(ts); 3992 break; 3993 3994 case INDEX_op_add2_i32: 3995 case INDEX_op_add2_i64: 3996 opc_new = INDEX_op_add; 3997 goto do_addsub2; 3998 case INDEX_op_sub2_i32: 3999 case INDEX_op_sub2_i64: 4000 opc_new = INDEX_op_sub; 4001 do_addsub2: 4002 nb_iargs = 4; 4003 nb_oargs = 2; 4004 /* Test if the high part of the operation is dead, but not 4005 the low part. The result can be optimized to a simple 4006 add or sub. This happens often for x86_64 guest when the 4007 cpu mode is set to 32 bit. */ 4008 if (arg_temp(op->args[1])->state == TS_DEAD) { 4009 if (arg_temp(op->args[0])->state == TS_DEAD) { 4010 goto do_remove; 4011 } 4012 /* Replace the opcode and adjust the args in place, 4013 leaving 3 unused args at the end. */ 4014 op->opc = opc = opc_new; 4015 op->args[1] = op->args[2]; 4016 op->args[2] = op->args[4]; 4017 /* Fall through and mark the single-word operation live. */ 4018 nb_iargs = 2; 4019 nb_oargs = 1; 4020 } 4021 goto do_not_remove; 4022 4023 case INDEX_op_muls2_i32: 4024 case INDEX_op_muls2_i64: 4025 opc_new = INDEX_op_mul; 4026 opc_new2 = INDEX_op_mulsh; 4027 goto do_mul2; 4028 case INDEX_op_mulu2_i32: 4029 case INDEX_op_mulu2_i64: 4030 opc_new = INDEX_op_mul; 4031 opc_new2 = INDEX_op_muluh; 4032 do_mul2: 4033 nb_iargs = 2; 4034 nb_oargs = 2; 4035 if (arg_temp(op->args[1])->state == TS_DEAD) { 4036 if (arg_temp(op->args[0])->state == TS_DEAD) { 4037 /* Both parts of the operation are dead. */ 4038 goto do_remove; 4039 } 4040 /* The high part of the operation is dead; generate the low. */ 4041 op->opc = opc = opc_new; 4042 op->args[1] = op->args[2]; 4043 op->args[2] = op->args[3]; 4044 } else if (arg_temp(op->args[0])->state == TS_DEAD && 4045 tcg_op_supported(opc_new2, TCGOP_TYPE(op), 0)) { 4046 /* The low part of the operation is dead; generate the high. */ 4047 op->opc = opc = opc_new2; 4048 op->args[0] = op->args[1]; 4049 op->args[1] = op->args[2]; 4050 op->args[2] = op->args[3]; 4051 } else { 4052 goto do_not_remove; 4053 } 4054 /* Mark the single-word operation live. */ 4055 nb_oargs = 1; 4056 goto do_not_remove; 4057 4058 default: 4059 /* XXX: optimize by hardcoding common cases (e.g. triadic ops) */ 4060 nb_iargs = def->nb_iargs; 4061 nb_oargs = def->nb_oargs; 4062 4063 /* Test if the operation can be removed because all 4064 its outputs are dead. We assume that nb_oargs == 0 4065 implies side effects */ 4066 if (!(def->flags & TCG_OPF_SIDE_EFFECTS) && nb_oargs != 0) { 4067 for (i = 0; i < nb_oargs; i++) { 4068 if (arg_temp(op->args[i])->state != TS_DEAD) { 4069 goto do_not_remove; 4070 } 4071 } 4072 goto do_remove; 4073 } 4074 goto do_not_remove; 4075 4076 do_remove: 4077 tcg_op_remove(s, op); 4078 break; 4079 4080 do_not_remove: 4081 for (i = 0; i < nb_oargs; i++) { 4082 ts = arg_temp(op->args[i]); 4083 4084 /* Remember the preference of the uses that followed. */ 4085 if (i < ARRAY_SIZE(op->output_pref)) { 4086 op->output_pref[i] = *la_temp_pref(ts); 4087 } 4088 4089 /* Output args are dead. */ 4090 if (ts->state & TS_DEAD) { 4091 arg_life |= DEAD_ARG << i; 4092 } 4093 if (ts->state & TS_MEM) { 4094 arg_life |= SYNC_ARG << i; 4095 } 4096 ts->state = TS_DEAD; 4097 la_reset_pref(ts); 4098 } 4099 4100 /* If end of basic block, update. */ 4101 if (def->flags & TCG_OPF_BB_EXIT) { 4102 la_func_end(s, nb_globals, nb_temps); 4103 } else if (def->flags & TCG_OPF_COND_BRANCH) { 4104 la_bb_sync(s, nb_globals, nb_temps); 4105 } else if (def->flags & TCG_OPF_BB_END) { 4106 la_bb_end(s, nb_globals, nb_temps); 4107 } else if (def->flags & TCG_OPF_SIDE_EFFECTS) { 4108 la_global_sync(s, nb_globals); 4109 if (def->flags & TCG_OPF_CALL_CLOBBER) { 4110 la_cross_call(s, nb_temps); 4111 } 4112 } 4113 4114 /* Record arguments that die in this opcode. */ 4115 for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) { 4116 ts = arg_temp(op->args[i]); 4117 if (ts->state & TS_DEAD) { 4118 arg_life |= DEAD_ARG << i; 4119 } 4120 } 4121 4122 /* Input arguments are live for preceding opcodes. */ 4123 for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) { 4124 ts = arg_temp(op->args[i]); 4125 if (ts->state & TS_DEAD) { 4126 /* For operands that were dead, initially allow 4127 all regs for the type. */ 4128 *la_temp_pref(ts) = tcg_target_available_regs[ts->type]; 4129 ts->state &= ~TS_DEAD; 4130 } 4131 } 4132 4133 /* Incorporate constraints for this operand. */ 4134 switch (opc) { 4135 case INDEX_op_mov: 4136 /* Note that these are TCG_OPF_NOT_PRESENT and do not 4137 have proper constraints. That said, special case 4138 moves to propagate preferences backward. */ 4139 if (IS_DEAD_ARG(1)) { 4140 *la_temp_pref(arg_temp(op->args[0])) 4141 = *la_temp_pref(arg_temp(op->args[1])); 4142 } 4143 break; 4144 4145 default: 4146 args_ct = opcode_args_ct(op); 4147 for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) { 4148 const TCGArgConstraint *ct = &args_ct[i]; 4149 TCGRegSet set, *pset; 4150 4151 ts = arg_temp(op->args[i]); 4152 pset = la_temp_pref(ts); 4153 set = *pset; 4154 4155 set &= ct->regs; 4156 if (ct->ialias) { 4157 set &= output_pref(op, ct->alias_index); 4158 } 4159 /* If the combination is not possible, restart. */ 4160 if (set == 0) { 4161 set = ct->regs; 4162 } 4163 *pset = set; 4164 } 4165 break; 4166 } 4167 break; 4168 } 4169 op->life = arg_life; 4170 } 4171 } 4172 4173 /* Liveness analysis: Convert indirect regs to direct temporaries. */ 4174 static bool __attribute__((noinline)) 4175 liveness_pass_2(TCGContext *s) 4176 { 4177 int nb_globals = s->nb_globals; 4178 int nb_temps, i; 4179 bool changes = false; 4180 TCGOp *op, *op_next; 4181 4182 /* Create a temporary for each indirect global. */ 4183 for (i = 0; i < nb_globals; ++i) { 4184 TCGTemp *its = &s->temps[i]; 4185 if (its->indirect_reg) { 4186 TCGTemp *dts = tcg_temp_alloc(s); 4187 dts->type = its->type; 4188 dts->base_type = its->base_type; 4189 dts->temp_subindex = its->temp_subindex; 4190 dts->kind = TEMP_EBB; 4191 its->state_ptr = dts; 4192 } else { 4193 its->state_ptr = NULL; 4194 } 4195 /* All globals begin dead. */ 4196 its->state = TS_DEAD; 4197 } 4198 for (nb_temps = s->nb_temps; i < nb_temps; ++i) { 4199 TCGTemp *its = &s->temps[i]; 4200 its->state_ptr = NULL; 4201 its->state = TS_DEAD; 4202 } 4203 4204 QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) { 4205 TCGOpcode opc = op->opc; 4206 const TCGOpDef *def = &tcg_op_defs[opc]; 4207 TCGLifeData arg_life = op->life; 4208 int nb_iargs, nb_oargs, call_flags; 4209 TCGTemp *arg_ts, *dir_ts; 4210 4211 if (opc == INDEX_op_call) { 4212 nb_oargs = TCGOP_CALLO(op); 4213 nb_iargs = TCGOP_CALLI(op); 4214 call_flags = tcg_call_flags(op); 4215 } else { 4216 nb_iargs = def->nb_iargs; 4217 nb_oargs = def->nb_oargs; 4218 4219 /* Set flags similar to how calls require. */ 4220 if (def->flags & TCG_OPF_COND_BRANCH) { 4221 /* Like reading globals: sync_globals */ 4222 call_flags = TCG_CALL_NO_WRITE_GLOBALS; 4223 } else if (def->flags & TCG_OPF_BB_END) { 4224 /* Like writing globals: save_globals */ 4225 call_flags = 0; 4226 } else if (def->flags & TCG_OPF_SIDE_EFFECTS) { 4227 /* Like reading globals: sync_globals */ 4228 call_flags = TCG_CALL_NO_WRITE_GLOBALS; 4229 } else { 4230 /* No effect on globals. */ 4231 call_flags = (TCG_CALL_NO_READ_GLOBALS | 4232 TCG_CALL_NO_WRITE_GLOBALS); 4233 } 4234 } 4235 4236 /* Make sure that input arguments are available. */ 4237 for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) { 4238 arg_ts = arg_temp(op->args[i]); 4239 dir_ts = arg_ts->state_ptr; 4240 if (dir_ts && arg_ts->state == TS_DEAD) { 4241 TCGOpcode lopc = (arg_ts->type == TCG_TYPE_I32 4242 ? INDEX_op_ld_i32 4243 : INDEX_op_ld_i64); 4244 TCGOp *lop = tcg_op_insert_before(s, op, lopc, 4245 arg_ts->type, 3); 4246 4247 lop->args[0] = temp_arg(dir_ts); 4248 lop->args[1] = temp_arg(arg_ts->mem_base); 4249 lop->args[2] = arg_ts->mem_offset; 4250 4251 /* Loaded, but synced with memory. */ 4252 arg_ts->state = TS_MEM; 4253 } 4254 } 4255 4256 /* Perform input replacement, and mark inputs that became dead. 4257 No action is required except keeping temp_state up to date 4258 so that we reload when needed. */ 4259 for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) { 4260 arg_ts = arg_temp(op->args[i]); 4261 dir_ts = arg_ts->state_ptr; 4262 if (dir_ts) { 4263 op->args[i] = temp_arg(dir_ts); 4264 changes = true; 4265 if (IS_DEAD_ARG(i)) { 4266 arg_ts->state = TS_DEAD; 4267 } 4268 } 4269 } 4270 4271 /* Liveness analysis should ensure that the following are 4272 all correct, for call sites and basic block end points. */ 4273 if (call_flags & TCG_CALL_NO_READ_GLOBALS) { 4274 /* Nothing to do */ 4275 } else if (call_flags & TCG_CALL_NO_WRITE_GLOBALS) { 4276 for (i = 0; i < nb_globals; ++i) { 4277 /* Liveness should see that globals are synced back, 4278 that is, either TS_DEAD or TS_MEM. */ 4279 arg_ts = &s->temps[i]; 4280 tcg_debug_assert(arg_ts->state_ptr == 0 4281 || arg_ts->state != 0); 4282 } 4283 } else { 4284 for (i = 0; i < nb_globals; ++i) { 4285 /* Liveness should see that globals are saved back, 4286 that is, TS_DEAD, waiting to be reloaded. */ 4287 arg_ts = &s->temps[i]; 4288 tcg_debug_assert(arg_ts->state_ptr == 0 4289 || arg_ts->state == TS_DEAD); 4290 } 4291 } 4292 4293 /* Outputs become available. */ 4294 if (opc == INDEX_op_mov) { 4295 arg_ts = arg_temp(op->args[0]); 4296 dir_ts = arg_ts->state_ptr; 4297 if (dir_ts) { 4298 op->args[0] = temp_arg(dir_ts); 4299 changes = true; 4300 4301 /* The output is now live and modified. */ 4302 arg_ts->state = 0; 4303 4304 if (NEED_SYNC_ARG(0)) { 4305 TCGOpcode sopc = (arg_ts->type == TCG_TYPE_I32 4306 ? INDEX_op_st_i32 4307 : INDEX_op_st_i64); 4308 TCGOp *sop = tcg_op_insert_after(s, op, sopc, 4309 arg_ts->type, 3); 4310 TCGTemp *out_ts = dir_ts; 4311 4312 if (IS_DEAD_ARG(0)) { 4313 out_ts = arg_temp(op->args[1]); 4314 arg_ts->state = TS_DEAD; 4315 tcg_op_remove(s, op); 4316 } else { 4317 arg_ts->state = TS_MEM; 4318 } 4319 4320 sop->args[0] = temp_arg(out_ts); 4321 sop->args[1] = temp_arg(arg_ts->mem_base); 4322 sop->args[2] = arg_ts->mem_offset; 4323 } else { 4324 tcg_debug_assert(!IS_DEAD_ARG(0)); 4325 } 4326 } 4327 } else { 4328 for (i = 0; i < nb_oargs; i++) { 4329 arg_ts = arg_temp(op->args[i]); 4330 dir_ts = arg_ts->state_ptr; 4331 if (!dir_ts) { 4332 continue; 4333 } 4334 op->args[i] = temp_arg(dir_ts); 4335 changes = true; 4336 4337 /* The output is now live and modified. */ 4338 arg_ts->state = 0; 4339 4340 /* Sync outputs upon their last write. */ 4341 if (NEED_SYNC_ARG(i)) { 4342 TCGOpcode sopc = (arg_ts->type == TCG_TYPE_I32 4343 ? INDEX_op_st_i32 4344 : INDEX_op_st_i64); 4345 TCGOp *sop = tcg_op_insert_after(s, op, sopc, 4346 arg_ts->type, 3); 4347 4348 sop->args[0] = temp_arg(dir_ts); 4349 sop->args[1] = temp_arg(arg_ts->mem_base); 4350 sop->args[2] = arg_ts->mem_offset; 4351 4352 arg_ts->state = TS_MEM; 4353 } 4354 /* Drop outputs that are dead. */ 4355 if (IS_DEAD_ARG(i)) { 4356 arg_ts->state = TS_DEAD; 4357 } 4358 } 4359 } 4360 } 4361 4362 return changes; 4363 } 4364 4365 static void temp_allocate_frame(TCGContext *s, TCGTemp *ts) 4366 { 4367 intptr_t off; 4368 int size, align; 4369 4370 /* When allocating an object, look at the full type. */ 4371 size = tcg_type_size(ts->base_type); 4372 switch (ts->base_type) { 4373 case TCG_TYPE_I32: 4374 align = 4; 4375 break; 4376 case TCG_TYPE_I64: 4377 case TCG_TYPE_V64: 4378 align = 8; 4379 break; 4380 case TCG_TYPE_I128: 4381 case TCG_TYPE_V128: 4382 case TCG_TYPE_V256: 4383 /* 4384 * Note that we do not require aligned storage for V256, 4385 * and that we provide alignment for I128 to match V128, 4386 * even if that's above what the host ABI requires. 4387 */ 4388 align = 16; 4389 break; 4390 default: 4391 g_assert_not_reached(); 4392 } 4393 4394 /* 4395 * Assume the stack is sufficiently aligned. 4396 * This affects e.g. ARM NEON, where we have 8 byte stack alignment 4397 * and do not require 16 byte vector alignment. This seems slightly 4398 * easier than fully parameterizing the above switch statement. 4399 */ 4400 align = MIN(TCG_TARGET_STACK_ALIGN, align); 4401 off = ROUND_UP(s->current_frame_offset, align); 4402 4403 /* If we've exhausted the stack frame, restart with a smaller TB. */ 4404 if (off + size > s->frame_end) { 4405 tcg_raise_tb_overflow(s); 4406 } 4407 s->current_frame_offset = off + size; 4408 #if defined(__sparc__) 4409 off += TCG_TARGET_STACK_BIAS; 4410 #endif 4411 4412 /* If the object was subdivided, assign memory to all the parts. */ 4413 if (ts->base_type != ts->type) { 4414 int part_size = tcg_type_size(ts->type); 4415 int part_count = size / part_size; 4416 4417 /* 4418 * Each part is allocated sequentially in tcg_temp_new_internal. 4419 * Jump back to the first part by subtracting the current index. 4420 */ 4421 ts -= ts->temp_subindex; 4422 for (int i = 0; i < part_count; ++i) { 4423 ts[i].mem_offset = off + i * part_size; 4424 ts[i].mem_base = s->frame_temp; 4425 ts[i].mem_allocated = 1; 4426 } 4427 } else { 4428 ts->mem_offset = off; 4429 ts->mem_base = s->frame_temp; 4430 ts->mem_allocated = 1; 4431 } 4432 } 4433 4434 /* Assign @reg to @ts, and update reg_to_temp[]. */ 4435 static void set_temp_val_reg(TCGContext *s, TCGTemp *ts, TCGReg reg) 4436 { 4437 if (ts->val_type == TEMP_VAL_REG) { 4438 TCGReg old = ts->reg; 4439 tcg_debug_assert(s->reg_to_temp[old] == ts); 4440 if (old == reg) { 4441 return; 4442 } 4443 s->reg_to_temp[old] = NULL; 4444 } 4445 tcg_debug_assert(s->reg_to_temp[reg] == NULL); 4446 s->reg_to_temp[reg] = ts; 4447 ts->val_type = TEMP_VAL_REG; 4448 ts->reg = reg; 4449 } 4450 4451 /* Assign a non-register value type to @ts, and update reg_to_temp[]. */ 4452 static void set_temp_val_nonreg(TCGContext *s, TCGTemp *ts, TCGTempVal type) 4453 { 4454 tcg_debug_assert(type != TEMP_VAL_REG); 4455 if (ts->val_type == TEMP_VAL_REG) { 4456 TCGReg reg = ts->reg; 4457 tcg_debug_assert(s->reg_to_temp[reg] == ts); 4458 s->reg_to_temp[reg] = NULL; 4459 } 4460 ts->val_type = type; 4461 } 4462 4463 static void temp_load(TCGContext *, TCGTemp *, TCGRegSet, TCGRegSet, TCGRegSet); 4464 4465 /* Mark a temporary as free or dead. If 'free_or_dead' is negative, 4466 mark it free; otherwise mark it dead. */ 4467 static void temp_free_or_dead(TCGContext *s, TCGTemp *ts, int free_or_dead) 4468 { 4469 TCGTempVal new_type; 4470 4471 switch (ts->kind) { 4472 case TEMP_FIXED: 4473 return; 4474 case TEMP_GLOBAL: 4475 case TEMP_TB: 4476 new_type = TEMP_VAL_MEM; 4477 break; 4478 case TEMP_EBB: 4479 new_type = free_or_dead < 0 ? TEMP_VAL_MEM : TEMP_VAL_DEAD; 4480 break; 4481 case TEMP_CONST: 4482 new_type = TEMP_VAL_CONST; 4483 break; 4484 default: 4485 g_assert_not_reached(); 4486 } 4487 set_temp_val_nonreg(s, ts, new_type); 4488 } 4489 4490 /* Mark a temporary as dead. */ 4491 static inline void temp_dead(TCGContext *s, TCGTemp *ts) 4492 { 4493 temp_free_or_dead(s, ts, 1); 4494 } 4495 4496 /* Sync a temporary to memory. 'allocated_regs' is used in case a temporary 4497 registers needs to be allocated to store a constant. If 'free_or_dead' 4498 is non-zero, subsequently release the temporary; if it is positive, the 4499 temp is dead; if it is negative, the temp is free. */ 4500 static void temp_sync(TCGContext *s, TCGTemp *ts, TCGRegSet allocated_regs, 4501 TCGRegSet preferred_regs, int free_or_dead) 4502 { 4503 if (!temp_readonly(ts) && !ts->mem_coherent) { 4504 if (!ts->mem_allocated) { 4505 temp_allocate_frame(s, ts); 4506 } 4507 switch (ts->val_type) { 4508 case TEMP_VAL_CONST: 4509 /* If we're going to free the temp immediately, then we won't 4510 require it later in a register, so attempt to store the 4511 constant to memory directly. */ 4512 if (free_or_dead 4513 && tcg_out_sti(s, ts->type, ts->val, 4514 ts->mem_base->reg, ts->mem_offset)) { 4515 break; 4516 } 4517 temp_load(s, ts, tcg_target_available_regs[ts->type], 4518 allocated_regs, preferred_regs); 4519 /* fallthrough */ 4520 4521 case TEMP_VAL_REG: 4522 tcg_out_st(s, ts->type, ts->reg, 4523 ts->mem_base->reg, ts->mem_offset); 4524 break; 4525 4526 case TEMP_VAL_MEM: 4527 break; 4528 4529 case TEMP_VAL_DEAD: 4530 default: 4531 g_assert_not_reached(); 4532 } 4533 ts->mem_coherent = 1; 4534 } 4535 if (free_or_dead) { 4536 temp_free_or_dead(s, ts, free_or_dead); 4537 } 4538 } 4539 4540 /* free register 'reg' by spilling the corresponding temporary if necessary */ 4541 static void tcg_reg_free(TCGContext *s, TCGReg reg, TCGRegSet allocated_regs) 4542 { 4543 TCGTemp *ts = s->reg_to_temp[reg]; 4544 if (ts != NULL) { 4545 temp_sync(s, ts, allocated_regs, 0, -1); 4546 } 4547 } 4548 4549 /** 4550 * tcg_reg_alloc: 4551 * @required_regs: Set of registers in which we must allocate. 4552 * @allocated_regs: Set of registers which must be avoided. 4553 * @preferred_regs: Set of registers we should prefer. 4554 * @rev: True if we search the registers in "indirect" order. 4555 * 4556 * The allocated register must be in @required_regs & ~@allocated_regs, 4557 * but if we can put it in @preferred_regs we may save a move later. 4558 */ 4559 static TCGReg tcg_reg_alloc(TCGContext *s, TCGRegSet required_regs, 4560 TCGRegSet allocated_regs, 4561 TCGRegSet preferred_regs, bool rev) 4562 { 4563 int i, j, f, n = ARRAY_SIZE(tcg_target_reg_alloc_order); 4564 TCGRegSet reg_ct[2]; 4565 const int *order; 4566 4567 reg_ct[1] = required_regs & ~allocated_regs; 4568 tcg_debug_assert(reg_ct[1] != 0); 4569 reg_ct[0] = reg_ct[1] & preferred_regs; 4570 4571 /* Skip the preferred_regs option if it cannot be satisfied, 4572 or if the preference made no difference. */ 4573 f = reg_ct[0] == 0 || reg_ct[0] == reg_ct[1]; 4574 4575 order = rev ? indirect_reg_alloc_order : tcg_target_reg_alloc_order; 4576 4577 /* Try free registers, preferences first. */ 4578 for (j = f; j < 2; j++) { 4579 TCGRegSet set = reg_ct[j]; 4580 4581 if (tcg_regset_single(set)) { 4582 /* One register in the set. */ 4583 TCGReg reg = tcg_regset_first(set); 4584 if (s->reg_to_temp[reg] == NULL) { 4585 return reg; 4586 } 4587 } else { 4588 for (i = 0; i < n; i++) { 4589 TCGReg reg = order[i]; 4590 if (s->reg_to_temp[reg] == NULL && 4591 tcg_regset_test_reg(set, reg)) { 4592 return reg; 4593 } 4594 } 4595 } 4596 } 4597 4598 /* We must spill something. */ 4599 for (j = f; j < 2; j++) { 4600 TCGRegSet set = reg_ct[j]; 4601 4602 if (tcg_regset_single(set)) { 4603 /* One register in the set. */ 4604 TCGReg reg = tcg_regset_first(set); 4605 tcg_reg_free(s, reg, allocated_regs); 4606 return reg; 4607 } else { 4608 for (i = 0; i < n; i++) { 4609 TCGReg reg = order[i]; 4610 if (tcg_regset_test_reg(set, reg)) { 4611 tcg_reg_free(s, reg, allocated_regs); 4612 return reg; 4613 } 4614 } 4615 } 4616 } 4617 4618 g_assert_not_reached(); 4619 } 4620 4621 static TCGReg tcg_reg_alloc_pair(TCGContext *s, TCGRegSet required_regs, 4622 TCGRegSet allocated_regs, 4623 TCGRegSet preferred_regs, bool rev) 4624 { 4625 int i, j, k, fmin, n = ARRAY_SIZE(tcg_target_reg_alloc_order); 4626 TCGRegSet reg_ct[2]; 4627 const int *order; 4628 4629 /* Ensure that if I is not in allocated_regs, I+1 is not either. */ 4630 reg_ct[1] = required_regs & ~(allocated_regs | (allocated_regs >> 1)); 4631 tcg_debug_assert(reg_ct[1] != 0); 4632 reg_ct[0] = reg_ct[1] & preferred_regs; 4633 4634 order = rev ? indirect_reg_alloc_order : tcg_target_reg_alloc_order; 4635 4636 /* 4637 * Skip the preferred_regs option if it cannot be satisfied, 4638 * or if the preference made no difference. 4639 */ 4640 k = reg_ct[0] == 0 || reg_ct[0] == reg_ct[1]; 4641 4642 /* 4643 * Minimize the number of flushes by looking for 2 free registers first, 4644 * then a single flush, then two flushes. 4645 */ 4646 for (fmin = 2; fmin >= 0; fmin--) { 4647 for (j = k; j < 2; j++) { 4648 TCGRegSet set = reg_ct[j]; 4649 4650 for (i = 0; i < n; i++) { 4651 TCGReg reg = order[i]; 4652 4653 if (tcg_regset_test_reg(set, reg)) { 4654 int f = !s->reg_to_temp[reg] + !s->reg_to_temp[reg + 1]; 4655 if (f >= fmin) { 4656 tcg_reg_free(s, reg, allocated_regs); 4657 tcg_reg_free(s, reg + 1, allocated_regs); 4658 return reg; 4659 } 4660 } 4661 } 4662 } 4663 } 4664 g_assert_not_reached(); 4665 } 4666 4667 /* Make sure the temporary is in a register. If needed, allocate the register 4668 from DESIRED while avoiding ALLOCATED. */ 4669 static void temp_load(TCGContext *s, TCGTemp *ts, TCGRegSet desired_regs, 4670 TCGRegSet allocated_regs, TCGRegSet preferred_regs) 4671 { 4672 TCGReg reg; 4673 4674 switch (ts->val_type) { 4675 case TEMP_VAL_REG: 4676 return; 4677 case TEMP_VAL_CONST: 4678 reg = tcg_reg_alloc(s, desired_regs, allocated_regs, 4679 preferred_regs, ts->indirect_base); 4680 if (ts->type <= TCG_TYPE_I64) { 4681 tcg_out_movi(s, ts->type, reg, ts->val); 4682 } else { 4683 uint64_t val = ts->val; 4684 MemOp vece = MO_64; 4685 4686 /* 4687 * Find the minimal vector element that matches the constant. 4688 * The targets will, in general, have to do this search anyway, 4689 * do this generically. 4690 */ 4691 if (val == dup_const(MO_8, val)) { 4692 vece = MO_8; 4693 } else if (val == dup_const(MO_16, val)) { 4694 vece = MO_16; 4695 } else if (val == dup_const(MO_32, val)) { 4696 vece = MO_32; 4697 } 4698 4699 tcg_out_dupi_vec(s, ts->type, vece, reg, ts->val); 4700 } 4701 ts->mem_coherent = 0; 4702 break; 4703 case TEMP_VAL_MEM: 4704 if (!ts->mem_allocated) { 4705 temp_allocate_frame(s, ts); 4706 } 4707 reg = tcg_reg_alloc(s, desired_regs, allocated_regs, 4708 preferred_regs, ts->indirect_base); 4709 tcg_out_ld(s, ts->type, reg, ts->mem_base->reg, ts->mem_offset); 4710 ts->mem_coherent = 1; 4711 break; 4712 case TEMP_VAL_DEAD: 4713 default: 4714 g_assert_not_reached(); 4715 } 4716 set_temp_val_reg(s, ts, reg); 4717 } 4718 4719 /* Save a temporary to memory. 'allocated_regs' is used in case a 4720 temporary registers needs to be allocated to store a constant. */ 4721 static void temp_save(TCGContext *s, TCGTemp *ts, TCGRegSet allocated_regs) 4722 { 4723 /* The liveness analysis already ensures that globals are back 4724 in memory. Keep an tcg_debug_assert for safety. */ 4725 tcg_debug_assert(ts->val_type == TEMP_VAL_MEM || temp_readonly(ts)); 4726 } 4727 4728 /* save globals to their canonical location and assume they can be 4729 modified be the following code. 'allocated_regs' is used in case a 4730 temporary registers needs to be allocated to store a constant. */ 4731 static void save_globals(TCGContext *s, TCGRegSet allocated_regs) 4732 { 4733 int i, n; 4734 4735 for (i = 0, n = s->nb_globals; i < n; i++) { 4736 temp_save(s, &s->temps[i], allocated_regs); 4737 } 4738 } 4739 4740 /* sync globals to their canonical location and assume they can be 4741 read by the following code. 'allocated_regs' is used in case a 4742 temporary registers needs to be allocated to store a constant. */ 4743 static void sync_globals(TCGContext *s, TCGRegSet allocated_regs) 4744 { 4745 int i, n; 4746 4747 for (i = 0, n = s->nb_globals; i < n; i++) { 4748 TCGTemp *ts = &s->temps[i]; 4749 tcg_debug_assert(ts->val_type != TEMP_VAL_REG 4750 || ts->kind == TEMP_FIXED 4751 || ts->mem_coherent); 4752 } 4753 } 4754 4755 /* at the end of a basic block, we assume all temporaries are dead and 4756 all globals are stored at their canonical location. */ 4757 static void tcg_reg_alloc_bb_end(TCGContext *s, TCGRegSet allocated_regs) 4758 { 4759 int i; 4760 4761 for (i = s->nb_globals; i < s->nb_temps; i++) { 4762 TCGTemp *ts = &s->temps[i]; 4763 4764 switch (ts->kind) { 4765 case TEMP_TB: 4766 temp_save(s, ts, allocated_regs); 4767 break; 4768 case TEMP_EBB: 4769 /* The liveness analysis already ensures that temps are dead. 4770 Keep an tcg_debug_assert for safety. */ 4771 tcg_debug_assert(ts->val_type == TEMP_VAL_DEAD); 4772 break; 4773 case TEMP_CONST: 4774 /* Similarly, we should have freed any allocated register. */ 4775 tcg_debug_assert(ts->val_type == TEMP_VAL_CONST); 4776 break; 4777 default: 4778 g_assert_not_reached(); 4779 } 4780 } 4781 4782 save_globals(s, allocated_regs); 4783 } 4784 4785 /* 4786 * At a conditional branch, we assume all temporaries are dead unless 4787 * explicitly live-across-conditional-branch; all globals and local 4788 * temps are synced to their location. 4789 */ 4790 static void tcg_reg_alloc_cbranch(TCGContext *s, TCGRegSet allocated_regs) 4791 { 4792 sync_globals(s, allocated_regs); 4793 4794 for (int i = s->nb_globals; i < s->nb_temps; i++) { 4795 TCGTemp *ts = &s->temps[i]; 4796 /* 4797 * The liveness analysis already ensures that temps are dead. 4798 * Keep tcg_debug_asserts for safety. 4799 */ 4800 switch (ts->kind) { 4801 case TEMP_TB: 4802 tcg_debug_assert(ts->val_type != TEMP_VAL_REG || ts->mem_coherent); 4803 break; 4804 case TEMP_EBB: 4805 case TEMP_CONST: 4806 break; 4807 default: 4808 g_assert_not_reached(); 4809 } 4810 } 4811 } 4812 4813 /* 4814 * Specialized code generation for INDEX_op_mov_* with a constant. 4815 */ 4816 static void tcg_reg_alloc_do_movi(TCGContext *s, TCGTemp *ots, 4817 tcg_target_ulong val, TCGLifeData arg_life, 4818 TCGRegSet preferred_regs) 4819 { 4820 /* ENV should not be modified. */ 4821 tcg_debug_assert(!temp_readonly(ots)); 4822 4823 /* The movi is not explicitly generated here. */ 4824 set_temp_val_nonreg(s, ots, TEMP_VAL_CONST); 4825 ots->val = val; 4826 ots->mem_coherent = 0; 4827 if (NEED_SYNC_ARG(0)) { 4828 temp_sync(s, ots, s->reserved_regs, preferred_regs, IS_DEAD_ARG(0)); 4829 } else if (IS_DEAD_ARG(0)) { 4830 temp_dead(s, ots); 4831 } 4832 } 4833 4834 /* 4835 * Specialized code generation for INDEX_op_mov_*. 4836 */ 4837 static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op) 4838 { 4839 const TCGLifeData arg_life = op->life; 4840 TCGRegSet allocated_regs, preferred_regs; 4841 TCGTemp *ts, *ots; 4842 TCGType otype, itype; 4843 TCGReg oreg, ireg; 4844 4845 allocated_regs = s->reserved_regs; 4846 preferred_regs = output_pref(op, 0); 4847 ots = arg_temp(op->args[0]); 4848 ts = arg_temp(op->args[1]); 4849 4850 /* ENV should not be modified. */ 4851 tcg_debug_assert(!temp_readonly(ots)); 4852 4853 /* Note that otype != itype for no-op truncation. */ 4854 otype = ots->type; 4855 itype = ts->type; 4856 4857 if (ts->val_type == TEMP_VAL_CONST) { 4858 /* propagate constant or generate sti */ 4859 tcg_target_ulong val = ts->val; 4860 if (IS_DEAD_ARG(1)) { 4861 temp_dead(s, ts); 4862 } 4863 tcg_reg_alloc_do_movi(s, ots, val, arg_life, preferred_regs); 4864 return; 4865 } 4866 4867 /* If the source value is in memory we're going to be forced 4868 to have it in a register in order to perform the copy. Copy 4869 the SOURCE value into its own register first, that way we 4870 don't have to reload SOURCE the next time it is used. */ 4871 if (ts->val_type == TEMP_VAL_MEM) { 4872 temp_load(s, ts, tcg_target_available_regs[itype], 4873 allocated_regs, preferred_regs); 4874 } 4875 tcg_debug_assert(ts->val_type == TEMP_VAL_REG); 4876 ireg = ts->reg; 4877 4878 if (IS_DEAD_ARG(0)) { 4879 /* mov to a non-saved dead register makes no sense (even with 4880 liveness analysis disabled). */ 4881 tcg_debug_assert(NEED_SYNC_ARG(0)); 4882 if (!ots->mem_allocated) { 4883 temp_allocate_frame(s, ots); 4884 } 4885 tcg_out_st(s, otype, ireg, ots->mem_base->reg, ots->mem_offset); 4886 if (IS_DEAD_ARG(1)) { 4887 temp_dead(s, ts); 4888 } 4889 temp_dead(s, ots); 4890 return; 4891 } 4892 4893 if (IS_DEAD_ARG(1) && ts->kind != TEMP_FIXED) { 4894 /* 4895 * The mov can be suppressed. Kill input first, so that it 4896 * is unlinked from reg_to_temp, then set the output to the 4897 * reg that we saved from the input. 4898 */ 4899 temp_dead(s, ts); 4900 oreg = ireg; 4901 } else { 4902 if (ots->val_type == TEMP_VAL_REG) { 4903 oreg = ots->reg; 4904 } else { 4905 /* Make sure to not spill the input register during allocation. */ 4906 oreg = tcg_reg_alloc(s, tcg_target_available_regs[otype], 4907 allocated_regs | ((TCGRegSet)1 << ireg), 4908 preferred_regs, ots->indirect_base); 4909 } 4910 if (!tcg_out_mov(s, otype, oreg, ireg)) { 4911 /* 4912 * Cross register class move not supported. 4913 * Store the source register into the destination slot 4914 * and leave the destination temp as TEMP_VAL_MEM. 4915 */ 4916 assert(!temp_readonly(ots)); 4917 if (!ts->mem_allocated) { 4918 temp_allocate_frame(s, ots); 4919 } 4920 tcg_out_st(s, ts->type, ireg, ots->mem_base->reg, ots->mem_offset); 4921 set_temp_val_nonreg(s, ts, TEMP_VAL_MEM); 4922 ots->mem_coherent = 1; 4923 return; 4924 } 4925 } 4926 set_temp_val_reg(s, ots, oreg); 4927 ots->mem_coherent = 0; 4928 4929 if (NEED_SYNC_ARG(0)) { 4930 temp_sync(s, ots, allocated_regs, 0, 0); 4931 } 4932 } 4933 4934 /* 4935 * Specialized code generation for INDEX_op_dup_vec. 4936 */ 4937 static void tcg_reg_alloc_dup(TCGContext *s, const TCGOp *op) 4938 { 4939 const TCGLifeData arg_life = op->life; 4940 TCGRegSet dup_out_regs, dup_in_regs; 4941 const TCGArgConstraint *dup_args_ct; 4942 TCGTemp *its, *ots; 4943 TCGType itype, vtype; 4944 unsigned vece; 4945 int lowpart_ofs; 4946 bool ok; 4947 4948 ots = arg_temp(op->args[0]); 4949 its = arg_temp(op->args[1]); 4950 4951 /* ENV should not be modified. */ 4952 tcg_debug_assert(!temp_readonly(ots)); 4953 4954 itype = its->type; 4955 vece = TCGOP_VECE(op); 4956 vtype = TCGOP_TYPE(op); 4957 4958 if (its->val_type == TEMP_VAL_CONST) { 4959 /* Propagate constant via movi -> dupi. */ 4960 tcg_target_ulong val = its->val; 4961 if (IS_DEAD_ARG(1)) { 4962 temp_dead(s, its); 4963 } 4964 tcg_reg_alloc_do_movi(s, ots, val, arg_life, output_pref(op, 0)); 4965 return; 4966 } 4967 4968 dup_args_ct = opcode_args_ct(op); 4969 dup_out_regs = dup_args_ct[0].regs; 4970 dup_in_regs = dup_args_ct[1].regs; 4971 4972 /* Allocate the output register now. */ 4973 if (ots->val_type != TEMP_VAL_REG) { 4974 TCGRegSet allocated_regs = s->reserved_regs; 4975 TCGReg oreg; 4976 4977 if (!IS_DEAD_ARG(1) && its->val_type == TEMP_VAL_REG) { 4978 /* Make sure to not spill the input register. */ 4979 tcg_regset_set_reg(allocated_regs, its->reg); 4980 } 4981 oreg = tcg_reg_alloc(s, dup_out_regs, allocated_regs, 4982 output_pref(op, 0), ots->indirect_base); 4983 set_temp_val_reg(s, ots, oreg); 4984 } 4985 4986 switch (its->val_type) { 4987 case TEMP_VAL_REG: 4988 /* 4989 * The dup constriaints must be broad, covering all possible VECE. 4990 * However, tcg_op_dup_vec() gets to see the VECE and we allow it 4991 * to fail, indicating that extra moves are required for that case. 4992 */ 4993 if (tcg_regset_test_reg(dup_in_regs, its->reg)) { 4994 if (tcg_out_dup_vec(s, vtype, vece, ots->reg, its->reg)) { 4995 goto done; 4996 } 4997 /* Try again from memory or a vector input register. */ 4998 } 4999 if (!its->mem_coherent) { 5000 /* 5001 * The input register is not synced, and so an extra store 5002 * would be required to use memory. Attempt an integer-vector 5003 * register move first. We do not have a TCGRegSet for this. 5004 */ 5005 if (tcg_out_mov(s, itype, ots->reg, its->reg)) { 5006 break; 5007 } 5008 /* Sync the temp back to its slot and load from there. */ 5009 temp_sync(s, its, s->reserved_regs, 0, 0); 5010 } 5011 /* fall through */ 5012 5013 case TEMP_VAL_MEM: 5014 lowpart_ofs = 0; 5015 if (HOST_BIG_ENDIAN) { 5016 lowpart_ofs = tcg_type_size(itype) - (1 << vece); 5017 } 5018 if (tcg_out_dupm_vec(s, vtype, vece, ots->reg, its->mem_base->reg, 5019 its->mem_offset + lowpart_ofs)) { 5020 goto done; 5021 } 5022 /* Load the input into the destination vector register. */ 5023 tcg_out_ld(s, itype, ots->reg, its->mem_base->reg, its->mem_offset); 5024 break; 5025 5026 default: 5027 g_assert_not_reached(); 5028 } 5029 5030 /* We now have a vector input register, so dup must succeed. */ 5031 ok = tcg_out_dup_vec(s, vtype, vece, ots->reg, ots->reg); 5032 tcg_debug_assert(ok); 5033 5034 done: 5035 ots->mem_coherent = 0; 5036 if (IS_DEAD_ARG(1)) { 5037 temp_dead(s, its); 5038 } 5039 if (NEED_SYNC_ARG(0)) { 5040 temp_sync(s, ots, s->reserved_regs, 0, 0); 5041 } 5042 if (IS_DEAD_ARG(0)) { 5043 temp_dead(s, ots); 5044 } 5045 } 5046 5047 static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) 5048 { 5049 const TCGLifeData arg_life = op->life; 5050 const TCGOpDef * const def = &tcg_op_defs[op->opc]; 5051 TCGRegSet i_allocated_regs; 5052 TCGRegSet o_allocated_regs; 5053 int i, k, nb_iargs, nb_oargs; 5054 TCGReg reg; 5055 TCGArg arg; 5056 const TCGArgConstraint *args_ct; 5057 const TCGArgConstraint *arg_ct; 5058 TCGTemp *ts; 5059 TCGArg new_args[TCG_MAX_OP_ARGS]; 5060 int const_args[TCG_MAX_OP_ARGS]; 5061 TCGCond op_cond; 5062 5063 nb_oargs = def->nb_oargs; 5064 nb_iargs = def->nb_iargs; 5065 5066 /* copy constants */ 5067 memcpy(new_args + nb_oargs + nb_iargs, 5068 op->args + nb_oargs + nb_iargs, 5069 sizeof(TCGArg) * def->nb_cargs); 5070 5071 i_allocated_regs = s->reserved_regs; 5072 o_allocated_regs = s->reserved_regs; 5073 5074 switch (op->opc) { 5075 case INDEX_op_brcond_i32: 5076 case INDEX_op_brcond_i64: 5077 op_cond = op->args[2]; 5078 break; 5079 case INDEX_op_setcond_i32: 5080 case INDEX_op_setcond_i64: 5081 case INDEX_op_negsetcond_i32: 5082 case INDEX_op_negsetcond_i64: 5083 case INDEX_op_cmp_vec: 5084 op_cond = op->args[3]; 5085 break; 5086 case INDEX_op_brcond2_i32: 5087 op_cond = op->args[4]; 5088 break; 5089 case INDEX_op_movcond_i32: 5090 case INDEX_op_movcond_i64: 5091 case INDEX_op_setcond2_i32: 5092 case INDEX_op_cmpsel_vec: 5093 op_cond = op->args[5]; 5094 break; 5095 default: 5096 /* No condition within opcode. */ 5097 op_cond = TCG_COND_ALWAYS; 5098 break; 5099 } 5100 5101 args_ct = opcode_args_ct(op); 5102 5103 /* satisfy input constraints */ 5104 for (k = 0; k < nb_iargs; k++) { 5105 TCGRegSet i_preferred_regs, i_required_regs; 5106 bool allocate_new_reg, copyto_new_reg; 5107 TCGTemp *ts2; 5108 int i1, i2; 5109 5110 i = args_ct[nb_oargs + k].sort_index; 5111 arg = op->args[i]; 5112 arg_ct = &args_ct[i]; 5113 ts = arg_temp(arg); 5114 5115 if (ts->val_type == TEMP_VAL_CONST) { 5116 #ifdef TCG_REG_ZERO 5117 if (ts->val == 0 && (arg_ct->ct & TCG_CT_REG_ZERO)) { 5118 /* Hardware zero register: indicate register via non-const. */ 5119 const_args[i] = 0; 5120 new_args[i] = TCG_REG_ZERO; 5121 continue; 5122 } 5123 #endif 5124 5125 if (tcg_target_const_match(ts->val, arg_ct->ct, ts->type, 5126 op_cond, TCGOP_VECE(op))) { 5127 /* constant is OK for instruction */ 5128 const_args[i] = 1; 5129 new_args[i] = ts->val; 5130 continue; 5131 } 5132 } 5133 5134 reg = ts->reg; 5135 i_preferred_regs = 0; 5136 i_required_regs = arg_ct->regs; 5137 allocate_new_reg = false; 5138 copyto_new_reg = false; 5139 5140 switch (arg_ct->pair) { 5141 case 0: /* not paired */ 5142 if (arg_ct->ialias) { 5143 i_preferred_regs = output_pref(op, arg_ct->alias_index); 5144 5145 /* 5146 * If the input is readonly, then it cannot also be an 5147 * output and aliased to itself. If the input is not 5148 * dead after the instruction, we must allocate a new 5149 * register and move it. 5150 */ 5151 if (temp_readonly(ts) || !IS_DEAD_ARG(i) 5152 || args_ct[arg_ct->alias_index].newreg) { 5153 allocate_new_reg = true; 5154 } else if (ts->val_type == TEMP_VAL_REG) { 5155 /* 5156 * Check if the current register has already been 5157 * allocated for another input. 5158 */ 5159 allocate_new_reg = 5160 tcg_regset_test_reg(i_allocated_regs, reg); 5161 } 5162 } 5163 if (!allocate_new_reg) { 5164 temp_load(s, ts, i_required_regs, i_allocated_regs, 5165 i_preferred_regs); 5166 reg = ts->reg; 5167 allocate_new_reg = !tcg_regset_test_reg(i_required_regs, reg); 5168 } 5169 if (allocate_new_reg) { 5170 /* 5171 * Allocate a new register matching the constraint 5172 * and move the temporary register into it. 5173 */ 5174 temp_load(s, ts, tcg_target_available_regs[ts->type], 5175 i_allocated_regs, 0); 5176 reg = tcg_reg_alloc(s, i_required_regs, i_allocated_regs, 5177 i_preferred_regs, ts->indirect_base); 5178 copyto_new_reg = true; 5179 } 5180 break; 5181 5182 case 1: 5183 /* First of an input pair; if i1 == i2, the second is an output. */ 5184 i1 = i; 5185 i2 = arg_ct->pair_index; 5186 ts2 = i1 != i2 ? arg_temp(op->args[i2]) : NULL; 5187 5188 /* 5189 * It is easier to default to allocating a new pair 5190 * and to identify a few cases where it's not required. 5191 */ 5192 if (arg_ct->ialias) { 5193 i_preferred_regs = output_pref(op, arg_ct->alias_index); 5194 if (IS_DEAD_ARG(i1) && 5195 IS_DEAD_ARG(i2) && 5196 !temp_readonly(ts) && 5197 ts->val_type == TEMP_VAL_REG && 5198 ts->reg < TCG_TARGET_NB_REGS - 1 && 5199 tcg_regset_test_reg(i_required_regs, reg) && 5200 !tcg_regset_test_reg(i_allocated_regs, reg) && 5201 !tcg_regset_test_reg(i_allocated_regs, reg + 1) && 5202 (ts2 5203 ? ts2->val_type == TEMP_VAL_REG && 5204 ts2->reg == reg + 1 && 5205 !temp_readonly(ts2) 5206 : s->reg_to_temp[reg + 1] == NULL)) { 5207 break; 5208 } 5209 } else { 5210 /* Without aliasing, the pair must also be an input. */ 5211 tcg_debug_assert(ts2); 5212 if (ts->val_type == TEMP_VAL_REG && 5213 ts2->val_type == TEMP_VAL_REG && 5214 ts2->reg == reg + 1 && 5215 tcg_regset_test_reg(i_required_regs, reg)) { 5216 break; 5217 } 5218 } 5219 reg = tcg_reg_alloc_pair(s, i_required_regs, i_allocated_regs, 5220 0, ts->indirect_base); 5221 goto do_pair; 5222 5223 case 2: /* pair second */ 5224 reg = new_args[arg_ct->pair_index] + 1; 5225 goto do_pair; 5226 5227 case 3: /* ialias with second output, no first input */ 5228 tcg_debug_assert(arg_ct->ialias); 5229 i_preferred_regs = output_pref(op, arg_ct->alias_index); 5230 5231 if (IS_DEAD_ARG(i) && 5232 !temp_readonly(ts) && 5233 ts->val_type == TEMP_VAL_REG && 5234 reg > 0 && 5235 s->reg_to_temp[reg - 1] == NULL && 5236 tcg_regset_test_reg(i_required_regs, reg) && 5237 !tcg_regset_test_reg(i_allocated_regs, reg) && 5238 !tcg_regset_test_reg(i_allocated_regs, reg - 1)) { 5239 tcg_regset_set_reg(i_allocated_regs, reg - 1); 5240 break; 5241 } 5242 reg = tcg_reg_alloc_pair(s, i_required_regs >> 1, 5243 i_allocated_regs, 0, 5244 ts->indirect_base); 5245 tcg_regset_set_reg(i_allocated_regs, reg); 5246 reg += 1; 5247 goto do_pair; 5248 5249 do_pair: 5250 /* 5251 * If an aliased input is not dead after the instruction, 5252 * we must allocate a new register and move it. 5253 */ 5254 if (arg_ct->ialias && (!IS_DEAD_ARG(i) || temp_readonly(ts))) { 5255 TCGRegSet t_allocated_regs = i_allocated_regs; 5256 5257 /* 5258 * Because of the alias, and the continued life, make sure 5259 * that the temp is somewhere *other* than the reg pair, 5260 * and we get a copy in reg. 5261 */ 5262 tcg_regset_set_reg(t_allocated_regs, reg); 5263 tcg_regset_set_reg(t_allocated_regs, reg + 1); 5264 if (ts->val_type == TEMP_VAL_REG && ts->reg == reg) { 5265 /* If ts was already in reg, copy it somewhere else. */ 5266 TCGReg nr; 5267 bool ok; 5268 5269 tcg_debug_assert(ts->kind != TEMP_FIXED); 5270 nr = tcg_reg_alloc(s, tcg_target_available_regs[ts->type], 5271 t_allocated_regs, 0, ts->indirect_base); 5272 ok = tcg_out_mov(s, ts->type, nr, reg); 5273 tcg_debug_assert(ok); 5274 5275 set_temp_val_reg(s, ts, nr); 5276 } else { 5277 temp_load(s, ts, tcg_target_available_regs[ts->type], 5278 t_allocated_regs, 0); 5279 copyto_new_reg = true; 5280 } 5281 } else { 5282 /* Preferably allocate to reg, otherwise copy. */ 5283 i_required_regs = (TCGRegSet)1 << reg; 5284 temp_load(s, ts, i_required_regs, i_allocated_regs, 5285 i_preferred_regs); 5286 copyto_new_reg = ts->reg != reg; 5287 } 5288 break; 5289 5290 default: 5291 g_assert_not_reached(); 5292 } 5293 5294 if (copyto_new_reg) { 5295 if (!tcg_out_mov(s, ts->type, reg, ts->reg)) { 5296 /* 5297 * Cross register class move not supported. Sync the 5298 * temp back to its slot and load from there. 5299 */ 5300 temp_sync(s, ts, i_allocated_regs, 0, 0); 5301 tcg_out_ld(s, ts->type, reg, 5302 ts->mem_base->reg, ts->mem_offset); 5303 } 5304 } 5305 new_args[i] = reg; 5306 const_args[i] = 0; 5307 tcg_regset_set_reg(i_allocated_regs, reg); 5308 } 5309 5310 /* mark dead temporaries and free the associated registers */ 5311 for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) { 5312 if (IS_DEAD_ARG(i)) { 5313 temp_dead(s, arg_temp(op->args[i])); 5314 } 5315 } 5316 5317 if (def->flags & TCG_OPF_COND_BRANCH) { 5318 tcg_reg_alloc_cbranch(s, i_allocated_regs); 5319 } else if (def->flags & TCG_OPF_BB_END) { 5320 tcg_reg_alloc_bb_end(s, i_allocated_regs); 5321 } else { 5322 if (def->flags & TCG_OPF_CALL_CLOBBER) { 5323 /* XXX: permit generic clobber register list ? */ 5324 for (i = 0; i < TCG_TARGET_NB_REGS; i++) { 5325 if (tcg_regset_test_reg(tcg_target_call_clobber_regs, i)) { 5326 tcg_reg_free(s, i, i_allocated_regs); 5327 } 5328 } 5329 } 5330 if (def->flags & TCG_OPF_SIDE_EFFECTS) { 5331 /* sync globals if the op has side effects and might trigger 5332 an exception. */ 5333 sync_globals(s, i_allocated_regs); 5334 } 5335 5336 /* satisfy the output constraints */ 5337 for (k = 0; k < nb_oargs; k++) { 5338 i = args_ct[k].sort_index; 5339 arg = op->args[i]; 5340 arg_ct = &args_ct[i]; 5341 ts = arg_temp(arg); 5342 5343 /* ENV should not be modified. */ 5344 tcg_debug_assert(!temp_readonly(ts)); 5345 5346 switch (arg_ct->pair) { 5347 case 0: /* not paired */ 5348 if (arg_ct->oalias && !const_args[arg_ct->alias_index]) { 5349 reg = new_args[arg_ct->alias_index]; 5350 } else if (arg_ct->newreg) { 5351 reg = tcg_reg_alloc(s, arg_ct->regs, 5352 i_allocated_regs | o_allocated_regs, 5353 output_pref(op, k), ts->indirect_base); 5354 } else { 5355 reg = tcg_reg_alloc(s, arg_ct->regs, o_allocated_regs, 5356 output_pref(op, k), ts->indirect_base); 5357 } 5358 break; 5359 5360 case 1: /* first of pair */ 5361 if (arg_ct->oalias) { 5362 reg = new_args[arg_ct->alias_index]; 5363 } else if (arg_ct->newreg) { 5364 reg = tcg_reg_alloc_pair(s, arg_ct->regs, 5365 i_allocated_regs | o_allocated_regs, 5366 output_pref(op, k), 5367 ts->indirect_base); 5368 } else { 5369 reg = tcg_reg_alloc_pair(s, arg_ct->regs, o_allocated_regs, 5370 output_pref(op, k), 5371 ts->indirect_base); 5372 } 5373 break; 5374 5375 case 2: /* second of pair */ 5376 if (arg_ct->oalias) { 5377 reg = new_args[arg_ct->alias_index]; 5378 } else { 5379 reg = new_args[arg_ct->pair_index] + 1; 5380 } 5381 break; 5382 5383 case 3: /* first of pair, aliasing with a second input */ 5384 tcg_debug_assert(!arg_ct->newreg); 5385 reg = new_args[arg_ct->pair_index] - 1; 5386 break; 5387 5388 default: 5389 g_assert_not_reached(); 5390 } 5391 tcg_regset_set_reg(o_allocated_regs, reg); 5392 set_temp_val_reg(s, ts, reg); 5393 ts->mem_coherent = 0; 5394 new_args[i] = reg; 5395 } 5396 } 5397 5398 /* emit instruction */ 5399 TCGType type = TCGOP_TYPE(op); 5400 switch (op->opc) { 5401 case INDEX_op_ext_i32_i64: 5402 tcg_out_exts_i32_i64(s, new_args[0], new_args[1]); 5403 break; 5404 case INDEX_op_extu_i32_i64: 5405 tcg_out_extu_i32_i64(s, new_args[0], new_args[1]); 5406 break; 5407 case INDEX_op_extrl_i64_i32: 5408 tcg_out_extrl_i64_i32(s, new_args[0], new_args[1]); 5409 break; 5410 5411 case INDEX_op_add: 5412 case INDEX_op_and: 5413 case INDEX_op_andc: 5414 case INDEX_op_divs: 5415 case INDEX_op_divu: 5416 case INDEX_op_eqv: 5417 case INDEX_op_mul: 5418 case INDEX_op_mulsh: 5419 case INDEX_op_muluh: 5420 case INDEX_op_nand: 5421 case INDEX_op_nor: 5422 case INDEX_op_or: 5423 case INDEX_op_orc: 5424 case INDEX_op_rems: 5425 case INDEX_op_remu: 5426 case INDEX_op_xor: 5427 { 5428 const TCGOutOpBinary *out = 5429 container_of(all_outop[op->opc], TCGOutOpBinary, base); 5430 5431 /* Constants should never appear in the first source operand. */ 5432 tcg_debug_assert(!const_args[1]); 5433 if (const_args[2]) { 5434 out->out_rri(s, type, new_args[0], new_args[1], new_args[2]); 5435 } else { 5436 out->out_rrr(s, type, new_args[0], new_args[1], new_args[2]); 5437 } 5438 } 5439 break; 5440 5441 case INDEX_op_sub: 5442 { 5443 const TCGOutOpSubtract *out = &outop_sub; 5444 5445 /* 5446 * Constants should never appear in the second source operand. 5447 * These are folded to add with negative constant. 5448 */ 5449 tcg_debug_assert(!const_args[2]); 5450 if (const_args[1]) { 5451 out->out_rir(s, type, new_args[0], new_args[1], new_args[2]); 5452 } else { 5453 out->out_rrr(s, type, new_args[0], new_args[1], new_args[2]); 5454 } 5455 } 5456 break; 5457 5458 case INDEX_op_neg: 5459 case INDEX_op_not: 5460 { 5461 const TCGOutOpUnary *out = 5462 container_of(all_outop[op->opc], TCGOutOpUnary, base); 5463 5464 /* Constants should have been folded. */ 5465 tcg_debug_assert(!const_args[1]); 5466 out->out_rr(s, type, new_args[0], new_args[1]); 5467 } 5468 break; 5469 5470 case INDEX_op_divs2: 5471 case INDEX_op_divu2: 5472 { 5473 const TCGOutOpDivRem *out = 5474 container_of(all_outop[op->opc], TCGOutOpDivRem, base); 5475 5476 /* Only used by x86 and s390x, which use matching constraints. */ 5477 tcg_debug_assert(new_args[0] == new_args[2]); 5478 tcg_debug_assert(new_args[1] == new_args[3]); 5479 tcg_debug_assert(!const_args[4]); 5480 out->out_rr01r(s, type, new_args[0], new_args[1], new_args[4]); 5481 } 5482 break; 5483 5484 default: 5485 if (def->flags & TCG_OPF_VECTOR) { 5486 tcg_out_vec_op(s, op->opc, type - TCG_TYPE_V64, 5487 TCGOP_VECE(op), new_args, const_args); 5488 } else { 5489 tcg_out_op(s, op->opc, type, new_args, const_args); 5490 } 5491 break; 5492 } 5493 5494 /* move the outputs in the correct register if needed */ 5495 for(i = 0; i < nb_oargs; i++) { 5496 ts = arg_temp(op->args[i]); 5497 5498 /* ENV should not be modified. */ 5499 tcg_debug_assert(!temp_readonly(ts)); 5500 5501 if (NEED_SYNC_ARG(i)) { 5502 temp_sync(s, ts, o_allocated_regs, 0, IS_DEAD_ARG(i)); 5503 } else if (IS_DEAD_ARG(i)) { 5504 temp_dead(s, ts); 5505 } 5506 } 5507 } 5508 5509 static bool tcg_reg_alloc_dup2(TCGContext *s, const TCGOp *op) 5510 { 5511 const TCGLifeData arg_life = op->life; 5512 TCGTemp *ots, *itsl, *itsh; 5513 TCGType vtype = TCGOP_TYPE(op); 5514 5515 /* This opcode is only valid for 32-bit hosts, for 64-bit elements. */ 5516 tcg_debug_assert(TCG_TARGET_REG_BITS == 32); 5517 tcg_debug_assert(TCGOP_VECE(op) == MO_64); 5518 5519 ots = arg_temp(op->args[0]); 5520 itsl = arg_temp(op->args[1]); 5521 itsh = arg_temp(op->args[2]); 5522 5523 /* ENV should not be modified. */ 5524 tcg_debug_assert(!temp_readonly(ots)); 5525 5526 /* Allocate the output register now. */ 5527 if (ots->val_type != TEMP_VAL_REG) { 5528 TCGRegSet allocated_regs = s->reserved_regs; 5529 TCGRegSet dup_out_regs = opcode_args_ct(op)[0].regs; 5530 TCGReg oreg; 5531 5532 /* Make sure to not spill the input registers. */ 5533 if (!IS_DEAD_ARG(1) && itsl->val_type == TEMP_VAL_REG) { 5534 tcg_regset_set_reg(allocated_regs, itsl->reg); 5535 } 5536 if (!IS_DEAD_ARG(2) && itsh->val_type == TEMP_VAL_REG) { 5537 tcg_regset_set_reg(allocated_regs, itsh->reg); 5538 } 5539 5540 oreg = tcg_reg_alloc(s, dup_out_regs, allocated_regs, 5541 output_pref(op, 0), ots->indirect_base); 5542 set_temp_val_reg(s, ots, oreg); 5543 } 5544 5545 /* Promote dup2 of immediates to dupi_vec. */ 5546 if (itsl->val_type == TEMP_VAL_CONST && itsh->val_type == TEMP_VAL_CONST) { 5547 uint64_t val = deposit64(itsl->val, 32, 32, itsh->val); 5548 MemOp vece = MO_64; 5549 5550 if (val == dup_const(MO_8, val)) { 5551 vece = MO_8; 5552 } else if (val == dup_const(MO_16, val)) { 5553 vece = MO_16; 5554 } else if (val == dup_const(MO_32, val)) { 5555 vece = MO_32; 5556 } 5557 5558 tcg_out_dupi_vec(s, vtype, vece, ots->reg, val); 5559 goto done; 5560 } 5561 5562 /* If the two inputs form one 64-bit value, try dupm_vec. */ 5563 if (itsl->temp_subindex == HOST_BIG_ENDIAN && 5564 itsh->temp_subindex == !HOST_BIG_ENDIAN && 5565 itsl == itsh + (HOST_BIG_ENDIAN ? 1 : -1)) { 5566 TCGTemp *its = itsl - HOST_BIG_ENDIAN; 5567 5568 temp_sync(s, its + 0, s->reserved_regs, 0, 0); 5569 temp_sync(s, its + 1, s->reserved_regs, 0, 0); 5570 5571 if (tcg_out_dupm_vec(s, vtype, MO_64, ots->reg, 5572 its->mem_base->reg, its->mem_offset)) { 5573 goto done; 5574 } 5575 } 5576 5577 /* Fall back to generic expansion. */ 5578 return false; 5579 5580 done: 5581 ots->mem_coherent = 0; 5582 if (IS_DEAD_ARG(1)) { 5583 temp_dead(s, itsl); 5584 } 5585 if (IS_DEAD_ARG(2)) { 5586 temp_dead(s, itsh); 5587 } 5588 if (NEED_SYNC_ARG(0)) { 5589 temp_sync(s, ots, s->reserved_regs, 0, IS_DEAD_ARG(0)); 5590 } else if (IS_DEAD_ARG(0)) { 5591 temp_dead(s, ots); 5592 } 5593 return true; 5594 } 5595 5596 static void load_arg_reg(TCGContext *s, TCGReg reg, TCGTemp *ts, 5597 TCGRegSet allocated_regs) 5598 { 5599 if (ts->val_type == TEMP_VAL_REG) { 5600 if (ts->reg != reg) { 5601 tcg_reg_free(s, reg, allocated_regs); 5602 if (!tcg_out_mov(s, ts->type, reg, ts->reg)) { 5603 /* 5604 * Cross register class move not supported. Sync the 5605 * temp back to its slot and load from there. 5606 */ 5607 temp_sync(s, ts, allocated_regs, 0, 0); 5608 tcg_out_ld(s, ts->type, reg, 5609 ts->mem_base->reg, ts->mem_offset); 5610 } 5611 } 5612 } else { 5613 TCGRegSet arg_set = 0; 5614 5615 tcg_reg_free(s, reg, allocated_regs); 5616 tcg_regset_set_reg(arg_set, reg); 5617 temp_load(s, ts, arg_set, allocated_regs, 0); 5618 } 5619 } 5620 5621 static void load_arg_stk(TCGContext *s, unsigned arg_slot, TCGTemp *ts, 5622 TCGRegSet allocated_regs) 5623 { 5624 /* 5625 * When the destination is on the stack, load up the temp and store. 5626 * If there are many call-saved registers, the temp might live to 5627 * see another use; otherwise it'll be discarded. 5628 */ 5629 temp_load(s, ts, tcg_target_available_regs[ts->type], allocated_regs, 0); 5630 tcg_out_st(s, ts->type, ts->reg, TCG_REG_CALL_STACK, 5631 arg_slot_stk_ofs(arg_slot)); 5632 } 5633 5634 static void load_arg_normal(TCGContext *s, const TCGCallArgumentLoc *l, 5635 TCGTemp *ts, TCGRegSet *allocated_regs) 5636 { 5637 if (arg_slot_reg_p(l->arg_slot)) { 5638 TCGReg reg = tcg_target_call_iarg_regs[l->arg_slot]; 5639 load_arg_reg(s, reg, ts, *allocated_regs); 5640 tcg_regset_set_reg(*allocated_regs, reg); 5641 } else { 5642 load_arg_stk(s, l->arg_slot, ts, *allocated_regs); 5643 } 5644 } 5645 5646 static void load_arg_ref(TCGContext *s, unsigned arg_slot, TCGReg ref_base, 5647 intptr_t ref_off, TCGRegSet *allocated_regs) 5648 { 5649 TCGReg reg; 5650 5651 if (arg_slot_reg_p(arg_slot)) { 5652 reg = tcg_target_call_iarg_regs[arg_slot]; 5653 tcg_reg_free(s, reg, *allocated_regs); 5654 tcg_out_addi_ptr(s, reg, ref_base, ref_off); 5655 tcg_regset_set_reg(*allocated_regs, reg); 5656 } else { 5657 reg = tcg_reg_alloc(s, tcg_target_available_regs[TCG_TYPE_PTR], 5658 *allocated_regs, 0, false); 5659 tcg_out_addi_ptr(s, reg, ref_base, ref_off); 5660 tcg_out_st(s, TCG_TYPE_PTR, reg, TCG_REG_CALL_STACK, 5661 arg_slot_stk_ofs(arg_slot)); 5662 } 5663 } 5664 5665 static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) 5666 { 5667 const int nb_oargs = TCGOP_CALLO(op); 5668 const int nb_iargs = TCGOP_CALLI(op); 5669 const TCGLifeData arg_life = op->life; 5670 const TCGHelperInfo *info = tcg_call_info(op); 5671 TCGRegSet allocated_regs = s->reserved_regs; 5672 int i; 5673 5674 /* 5675 * Move inputs into place in reverse order, 5676 * so that we place stacked arguments first. 5677 */ 5678 for (i = nb_iargs - 1; i >= 0; --i) { 5679 const TCGCallArgumentLoc *loc = &info->in[i]; 5680 TCGTemp *ts = arg_temp(op->args[nb_oargs + i]); 5681 5682 switch (loc->kind) { 5683 case TCG_CALL_ARG_NORMAL: 5684 case TCG_CALL_ARG_EXTEND_U: 5685 case TCG_CALL_ARG_EXTEND_S: 5686 load_arg_normal(s, loc, ts, &allocated_regs); 5687 break; 5688 case TCG_CALL_ARG_BY_REF: 5689 load_arg_stk(s, loc->ref_slot, ts, allocated_regs); 5690 load_arg_ref(s, loc->arg_slot, TCG_REG_CALL_STACK, 5691 arg_slot_stk_ofs(loc->ref_slot), 5692 &allocated_regs); 5693 break; 5694 case TCG_CALL_ARG_BY_REF_N: 5695 load_arg_stk(s, loc->ref_slot, ts, allocated_regs); 5696 break; 5697 default: 5698 g_assert_not_reached(); 5699 } 5700 } 5701 5702 /* Mark dead temporaries and free the associated registers. */ 5703 for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) { 5704 if (IS_DEAD_ARG(i)) { 5705 temp_dead(s, arg_temp(op->args[i])); 5706 } 5707 } 5708 5709 /* Clobber call registers. */ 5710 for (i = 0; i < TCG_TARGET_NB_REGS; i++) { 5711 if (tcg_regset_test_reg(tcg_target_call_clobber_regs, i)) { 5712 tcg_reg_free(s, i, allocated_regs); 5713 } 5714 } 5715 5716 /* 5717 * Save globals if they might be written by the helper, 5718 * sync them if they might be read. 5719 */ 5720 if (info->flags & TCG_CALL_NO_READ_GLOBALS) { 5721 /* Nothing to do */ 5722 } else if (info->flags & TCG_CALL_NO_WRITE_GLOBALS) { 5723 sync_globals(s, allocated_regs); 5724 } else { 5725 save_globals(s, allocated_regs); 5726 } 5727 5728 /* 5729 * If the ABI passes a pointer to the returned struct as the first 5730 * argument, load that now. Pass a pointer to the output home slot. 5731 */ 5732 if (info->out_kind == TCG_CALL_RET_BY_REF) { 5733 TCGTemp *ts = arg_temp(op->args[0]); 5734 5735 if (!ts->mem_allocated) { 5736 temp_allocate_frame(s, ts); 5737 } 5738 load_arg_ref(s, 0, ts->mem_base->reg, ts->mem_offset, &allocated_regs); 5739 } 5740 5741 tcg_out_call(s, tcg_call_func(op), info); 5742 5743 /* Assign output registers and emit moves if needed. */ 5744 switch (info->out_kind) { 5745 case TCG_CALL_RET_NORMAL: 5746 for (i = 0; i < nb_oargs; i++) { 5747 TCGTemp *ts = arg_temp(op->args[i]); 5748 TCGReg reg = tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL, i); 5749 5750 /* ENV should not be modified. */ 5751 tcg_debug_assert(!temp_readonly(ts)); 5752 5753 set_temp_val_reg(s, ts, reg); 5754 ts->mem_coherent = 0; 5755 } 5756 break; 5757 5758 case TCG_CALL_RET_BY_VEC: 5759 { 5760 TCGTemp *ts = arg_temp(op->args[0]); 5761 5762 tcg_debug_assert(ts->base_type == TCG_TYPE_I128); 5763 tcg_debug_assert(ts->temp_subindex == 0); 5764 if (!ts->mem_allocated) { 5765 temp_allocate_frame(s, ts); 5766 } 5767 tcg_out_st(s, TCG_TYPE_V128, 5768 tcg_target_call_oarg_reg(TCG_CALL_RET_BY_VEC, 0), 5769 ts->mem_base->reg, ts->mem_offset); 5770 } 5771 /* fall through to mark all parts in memory */ 5772 5773 case TCG_CALL_RET_BY_REF: 5774 /* The callee has performed a write through the reference. */ 5775 for (i = 0; i < nb_oargs; i++) { 5776 TCGTemp *ts = arg_temp(op->args[i]); 5777 ts->val_type = TEMP_VAL_MEM; 5778 } 5779 break; 5780 5781 default: 5782 g_assert_not_reached(); 5783 } 5784 5785 /* Flush or discard output registers as needed. */ 5786 for (i = 0; i < nb_oargs; i++) { 5787 TCGTemp *ts = arg_temp(op->args[i]); 5788 if (NEED_SYNC_ARG(i)) { 5789 temp_sync(s, ts, s->reserved_regs, 0, IS_DEAD_ARG(i)); 5790 } else if (IS_DEAD_ARG(i)) { 5791 temp_dead(s, ts); 5792 } 5793 } 5794 } 5795 5796 /** 5797 * atom_and_align_for_opc: 5798 * @s: tcg context 5799 * @opc: memory operation code 5800 * @host_atom: MO_ATOM_{IFALIGN,WITHIN16,SUBALIGN} for host operations 5801 * @allow_two_ops: true if we are prepared to issue two operations 5802 * 5803 * Return the alignment and atomicity to use for the inline fast path 5804 * for the given memory operation. The alignment may be larger than 5805 * that specified in @opc, and the correct alignment will be diagnosed 5806 * by the slow path helper. 5807 * 5808 * If @allow_two_ops, the host is prepared to test for 2x alignment, 5809 * and issue two loads or stores for subalignment. 5810 */ 5811 static TCGAtomAlign atom_and_align_for_opc(TCGContext *s, MemOp opc, 5812 MemOp host_atom, bool allow_two_ops) 5813 { 5814 MemOp align = memop_alignment_bits(opc); 5815 MemOp size = opc & MO_SIZE; 5816 MemOp half = size ? size - 1 : 0; 5817 MemOp atom = opc & MO_ATOM_MASK; 5818 MemOp atmax; 5819 5820 switch (atom) { 5821 case MO_ATOM_NONE: 5822 /* The operation requires no specific atomicity. */ 5823 atmax = MO_8; 5824 break; 5825 5826 case MO_ATOM_IFALIGN: 5827 atmax = size; 5828 break; 5829 5830 case MO_ATOM_IFALIGN_PAIR: 5831 atmax = half; 5832 break; 5833 5834 case MO_ATOM_WITHIN16: 5835 atmax = size; 5836 if (size == MO_128) { 5837 /* Misalignment implies !within16, and therefore no atomicity. */ 5838 } else if (host_atom != MO_ATOM_WITHIN16) { 5839 /* The host does not implement within16, so require alignment. */ 5840 align = MAX(align, size); 5841 } 5842 break; 5843 5844 case MO_ATOM_WITHIN16_PAIR: 5845 atmax = size; 5846 /* 5847 * Misalignment implies !within16, and therefore half atomicity. 5848 * Any host prepared for two operations can implement this with 5849 * half alignment. 5850 */ 5851 if (host_atom != MO_ATOM_WITHIN16 && allow_two_ops) { 5852 align = MAX(align, half); 5853 } 5854 break; 5855 5856 case MO_ATOM_SUBALIGN: 5857 atmax = size; 5858 if (host_atom != MO_ATOM_SUBALIGN) { 5859 /* If unaligned but not odd, there are subobjects up to half. */ 5860 if (allow_two_ops) { 5861 align = MAX(align, half); 5862 } else { 5863 align = MAX(align, size); 5864 } 5865 } 5866 break; 5867 5868 default: 5869 g_assert_not_reached(); 5870 } 5871 5872 return (TCGAtomAlign){ .atom = atmax, .align = align }; 5873 } 5874 5875 /* 5876 * Similarly for qemu_ld/st slow path helpers. 5877 * We must re-implement tcg_gen_callN and tcg_reg_alloc_call simultaneously, 5878 * using only the provided backend tcg_out_* functions. 5879 */ 5880 5881 static int tcg_out_helper_stk_ofs(TCGType type, unsigned slot) 5882 { 5883 int ofs = arg_slot_stk_ofs(slot); 5884 5885 /* 5886 * Each stack slot is TCG_TARGET_LONG_BITS. If the host does not 5887 * require extension to uint64_t, adjust the address for uint32_t. 5888 */ 5889 if (HOST_BIG_ENDIAN && 5890 TCG_TARGET_REG_BITS == 64 && 5891 type == TCG_TYPE_I32) { 5892 ofs += 4; 5893 } 5894 return ofs; 5895 } 5896 5897 static void tcg_out_helper_load_slots(TCGContext *s, 5898 unsigned nmov, TCGMovExtend *mov, 5899 const TCGLdstHelperParam *parm) 5900 { 5901 unsigned i; 5902 TCGReg dst3; 5903 5904 /* 5905 * Start from the end, storing to the stack first. 5906 * This frees those registers, so we need not consider overlap. 5907 */ 5908 for (i = nmov; i-- > 0; ) { 5909 unsigned slot = mov[i].dst; 5910 5911 if (arg_slot_reg_p(slot)) { 5912 goto found_reg; 5913 } 5914 5915 TCGReg src = mov[i].src; 5916 TCGType dst_type = mov[i].dst_type; 5917 MemOp dst_mo = dst_type == TCG_TYPE_I32 ? MO_32 : MO_64; 5918 5919 /* The argument is going onto the stack; extend into scratch. */ 5920 if ((mov[i].src_ext & MO_SIZE) != dst_mo) { 5921 tcg_debug_assert(parm->ntmp != 0); 5922 mov[i].dst = src = parm->tmp[0]; 5923 tcg_out_movext1(s, &mov[i]); 5924 } 5925 5926 tcg_out_st(s, dst_type, src, TCG_REG_CALL_STACK, 5927 tcg_out_helper_stk_ofs(dst_type, slot)); 5928 } 5929 return; 5930 5931 found_reg: 5932 /* 5933 * The remaining arguments are in registers. 5934 * Convert slot numbers to argument registers. 5935 */ 5936 nmov = i + 1; 5937 for (i = 0; i < nmov; ++i) { 5938 mov[i].dst = tcg_target_call_iarg_regs[mov[i].dst]; 5939 } 5940 5941 switch (nmov) { 5942 case 4: 5943 /* The backend must have provided enough temps for the worst case. */ 5944 tcg_debug_assert(parm->ntmp >= 2); 5945 5946 dst3 = mov[3].dst; 5947 for (unsigned j = 0; j < 3; ++j) { 5948 if (dst3 == mov[j].src) { 5949 /* 5950 * Conflict. Copy the source to a temporary, perform the 5951 * remaining moves, then the extension from our scratch 5952 * on the way out. 5953 */ 5954 TCGReg scratch = parm->tmp[1]; 5955 5956 tcg_out_mov(s, mov[3].src_type, scratch, mov[3].src); 5957 tcg_out_movext3(s, mov, mov + 1, mov + 2, parm->tmp[0]); 5958 tcg_out_movext1_new_src(s, &mov[3], scratch); 5959 break; 5960 } 5961 } 5962 5963 /* No conflicts: perform this move and continue. */ 5964 tcg_out_movext1(s, &mov[3]); 5965 /* fall through */ 5966 5967 case 3: 5968 tcg_out_movext3(s, mov, mov + 1, mov + 2, 5969 parm->ntmp ? parm->tmp[0] : -1); 5970 break; 5971 case 2: 5972 tcg_out_movext2(s, mov, mov + 1, 5973 parm->ntmp ? parm->tmp[0] : -1); 5974 break; 5975 case 1: 5976 tcg_out_movext1(s, mov); 5977 break; 5978 default: 5979 g_assert_not_reached(); 5980 } 5981 } 5982 5983 static void tcg_out_helper_load_imm(TCGContext *s, unsigned slot, 5984 TCGType type, tcg_target_long imm, 5985 const TCGLdstHelperParam *parm) 5986 { 5987 if (arg_slot_reg_p(slot)) { 5988 tcg_out_movi(s, type, tcg_target_call_iarg_regs[slot], imm); 5989 } else { 5990 int ofs = tcg_out_helper_stk_ofs(type, slot); 5991 if (!tcg_out_sti(s, type, imm, TCG_REG_CALL_STACK, ofs)) { 5992 tcg_debug_assert(parm->ntmp != 0); 5993 tcg_out_movi(s, type, parm->tmp[0], imm); 5994 tcg_out_st(s, type, parm->tmp[0], TCG_REG_CALL_STACK, ofs); 5995 } 5996 } 5997 } 5998 5999 static void tcg_out_helper_load_common_args(TCGContext *s, 6000 const TCGLabelQemuLdst *ldst, 6001 const TCGLdstHelperParam *parm, 6002 const TCGHelperInfo *info, 6003 unsigned next_arg) 6004 { 6005 TCGMovExtend ptr_mov = { 6006 .dst_type = TCG_TYPE_PTR, 6007 .src_type = TCG_TYPE_PTR, 6008 .src_ext = sizeof(void *) == 4 ? MO_32 : MO_64 6009 }; 6010 const TCGCallArgumentLoc *loc = &info->in[0]; 6011 TCGType type; 6012 unsigned slot; 6013 tcg_target_ulong imm; 6014 6015 /* 6016 * Handle env, which is always first. 6017 */ 6018 ptr_mov.dst = loc->arg_slot; 6019 ptr_mov.src = TCG_AREG0; 6020 tcg_out_helper_load_slots(s, 1, &ptr_mov, parm); 6021 6022 /* 6023 * Handle oi. 6024 */ 6025 imm = ldst->oi; 6026 loc = &info->in[next_arg]; 6027 type = TCG_TYPE_I32; 6028 switch (loc->kind) { 6029 case TCG_CALL_ARG_NORMAL: 6030 break; 6031 case TCG_CALL_ARG_EXTEND_U: 6032 case TCG_CALL_ARG_EXTEND_S: 6033 /* No extension required for MemOpIdx. */ 6034 tcg_debug_assert(imm <= INT32_MAX); 6035 type = TCG_TYPE_REG; 6036 break; 6037 default: 6038 g_assert_not_reached(); 6039 } 6040 tcg_out_helper_load_imm(s, loc->arg_slot, type, imm, parm); 6041 next_arg++; 6042 6043 /* 6044 * Handle ra. 6045 */ 6046 loc = &info->in[next_arg]; 6047 slot = loc->arg_slot; 6048 if (parm->ra_gen) { 6049 int arg_reg = -1; 6050 TCGReg ra_reg; 6051 6052 if (arg_slot_reg_p(slot)) { 6053 arg_reg = tcg_target_call_iarg_regs[slot]; 6054 } 6055 ra_reg = parm->ra_gen(s, ldst, arg_reg); 6056 6057 ptr_mov.dst = slot; 6058 ptr_mov.src = ra_reg; 6059 tcg_out_helper_load_slots(s, 1, &ptr_mov, parm); 6060 } else { 6061 imm = (uintptr_t)ldst->raddr; 6062 tcg_out_helper_load_imm(s, slot, TCG_TYPE_PTR, imm, parm); 6063 } 6064 } 6065 6066 static unsigned tcg_out_helper_add_mov(TCGMovExtend *mov, 6067 const TCGCallArgumentLoc *loc, 6068 TCGType dst_type, TCGType src_type, 6069 TCGReg lo, TCGReg hi) 6070 { 6071 MemOp reg_mo; 6072 6073 if (dst_type <= TCG_TYPE_REG) { 6074 MemOp src_ext; 6075 6076 switch (loc->kind) { 6077 case TCG_CALL_ARG_NORMAL: 6078 src_ext = src_type == TCG_TYPE_I32 ? MO_32 : MO_64; 6079 break; 6080 case TCG_CALL_ARG_EXTEND_U: 6081 dst_type = TCG_TYPE_REG; 6082 src_ext = MO_UL; 6083 break; 6084 case TCG_CALL_ARG_EXTEND_S: 6085 dst_type = TCG_TYPE_REG; 6086 src_ext = MO_SL; 6087 break; 6088 default: 6089 g_assert_not_reached(); 6090 } 6091 6092 mov[0].dst = loc->arg_slot; 6093 mov[0].dst_type = dst_type; 6094 mov[0].src = lo; 6095 mov[0].src_type = src_type; 6096 mov[0].src_ext = src_ext; 6097 return 1; 6098 } 6099 6100 if (TCG_TARGET_REG_BITS == 32) { 6101 assert(dst_type == TCG_TYPE_I64); 6102 reg_mo = MO_32; 6103 } else { 6104 assert(dst_type == TCG_TYPE_I128); 6105 reg_mo = MO_64; 6106 } 6107 6108 mov[0].dst = loc[HOST_BIG_ENDIAN].arg_slot; 6109 mov[0].src = lo; 6110 mov[0].dst_type = TCG_TYPE_REG; 6111 mov[0].src_type = TCG_TYPE_REG; 6112 mov[0].src_ext = reg_mo; 6113 6114 mov[1].dst = loc[!HOST_BIG_ENDIAN].arg_slot; 6115 mov[1].src = hi; 6116 mov[1].dst_type = TCG_TYPE_REG; 6117 mov[1].src_type = TCG_TYPE_REG; 6118 mov[1].src_ext = reg_mo; 6119 6120 return 2; 6121 } 6122 6123 static void tcg_out_ld_helper_args(TCGContext *s, const TCGLabelQemuLdst *ldst, 6124 const TCGLdstHelperParam *parm) 6125 { 6126 const TCGHelperInfo *info; 6127 const TCGCallArgumentLoc *loc; 6128 TCGMovExtend mov[2]; 6129 unsigned next_arg, nmov; 6130 MemOp mop = get_memop(ldst->oi); 6131 6132 switch (mop & MO_SIZE) { 6133 case MO_8: 6134 case MO_16: 6135 case MO_32: 6136 info = &info_helper_ld32_mmu; 6137 break; 6138 case MO_64: 6139 info = &info_helper_ld64_mmu; 6140 break; 6141 case MO_128: 6142 info = &info_helper_ld128_mmu; 6143 break; 6144 default: 6145 g_assert_not_reached(); 6146 } 6147 6148 /* Defer env argument. */ 6149 next_arg = 1; 6150 6151 loc = &info->in[next_arg]; 6152 if (TCG_TARGET_REG_BITS == 32 && s->addr_type == TCG_TYPE_I32) { 6153 /* 6154 * 32-bit host with 32-bit guest: zero-extend the guest address 6155 * to 64-bits for the helper by storing the low part, then 6156 * load a zero for the high part. 6157 */ 6158 tcg_out_helper_add_mov(mov, loc + HOST_BIG_ENDIAN, 6159 TCG_TYPE_I32, TCG_TYPE_I32, 6160 ldst->addr_reg, -1); 6161 tcg_out_helper_load_slots(s, 1, mov, parm); 6162 6163 tcg_out_helper_load_imm(s, loc[!HOST_BIG_ENDIAN].arg_slot, 6164 TCG_TYPE_I32, 0, parm); 6165 next_arg += 2; 6166 } else { 6167 nmov = tcg_out_helper_add_mov(mov, loc, TCG_TYPE_I64, s->addr_type, 6168 ldst->addr_reg, -1); 6169 tcg_out_helper_load_slots(s, nmov, mov, parm); 6170 next_arg += nmov; 6171 } 6172 6173 switch (info->out_kind) { 6174 case TCG_CALL_RET_NORMAL: 6175 case TCG_CALL_RET_BY_VEC: 6176 break; 6177 case TCG_CALL_RET_BY_REF: 6178 /* 6179 * The return reference is in the first argument slot. 6180 * We need memory in which to return: re-use the top of stack. 6181 */ 6182 { 6183 int ofs_slot0 = TCG_TARGET_CALL_STACK_OFFSET; 6184 6185 if (arg_slot_reg_p(0)) { 6186 tcg_out_addi_ptr(s, tcg_target_call_iarg_regs[0], 6187 TCG_REG_CALL_STACK, ofs_slot0); 6188 } else { 6189 tcg_debug_assert(parm->ntmp != 0); 6190 tcg_out_addi_ptr(s, parm->tmp[0], 6191 TCG_REG_CALL_STACK, ofs_slot0); 6192 tcg_out_st(s, TCG_TYPE_PTR, parm->tmp[0], 6193 TCG_REG_CALL_STACK, ofs_slot0); 6194 } 6195 } 6196 break; 6197 default: 6198 g_assert_not_reached(); 6199 } 6200 6201 tcg_out_helper_load_common_args(s, ldst, parm, info, next_arg); 6202 } 6203 6204 static void tcg_out_ld_helper_ret(TCGContext *s, const TCGLabelQemuLdst *ldst, 6205 bool load_sign, 6206 const TCGLdstHelperParam *parm) 6207 { 6208 MemOp mop = get_memop(ldst->oi); 6209 TCGMovExtend mov[2]; 6210 int ofs_slot0; 6211 6212 switch (ldst->type) { 6213 case TCG_TYPE_I64: 6214 if (TCG_TARGET_REG_BITS == 32) { 6215 break; 6216 } 6217 /* fall through */ 6218 6219 case TCG_TYPE_I32: 6220 mov[0].dst = ldst->datalo_reg; 6221 mov[0].src = tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL, 0); 6222 mov[0].dst_type = ldst->type; 6223 mov[0].src_type = TCG_TYPE_REG; 6224 6225 /* 6226 * If load_sign, then we allowed the helper to perform the 6227 * appropriate sign extension to tcg_target_ulong, and all 6228 * we need now is a plain move. 6229 * 6230 * If they do not, then we expect the relevant extension 6231 * instruction to be no more expensive than a move, and 6232 * we thus save the icache etc by only using one of two 6233 * helper functions. 6234 */ 6235 if (load_sign || !(mop & MO_SIGN)) { 6236 if (TCG_TARGET_REG_BITS == 32 || ldst->type == TCG_TYPE_I32) { 6237 mov[0].src_ext = MO_32; 6238 } else { 6239 mov[0].src_ext = MO_64; 6240 } 6241 } else { 6242 mov[0].src_ext = mop & MO_SSIZE; 6243 } 6244 tcg_out_movext1(s, mov); 6245 return; 6246 6247 case TCG_TYPE_I128: 6248 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 6249 ofs_slot0 = TCG_TARGET_CALL_STACK_OFFSET; 6250 switch (TCG_TARGET_CALL_RET_I128) { 6251 case TCG_CALL_RET_NORMAL: 6252 break; 6253 case TCG_CALL_RET_BY_VEC: 6254 tcg_out_st(s, TCG_TYPE_V128, 6255 tcg_target_call_oarg_reg(TCG_CALL_RET_BY_VEC, 0), 6256 TCG_REG_CALL_STACK, ofs_slot0); 6257 /* fall through */ 6258 case TCG_CALL_RET_BY_REF: 6259 tcg_out_ld(s, TCG_TYPE_I64, ldst->datalo_reg, 6260 TCG_REG_CALL_STACK, ofs_slot0 + 8 * HOST_BIG_ENDIAN); 6261 tcg_out_ld(s, TCG_TYPE_I64, ldst->datahi_reg, 6262 TCG_REG_CALL_STACK, ofs_slot0 + 8 * !HOST_BIG_ENDIAN); 6263 return; 6264 default: 6265 g_assert_not_reached(); 6266 } 6267 break; 6268 6269 default: 6270 g_assert_not_reached(); 6271 } 6272 6273 mov[0].dst = ldst->datalo_reg; 6274 mov[0].src = 6275 tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL, HOST_BIG_ENDIAN); 6276 mov[0].dst_type = TCG_TYPE_REG; 6277 mov[0].src_type = TCG_TYPE_REG; 6278 mov[0].src_ext = TCG_TARGET_REG_BITS == 32 ? MO_32 : MO_64; 6279 6280 mov[1].dst = ldst->datahi_reg; 6281 mov[1].src = 6282 tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL, !HOST_BIG_ENDIAN); 6283 mov[1].dst_type = TCG_TYPE_REG; 6284 mov[1].src_type = TCG_TYPE_REG; 6285 mov[1].src_ext = TCG_TARGET_REG_BITS == 32 ? MO_32 : MO_64; 6286 6287 tcg_out_movext2(s, mov, mov + 1, parm->ntmp ? parm->tmp[0] : -1); 6288 } 6289 6290 static void tcg_out_st_helper_args(TCGContext *s, const TCGLabelQemuLdst *ldst, 6291 const TCGLdstHelperParam *parm) 6292 { 6293 const TCGHelperInfo *info; 6294 const TCGCallArgumentLoc *loc; 6295 TCGMovExtend mov[4]; 6296 TCGType data_type; 6297 unsigned next_arg, nmov, n; 6298 MemOp mop = get_memop(ldst->oi); 6299 6300 switch (mop & MO_SIZE) { 6301 case MO_8: 6302 case MO_16: 6303 case MO_32: 6304 info = &info_helper_st32_mmu; 6305 data_type = TCG_TYPE_I32; 6306 break; 6307 case MO_64: 6308 info = &info_helper_st64_mmu; 6309 data_type = TCG_TYPE_I64; 6310 break; 6311 case MO_128: 6312 info = &info_helper_st128_mmu; 6313 data_type = TCG_TYPE_I128; 6314 break; 6315 default: 6316 g_assert_not_reached(); 6317 } 6318 6319 /* Defer env argument. */ 6320 next_arg = 1; 6321 nmov = 0; 6322 6323 /* Handle addr argument. */ 6324 loc = &info->in[next_arg]; 6325 tcg_debug_assert(s->addr_type <= TCG_TYPE_REG); 6326 if (TCG_TARGET_REG_BITS == 32) { 6327 /* 6328 * 32-bit host (and thus 32-bit guest): zero-extend the guest address 6329 * to 64-bits for the helper by storing the low part. Later, 6330 * after we have processed the register inputs, we will load a 6331 * zero for the high part. 6332 */ 6333 tcg_out_helper_add_mov(mov, loc + HOST_BIG_ENDIAN, 6334 TCG_TYPE_I32, TCG_TYPE_I32, 6335 ldst->addr_reg, -1); 6336 next_arg += 2; 6337 nmov += 1; 6338 } else { 6339 n = tcg_out_helper_add_mov(mov, loc, TCG_TYPE_I64, s->addr_type, 6340 ldst->addr_reg, -1); 6341 next_arg += n; 6342 nmov += n; 6343 } 6344 6345 /* Handle data argument. */ 6346 loc = &info->in[next_arg]; 6347 switch (loc->kind) { 6348 case TCG_CALL_ARG_NORMAL: 6349 case TCG_CALL_ARG_EXTEND_U: 6350 case TCG_CALL_ARG_EXTEND_S: 6351 n = tcg_out_helper_add_mov(mov + nmov, loc, data_type, ldst->type, 6352 ldst->datalo_reg, ldst->datahi_reg); 6353 next_arg += n; 6354 nmov += n; 6355 tcg_out_helper_load_slots(s, nmov, mov, parm); 6356 break; 6357 6358 case TCG_CALL_ARG_BY_REF: 6359 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 6360 tcg_debug_assert(data_type == TCG_TYPE_I128); 6361 tcg_out_st(s, TCG_TYPE_I64, 6362 HOST_BIG_ENDIAN ? ldst->datahi_reg : ldst->datalo_reg, 6363 TCG_REG_CALL_STACK, arg_slot_stk_ofs(loc[0].ref_slot)); 6364 tcg_out_st(s, TCG_TYPE_I64, 6365 HOST_BIG_ENDIAN ? ldst->datalo_reg : ldst->datahi_reg, 6366 TCG_REG_CALL_STACK, arg_slot_stk_ofs(loc[1].ref_slot)); 6367 6368 tcg_out_helper_load_slots(s, nmov, mov, parm); 6369 6370 if (arg_slot_reg_p(loc->arg_slot)) { 6371 tcg_out_addi_ptr(s, tcg_target_call_iarg_regs[loc->arg_slot], 6372 TCG_REG_CALL_STACK, 6373 arg_slot_stk_ofs(loc->ref_slot)); 6374 } else { 6375 tcg_debug_assert(parm->ntmp != 0); 6376 tcg_out_addi_ptr(s, parm->tmp[0], TCG_REG_CALL_STACK, 6377 arg_slot_stk_ofs(loc->ref_slot)); 6378 tcg_out_st(s, TCG_TYPE_PTR, parm->tmp[0], 6379 TCG_REG_CALL_STACK, arg_slot_stk_ofs(loc->arg_slot)); 6380 } 6381 next_arg += 2; 6382 break; 6383 6384 default: 6385 g_assert_not_reached(); 6386 } 6387 6388 if (TCG_TARGET_REG_BITS == 32) { 6389 /* Zero extend the address by loading a zero for the high part. */ 6390 loc = &info->in[1 + !HOST_BIG_ENDIAN]; 6391 tcg_out_helper_load_imm(s, loc->arg_slot, TCG_TYPE_I32, 0, parm); 6392 } 6393 6394 tcg_out_helper_load_common_args(s, ldst, parm, info, next_arg); 6395 } 6396 6397 int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start) 6398 { 6399 int i, start_words, num_insns; 6400 TCGOp *op; 6401 6402 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP) 6403 && qemu_log_in_addr_range(pc_start))) { 6404 FILE *logfile = qemu_log_trylock(); 6405 if (logfile) { 6406 fprintf(logfile, "OP:\n"); 6407 tcg_dump_ops(s, logfile, false); 6408 fprintf(logfile, "\n"); 6409 qemu_log_unlock(logfile); 6410 } 6411 } 6412 6413 #ifdef CONFIG_DEBUG_TCG 6414 /* Ensure all labels referenced have been emitted. */ 6415 { 6416 TCGLabel *l; 6417 bool error = false; 6418 6419 QSIMPLEQ_FOREACH(l, &s->labels, next) { 6420 if (unlikely(!l->present) && !QSIMPLEQ_EMPTY(&l->branches)) { 6421 qemu_log_mask(CPU_LOG_TB_OP, 6422 "$L%d referenced but not present.\n", l->id); 6423 error = true; 6424 } 6425 } 6426 assert(!error); 6427 } 6428 #endif 6429 6430 /* Do not reuse any EBB that may be allocated within the TB. */ 6431 tcg_temp_ebb_reset_freed(s); 6432 6433 tcg_optimize(s); 6434 6435 reachable_code_pass(s); 6436 liveness_pass_0(s); 6437 liveness_pass_1(s); 6438 6439 if (s->nb_indirects > 0) { 6440 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_IND) 6441 && qemu_log_in_addr_range(pc_start))) { 6442 FILE *logfile = qemu_log_trylock(); 6443 if (logfile) { 6444 fprintf(logfile, "OP before indirect lowering:\n"); 6445 tcg_dump_ops(s, logfile, false); 6446 fprintf(logfile, "\n"); 6447 qemu_log_unlock(logfile); 6448 } 6449 } 6450 6451 /* Replace indirect temps with direct temps. */ 6452 if (liveness_pass_2(s)) { 6453 /* If changes were made, re-run liveness. */ 6454 liveness_pass_1(s); 6455 } 6456 } 6457 6458 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT) 6459 && qemu_log_in_addr_range(pc_start))) { 6460 FILE *logfile = qemu_log_trylock(); 6461 if (logfile) { 6462 fprintf(logfile, "OP after optimization and liveness analysis:\n"); 6463 tcg_dump_ops(s, logfile, true); 6464 fprintf(logfile, "\n"); 6465 qemu_log_unlock(logfile); 6466 } 6467 } 6468 6469 /* Initialize goto_tb jump offsets. */ 6470 tb->jmp_reset_offset[0] = TB_JMP_OFFSET_INVALID; 6471 tb->jmp_reset_offset[1] = TB_JMP_OFFSET_INVALID; 6472 tb->jmp_insn_offset[0] = TB_JMP_OFFSET_INVALID; 6473 tb->jmp_insn_offset[1] = TB_JMP_OFFSET_INVALID; 6474 6475 tcg_reg_alloc_start(s); 6476 6477 /* 6478 * Reset the buffer pointers when restarting after overflow. 6479 * TODO: Move this into translate-all.c with the rest of the 6480 * buffer management. Having only this done here is confusing. 6481 */ 6482 s->code_buf = tcg_splitwx_to_rw(tb->tc.ptr); 6483 s->code_ptr = s->code_buf; 6484 s->data_gen_ptr = NULL; 6485 6486 QSIMPLEQ_INIT(&s->ldst_labels); 6487 s->pool_labels = NULL; 6488 6489 start_words = s->insn_start_words; 6490 s->gen_insn_data = 6491 tcg_malloc(sizeof(uint64_t) * s->gen_tb->icount * start_words); 6492 6493 tcg_out_tb_start(s); 6494 6495 num_insns = -1; 6496 QTAILQ_FOREACH(op, &s->ops, link) { 6497 TCGOpcode opc = op->opc; 6498 6499 switch (opc) { 6500 case INDEX_op_mov: 6501 case INDEX_op_mov_vec: 6502 tcg_reg_alloc_mov(s, op); 6503 break; 6504 case INDEX_op_dup_vec: 6505 tcg_reg_alloc_dup(s, op); 6506 break; 6507 case INDEX_op_insn_start: 6508 if (num_insns >= 0) { 6509 size_t off = tcg_current_code_size(s); 6510 s->gen_insn_end_off[num_insns] = off; 6511 /* Assert that we do not overflow our stored offset. */ 6512 assert(s->gen_insn_end_off[num_insns] == off); 6513 } 6514 num_insns++; 6515 for (i = 0; i < start_words; ++i) { 6516 s->gen_insn_data[num_insns * start_words + i] = 6517 tcg_get_insn_start_param(op, i); 6518 } 6519 break; 6520 case INDEX_op_discard: 6521 temp_dead(s, arg_temp(op->args[0])); 6522 break; 6523 case INDEX_op_set_label: 6524 tcg_reg_alloc_bb_end(s, s->reserved_regs); 6525 tcg_out_label(s, arg_label(op->args[0])); 6526 break; 6527 case INDEX_op_call: 6528 tcg_reg_alloc_call(s, op); 6529 break; 6530 case INDEX_op_exit_tb: 6531 tcg_out_exit_tb(s, op->args[0]); 6532 break; 6533 case INDEX_op_goto_tb: 6534 tcg_out_goto_tb(s, op->args[0]); 6535 break; 6536 case INDEX_op_dup2_vec: 6537 if (tcg_reg_alloc_dup2(s, op)) { 6538 break; 6539 } 6540 /* fall through */ 6541 default: 6542 /* Sanity check that we've not introduced any unhandled opcodes. */ 6543 tcg_debug_assert(tcg_op_supported(opc, TCGOP_TYPE(op), 6544 TCGOP_FLAGS(op))); 6545 /* Note: in order to speed up the code, it would be much 6546 faster to have specialized register allocator functions for 6547 some common argument patterns */ 6548 tcg_reg_alloc_op(s, op); 6549 break; 6550 } 6551 /* Test for (pending) buffer overflow. The assumption is that any 6552 one operation beginning below the high water mark cannot overrun 6553 the buffer completely. Thus we can test for overflow after 6554 generating code without having to check during generation. */ 6555 if (unlikely((void *)s->code_ptr > s->code_gen_highwater)) { 6556 return -1; 6557 } 6558 /* Test for TB overflow, as seen by gen_insn_end_off. */ 6559 if (unlikely(tcg_current_code_size(s) > UINT16_MAX)) { 6560 return -2; 6561 } 6562 } 6563 tcg_debug_assert(num_insns + 1 == s->gen_tb->icount); 6564 s->gen_insn_end_off[num_insns] = tcg_current_code_size(s); 6565 6566 /* Generate TB finalization at the end of block */ 6567 i = tcg_out_ldst_finalize(s); 6568 if (i < 0) { 6569 return i; 6570 } 6571 i = tcg_out_pool_finalize(s); 6572 if (i < 0) { 6573 return i; 6574 } 6575 if (!tcg_resolve_relocs(s)) { 6576 return -2; 6577 } 6578 6579 #ifndef CONFIG_TCG_INTERPRETER 6580 /* flush instruction cache */ 6581 flush_idcache_range((uintptr_t)tcg_splitwx_to_rx(s->code_buf), 6582 (uintptr_t)s->code_buf, 6583 tcg_ptr_byte_diff(s->code_ptr, s->code_buf)); 6584 #endif 6585 6586 return tcg_current_code_size(s); 6587 } 6588 6589 #ifdef ELF_HOST_MACHINE 6590 /* In order to use this feature, the backend needs to do three things: 6591 6592 (1) Define ELF_HOST_MACHINE to indicate both what value to 6593 put into the ELF image and to indicate support for the feature. 6594 6595 (2) Define tcg_register_jit. This should create a buffer containing 6596 the contents of a .debug_frame section that describes the post- 6597 prologue unwind info for the tcg machine. 6598 6599 (3) Call tcg_register_jit_int, with the constructed .debug_frame. 6600 */ 6601 6602 /* Begin GDB interface. THE FOLLOWING MUST MATCH GDB DOCS. */ 6603 typedef enum { 6604 JIT_NOACTION = 0, 6605 JIT_REGISTER_FN, 6606 JIT_UNREGISTER_FN 6607 } jit_actions_t; 6608 6609 struct jit_code_entry { 6610 struct jit_code_entry *next_entry; 6611 struct jit_code_entry *prev_entry; 6612 const void *symfile_addr; 6613 uint64_t symfile_size; 6614 }; 6615 6616 struct jit_descriptor { 6617 uint32_t version; 6618 uint32_t action_flag; 6619 struct jit_code_entry *relevant_entry; 6620 struct jit_code_entry *first_entry; 6621 }; 6622 6623 void __jit_debug_register_code(void) __attribute__((noinline)); 6624 void __jit_debug_register_code(void) 6625 { 6626 asm(""); 6627 } 6628 6629 /* Must statically initialize the version, because GDB may check 6630 the version before we can set it. */ 6631 struct jit_descriptor __jit_debug_descriptor = { 1, 0, 0, 0 }; 6632 6633 /* End GDB interface. */ 6634 6635 static int find_string(const char *strtab, const char *str) 6636 { 6637 const char *p = strtab + 1; 6638 6639 while (1) { 6640 if (strcmp(p, str) == 0) { 6641 return p - strtab; 6642 } 6643 p += strlen(p) + 1; 6644 } 6645 } 6646 6647 static void tcg_register_jit_int(const void *buf_ptr, size_t buf_size, 6648 const void *debug_frame, 6649 size_t debug_frame_size) 6650 { 6651 struct __attribute__((packed)) DebugInfo { 6652 uint32_t len; 6653 uint16_t version; 6654 uint32_t abbrev; 6655 uint8_t ptr_size; 6656 uint8_t cu_die; 6657 uint16_t cu_lang; 6658 uintptr_t cu_low_pc; 6659 uintptr_t cu_high_pc; 6660 uint8_t fn_die; 6661 char fn_name[16]; 6662 uintptr_t fn_low_pc; 6663 uintptr_t fn_high_pc; 6664 uint8_t cu_eoc; 6665 }; 6666 6667 struct ElfImage { 6668 ElfW(Ehdr) ehdr; 6669 ElfW(Phdr) phdr; 6670 ElfW(Shdr) shdr[7]; 6671 ElfW(Sym) sym[2]; 6672 struct DebugInfo di; 6673 uint8_t da[24]; 6674 char str[80]; 6675 }; 6676 6677 struct ElfImage *img; 6678 6679 static const struct ElfImage img_template = { 6680 .ehdr = { 6681 .e_ident[EI_MAG0] = ELFMAG0, 6682 .e_ident[EI_MAG1] = ELFMAG1, 6683 .e_ident[EI_MAG2] = ELFMAG2, 6684 .e_ident[EI_MAG3] = ELFMAG3, 6685 .e_ident[EI_CLASS] = ELF_CLASS, 6686 .e_ident[EI_DATA] = ELF_DATA, 6687 .e_ident[EI_VERSION] = EV_CURRENT, 6688 .e_type = ET_EXEC, 6689 .e_machine = ELF_HOST_MACHINE, 6690 .e_version = EV_CURRENT, 6691 .e_phoff = offsetof(struct ElfImage, phdr), 6692 .e_shoff = offsetof(struct ElfImage, shdr), 6693 .e_ehsize = sizeof(ElfW(Shdr)), 6694 .e_phentsize = sizeof(ElfW(Phdr)), 6695 .e_phnum = 1, 6696 .e_shentsize = sizeof(ElfW(Shdr)), 6697 .e_shnum = ARRAY_SIZE(img->shdr), 6698 .e_shstrndx = ARRAY_SIZE(img->shdr) - 1, 6699 #ifdef ELF_HOST_FLAGS 6700 .e_flags = ELF_HOST_FLAGS, 6701 #endif 6702 #ifdef ELF_OSABI 6703 .e_ident[EI_OSABI] = ELF_OSABI, 6704 #endif 6705 }, 6706 .phdr = { 6707 .p_type = PT_LOAD, 6708 .p_flags = PF_X, 6709 }, 6710 .shdr = { 6711 [0] = { .sh_type = SHT_NULL }, 6712 /* Trick: The contents of code_gen_buffer are not present in 6713 this fake ELF file; that got allocated elsewhere. Therefore 6714 we mark .text as SHT_NOBITS (similar to .bss) so that readers 6715 will not look for contents. We can record any address. */ 6716 [1] = { /* .text */ 6717 .sh_type = SHT_NOBITS, 6718 .sh_flags = SHF_EXECINSTR | SHF_ALLOC, 6719 }, 6720 [2] = { /* .debug_info */ 6721 .sh_type = SHT_PROGBITS, 6722 .sh_offset = offsetof(struct ElfImage, di), 6723 .sh_size = sizeof(struct DebugInfo), 6724 }, 6725 [3] = { /* .debug_abbrev */ 6726 .sh_type = SHT_PROGBITS, 6727 .sh_offset = offsetof(struct ElfImage, da), 6728 .sh_size = sizeof(img->da), 6729 }, 6730 [4] = { /* .debug_frame */ 6731 .sh_type = SHT_PROGBITS, 6732 .sh_offset = sizeof(struct ElfImage), 6733 }, 6734 [5] = { /* .symtab */ 6735 .sh_type = SHT_SYMTAB, 6736 .sh_offset = offsetof(struct ElfImage, sym), 6737 .sh_size = sizeof(img->sym), 6738 .sh_info = 1, 6739 .sh_link = ARRAY_SIZE(img->shdr) - 1, 6740 .sh_entsize = sizeof(ElfW(Sym)), 6741 }, 6742 [6] = { /* .strtab */ 6743 .sh_type = SHT_STRTAB, 6744 .sh_offset = offsetof(struct ElfImage, str), 6745 .sh_size = sizeof(img->str), 6746 } 6747 }, 6748 .sym = { 6749 [1] = { /* code_gen_buffer */ 6750 .st_info = ELF_ST_INFO(STB_GLOBAL, STT_FUNC), 6751 .st_shndx = 1, 6752 } 6753 }, 6754 .di = { 6755 .len = sizeof(struct DebugInfo) - 4, 6756 .version = 2, 6757 .ptr_size = sizeof(void *), 6758 .cu_die = 1, 6759 .cu_lang = 0x8001, /* DW_LANG_Mips_Assembler */ 6760 .fn_die = 2, 6761 .fn_name = "code_gen_buffer" 6762 }, 6763 .da = { 6764 1, /* abbrev number (the cu) */ 6765 0x11, 1, /* DW_TAG_compile_unit, has children */ 6766 0x13, 0x5, /* DW_AT_language, DW_FORM_data2 */ 6767 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */ 6768 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */ 6769 0, 0, /* end of abbrev */ 6770 2, /* abbrev number (the fn) */ 6771 0x2e, 0, /* DW_TAG_subprogram, no children */ 6772 0x3, 0x8, /* DW_AT_name, DW_FORM_string */ 6773 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */ 6774 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */ 6775 0, 0, /* end of abbrev */ 6776 0 /* no more abbrev */ 6777 }, 6778 .str = "\0" ".text\0" ".debug_info\0" ".debug_abbrev\0" 6779 ".debug_frame\0" ".symtab\0" ".strtab\0" "code_gen_buffer", 6780 }; 6781 6782 /* We only need a single jit entry; statically allocate it. */ 6783 static struct jit_code_entry one_entry; 6784 6785 uintptr_t buf = (uintptr_t)buf_ptr; 6786 size_t img_size = sizeof(struct ElfImage) + debug_frame_size; 6787 DebugFrameHeader *dfh; 6788 6789 img = g_malloc(img_size); 6790 *img = img_template; 6791 6792 img->phdr.p_vaddr = buf; 6793 img->phdr.p_paddr = buf; 6794 img->phdr.p_memsz = buf_size; 6795 6796 img->shdr[1].sh_name = find_string(img->str, ".text"); 6797 img->shdr[1].sh_addr = buf; 6798 img->shdr[1].sh_size = buf_size; 6799 6800 img->shdr[2].sh_name = find_string(img->str, ".debug_info"); 6801 img->shdr[3].sh_name = find_string(img->str, ".debug_abbrev"); 6802 6803 img->shdr[4].sh_name = find_string(img->str, ".debug_frame"); 6804 img->shdr[4].sh_size = debug_frame_size; 6805 6806 img->shdr[5].sh_name = find_string(img->str, ".symtab"); 6807 img->shdr[6].sh_name = find_string(img->str, ".strtab"); 6808 6809 img->sym[1].st_name = find_string(img->str, "code_gen_buffer"); 6810 img->sym[1].st_value = buf; 6811 img->sym[1].st_size = buf_size; 6812 6813 img->di.cu_low_pc = buf; 6814 img->di.cu_high_pc = buf + buf_size; 6815 img->di.fn_low_pc = buf; 6816 img->di.fn_high_pc = buf + buf_size; 6817 6818 dfh = (DebugFrameHeader *)(img + 1); 6819 memcpy(dfh, debug_frame, debug_frame_size); 6820 dfh->fde.func_start = buf; 6821 dfh->fde.func_len = buf_size; 6822 6823 #ifdef DEBUG_JIT 6824 /* Enable this block to be able to debug the ELF image file creation. 6825 One can use readelf, objdump, or other inspection utilities. */ 6826 { 6827 g_autofree char *jit = g_strdup_printf("%s/qemu.jit", g_get_tmp_dir()); 6828 FILE *f = fopen(jit, "w+b"); 6829 if (f) { 6830 if (fwrite(img, img_size, 1, f) != img_size) { 6831 /* Avoid stupid unused return value warning for fwrite. */ 6832 } 6833 fclose(f); 6834 } 6835 } 6836 #endif 6837 6838 one_entry.symfile_addr = img; 6839 one_entry.symfile_size = img_size; 6840 6841 __jit_debug_descriptor.action_flag = JIT_REGISTER_FN; 6842 __jit_debug_descriptor.relevant_entry = &one_entry; 6843 __jit_debug_descriptor.first_entry = &one_entry; 6844 __jit_debug_register_code(); 6845 } 6846 #else 6847 /* No support for the feature. Provide the entry point expected by exec.c, 6848 and implement the internal function we declared earlier. */ 6849 6850 static void tcg_register_jit_int(const void *buf, size_t size, 6851 const void *debug_frame, 6852 size_t debug_frame_size) 6853 { 6854 } 6855 6856 void tcg_register_jit(const void *buf, size_t buf_size) 6857 { 6858 } 6859 #endif /* ELF_HOST_MACHINE */ 6860 6861 #if !TCG_TARGET_MAYBE_vec 6862 void tcg_expand_vec_op(TCGOpcode o, TCGType t, unsigned e, TCGArg a0, ...) 6863 { 6864 g_assert_not_reached(); 6865 } 6866 #endif 6867