1 /* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 /* define it to use liveness analysis (better code) */ 26 #define USE_TCG_OPTIMIZATIONS 27 28 #include "qemu/osdep.h" 29 30 /* Define to jump the ELF file used to communicate with GDB. */ 31 #undef DEBUG_JIT 32 33 #include "qemu/cutils.h" 34 #include "qemu/host-utils.h" 35 #include "qemu/timer.h" 36 37 /* Note: the long term plan is to reduce the dependencies on the QEMU 38 CPU definitions. Currently they are used for qemu_ld/st 39 instructions */ 40 #define NO_CPU_IO_DEFS 41 #include "cpu.h" 42 43 #include "exec/cpu-common.h" 44 #include "exec/exec-all.h" 45 46 #include "tcg-op.h" 47 48 #if UINTPTR_MAX == UINT32_MAX 49 # define ELF_CLASS ELFCLASS32 50 #else 51 # define ELF_CLASS ELFCLASS64 52 #endif 53 #ifdef HOST_WORDS_BIGENDIAN 54 # define ELF_DATA ELFDATA2MSB 55 #else 56 # define ELF_DATA ELFDATA2LSB 57 #endif 58 59 #include "elf.h" 60 #include "exec/log.h" 61 62 /* Forward declarations for functions declared in tcg-target.inc.c and 63 used here. */ 64 static void tcg_target_init(TCGContext *s); 65 static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode); 66 static void tcg_target_qemu_prologue(TCGContext *s); 67 static void patch_reloc(tcg_insn_unit *code_ptr, int type, 68 intptr_t value, intptr_t addend); 69 70 /* The CIE and FDE header definitions will be common to all hosts. */ 71 typedef struct { 72 uint32_t len __attribute__((aligned((sizeof(void *))))); 73 uint32_t id; 74 uint8_t version; 75 char augmentation[1]; 76 uint8_t code_align; 77 uint8_t data_align; 78 uint8_t return_column; 79 } DebugFrameCIE; 80 81 typedef struct QEMU_PACKED { 82 uint32_t len __attribute__((aligned((sizeof(void *))))); 83 uint32_t cie_offset; 84 uintptr_t func_start; 85 uintptr_t func_len; 86 } DebugFrameFDEHeader; 87 88 typedef struct QEMU_PACKED { 89 DebugFrameCIE cie; 90 DebugFrameFDEHeader fde; 91 } DebugFrameHeader; 92 93 static void tcg_register_jit_int(void *buf, size_t size, 94 const void *debug_frame, 95 size_t debug_frame_size) 96 __attribute__((unused)); 97 98 /* Forward declarations for functions declared and used in tcg-target.inc.c. */ 99 static const char *target_parse_constraint(TCGArgConstraint *ct, 100 const char *ct_str, TCGType type); 101 static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1, 102 intptr_t arg2); 103 static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg); 104 static void tcg_out_movi(TCGContext *s, TCGType type, 105 TCGReg ret, tcg_target_long arg); 106 static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, 107 const int *const_args); 108 static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1, 109 intptr_t arg2); 110 static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 111 TCGReg base, intptr_t ofs); 112 static void tcg_out_call(TCGContext *s, tcg_insn_unit *target); 113 static int tcg_target_const_match(tcg_target_long val, TCGType type, 114 const TCGArgConstraint *arg_ct); 115 #ifdef TCG_TARGET_NEED_LDST_LABELS 116 static bool tcg_out_ldst_finalize(TCGContext *s); 117 #endif 118 119 #define TCG_HIGHWATER 1024 120 121 static TCGRegSet tcg_target_available_regs[2]; 122 static TCGRegSet tcg_target_call_clobber_regs; 123 124 #if TCG_TARGET_INSN_UNIT_SIZE == 1 125 static __attribute__((unused)) inline void tcg_out8(TCGContext *s, uint8_t v) 126 { 127 *s->code_ptr++ = v; 128 } 129 130 static __attribute__((unused)) inline void tcg_patch8(tcg_insn_unit *p, 131 uint8_t v) 132 { 133 *p = v; 134 } 135 #endif 136 137 #if TCG_TARGET_INSN_UNIT_SIZE <= 2 138 static __attribute__((unused)) inline void tcg_out16(TCGContext *s, uint16_t v) 139 { 140 if (TCG_TARGET_INSN_UNIT_SIZE == 2) { 141 *s->code_ptr++ = v; 142 } else { 143 tcg_insn_unit *p = s->code_ptr; 144 memcpy(p, &v, sizeof(v)); 145 s->code_ptr = p + (2 / TCG_TARGET_INSN_UNIT_SIZE); 146 } 147 } 148 149 static __attribute__((unused)) inline void tcg_patch16(tcg_insn_unit *p, 150 uint16_t v) 151 { 152 if (TCG_TARGET_INSN_UNIT_SIZE == 2) { 153 *p = v; 154 } else { 155 memcpy(p, &v, sizeof(v)); 156 } 157 } 158 #endif 159 160 #if TCG_TARGET_INSN_UNIT_SIZE <= 4 161 static __attribute__((unused)) inline void tcg_out32(TCGContext *s, uint32_t v) 162 { 163 if (TCG_TARGET_INSN_UNIT_SIZE == 4) { 164 *s->code_ptr++ = v; 165 } else { 166 tcg_insn_unit *p = s->code_ptr; 167 memcpy(p, &v, sizeof(v)); 168 s->code_ptr = p + (4 / TCG_TARGET_INSN_UNIT_SIZE); 169 } 170 } 171 172 static __attribute__((unused)) inline void tcg_patch32(tcg_insn_unit *p, 173 uint32_t v) 174 { 175 if (TCG_TARGET_INSN_UNIT_SIZE == 4) { 176 *p = v; 177 } else { 178 memcpy(p, &v, sizeof(v)); 179 } 180 } 181 #endif 182 183 #if TCG_TARGET_INSN_UNIT_SIZE <= 8 184 static __attribute__((unused)) inline void tcg_out64(TCGContext *s, uint64_t v) 185 { 186 if (TCG_TARGET_INSN_UNIT_SIZE == 8) { 187 *s->code_ptr++ = v; 188 } else { 189 tcg_insn_unit *p = s->code_ptr; 190 memcpy(p, &v, sizeof(v)); 191 s->code_ptr = p + (8 / TCG_TARGET_INSN_UNIT_SIZE); 192 } 193 } 194 195 static __attribute__((unused)) inline void tcg_patch64(tcg_insn_unit *p, 196 uint64_t v) 197 { 198 if (TCG_TARGET_INSN_UNIT_SIZE == 8) { 199 *p = v; 200 } else { 201 memcpy(p, &v, sizeof(v)); 202 } 203 } 204 #endif 205 206 /* label relocation processing */ 207 208 static void tcg_out_reloc(TCGContext *s, tcg_insn_unit *code_ptr, int type, 209 TCGLabel *l, intptr_t addend) 210 { 211 TCGRelocation *r; 212 213 if (l->has_value) { 214 /* FIXME: This may break relocations on RISC targets that 215 modify instruction fields in place. The caller may not have 216 written the initial value. */ 217 patch_reloc(code_ptr, type, l->u.value, addend); 218 } else { 219 /* add a new relocation entry */ 220 r = tcg_malloc(sizeof(TCGRelocation)); 221 r->type = type; 222 r->ptr = code_ptr; 223 r->addend = addend; 224 r->next = l->u.first_reloc; 225 l->u.first_reloc = r; 226 } 227 } 228 229 static void tcg_out_label(TCGContext *s, TCGLabel *l, tcg_insn_unit *ptr) 230 { 231 intptr_t value = (intptr_t)ptr; 232 TCGRelocation *r; 233 234 tcg_debug_assert(!l->has_value); 235 236 for (r = l->u.first_reloc; r != NULL; r = r->next) { 237 patch_reloc(r->ptr, r->type, value, r->addend); 238 } 239 240 l->has_value = 1; 241 l->u.value_ptr = ptr; 242 } 243 244 TCGLabel *gen_new_label(void) 245 { 246 TCGContext *s = tcg_ctx; 247 TCGLabel *l = tcg_malloc(sizeof(TCGLabel)); 248 249 *l = (TCGLabel){ 250 .id = s->nb_labels++ 251 }; 252 253 return l; 254 } 255 256 #include "tcg-target.inc.c" 257 258 /* pool based memory allocation */ 259 void *tcg_malloc_internal(TCGContext *s, int size) 260 { 261 TCGPool *p; 262 int pool_size; 263 264 if (size > TCG_POOL_CHUNK_SIZE) { 265 /* big malloc: insert a new pool (XXX: could optimize) */ 266 p = g_malloc(sizeof(TCGPool) + size); 267 p->size = size; 268 p->next = s->pool_first_large; 269 s->pool_first_large = p; 270 return p->data; 271 } else { 272 p = s->pool_current; 273 if (!p) { 274 p = s->pool_first; 275 if (!p) 276 goto new_pool; 277 } else { 278 if (!p->next) { 279 new_pool: 280 pool_size = TCG_POOL_CHUNK_SIZE; 281 p = g_malloc(sizeof(TCGPool) + pool_size); 282 p->size = pool_size; 283 p->next = NULL; 284 if (s->pool_current) 285 s->pool_current->next = p; 286 else 287 s->pool_first = p; 288 } else { 289 p = p->next; 290 } 291 } 292 } 293 s->pool_current = p; 294 s->pool_cur = p->data + size; 295 s->pool_end = p->data + p->size; 296 return p->data; 297 } 298 299 void tcg_pool_reset(TCGContext *s) 300 { 301 TCGPool *p, *t; 302 for (p = s->pool_first_large; p; p = t) { 303 t = p->next; 304 g_free(p); 305 } 306 s->pool_first_large = NULL; 307 s->pool_cur = s->pool_end = NULL; 308 s->pool_current = NULL; 309 } 310 311 typedef struct TCGHelperInfo { 312 void *func; 313 const char *name; 314 unsigned flags; 315 unsigned sizemask; 316 } TCGHelperInfo; 317 318 #include "exec/helper-proto.h" 319 320 static const TCGHelperInfo all_helpers[] = { 321 #include "exec/helper-tcg.h" 322 }; 323 static GHashTable *helper_table; 324 325 static int indirect_reg_alloc_order[ARRAY_SIZE(tcg_target_reg_alloc_order)]; 326 static void process_op_defs(TCGContext *s); 327 328 void tcg_context_init(TCGContext *s) 329 { 330 int op, total_args, n, i; 331 TCGOpDef *def; 332 TCGArgConstraint *args_ct; 333 int *sorted_args; 334 335 memset(s, 0, sizeof(*s)); 336 s->nb_globals = 0; 337 338 /* Count total number of arguments and allocate the corresponding 339 space */ 340 total_args = 0; 341 for(op = 0; op < NB_OPS; op++) { 342 def = &tcg_op_defs[op]; 343 n = def->nb_iargs + def->nb_oargs; 344 total_args += n; 345 } 346 347 args_ct = g_malloc(sizeof(TCGArgConstraint) * total_args); 348 sorted_args = g_malloc(sizeof(int) * total_args); 349 350 for(op = 0; op < NB_OPS; op++) { 351 def = &tcg_op_defs[op]; 352 def->args_ct = args_ct; 353 def->sorted_args = sorted_args; 354 n = def->nb_iargs + def->nb_oargs; 355 sorted_args += n; 356 args_ct += n; 357 } 358 359 /* Register helpers. */ 360 /* Use g_direct_hash/equal for direct pointer comparisons on func. */ 361 helper_table = g_hash_table_new(NULL, NULL); 362 363 for (i = 0; i < ARRAY_SIZE(all_helpers); ++i) { 364 g_hash_table_insert(helper_table, (gpointer)all_helpers[i].func, 365 (gpointer)&all_helpers[i]); 366 } 367 368 tcg_target_init(s); 369 process_op_defs(s); 370 371 /* Reverse the order of the saved registers, assuming they're all at 372 the start of tcg_target_reg_alloc_order. */ 373 for (n = 0; n < ARRAY_SIZE(tcg_target_reg_alloc_order); ++n) { 374 int r = tcg_target_reg_alloc_order[n]; 375 if (tcg_regset_test_reg(tcg_target_call_clobber_regs, r)) { 376 break; 377 } 378 } 379 for (i = 0; i < n; ++i) { 380 indirect_reg_alloc_order[i] = tcg_target_reg_alloc_order[n - 1 - i]; 381 } 382 for (; i < ARRAY_SIZE(tcg_target_reg_alloc_order); ++i) { 383 indirect_reg_alloc_order[i] = tcg_target_reg_alloc_order[i]; 384 } 385 386 tcg_ctx = s; 387 } 388 389 /* 390 * Allocate TBs right before their corresponding translated code, making 391 * sure that TBs and code are on different cache lines. 392 */ 393 TranslationBlock *tcg_tb_alloc(TCGContext *s) 394 { 395 uintptr_t align = qemu_icache_linesize; 396 TranslationBlock *tb; 397 void *next; 398 399 tb = (void *)ROUND_UP((uintptr_t)s->code_gen_ptr, align); 400 next = (void *)ROUND_UP((uintptr_t)(tb + 1), align); 401 402 if (unlikely(next > s->code_gen_highwater)) { 403 return NULL; 404 } 405 s->code_gen_ptr = next; 406 s->data_gen_ptr = NULL; 407 return tb; 408 } 409 410 void tcg_prologue_init(TCGContext *s) 411 { 412 size_t prologue_size, total_size; 413 void *buf0, *buf1; 414 415 /* Put the prologue at the beginning of code_gen_buffer. */ 416 buf0 = s->code_gen_buffer; 417 s->code_ptr = buf0; 418 s->code_buf = buf0; 419 s->code_gen_prologue = buf0; 420 421 /* Generate the prologue. */ 422 tcg_target_qemu_prologue(s); 423 buf1 = s->code_ptr; 424 flush_icache_range((uintptr_t)buf0, (uintptr_t)buf1); 425 426 /* Deduct the prologue from the buffer. */ 427 prologue_size = tcg_current_code_size(s); 428 s->code_gen_ptr = buf1; 429 s->code_gen_buffer = buf1; 430 s->code_buf = buf1; 431 total_size = s->code_gen_buffer_size - prologue_size; 432 s->code_gen_buffer_size = total_size; 433 434 /* Compute a high-water mark, at which we voluntarily flush the buffer 435 and start over. The size here is arbitrary, significantly larger 436 than we expect the code generation for any one opcode to require. */ 437 s->code_gen_highwater = s->code_gen_buffer + (total_size - TCG_HIGHWATER); 438 439 tcg_register_jit(s->code_gen_buffer, total_size); 440 441 #ifdef DEBUG_DISAS 442 if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM)) { 443 qemu_log_lock(); 444 qemu_log("PROLOGUE: [size=%zu]\n", prologue_size); 445 log_disas(buf0, prologue_size); 446 qemu_log("\n"); 447 qemu_log_flush(); 448 qemu_log_unlock(); 449 } 450 #endif 451 452 /* Assert that goto_ptr is implemented completely. */ 453 if (TCG_TARGET_HAS_goto_ptr) { 454 tcg_debug_assert(s->code_gen_epilogue != NULL); 455 } 456 } 457 458 void tcg_func_start(TCGContext *s) 459 { 460 tcg_pool_reset(s); 461 s->nb_temps = s->nb_globals; 462 463 /* No temps have been previously allocated for size or locality. */ 464 memset(s->free_temps, 0, sizeof(s->free_temps)); 465 466 s->nb_labels = 0; 467 s->current_frame_offset = s->frame_start; 468 469 #ifdef CONFIG_DEBUG_TCG 470 s->goto_tb_issue_mask = 0; 471 #endif 472 473 s->gen_op_buf[0].next = 1; 474 s->gen_op_buf[0].prev = 0; 475 s->gen_next_op_idx = 1; 476 } 477 478 static inline TCGTemp *tcg_temp_alloc(TCGContext *s) 479 { 480 int n = s->nb_temps++; 481 tcg_debug_assert(n < TCG_MAX_TEMPS); 482 return memset(&s->temps[n], 0, sizeof(TCGTemp)); 483 } 484 485 static inline TCGTemp *tcg_global_alloc(TCGContext *s) 486 { 487 TCGTemp *ts; 488 489 tcg_debug_assert(s->nb_globals == s->nb_temps); 490 s->nb_globals++; 491 ts = tcg_temp_alloc(s); 492 ts->temp_global = 1; 493 494 return ts; 495 } 496 497 static TCGTemp *tcg_global_reg_new_internal(TCGContext *s, TCGType type, 498 TCGReg reg, const char *name) 499 { 500 TCGTemp *ts; 501 502 if (TCG_TARGET_REG_BITS == 32 && type != TCG_TYPE_I32) { 503 tcg_abort(); 504 } 505 506 ts = tcg_global_alloc(s); 507 ts->base_type = type; 508 ts->type = type; 509 ts->fixed_reg = 1; 510 ts->reg = reg; 511 ts->name = name; 512 tcg_regset_set_reg(s->reserved_regs, reg); 513 514 return ts; 515 } 516 517 void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size) 518 { 519 s->frame_start = start; 520 s->frame_end = start + size; 521 s->frame_temp 522 = tcg_global_reg_new_internal(s, TCG_TYPE_PTR, reg, "_frame"); 523 } 524 525 TCGv_i32 tcg_global_reg_new_i32(TCGReg reg, const char *name) 526 { 527 TCGContext *s = tcg_ctx; 528 TCGTemp *t; 529 530 if (tcg_regset_test_reg(s->reserved_regs, reg)) { 531 tcg_abort(); 532 } 533 t = tcg_global_reg_new_internal(s, TCG_TYPE_I32, reg, name); 534 return temp_tcgv_i32(t); 535 } 536 537 TCGv_i64 tcg_global_reg_new_i64(TCGReg reg, const char *name) 538 { 539 TCGContext *s = tcg_ctx; 540 TCGTemp *t; 541 542 if (tcg_regset_test_reg(s->reserved_regs, reg)) { 543 tcg_abort(); 544 } 545 t = tcg_global_reg_new_internal(s, TCG_TYPE_I64, reg, name); 546 return temp_tcgv_i64(t); 547 } 548 549 TCGTemp *tcg_global_mem_new_internal(TCGType type, TCGv_ptr base, 550 intptr_t offset, const char *name) 551 { 552 TCGContext *s = tcg_ctx; 553 TCGTemp *base_ts = tcgv_ptr_temp(base); 554 TCGTemp *ts = tcg_global_alloc(s); 555 int indirect_reg = 0, bigendian = 0; 556 #ifdef HOST_WORDS_BIGENDIAN 557 bigendian = 1; 558 #endif 559 560 if (!base_ts->fixed_reg) { 561 /* We do not support double-indirect registers. */ 562 tcg_debug_assert(!base_ts->indirect_reg); 563 base_ts->indirect_base = 1; 564 s->nb_indirects += (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64 565 ? 2 : 1); 566 indirect_reg = 1; 567 } 568 569 if (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64) { 570 TCGTemp *ts2 = tcg_global_alloc(s); 571 char buf[64]; 572 573 ts->base_type = TCG_TYPE_I64; 574 ts->type = TCG_TYPE_I32; 575 ts->indirect_reg = indirect_reg; 576 ts->mem_allocated = 1; 577 ts->mem_base = base_ts; 578 ts->mem_offset = offset + bigendian * 4; 579 pstrcpy(buf, sizeof(buf), name); 580 pstrcat(buf, sizeof(buf), "_0"); 581 ts->name = strdup(buf); 582 583 tcg_debug_assert(ts2 == ts + 1); 584 ts2->base_type = TCG_TYPE_I64; 585 ts2->type = TCG_TYPE_I32; 586 ts2->indirect_reg = indirect_reg; 587 ts2->mem_allocated = 1; 588 ts2->mem_base = base_ts; 589 ts2->mem_offset = offset + (1 - bigendian) * 4; 590 pstrcpy(buf, sizeof(buf), name); 591 pstrcat(buf, sizeof(buf), "_1"); 592 ts2->name = strdup(buf); 593 } else { 594 ts->base_type = type; 595 ts->type = type; 596 ts->indirect_reg = indirect_reg; 597 ts->mem_allocated = 1; 598 ts->mem_base = base_ts; 599 ts->mem_offset = offset; 600 ts->name = name; 601 } 602 return ts; 603 } 604 605 static TCGTemp *tcg_temp_new_internal(TCGType type, int temp_local) 606 { 607 TCGContext *s = tcg_ctx; 608 TCGTemp *ts; 609 int idx, k; 610 611 k = type + (temp_local ? TCG_TYPE_COUNT : 0); 612 idx = find_first_bit(s->free_temps[k].l, TCG_MAX_TEMPS); 613 if (idx < TCG_MAX_TEMPS) { 614 /* There is already an available temp with the right type. */ 615 clear_bit(idx, s->free_temps[k].l); 616 617 ts = &s->temps[idx]; 618 ts->temp_allocated = 1; 619 tcg_debug_assert(ts->base_type == type); 620 tcg_debug_assert(ts->temp_local == temp_local); 621 } else { 622 ts = tcg_temp_alloc(s); 623 if (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64) { 624 TCGTemp *ts2 = tcg_temp_alloc(s); 625 626 ts->base_type = type; 627 ts->type = TCG_TYPE_I32; 628 ts->temp_allocated = 1; 629 ts->temp_local = temp_local; 630 631 tcg_debug_assert(ts2 == ts + 1); 632 ts2->base_type = TCG_TYPE_I64; 633 ts2->type = TCG_TYPE_I32; 634 ts2->temp_allocated = 1; 635 ts2->temp_local = temp_local; 636 } else { 637 ts->base_type = type; 638 ts->type = type; 639 ts->temp_allocated = 1; 640 ts->temp_local = temp_local; 641 } 642 } 643 644 #if defined(CONFIG_DEBUG_TCG) 645 s->temps_in_use++; 646 #endif 647 return ts; 648 } 649 650 TCGv_i32 tcg_temp_new_internal_i32(int temp_local) 651 { 652 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, temp_local); 653 return temp_tcgv_i32(t); 654 } 655 656 TCGv_i64 tcg_temp_new_internal_i64(int temp_local) 657 { 658 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, temp_local); 659 return temp_tcgv_i64(t); 660 } 661 662 static void tcg_temp_free_internal(TCGTemp *ts) 663 { 664 TCGContext *s = tcg_ctx; 665 int k, idx; 666 667 #if defined(CONFIG_DEBUG_TCG) 668 s->temps_in_use--; 669 if (s->temps_in_use < 0) { 670 fprintf(stderr, "More temporaries freed than allocated!\n"); 671 } 672 #endif 673 674 tcg_debug_assert(ts->temp_global == 0); 675 tcg_debug_assert(ts->temp_allocated != 0); 676 ts->temp_allocated = 0; 677 678 idx = temp_idx(ts); 679 k = ts->base_type + (ts->temp_local ? TCG_TYPE_COUNT : 0); 680 set_bit(idx, s->free_temps[k].l); 681 } 682 683 void tcg_temp_free_i32(TCGv_i32 arg) 684 { 685 tcg_temp_free_internal(tcgv_i32_temp(arg)); 686 } 687 688 void tcg_temp_free_i64(TCGv_i64 arg) 689 { 690 tcg_temp_free_internal(tcgv_i64_temp(arg)); 691 } 692 693 TCGv_i32 tcg_const_i32(int32_t val) 694 { 695 TCGv_i32 t0; 696 t0 = tcg_temp_new_i32(); 697 tcg_gen_movi_i32(t0, val); 698 return t0; 699 } 700 701 TCGv_i64 tcg_const_i64(int64_t val) 702 { 703 TCGv_i64 t0; 704 t0 = tcg_temp_new_i64(); 705 tcg_gen_movi_i64(t0, val); 706 return t0; 707 } 708 709 TCGv_i32 tcg_const_local_i32(int32_t val) 710 { 711 TCGv_i32 t0; 712 t0 = tcg_temp_local_new_i32(); 713 tcg_gen_movi_i32(t0, val); 714 return t0; 715 } 716 717 TCGv_i64 tcg_const_local_i64(int64_t val) 718 { 719 TCGv_i64 t0; 720 t0 = tcg_temp_local_new_i64(); 721 tcg_gen_movi_i64(t0, val); 722 return t0; 723 } 724 725 #if defined(CONFIG_DEBUG_TCG) 726 void tcg_clear_temp_count(void) 727 { 728 TCGContext *s = tcg_ctx; 729 s->temps_in_use = 0; 730 } 731 732 int tcg_check_temp_count(void) 733 { 734 TCGContext *s = tcg_ctx; 735 if (s->temps_in_use) { 736 /* Clear the count so that we don't give another 737 * warning immediately next time around. 738 */ 739 s->temps_in_use = 0; 740 return 1; 741 } 742 return 0; 743 } 744 #endif 745 746 /* Return true if OP may appear in the opcode stream. 747 Test the runtime variable that controls each opcode. */ 748 bool tcg_op_supported(TCGOpcode op) 749 { 750 switch (op) { 751 case INDEX_op_discard: 752 case INDEX_op_set_label: 753 case INDEX_op_call: 754 case INDEX_op_br: 755 case INDEX_op_mb: 756 case INDEX_op_insn_start: 757 case INDEX_op_exit_tb: 758 case INDEX_op_goto_tb: 759 case INDEX_op_qemu_ld_i32: 760 case INDEX_op_qemu_st_i32: 761 case INDEX_op_qemu_ld_i64: 762 case INDEX_op_qemu_st_i64: 763 return true; 764 765 case INDEX_op_goto_ptr: 766 return TCG_TARGET_HAS_goto_ptr; 767 768 case INDEX_op_mov_i32: 769 case INDEX_op_movi_i32: 770 case INDEX_op_setcond_i32: 771 case INDEX_op_brcond_i32: 772 case INDEX_op_ld8u_i32: 773 case INDEX_op_ld8s_i32: 774 case INDEX_op_ld16u_i32: 775 case INDEX_op_ld16s_i32: 776 case INDEX_op_ld_i32: 777 case INDEX_op_st8_i32: 778 case INDEX_op_st16_i32: 779 case INDEX_op_st_i32: 780 case INDEX_op_add_i32: 781 case INDEX_op_sub_i32: 782 case INDEX_op_mul_i32: 783 case INDEX_op_and_i32: 784 case INDEX_op_or_i32: 785 case INDEX_op_xor_i32: 786 case INDEX_op_shl_i32: 787 case INDEX_op_shr_i32: 788 case INDEX_op_sar_i32: 789 return true; 790 791 case INDEX_op_movcond_i32: 792 return TCG_TARGET_HAS_movcond_i32; 793 case INDEX_op_div_i32: 794 case INDEX_op_divu_i32: 795 return TCG_TARGET_HAS_div_i32; 796 case INDEX_op_rem_i32: 797 case INDEX_op_remu_i32: 798 return TCG_TARGET_HAS_rem_i32; 799 case INDEX_op_div2_i32: 800 case INDEX_op_divu2_i32: 801 return TCG_TARGET_HAS_div2_i32; 802 case INDEX_op_rotl_i32: 803 case INDEX_op_rotr_i32: 804 return TCG_TARGET_HAS_rot_i32; 805 case INDEX_op_deposit_i32: 806 return TCG_TARGET_HAS_deposit_i32; 807 case INDEX_op_extract_i32: 808 return TCG_TARGET_HAS_extract_i32; 809 case INDEX_op_sextract_i32: 810 return TCG_TARGET_HAS_sextract_i32; 811 case INDEX_op_add2_i32: 812 return TCG_TARGET_HAS_add2_i32; 813 case INDEX_op_sub2_i32: 814 return TCG_TARGET_HAS_sub2_i32; 815 case INDEX_op_mulu2_i32: 816 return TCG_TARGET_HAS_mulu2_i32; 817 case INDEX_op_muls2_i32: 818 return TCG_TARGET_HAS_muls2_i32; 819 case INDEX_op_muluh_i32: 820 return TCG_TARGET_HAS_muluh_i32; 821 case INDEX_op_mulsh_i32: 822 return TCG_TARGET_HAS_mulsh_i32; 823 case INDEX_op_ext8s_i32: 824 return TCG_TARGET_HAS_ext8s_i32; 825 case INDEX_op_ext16s_i32: 826 return TCG_TARGET_HAS_ext16s_i32; 827 case INDEX_op_ext8u_i32: 828 return TCG_TARGET_HAS_ext8u_i32; 829 case INDEX_op_ext16u_i32: 830 return TCG_TARGET_HAS_ext16u_i32; 831 case INDEX_op_bswap16_i32: 832 return TCG_TARGET_HAS_bswap16_i32; 833 case INDEX_op_bswap32_i32: 834 return TCG_TARGET_HAS_bswap32_i32; 835 case INDEX_op_not_i32: 836 return TCG_TARGET_HAS_not_i32; 837 case INDEX_op_neg_i32: 838 return TCG_TARGET_HAS_neg_i32; 839 case INDEX_op_andc_i32: 840 return TCG_TARGET_HAS_andc_i32; 841 case INDEX_op_orc_i32: 842 return TCG_TARGET_HAS_orc_i32; 843 case INDEX_op_eqv_i32: 844 return TCG_TARGET_HAS_eqv_i32; 845 case INDEX_op_nand_i32: 846 return TCG_TARGET_HAS_nand_i32; 847 case INDEX_op_nor_i32: 848 return TCG_TARGET_HAS_nor_i32; 849 case INDEX_op_clz_i32: 850 return TCG_TARGET_HAS_clz_i32; 851 case INDEX_op_ctz_i32: 852 return TCG_TARGET_HAS_ctz_i32; 853 case INDEX_op_ctpop_i32: 854 return TCG_TARGET_HAS_ctpop_i32; 855 856 case INDEX_op_brcond2_i32: 857 case INDEX_op_setcond2_i32: 858 return TCG_TARGET_REG_BITS == 32; 859 860 case INDEX_op_mov_i64: 861 case INDEX_op_movi_i64: 862 case INDEX_op_setcond_i64: 863 case INDEX_op_brcond_i64: 864 case INDEX_op_ld8u_i64: 865 case INDEX_op_ld8s_i64: 866 case INDEX_op_ld16u_i64: 867 case INDEX_op_ld16s_i64: 868 case INDEX_op_ld32u_i64: 869 case INDEX_op_ld32s_i64: 870 case INDEX_op_ld_i64: 871 case INDEX_op_st8_i64: 872 case INDEX_op_st16_i64: 873 case INDEX_op_st32_i64: 874 case INDEX_op_st_i64: 875 case INDEX_op_add_i64: 876 case INDEX_op_sub_i64: 877 case INDEX_op_mul_i64: 878 case INDEX_op_and_i64: 879 case INDEX_op_or_i64: 880 case INDEX_op_xor_i64: 881 case INDEX_op_shl_i64: 882 case INDEX_op_shr_i64: 883 case INDEX_op_sar_i64: 884 case INDEX_op_ext_i32_i64: 885 case INDEX_op_extu_i32_i64: 886 return TCG_TARGET_REG_BITS == 64; 887 888 case INDEX_op_movcond_i64: 889 return TCG_TARGET_HAS_movcond_i64; 890 case INDEX_op_div_i64: 891 case INDEX_op_divu_i64: 892 return TCG_TARGET_HAS_div_i64; 893 case INDEX_op_rem_i64: 894 case INDEX_op_remu_i64: 895 return TCG_TARGET_HAS_rem_i64; 896 case INDEX_op_div2_i64: 897 case INDEX_op_divu2_i64: 898 return TCG_TARGET_HAS_div2_i64; 899 case INDEX_op_rotl_i64: 900 case INDEX_op_rotr_i64: 901 return TCG_TARGET_HAS_rot_i64; 902 case INDEX_op_deposit_i64: 903 return TCG_TARGET_HAS_deposit_i64; 904 case INDEX_op_extract_i64: 905 return TCG_TARGET_HAS_extract_i64; 906 case INDEX_op_sextract_i64: 907 return TCG_TARGET_HAS_sextract_i64; 908 case INDEX_op_extrl_i64_i32: 909 return TCG_TARGET_HAS_extrl_i64_i32; 910 case INDEX_op_extrh_i64_i32: 911 return TCG_TARGET_HAS_extrh_i64_i32; 912 case INDEX_op_ext8s_i64: 913 return TCG_TARGET_HAS_ext8s_i64; 914 case INDEX_op_ext16s_i64: 915 return TCG_TARGET_HAS_ext16s_i64; 916 case INDEX_op_ext32s_i64: 917 return TCG_TARGET_HAS_ext32s_i64; 918 case INDEX_op_ext8u_i64: 919 return TCG_TARGET_HAS_ext8u_i64; 920 case INDEX_op_ext16u_i64: 921 return TCG_TARGET_HAS_ext16u_i64; 922 case INDEX_op_ext32u_i64: 923 return TCG_TARGET_HAS_ext32u_i64; 924 case INDEX_op_bswap16_i64: 925 return TCG_TARGET_HAS_bswap16_i64; 926 case INDEX_op_bswap32_i64: 927 return TCG_TARGET_HAS_bswap32_i64; 928 case INDEX_op_bswap64_i64: 929 return TCG_TARGET_HAS_bswap64_i64; 930 case INDEX_op_not_i64: 931 return TCG_TARGET_HAS_not_i64; 932 case INDEX_op_neg_i64: 933 return TCG_TARGET_HAS_neg_i64; 934 case INDEX_op_andc_i64: 935 return TCG_TARGET_HAS_andc_i64; 936 case INDEX_op_orc_i64: 937 return TCG_TARGET_HAS_orc_i64; 938 case INDEX_op_eqv_i64: 939 return TCG_TARGET_HAS_eqv_i64; 940 case INDEX_op_nand_i64: 941 return TCG_TARGET_HAS_nand_i64; 942 case INDEX_op_nor_i64: 943 return TCG_TARGET_HAS_nor_i64; 944 case INDEX_op_clz_i64: 945 return TCG_TARGET_HAS_clz_i64; 946 case INDEX_op_ctz_i64: 947 return TCG_TARGET_HAS_ctz_i64; 948 case INDEX_op_ctpop_i64: 949 return TCG_TARGET_HAS_ctpop_i64; 950 case INDEX_op_add2_i64: 951 return TCG_TARGET_HAS_add2_i64; 952 case INDEX_op_sub2_i64: 953 return TCG_TARGET_HAS_sub2_i64; 954 case INDEX_op_mulu2_i64: 955 return TCG_TARGET_HAS_mulu2_i64; 956 case INDEX_op_muls2_i64: 957 return TCG_TARGET_HAS_muls2_i64; 958 case INDEX_op_muluh_i64: 959 return TCG_TARGET_HAS_muluh_i64; 960 case INDEX_op_mulsh_i64: 961 return TCG_TARGET_HAS_mulsh_i64; 962 963 case NB_OPS: 964 break; 965 } 966 g_assert_not_reached(); 967 } 968 969 /* Note: we convert the 64 bit args to 32 bit and do some alignment 970 and endian swap. Maybe it would be better to do the alignment 971 and endian swap in tcg_reg_alloc_call(). */ 972 void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) 973 { 974 TCGContext *s = tcg_ctx; 975 int i, real_args, nb_rets, pi; 976 unsigned sizemask, flags; 977 TCGHelperInfo *info; 978 TCGOp *op; 979 980 info = g_hash_table_lookup(helper_table, (gpointer)func); 981 flags = info->flags; 982 sizemask = info->sizemask; 983 984 #if defined(__sparc__) && !defined(__arch64__) \ 985 && !defined(CONFIG_TCG_INTERPRETER) 986 /* We have 64-bit values in one register, but need to pass as two 987 separate parameters. Split them. */ 988 int orig_sizemask = sizemask; 989 int orig_nargs = nargs; 990 TCGv_i64 retl, reth; 991 TCGTemp *split_args[MAX_OPC_PARAM]; 992 993 TCGV_UNUSED_I64(retl); 994 TCGV_UNUSED_I64(reth); 995 if (sizemask != 0) { 996 for (i = real_args = 0; i < nargs; ++i) { 997 int is_64bit = sizemask & (1 << (i+1)*2); 998 if (is_64bit) { 999 TCGv_i64 orig = temp_tcgv_i64(args[i]); 1000 TCGv_i32 h = tcg_temp_new_i32(); 1001 TCGv_i32 l = tcg_temp_new_i32(); 1002 tcg_gen_extr_i64_i32(l, h, orig); 1003 split_args[real_args++] = tcgv_i32_temp(h); 1004 split_args[real_args++] = tcgv_i32_temp(l); 1005 } else { 1006 split_args[real_args++] = args[i]; 1007 } 1008 } 1009 nargs = real_args; 1010 args = split_args; 1011 sizemask = 0; 1012 } 1013 #elif defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS == 64 1014 for (i = 0; i < nargs; ++i) { 1015 int is_64bit = sizemask & (1 << (i+1)*2); 1016 int is_signed = sizemask & (2 << (i+1)*2); 1017 if (!is_64bit) { 1018 TCGv_i64 temp = tcg_temp_new_i64(); 1019 TCGv_i64 orig = temp_tcgv_i64(args[i]); 1020 if (is_signed) { 1021 tcg_gen_ext32s_i64(temp, orig); 1022 } else { 1023 tcg_gen_ext32u_i64(temp, orig); 1024 } 1025 args[i] = tcgv_i64_temp(temp); 1026 } 1027 } 1028 #endif /* TCG_TARGET_EXTEND_ARGS */ 1029 1030 i = s->gen_next_op_idx; 1031 tcg_debug_assert(i < OPC_BUF_SIZE); 1032 s->gen_op_buf[0].prev = i; 1033 s->gen_next_op_idx = i + 1; 1034 op = &s->gen_op_buf[i]; 1035 1036 /* Set links for sequential allocation during translation. */ 1037 memset(op, 0, offsetof(TCGOp, args)); 1038 op->opc = INDEX_op_call; 1039 op->prev = i - 1; 1040 op->next = i + 1; 1041 1042 pi = 0; 1043 if (ret != NULL) { 1044 #if defined(__sparc__) && !defined(__arch64__) \ 1045 && !defined(CONFIG_TCG_INTERPRETER) 1046 if (orig_sizemask & 1) { 1047 /* The 32-bit ABI is going to return the 64-bit value in 1048 the %o0/%o1 register pair. Prepare for this by using 1049 two return temporaries, and reassemble below. */ 1050 retl = tcg_temp_new_i64(); 1051 reth = tcg_temp_new_i64(); 1052 op->args[pi++] = tcgv_i64_arg(reth); 1053 op->args[pi++] = tcgv_i64_arg(retl); 1054 nb_rets = 2; 1055 } else { 1056 op->args[pi++] = temp_arg(ret); 1057 nb_rets = 1; 1058 } 1059 #else 1060 if (TCG_TARGET_REG_BITS < 64 && (sizemask & 1)) { 1061 #ifdef HOST_WORDS_BIGENDIAN 1062 op->args[pi++] = temp_arg(ret + 1); 1063 op->args[pi++] = temp_arg(ret); 1064 #else 1065 op->args[pi++] = temp_arg(ret); 1066 op->args[pi++] = temp_arg(ret + 1); 1067 #endif 1068 nb_rets = 2; 1069 } else { 1070 op->args[pi++] = temp_arg(ret); 1071 nb_rets = 1; 1072 } 1073 #endif 1074 } else { 1075 nb_rets = 0; 1076 } 1077 op->callo = nb_rets; 1078 1079 real_args = 0; 1080 for (i = 0; i < nargs; i++) { 1081 int is_64bit = sizemask & (1 << (i+1)*2); 1082 if (TCG_TARGET_REG_BITS < 64 && is_64bit) { 1083 #ifdef TCG_TARGET_CALL_ALIGN_ARGS 1084 /* some targets want aligned 64 bit args */ 1085 if (real_args & 1) { 1086 op->args[pi++] = TCG_CALL_DUMMY_ARG; 1087 real_args++; 1088 } 1089 #endif 1090 /* If stack grows up, then we will be placing successive 1091 arguments at lower addresses, which means we need to 1092 reverse the order compared to how we would normally 1093 treat either big or little-endian. For those arguments 1094 that will wind up in registers, this still works for 1095 HPPA (the only current STACK_GROWSUP target) since the 1096 argument registers are *also* allocated in decreasing 1097 order. If another such target is added, this logic may 1098 have to get more complicated to differentiate between 1099 stack arguments and register arguments. */ 1100 #if defined(HOST_WORDS_BIGENDIAN) != defined(TCG_TARGET_STACK_GROWSUP) 1101 op->args[pi++] = temp_arg(args[i] + 1); 1102 op->args[pi++] = temp_arg(args[i]); 1103 #else 1104 op->args[pi++] = temp_arg(args[i]); 1105 op->args[pi++] = temp_arg(args[i] + 1); 1106 #endif 1107 real_args += 2; 1108 continue; 1109 } 1110 1111 op->args[pi++] = temp_arg(args[i]); 1112 real_args++; 1113 } 1114 op->args[pi++] = (uintptr_t)func; 1115 op->args[pi++] = flags; 1116 op->calli = real_args; 1117 1118 /* Make sure the fields didn't overflow. */ 1119 tcg_debug_assert(op->calli == real_args); 1120 tcg_debug_assert(pi <= ARRAY_SIZE(op->args)); 1121 1122 #if defined(__sparc__) && !defined(__arch64__) \ 1123 && !defined(CONFIG_TCG_INTERPRETER) 1124 /* Free all of the parts we allocated above. */ 1125 for (i = real_args = 0; i < orig_nargs; ++i) { 1126 int is_64bit = orig_sizemask & (1 << (i+1)*2); 1127 if (is_64bit) { 1128 tcg_temp_free_internal(args[real_args++]); 1129 tcg_temp_free_internal(args[real_args++]); 1130 } else { 1131 real_args++; 1132 } 1133 } 1134 if (orig_sizemask & 1) { 1135 /* The 32-bit ABI returned two 32-bit pieces. Re-assemble them. 1136 Note that describing these as TCGv_i64 eliminates an unnecessary 1137 zero-extension that tcg_gen_concat_i32_i64 would create. */ 1138 tcg_gen_concat32_i64(temp_tcgv_i64(ret), retl, reth); 1139 tcg_temp_free_i64(retl); 1140 tcg_temp_free_i64(reth); 1141 } 1142 #elif defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS == 64 1143 for (i = 0; i < nargs; ++i) { 1144 int is_64bit = sizemask & (1 << (i+1)*2); 1145 if (!is_64bit) { 1146 tcg_temp_free_internal(args[i]); 1147 } 1148 } 1149 #endif /* TCG_TARGET_EXTEND_ARGS */ 1150 } 1151 1152 static void tcg_reg_alloc_start(TCGContext *s) 1153 { 1154 int i, n; 1155 TCGTemp *ts; 1156 1157 for (i = 0, n = s->nb_globals; i < n; i++) { 1158 ts = &s->temps[i]; 1159 ts->val_type = (ts->fixed_reg ? TEMP_VAL_REG : TEMP_VAL_MEM); 1160 } 1161 for (n = s->nb_temps; i < n; i++) { 1162 ts = &s->temps[i]; 1163 ts->val_type = (ts->temp_local ? TEMP_VAL_MEM : TEMP_VAL_DEAD); 1164 ts->mem_allocated = 0; 1165 ts->fixed_reg = 0; 1166 } 1167 1168 memset(s->reg_to_temp, 0, sizeof(s->reg_to_temp)); 1169 } 1170 1171 static char *tcg_get_arg_str_ptr(TCGContext *s, char *buf, int buf_size, 1172 TCGTemp *ts) 1173 { 1174 int idx = temp_idx(ts); 1175 1176 if (ts->temp_global) { 1177 pstrcpy(buf, buf_size, ts->name); 1178 } else if (ts->temp_local) { 1179 snprintf(buf, buf_size, "loc%d", idx - s->nb_globals); 1180 } else { 1181 snprintf(buf, buf_size, "tmp%d", idx - s->nb_globals); 1182 } 1183 return buf; 1184 } 1185 1186 static char *tcg_get_arg_str(TCGContext *s, char *buf, 1187 int buf_size, TCGArg arg) 1188 { 1189 return tcg_get_arg_str_ptr(s, buf, buf_size, arg_temp(arg)); 1190 } 1191 1192 /* Find helper name. */ 1193 static inline const char *tcg_find_helper(TCGContext *s, uintptr_t val) 1194 { 1195 const char *ret = NULL; 1196 if (helper_table) { 1197 TCGHelperInfo *info = g_hash_table_lookup(helper_table, (gpointer)val); 1198 if (info) { 1199 ret = info->name; 1200 } 1201 } 1202 return ret; 1203 } 1204 1205 static const char * const cond_name[] = 1206 { 1207 [TCG_COND_NEVER] = "never", 1208 [TCG_COND_ALWAYS] = "always", 1209 [TCG_COND_EQ] = "eq", 1210 [TCG_COND_NE] = "ne", 1211 [TCG_COND_LT] = "lt", 1212 [TCG_COND_GE] = "ge", 1213 [TCG_COND_LE] = "le", 1214 [TCG_COND_GT] = "gt", 1215 [TCG_COND_LTU] = "ltu", 1216 [TCG_COND_GEU] = "geu", 1217 [TCG_COND_LEU] = "leu", 1218 [TCG_COND_GTU] = "gtu" 1219 }; 1220 1221 static const char * const ldst_name[] = 1222 { 1223 [MO_UB] = "ub", 1224 [MO_SB] = "sb", 1225 [MO_LEUW] = "leuw", 1226 [MO_LESW] = "lesw", 1227 [MO_LEUL] = "leul", 1228 [MO_LESL] = "lesl", 1229 [MO_LEQ] = "leq", 1230 [MO_BEUW] = "beuw", 1231 [MO_BESW] = "besw", 1232 [MO_BEUL] = "beul", 1233 [MO_BESL] = "besl", 1234 [MO_BEQ] = "beq", 1235 }; 1236 1237 static const char * const alignment_name[(MO_AMASK >> MO_ASHIFT) + 1] = { 1238 #ifdef ALIGNED_ONLY 1239 [MO_UNALN >> MO_ASHIFT] = "un+", 1240 [MO_ALIGN >> MO_ASHIFT] = "", 1241 #else 1242 [MO_UNALN >> MO_ASHIFT] = "", 1243 [MO_ALIGN >> MO_ASHIFT] = "al+", 1244 #endif 1245 [MO_ALIGN_2 >> MO_ASHIFT] = "al2+", 1246 [MO_ALIGN_4 >> MO_ASHIFT] = "al4+", 1247 [MO_ALIGN_8 >> MO_ASHIFT] = "al8+", 1248 [MO_ALIGN_16 >> MO_ASHIFT] = "al16+", 1249 [MO_ALIGN_32 >> MO_ASHIFT] = "al32+", 1250 [MO_ALIGN_64 >> MO_ASHIFT] = "al64+", 1251 }; 1252 1253 void tcg_dump_ops(TCGContext *s) 1254 { 1255 char buf[128]; 1256 TCGOp *op; 1257 int oi; 1258 1259 for (oi = s->gen_op_buf[0].next; oi != 0; oi = op->next) { 1260 int i, k, nb_oargs, nb_iargs, nb_cargs; 1261 const TCGOpDef *def; 1262 TCGOpcode c; 1263 int col = 0; 1264 1265 op = &s->gen_op_buf[oi]; 1266 c = op->opc; 1267 def = &tcg_op_defs[c]; 1268 1269 if (c == INDEX_op_insn_start) { 1270 col += qemu_log("%s ----", oi != s->gen_op_buf[0].next ? "\n" : ""); 1271 1272 for (i = 0; i < TARGET_INSN_START_WORDS; ++i) { 1273 target_ulong a; 1274 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS 1275 a = deposit64(op->args[i * 2], 32, 32, op->args[i * 2 + 1]); 1276 #else 1277 a = op->args[i]; 1278 #endif 1279 col += qemu_log(" " TARGET_FMT_lx, a); 1280 } 1281 } else if (c == INDEX_op_call) { 1282 /* variable number of arguments */ 1283 nb_oargs = op->callo; 1284 nb_iargs = op->calli; 1285 nb_cargs = def->nb_cargs; 1286 1287 /* function name, flags, out args */ 1288 col += qemu_log(" %s %s,$0x%" TCG_PRIlx ",$%d", def->name, 1289 tcg_find_helper(s, op->args[nb_oargs + nb_iargs]), 1290 op->args[nb_oargs + nb_iargs + 1], nb_oargs); 1291 for (i = 0; i < nb_oargs; i++) { 1292 col += qemu_log(",%s", tcg_get_arg_str(s, buf, sizeof(buf), 1293 op->args[i])); 1294 } 1295 for (i = 0; i < nb_iargs; i++) { 1296 TCGArg arg = op->args[nb_oargs + i]; 1297 const char *t = "<dummy>"; 1298 if (arg != TCG_CALL_DUMMY_ARG) { 1299 t = tcg_get_arg_str(s, buf, sizeof(buf), arg); 1300 } 1301 col += qemu_log(",%s", t); 1302 } 1303 } else { 1304 col += qemu_log(" %s ", def->name); 1305 1306 nb_oargs = def->nb_oargs; 1307 nb_iargs = def->nb_iargs; 1308 nb_cargs = def->nb_cargs; 1309 1310 k = 0; 1311 for (i = 0; i < nb_oargs; i++) { 1312 if (k != 0) { 1313 col += qemu_log(","); 1314 } 1315 col += qemu_log("%s", tcg_get_arg_str(s, buf, sizeof(buf), 1316 op->args[k++])); 1317 } 1318 for (i = 0; i < nb_iargs; i++) { 1319 if (k != 0) { 1320 col += qemu_log(","); 1321 } 1322 col += qemu_log("%s", tcg_get_arg_str(s, buf, sizeof(buf), 1323 op->args[k++])); 1324 } 1325 switch (c) { 1326 case INDEX_op_brcond_i32: 1327 case INDEX_op_setcond_i32: 1328 case INDEX_op_movcond_i32: 1329 case INDEX_op_brcond2_i32: 1330 case INDEX_op_setcond2_i32: 1331 case INDEX_op_brcond_i64: 1332 case INDEX_op_setcond_i64: 1333 case INDEX_op_movcond_i64: 1334 if (op->args[k] < ARRAY_SIZE(cond_name) 1335 && cond_name[op->args[k]]) { 1336 col += qemu_log(",%s", cond_name[op->args[k++]]); 1337 } else { 1338 col += qemu_log(",$0x%" TCG_PRIlx, op->args[k++]); 1339 } 1340 i = 1; 1341 break; 1342 case INDEX_op_qemu_ld_i32: 1343 case INDEX_op_qemu_st_i32: 1344 case INDEX_op_qemu_ld_i64: 1345 case INDEX_op_qemu_st_i64: 1346 { 1347 TCGMemOpIdx oi = op->args[k++]; 1348 TCGMemOp op = get_memop(oi); 1349 unsigned ix = get_mmuidx(oi); 1350 1351 if (op & ~(MO_AMASK | MO_BSWAP | MO_SSIZE)) { 1352 col += qemu_log(",$0x%x,%u", op, ix); 1353 } else { 1354 const char *s_al, *s_op; 1355 s_al = alignment_name[(op & MO_AMASK) >> MO_ASHIFT]; 1356 s_op = ldst_name[op & (MO_BSWAP | MO_SSIZE)]; 1357 col += qemu_log(",%s%s,%u", s_al, s_op, ix); 1358 } 1359 i = 1; 1360 } 1361 break; 1362 default: 1363 i = 0; 1364 break; 1365 } 1366 switch (c) { 1367 case INDEX_op_set_label: 1368 case INDEX_op_br: 1369 case INDEX_op_brcond_i32: 1370 case INDEX_op_brcond_i64: 1371 case INDEX_op_brcond2_i32: 1372 col += qemu_log("%s$L%d", k ? "," : "", 1373 arg_label(op->args[k])->id); 1374 i++, k++; 1375 break; 1376 default: 1377 break; 1378 } 1379 for (; i < nb_cargs; i++, k++) { 1380 col += qemu_log("%s$0x%" TCG_PRIlx, k ? "," : "", op->args[k]); 1381 } 1382 } 1383 if (op->life) { 1384 unsigned life = op->life; 1385 1386 for (; col < 48; ++col) { 1387 putc(' ', qemu_logfile); 1388 } 1389 1390 if (life & (SYNC_ARG * 3)) { 1391 qemu_log(" sync:"); 1392 for (i = 0; i < 2; ++i) { 1393 if (life & (SYNC_ARG << i)) { 1394 qemu_log(" %d", i); 1395 } 1396 } 1397 } 1398 life /= DEAD_ARG; 1399 if (life) { 1400 qemu_log(" dead:"); 1401 for (i = 0; life; ++i, life >>= 1) { 1402 if (life & 1) { 1403 qemu_log(" %d", i); 1404 } 1405 } 1406 } 1407 } 1408 qemu_log("\n"); 1409 } 1410 } 1411 1412 /* we give more priority to constraints with less registers */ 1413 static int get_constraint_priority(const TCGOpDef *def, int k) 1414 { 1415 const TCGArgConstraint *arg_ct; 1416 1417 int i, n; 1418 arg_ct = &def->args_ct[k]; 1419 if (arg_ct->ct & TCG_CT_ALIAS) { 1420 /* an alias is equivalent to a single register */ 1421 n = 1; 1422 } else { 1423 if (!(arg_ct->ct & TCG_CT_REG)) 1424 return 0; 1425 n = 0; 1426 for(i = 0; i < TCG_TARGET_NB_REGS; i++) { 1427 if (tcg_regset_test_reg(arg_ct->u.regs, i)) 1428 n++; 1429 } 1430 } 1431 return TCG_TARGET_NB_REGS - n + 1; 1432 } 1433 1434 /* sort from highest priority to lowest */ 1435 static void sort_constraints(TCGOpDef *def, int start, int n) 1436 { 1437 int i, j, p1, p2, tmp; 1438 1439 for(i = 0; i < n; i++) 1440 def->sorted_args[start + i] = start + i; 1441 if (n <= 1) 1442 return; 1443 for(i = 0; i < n - 1; i++) { 1444 for(j = i + 1; j < n; j++) { 1445 p1 = get_constraint_priority(def, def->sorted_args[start + i]); 1446 p2 = get_constraint_priority(def, def->sorted_args[start + j]); 1447 if (p1 < p2) { 1448 tmp = def->sorted_args[start + i]; 1449 def->sorted_args[start + i] = def->sorted_args[start + j]; 1450 def->sorted_args[start + j] = tmp; 1451 } 1452 } 1453 } 1454 } 1455 1456 static void process_op_defs(TCGContext *s) 1457 { 1458 TCGOpcode op; 1459 1460 for (op = 0; op < NB_OPS; op++) { 1461 TCGOpDef *def = &tcg_op_defs[op]; 1462 const TCGTargetOpDef *tdefs; 1463 TCGType type; 1464 int i, nb_args; 1465 1466 if (def->flags & TCG_OPF_NOT_PRESENT) { 1467 continue; 1468 } 1469 1470 nb_args = def->nb_iargs + def->nb_oargs; 1471 if (nb_args == 0) { 1472 continue; 1473 } 1474 1475 tdefs = tcg_target_op_def(op); 1476 /* Missing TCGTargetOpDef entry. */ 1477 tcg_debug_assert(tdefs != NULL); 1478 1479 type = (def->flags & TCG_OPF_64BIT ? TCG_TYPE_I64 : TCG_TYPE_I32); 1480 for (i = 0; i < nb_args; i++) { 1481 const char *ct_str = tdefs->args_ct_str[i]; 1482 /* Incomplete TCGTargetOpDef entry. */ 1483 tcg_debug_assert(ct_str != NULL); 1484 1485 def->args_ct[i].u.regs = 0; 1486 def->args_ct[i].ct = 0; 1487 while (*ct_str != '\0') { 1488 switch(*ct_str) { 1489 case '0' ... '9': 1490 { 1491 int oarg = *ct_str - '0'; 1492 tcg_debug_assert(ct_str == tdefs->args_ct_str[i]); 1493 tcg_debug_assert(oarg < def->nb_oargs); 1494 tcg_debug_assert(def->args_ct[oarg].ct & TCG_CT_REG); 1495 /* TCG_CT_ALIAS is for the output arguments. 1496 The input is tagged with TCG_CT_IALIAS. */ 1497 def->args_ct[i] = def->args_ct[oarg]; 1498 def->args_ct[oarg].ct |= TCG_CT_ALIAS; 1499 def->args_ct[oarg].alias_index = i; 1500 def->args_ct[i].ct |= TCG_CT_IALIAS; 1501 def->args_ct[i].alias_index = oarg; 1502 } 1503 ct_str++; 1504 break; 1505 case '&': 1506 def->args_ct[i].ct |= TCG_CT_NEWREG; 1507 ct_str++; 1508 break; 1509 case 'i': 1510 def->args_ct[i].ct |= TCG_CT_CONST; 1511 ct_str++; 1512 break; 1513 default: 1514 ct_str = target_parse_constraint(&def->args_ct[i], 1515 ct_str, type); 1516 /* Typo in TCGTargetOpDef constraint. */ 1517 tcg_debug_assert(ct_str != NULL); 1518 } 1519 } 1520 } 1521 1522 /* TCGTargetOpDef entry with too much information? */ 1523 tcg_debug_assert(i == TCG_MAX_OP_ARGS || tdefs->args_ct_str[i] == NULL); 1524 1525 /* sort the constraints (XXX: this is just an heuristic) */ 1526 sort_constraints(def, 0, def->nb_oargs); 1527 sort_constraints(def, def->nb_oargs, def->nb_iargs); 1528 } 1529 } 1530 1531 void tcg_op_remove(TCGContext *s, TCGOp *op) 1532 { 1533 int next = op->next; 1534 int prev = op->prev; 1535 1536 /* We should never attempt to remove the list terminator. */ 1537 tcg_debug_assert(op != &s->gen_op_buf[0]); 1538 1539 s->gen_op_buf[next].prev = prev; 1540 s->gen_op_buf[prev].next = next; 1541 1542 memset(op, 0, sizeof(*op)); 1543 1544 #ifdef CONFIG_PROFILER 1545 s->del_op_count++; 1546 #endif 1547 } 1548 1549 TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *old_op, 1550 TCGOpcode opc, int nargs) 1551 { 1552 int oi = s->gen_next_op_idx; 1553 int prev = old_op->prev; 1554 int next = old_op - s->gen_op_buf; 1555 TCGOp *new_op; 1556 1557 tcg_debug_assert(oi < OPC_BUF_SIZE); 1558 s->gen_next_op_idx = oi + 1; 1559 1560 new_op = &s->gen_op_buf[oi]; 1561 *new_op = (TCGOp){ 1562 .opc = opc, 1563 .prev = prev, 1564 .next = next 1565 }; 1566 s->gen_op_buf[prev].next = oi; 1567 old_op->prev = oi; 1568 1569 return new_op; 1570 } 1571 1572 TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *old_op, 1573 TCGOpcode opc, int nargs) 1574 { 1575 int oi = s->gen_next_op_idx; 1576 int prev = old_op - s->gen_op_buf; 1577 int next = old_op->next; 1578 TCGOp *new_op; 1579 1580 tcg_debug_assert(oi < OPC_BUF_SIZE); 1581 s->gen_next_op_idx = oi + 1; 1582 1583 new_op = &s->gen_op_buf[oi]; 1584 *new_op = (TCGOp){ 1585 .opc = opc, 1586 .prev = prev, 1587 .next = next 1588 }; 1589 s->gen_op_buf[next].prev = oi; 1590 old_op->next = oi; 1591 1592 return new_op; 1593 } 1594 1595 #define TS_DEAD 1 1596 #define TS_MEM 2 1597 1598 #define IS_DEAD_ARG(n) (arg_life & (DEAD_ARG << (n))) 1599 #define NEED_SYNC_ARG(n) (arg_life & (SYNC_ARG << (n))) 1600 1601 /* liveness analysis: end of function: all temps are dead, and globals 1602 should be in memory. */ 1603 static void tcg_la_func_end(TCGContext *s) 1604 { 1605 int ng = s->nb_globals; 1606 int nt = s->nb_temps; 1607 int i; 1608 1609 for (i = 0; i < ng; ++i) { 1610 s->temps[i].state = TS_DEAD | TS_MEM; 1611 } 1612 for (i = ng; i < nt; ++i) { 1613 s->temps[i].state = TS_DEAD; 1614 } 1615 } 1616 1617 /* liveness analysis: end of basic block: all temps are dead, globals 1618 and local temps should be in memory. */ 1619 static void tcg_la_bb_end(TCGContext *s) 1620 { 1621 int ng = s->nb_globals; 1622 int nt = s->nb_temps; 1623 int i; 1624 1625 for (i = 0; i < ng; ++i) { 1626 s->temps[i].state = TS_DEAD | TS_MEM; 1627 } 1628 for (i = ng; i < nt; ++i) { 1629 s->temps[i].state = (s->temps[i].temp_local 1630 ? TS_DEAD | TS_MEM 1631 : TS_DEAD); 1632 } 1633 } 1634 1635 /* Liveness analysis : update the opc_arg_life array to tell if a 1636 given input arguments is dead. Instructions updating dead 1637 temporaries are removed. */ 1638 static void liveness_pass_1(TCGContext *s) 1639 { 1640 int nb_globals = s->nb_globals; 1641 int oi, oi_prev; 1642 1643 tcg_la_func_end(s); 1644 1645 for (oi = s->gen_op_buf[0].prev; oi != 0; oi = oi_prev) { 1646 int i, nb_iargs, nb_oargs; 1647 TCGOpcode opc_new, opc_new2; 1648 bool have_opc_new2; 1649 TCGLifeData arg_life = 0; 1650 TCGTemp *arg_ts; 1651 1652 TCGOp * const op = &s->gen_op_buf[oi]; 1653 TCGOpcode opc = op->opc; 1654 const TCGOpDef *def = &tcg_op_defs[opc]; 1655 1656 oi_prev = op->prev; 1657 1658 switch (opc) { 1659 case INDEX_op_call: 1660 { 1661 int call_flags; 1662 1663 nb_oargs = op->callo; 1664 nb_iargs = op->calli; 1665 call_flags = op->args[nb_oargs + nb_iargs + 1]; 1666 1667 /* pure functions can be removed if their result is unused */ 1668 if (call_flags & TCG_CALL_NO_SIDE_EFFECTS) { 1669 for (i = 0; i < nb_oargs; i++) { 1670 arg_ts = arg_temp(op->args[i]); 1671 if (arg_ts->state != TS_DEAD) { 1672 goto do_not_remove_call; 1673 } 1674 } 1675 goto do_remove; 1676 } else { 1677 do_not_remove_call: 1678 1679 /* output args are dead */ 1680 for (i = 0; i < nb_oargs; i++) { 1681 arg_ts = arg_temp(op->args[i]); 1682 if (arg_ts->state & TS_DEAD) { 1683 arg_life |= DEAD_ARG << i; 1684 } 1685 if (arg_ts->state & TS_MEM) { 1686 arg_life |= SYNC_ARG << i; 1687 } 1688 arg_ts->state = TS_DEAD; 1689 } 1690 1691 if (!(call_flags & (TCG_CALL_NO_WRITE_GLOBALS | 1692 TCG_CALL_NO_READ_GLOBALS))) { 1693 /* globals should go back to memory */ 1694 for (i = 0; i < nb_globals; i++) { 1695 s->temps[i].state = TS_DEAD | TS_MEM; 1696 } 1697 } else if (!(call_flags & TCG_CALL_NO_READ_GLOBALS)) { 1698 /* globals should be synced to memory */ 1699 for (i = 0; i < nb_globals; i++) { 1700 s->temps[i].state |= TS_MEM; 1701 } 1702 } 1703 1704 /* record arguments that die in this helper */ 1705 for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) { 1706 arg_ts = arg_temp(op->args[i]); 1707 if (arg_ts && arg_ts->state & TS_DEAD) { 1708 arg_life |= DEAD_ARG << i; 1709 } 1710 } 1711 /* input arguments are live for preceding opcodes */ 1712 for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) { 1713 arg_ts = arg_temp(op->args[i]); 1714 if (arg_ts) { 1715 arg_ts->state &= ~TS_DEAD; 1716 } 1717 } 1718 } 1719 } 1720 break; 1721 case INDEX_op_insn_start: 1722 break; 1723 case INDEX_op_discard: 1724 /* mark the temporary as dead */ 1725 arg_temp(op->args[0])->state = TS_DEAD; 1726 break; 1727 1728 case INDEX_op_add2_i32: 1729 opc_new = INDEX_op_add_i32; 1730 goto do_addsub2; 1731 case INDEX_op_sub2_i32: 1732 opc_new = INDEX_op_sub_i32; 1733 goto do_addsub2; 1734 case INDEX_op_add2_i64: 1735 opc_new = INDEX_op_add_i64; 1736 goto do_addsub2; 1737 case INDEX_op_sub2_i64: 1738 opc_new = INDEX_op_sub_i64; 1739 do_addsub2: 1740 nb_iargs = 4; 1741 nb_oargs = 2; 1742 /* Test if the high part of the operation is dead, but not 1743 the low part. The result can be optimized to a simple 1744 add or sub. This happens often for x86_64 guest when the 1745 cpu mode is set to 32 bit. */ 1746 if (arg_temp(op->args[1])->state == TS_DEAD) { 1747 if (arg_temp(op->args[0])->state == TS_DEAD) { 1748 goto do_remove; 1749 } 1750 /* Replace the opcode and adjust the args in place, 1751 leaving 3 unused args at the end. */ 1752 op->opc = opc = opc_new; 1753 op->args[1] = op->args[2]; 1754 op->args[2] = op->args[4]; 1755 /* Fall through and mark the single-word operation live. */ 1756 nb_iargs = 2; 1757 nb_oargs = 1; 1758 } 1759 goto do_not_remove; 1760 1761 case INDEX_op_mulu2_i32: 1762 opc_new = INDEX_op_mul_i32; 1763 opc_new2 = INDEX_op_muluh_i32; 1764 have_opc_new2 = TCG_TARGET_HAS_muluh_i32; 1765 goto do_mul2; 1766 case INDEX_op_muls2_i32: 1767 opc_new = INDEX_op_mul_i32; 1768 opc_new2 = INDEX_op_mulsh_i32; 1769 have_opc_new2 = TCG_TARGET_HAS_mulsh_i32; 1770 goto do_mul2; 1771 case INDEX_op_mulu2_i64: 1772 opc_new = INDEX_op_mul_i64; 1773 opc_new2 = INDEX_op_muluh_i64; 1774 have_opc_new2 = TCG_TARGET_HAS_muluh_i64; 1775 goto do_mul2; 1776 case INDEX_op_muls2_i64: 1777 opc_new = INDEX_op_mul_i64; 1778 opc_new2 = INDEX_op_mulsh_i64; 1779 have_opc_new2 = TCG_TARGET_HAS_mulsh_i64; 1780 goto do_mul2; 1781 do_mul2: 1782 nb_iargs = 2; 1783 nb_oargs = 2; 1784 if (arg_temp(op->args[1])->state == TS_DEAD) { 1785 if (arg_temp(op->args[0])->state == TS_DEAD) { 1786 /* Both parts of the operation are dead. */ 1787 goto do_remove; 1788 } 1789 /* The high part of the operation is dead; generate the low. */ 1790 op->opc = opc = opc_new; 1791 op->args[1] = op->args[2]; 1792 op->args[2] = op->args[3]; 1793 } else if (arg_temp(op->args[0])->state == TS_DEAD && have_opc_new2) { 1794 /* The low part of the operation is dead; generate the high. */ 1795 op->opc = opc = opc_new2; 1796 op->args[0] = op->args[1]; 1797 op->args[1] = op->args[2]; 1798 op->args[2] = op->args[3]; 1799 } else { 1800 goto do_not_remove; 1801 } 1802 /* Mark the single-word operation live. */ 1803 nb_oargs = 1; 1804 goto do_not_remove; 1805 1806 default: 1807 /* XXX: optimize by hardcoding common cases (e.g. triadic ops) */ 1808 nb_iargs = def->nb_iargs; 1809 nb_oargs = def->nb_oargs; 1810 1811 /* Test if the operation can be removed because all 1812 its outputs are dead. We assume that nb_oargs == 0 1813 implies side effects */ 1814 if (!(def->flags & TCG_OPF_SIDE_EFFECTS) && nb_oargs != 0) { 1815 for (i = 0; i < nb_oargs; i++) { 1816 if (arg_temp(op->args[i])->state != TS_DEAD) { 1817 goto do_not_remove; 1818 } 1819 } 1820 do_remove: 1821 tcg_op_remove(s, op); 1822 } else { 1823 do_not_remove: 1824 /* output args are dead */ 1825 for (i = 0; i < nb_oargs; i++) { 1826 arg_ts = arg_temp(op->args[i]); 1827 if (arg_ts->state & TS_DEAD) { 1828 arg_life |= DEAD_ARG << i; 1829 } 1830 if (arg_ts->state & TS_MEM) { 1831 arg_life |= SYNC_ARG << i; 1832 } 1833 arg_ts->state = TS_DEAD; 1834 } 1835 1836 /* if end of basic block, update */ 1837 if (def->flags & TCG_OPF_BB_END) { 1838 tcg_la_bb_end(s); 1839 } else if (def->flags & TCG_OPF_SIDE_EFFECTS) { 1840 /* globals should be synced to memory */ 1841 for (i = 0; i < nb_globals; i++) { 1842 s->temps[i].state |= TS_MEM; 1843 } 1844 } 1845 1846 /* record arguments that die in this opcode */ 1847 for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) { 1848 arg_ts = arg_temp(op->args[i]); 1849 if (arg_ts->state & TS_DEAD) { 1850 arg_life |= DEAD_ARG << i; 1851 } 1852 } 1853 /* input arguments are live for preceding opcodes */ 1854 for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) { 1855 arg_temp(op->args[i])->state &= ~TS_DEAD; 1856 } 1857 } 1858 break; 1859 } 1860 op->life = arg_life; 1861 } 1862 } 1863 1864 /* Liveness analysis: Convert indirect regs to direct temporaries. */ 1865 static bool liveness_pass_2(TCGContext *s) 1866 { 1867 int nb_globals = s->nb_globals; 1868 int nb_temps, i, oi, oi_next; 1869 bool changes = false; 1870 1871 /* Create a temporary for each indirect global. */ 1872 for (i = 0; i < nb_globals; ++i) { 1873 TCGTemp *its = &s->temps[i]; 1874 if (its->indirect_reg) { 1875 TCGTemp *dts = tcg_temp_alloc(s); 1876 dts->type = its->type; 1877 dts->base_type = its->base_type; 1878 its->state_ptr = dts; 1879 } else { 1880 its->state_ptr = NULL; 1881 } 1882 /* All globals begin dead. */ 1883 its->state = TS_DEAD; 1884 } 1885 for (nb_temps = s->nb_temps; i < nb_temps; ++i) { 1886 TCGTemp *its = &s->temps[i]; 1887 its->state_ptr = NULL; 1888 its->state = TS_DEAD; 1889 } 1890 1891 for (oi = s->gen_op_buf[0].next; oi != 0; oi = oi_next) { 1892 TCGOp *op = &s->gen_op_buf[oi]; 1893 TCGOpcode opc = op->opc; 1894 const TCGOpDef *def = &tcg_op_defs[opc]; 1895 TCGLifeData arg_life = op->life; 1896 int nb_iargs, nb_oargs, call_flags; 1897 TCGTemp *arg_ts, *dir_ts; 1898 1899 oi_next = op->next; 1900 1901 if (opc == INDEX_op_call) { 1902 nb_oargs = op->callo; 1903 nb_iargs = op->calli; 1904 call_flags = op->args[nb_oargs + nb_iargs + 1]; 1905 } else { 1906 nb_iargs = def->nb_iargs; 1907 nb_oargs = def->nb_oargs; 1908 1909 /* Set flags similar to how calls require. */ 1910 if (def->flags & TCG_OPF_BB_END) { 1911 /* Like writing globals: save_globals */ 1912 call_flags = 0; 1913 } else if (def->flags & TCG_OPF_SIDE_EFFECTS) { 1914 /* Like reading globals: sync_globals */ 1915 call_flags = TCG_CALL_NO_WRITE_GLOBALS; 1916 } else { 1917 /* No effect on globals. */ 1918 call_flags = (TCG_CALL_NO_READ_GLOBALS | 1919 TCG_CALL_NO_WRITE_GLOBALS); 1920 } 1921 } 1922 1923 /* Make sure that input arguments are available. */ 1924 for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) { 1925 arg_ts = arg_temp(op->args[i]); 1926 if (arg_ts) { 1927 dir_ts = arg_ts->state_ptr; 1928 if (dir_ts && arg_ts->state == TS_DEAD) { 1929 TCGOpcode lopc = (arg_ts->type == TCG_TYPE_I32 1930 ? INDEX_op_ld_i32 1931 : INDEX_op_ld_i64); 1932 TCGOp *lop = tcg_op_insert_before(s, op, lopc, 3); 1933 1934 lop->args[0] = temp_arg(dir_ts); 1935 lop->args[1] = temp_arg(arg_ts->mem_base); 1936 lop->args[2] = arg_ts->mem_offset; 1937 1938 /* Loaded, but synced with memory. */ 1939 arg_ts->state = TS_MEM; 1940 } 1941 } 1942 } 1943 1944 /* Perform input replacement, and mark inputs that became dead. 1945 No action is required except keeping temp_state up to date 1946 so that we reload when needed. */ 1947 for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) { 1948 arg_ts = arg_temp(op->args[i]); 1949 if (arg_ts) { 1950 dir_ts = arg_ts->state_ptr; 1951 if (dir_ts) { 1952 op->args[i] = temp_arg(dir_ts); 1953 changes = true; 1954 if (IS_DEAD_ARG(i)) { 1955 arg_ts->state = TS_DEAD; 1956 } 1957 } 1958 } 1959 } 1960 1961 /* Liveness analysis should ensure that the following are 1962 all correct, for call sites and basic block end points. */ 1963 if (call_flags & TCG_CALL_NO_READ_GLOBALS) { 1964 /* Nothing to do */ 1965 } else if (call_flags & TCG_CALL_NO_WRITE_GLOBALS) { 1966 for (i = 0; i < nb_globals; ++i) { 1967 /* Liveness should see that globals are synced back, 1968 that is, either TS_DEAD or TS_MEM. */ 1969 arg_ts = &s->temps[i]; 1970 tcg_debug_assert(arg_ts->state_ptr == 0 1971 || arg_ts->state != 0); 1972 } 1973 } else { 1974 for (i = 0; i < nb_globals; ++i) { 1975 /* Liveness should see that globals are saved back, 1976 that is, TS_DEAD, waiting to be reloaded. */ 1977 arg_ts = &s->temps[i]; 1978 tcg_debug_assert(arg_ts->state_ptr == 0 1979 || arg_ts->state == TS_DEAD); 1980 } 1981 } 1982 1983 /* Outputs become available. */ 1984 for (i = 0; i < nb_oargs; i++) { 1985 arg_ts = arg_temp(op->args[i]); 1986 dir_ts = arg_ts->state_ptr; 1987 if (!dir_ts) { 1988 continue; 1989 } 1990 op->args[i] = temp_arg(dir_ts); 1991 changes = true; 1992 1993 /* The output is now live and modified. */ 1994 arg_ts->state = 0; 1995 1996 /* Sync outputs upon their last write. */ 1997 if (NEED_SYNC_ARG(i)) { 1998 TCGOpcode sopc = (arg_ts->type == TCG_TYPE_I32 1999 ? INDEX_op_st_i32 2000 : INDEX_op_st_i64); 2001 TCGOp *sop = tcg_op_insert_after(s, op, sopc, 3); 2002 2003 sop->args[0] = temp_arg(dir_ts); 2004 sop->args[1] = temp_arg(arg_ts->mem_base); 2005 sop->args[2] = arg_ts->mem_offset; 2006 2007 arg_ts->state = TS_MEM; 2008 } 2009 /* Drop outputs that are dead. */ 2010 if (IS_DEAD_ARG(i)) { 2011 arg_ts->state = TS_DEAD; 2012 } 2013 } 2014 } 2015 2016 return changes; 2017 } 2018 2019 #ifdef CONFIG_DEBUG_TCG 2020 static void dump_regs(TCGContext *s) 2021 { 2022 TCGTemp *ts; 2023 int i; 2024 char buf[64]; 2025 2026 for(i = 0; i < s->nb_temps; i++) { 2027 ts = &s->temps[i]; 2028 printf(" %10s: ", tcg_get_arg_str_ptr(s, buf, sizeof(buf), ts)); 2029 switch(ts->val_type) { 2030 case TEMP_VAL_REG: 2031 printf("%s", tcg_target_reg_names[ts->reg]); 2032 break; 2033 case TEMP_VAL_MEM: 2034 printf("%d(%s)", (int)ts->mem_offset, 2035 tcg_target_reg_names[ts->mem_base->reg]); 2036 break; 2037 case TEMP_VAL_CONST: 2038 printf("$0x%" TCG_PRIlx, ts->val); 2039 break; 2040 case TEMP_VAL_DEAD: 2041 printf("D"); 2042 break; 2043 default: 2044 printf("???"); 2045 break; 2046 } 2047 printf("\n"); 2048 } 2049 2050 for(i = 0; i < TCG_TARGET_NB_REGS; i++) { 2051 if (s->reg_to_temp[i] != NULL) { 2052 printf("%s: %s\n", 2053 tcg_target_reg_names[i], 2054 tcg_get_arg_str_ptr(s, buf, sizeof(buf), s->reg_to_temp[i])); 2055 } 2056 } 2057 } 2058 2059 static void check_regs(TCGContext *s) 2060 { 2061 int reg; 2062 int k; 2063 TCGTemp *ts; 2064 char buf[64]; 2065 2066 for (reg = 0; reg < TCG_TARGET_NB_REGS; reg++) { 2067 ts = s->reg_to_temp[reg]; 2068 if (ts != NULL) { 2069 if (ts->val_type != TEMP_VAL_REG || ts->reg != reg) { 2070 printf("Inconsistency for register %s:\n", 2071 tcg_target_reg_names[reg]); 2072 goto fail; 2073 } 2074 } 2075 } 2076 for (k = 0; k < s->nb_temps; k++) { 2077 ts = &s->temps[k]; 2078 if (ts->val_type == TEMP_VAL_REG && !ts->fixed_reg 2079 && s->reg_to_temp[ts->reg] != ts) { 2080 printf("Inconsistency for temp %s:\n", 2081 tcg_get_arg_str_ptr(s, buf, sizeof(buf), ts)); 2082 fail: 2083 printf("reg state:\n"); 2084 dump_regs(s); 2085 tcg_abort(); 2086 } 2087 } 2088 } 2089 #endif 2090 2091 static void temp_allocate_frame(TCGContext *s, TCGTemp *ts) 2092 { 2093 #if !(defined(__sparc__) && TCG_TARGET_REG_BITS == 64) 2094 /* Sparc64 stack is accessed with offset of 2047 */ 2095 s->current_frame_offset = (s->current_frame_offset + 2096 (tcg_target_long)sizeof(tcg_target_long) - 1) & 2097 ~(sizeof(tcg_target_long) - 1); 2098 #endif 2099 if (s->current_frame_offset + (tcg_target_long)sizeof(tcg_target_long) > 2100 s->frame_end) { 2101 tcg_abort(); 2102 } 2103 ts->mem_offset = s->current_frame_offset; 2104 ts->mem_base = s->frame_temp; 2105 ts->mem_allocated = 1; 2106 s->current_frame_offset += sizeof(tcg_target_long); 2107 } 2108 2109 static void temp_load(TCGContext *, TCGTemp *, TCGRegSet, TCGRegSet); 2110 2111 /* Mark a temporary as free or dead. If 'free_or_dead' is negative, 2112 mark it free; otherwise mark it dead. */ 2113 static void temp_free_or_dead(TCGContext *s, TCGTemp *ts, int free_or_dead) 2114 { 2115 if (ts->fixed_reg) { 2116 return; 2117 } 2118 if (ts->val_type == TEMP_VAL_REG) { 2119 s->reg_to_temp[ts->reg] = NULL; 2120 } 2121 ts->val_type = (free_or_dead < 0 2122 || ts->temp_local 2123 || ts->temp_global 2124 ? TEMP_VAL_MEM : TEMP_VAL_DEAD); 2125 } 2126 2127 /* Mark a temporary as dead. */ 2128 static inline void temp_dead(TCGContext *s, TCGTemp *ts) 2129 { 2130 temp_free_or_dead(s, ts, 1); 2131 } 2132 2133 /* Sync a temporary to memory. 'allocated_regs' is used in case a temporary 2134 registers needs to be allocated to store a constant. If 'free_or_dead' 2135 is non-zero, subsequently release the temporary; if it is positive, the 2136 temp is dead; if it is negative, the temp is free. */ 2137 static void temp_sync(TCGContext *s, TCGTemp *ts, 2138 TCGRegSet allocated_regs, int free_or_dead) 2139 { 2140 if (ts->fixed_reg) { 2141 return; 2142 } 2143 if (!ts->mem_coherent) { 2144 if (!ts->mem_allocated) { 2145 temp_allocate_frame(s, ts); 2146 } 2147 switch (ts->val_type) { 2148 case TEMP_VAL_CONST: 2149 /* If we're going to free the temp immediately, then we won't 2150 require it later in a register, so attempt to store the 2151 constant to memory directly. */ 2152 if (free_or_dead 2153 && tcg_out_sti(s, ts->type, ts->val, 2154 ts->mem_base->reg, ts->mem_offset)) { 2155 break; 2156 } 2157 temp_load(s, ts, tcg_target_available_regs[ts->type], 2158 allocated_regs); 2159 /* fallthrough */ 2160 2161 case TEMP_VAL_REG: 2162 tcg_out_st(s, ts->type, ts->reg, 2163 ts->mem_base->reg, ts->mem_offset); 2164 break; 2165 2166 case TEMP_VAL_MEM: 2167 break; 2168 2169 case TEMP_VAL_DEAD: 2170 default: 2171 tcg_abort(); 2172 } 2173 ts->mem_coherent = 1; 2174 } 2175 if (free_or_dead) { 2176 temp_free_or_dead(s, ts, free_or_dead); 2177 } 2178 } 2179 2180 /* free register 'reg' by spilling the corresponding temporary if necessary */ 2181 static void tcg_reg_free(TCGContext *s, TCGReg reg, TCGRegSet allocated_regs) 2182 { 2183 TCGTemp *ts = s->reg_to_temp[reg]; 2184 if (ts != NULL) { 2185 temp_sync(s, ts, allocated_regs, -1); 2186 } 2187 } 2188 2189 /* Allocate a register belonging to reg1 & ~reg2 */ 2190 static TCGReg tcg_reg_alloc(TCGContext *s, TCGRegSet desired_regs, 2191 TCGRegSet allocated_regs, bool rev) 2192 { 2193 int i, n = ARRAY_SIZE(tcg_target_reg_alloc_order); 2194 const int *order; 2195 TCGReg reg; 2196 TCGRegSet reg_ct; 2197 2198 reg_ct = desired_regs & ~allocated_regs; 2199 order = rev ? indirect_reg_alloc_order : tcg_target_reg_alloc_order; 2200 2201 /* first try free registers */ 2202 for(i = 0; i < n; i++) { 2203 reg = order[i]; 2204 if (tcg_regset_test_reg(reg_ct, reg) && s->reg_to_temp[reg] == NULL) 2205 return reg; 2206 } 2207 2208 /* XXX: do better spill choice */ 2209 for(i = 0; i < n; i++) { 2210 reg = order[i]; 2211 if (tcg_regset_test_reg(reg_ct, reg)) { 2212 tcg_reg_free(s, reg, allocated_regs); 2213 return reg; 2214 } 2215 } 2216 2217 tcg_abort(); 2218 } 2219 2220 /* Make sure the temporary is in a register. If needed, allocate the register 2221 from DESIRED while avoiding ALLOCATED. */ 2222 static void temp_load(TCGContext *s, TCGTemp *ts, TCGRegSet desired_regs, 2223 TCGRegSet allocated_regs) 2224 { 2225 TCGReg reg; 2226 2227 switch (ts->val_type) { 2228 case TEMP_VAL_REG: 2229 return; 2230 case TEMP_VAL_CONST: 2231 reg = tcg_reg_alloc(s, desired_regs, allocated_regs, ts->indirect_base); 2232 tcg_out_movi(s, ts->type, reg, ts->val); 2233 ts->mem_coherent = 0; 2234 break; 2235 case TEMP_VAL_MEM: 2236 reg = tcg_reg_alloc(s, desired_regs, allocated_regs, ts->indirect_base); 2237 tcg_out_ld(s, ts->type, reg, ts->mem_base->reg, ts->mem_offset); 2238 ts->mem_coherent = 1; 2239 break; 2240 case TEMP_VAL_DEAD: 2241 default: 2242 tcg_abort(); 2243 } 2244 ts->reg = reg; 2245 ts->val_type = TEMP_VAL_REG; 2246 s->reg_to_temp[reg] = ts; 2247 } 2248 2249 /* Save a temporary to memory. 'allocated_regs' is used in case a 2250 temporary registers needs to be allocated to store a constant. */ 2251 static void temp_save(TCGContext *s, TCGTemp *ts, TCGRegSet allocated_regs) 2252 { 2253 /* The liveness analysis already ensures that globals are back 2254 in memory. Keep an tcg_debug_assert for safety. */ 2255 tcg_debug_assert(ts->val_type == TEMP_VAL_MEM || ts->fixed_reg); 2256 } 2257 2258 /* save globals to their canonical location and assume they can be 2259 modified be the following code. 'allocated_regs' is used in case a 2260 temporary registers needs to be allocated to store a constant. */ 2261 static void save_globals(TCGContext *s, TCGRegSet allocated_regs) 2262 { 2263 int i, n; 2264 2265 for (i = 0, n = s->nb_globals; i < n; i++) { 2266 temp_save(s, &s->temps[i], allocated_regs); 2267 } 2268 } 2269 2270 /* sync globals to their canonical location and assume they can be 2271 read by the following code. 'allocated_regs' is used in case a 2272 temporary registers needs to be allocated to store a constant. */ 2273 static void sync_globals(TCGContext *s, TCGRegSet allocated_regs) 2274 { 2275 int i, n; 2276 2277 for (i = 0, n = s->nb_globals; i < n; i++) { 2278 TCGTemp *ts = &s->temps[i]; 2279 tcg_debug_assert(ts->val_type != TEMP_VAL_REG 2280 || ts->fixed_reg 2281 || ts->mem_coherent); 2282 } 2283 } 2284 2285 /* at the end of a basic block, we assume all temporaries are dead and 2286 all globals are stored at their canonical location. */ 2287 static void tcg_reg_alloc_bb_end(TCGContext *s, TCGRegSet allocated_regs) 2288 { 2289 int i; 2290 2291 for (i = s->nb_globals; i < s->nb_temps; i++) { 2292 TCGTemp *ts = &s->temps[i]; 2293 if (ts->temp_local) { 2294 temp_save(s, ts, allocated_regs); 2295 } else { 2296 /* The liveness analysis already ensures that temps are dead. 2297 Keep an tcg_debug_assert for safety. */ 2298 tcg_debug_assert(ts->val_type == TEMP_VAL_DEAD); 2299 } 2300 } 2301 2302 save_globals(s, allocated_regs); 2303 } 2304 2305 static void tcg_reg_alloc_do_movi(TCGContext *s, TCGTemp *ots, 2306 tcg_target_ulong val, TCGLifeData arg_life) 2307 { 2308 if (ots->fixed_reg) { 2309 /* For fixed registers, we do not do any constant propagation. */ 2310 tcg_out_movi(s, ots->type, ots->reg, val); 2311 return; 2312 } 2313 2314 /* The movi is not explicitly generated here. */ 2315 if (ots->val_type == TEMP_VAL_REG) { 2316 s->reg_to_temp[ots->reg] = NULL; 2317 } 2318 ots->val_type = TEMP_VAL_CONST; 2319 ots->val = val; 2320 ots->mem_coherent = 0; 2321 if (NEED_SYNC_ARG(0)) { 2322 temp_sync(s, ots, s->reserved_regs, IS_DEAD_ARG(0)); 2323 } else if (IS_DEAD_ARG(0)) { 2324 temp_dead(s, ots); 2325 } 2326 } 2327 2328 static void tcg_reg_alloc_movi(TCGContext *s, const TCGOp *op) 2329 { 2330 TCGTemp *ots = arg_temp(op->args[0]); 2331 tcg_target_ulong val = op->args[1]; 2332 2333 tcg_reg_alloc_do_movi(s, ots, val, op->life); 2334 } 2335 2336 static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op) 2337 { 2338 const TCGLifeData arg_life = op->life; 2339 TCGRegSet allocated_regs; 2340 TCGTemp *ts, *ots; 2341 TCGType otype, itype; 2342 2343 allocated_regs = s->reserved_regs; 2344 ots = arg_temp(op->args[0]); 2345 ts = arg_temp(op->args[1]); 2346 2347 /* Note that otype != itype for no-op truncation. */ 2348 otype = ots->type; 2349 itype = ts->type; 2350 2351 if (ts->val_type == TEMP_VAL_CONST) { 2352 /* propagate constant or generate sti */ 2353 tcg_target_ulong val = ts->val; 2354 if (IS_DEAD_ARG(1)) { 2355 temp_dead(s, ts); 2356 } 2357 tcg_reg_alloc_do_movi(s, ots, val, arg_life); 2358 return; 2359 } 2360 2361 /* If the source value is in memory we're going to be forced 2362 to have it in a register in order to perform the copy. Copy 2363 the SOURCE value into its own register first, that way we 2364 don't have to reload SOURCE the next time it is used. */ 2365 if (ts->val_type == TEMP_VAL_MEM) { 2366 temp_load(s, ts, tcg_target_available_regs[itype], allocated_regs); 2367 } 2368 2369 tcg_debug_assert(ts->val_type == TEMP_VAL_REG); 2370 if (IS_DEAD_ARG(0) && !ots->fixed_reg) { 2371 /* mov to a non-saved dead register makes no sense (even with 2372 liveness analysis disabled). */ 2373 tcg_debug_assert(NEED_SYNC_ARG(0)); 2374 if (!ots->mem_allocated) { 2375 temp_allocate_frame(s, ots); 2376 } 2377 tcg_out_st(s, otype, ts->reg, ots->mem_base->reg, ots->mem_offset); 2378 if (IS_DEAD_ARG(1)) { 2379 temp_dead(s, ts); 2380 } 2381 temp_dead(s, ots); 2382 } else { 2383 if (IS_DEAD_ARG(1) && !ts->fixed_reg && !ots->fixed_reg) { 2384 /* the mov can be suppressed */ 2385 if (ots->val_type == TEMP_VAL_REG) { 2386 s->reg_to_temp[ots->reg] = NULL; 2387 } 2388 ots->reg = ts->reg; 2389 temp_dead(s, ts); 2390 } else { 2391 if (ots->val_type != TEMP_VAL_REG) { 2392 /* When allocating a new register, make sure to not spill the 2393 input one. */ 2394 tcg_regset_set_reg(allocated_regs, ts->reg); 2395 ots->reg = tcg_reg_alloc(s, tcg_target_available_regs[otype], 2396 allocated_regs, ots->indirect_base); 2397 } 2398 tcg_out_mov(s, otype, ots->reg, ts->reg); 2399 } 2400 ots->val_type = TEMP_VAL_REG; 2401 ots->mem_coherent = 0; 2402 s->reg_to_temp[ots->reg] = ots; 2403 if (NEED_SYNC_ARG(0)) { 2404 temp_sync(s, ots, allocated_regs, 0); 2405 } 2406 } 2407 } 2408 2409 static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) 2410 { 2411 const TCGLifeData arg_life = op->life; 2412 const TCGOpDef * const def = &tcg_op_defs[op->opc]; 2413 TCGRegSet i_allocated_regs; 2414 TCGRegSet o_allocated_regs; 2415 int i, k, nb_iargs, nb_oargs; 2416 TCGReg reg; 2417 TCGArg arg; 2418 const TCGArgConstraint *arg_ct; 2419 TCGTemp *ts; 2420 TCGArg new_args[TCG_MAX_OP_ARGS]; 2421 int const_args[TCG_MAX_OP_ARGS]; 2422 2423 nb_oargs = def->nb_oargs; 2424 nb_iargs = def->nb_iargs; 2425 2426 /* copy constants */ 2427 memcpy(new_args + nb_oargs + nb_iargs, 2428 op->args + nb_oargs + nb_iargs, 2429 sizeof(TCGArg) * def->nb_cargs); 2430 2431 i_allocated_regs = s->reserved_regs; 2432 o_allocated_regs = s->reserved_regs; 2433 2434 /* satisfy input constraints */ 2435 for (k = 0; k < nb_iargs; k++) { 2436 i = def->sorted_args[nb_oargs + k]; 2437 arg = op->args[i]; 2438 arg_ct = &def->args_ct[i]; 2439 ts = arg_temp(arg); 2440 2441 if (ts->val_type == TEMP_VAL_CONST 2442 && tcg_target_const_match(ts->val, ts->type, arg_ct)) { 2443 /* constant is OK for instruction */ 2444 const_args[i] = 1; 2445 new_args[i] = ts->val; 2446 goto iarg_end; 2447 } 2448 2449 temp_load(s, ts, arg_ct->u.regs, i_allocated_regs); 2450 2451 if (arg_ct->ct & TCG_CT_IALIAS) { 2452 if (ts->fixed_reg) { 2453 /* if fixed register, we must allocate a new register 2454 if the alias is not the same register */ 2455 if (arg != op->args[arg_ct->alias_index]) 2456 goto allocate_in_reg; 2457 } else { 2458 /* if the input is aliased to an output and if it is 2459 not dead after the instruction, we must allocate 2460 a new register and move it */ 2461 if (!IS_DEAD_ARG(i)) { 2462 goto allocate_in_reg; 2463 } 2464 /* check if the current register has already been allocated 2465 for another input aliased to an output */ 2466 int k2, i2; 2467 for (k2 = 0 ; k2 < k ; k2++) { 2468 i2 = def->sorted_args[nb_oargs + k2]; 2469 if ((def->args_ct[i2].ct & TCG_CT_IALIAS) && 2470 (new_args[i2] == ts->reg)) { 2471 goto allocate_in_reg; 2472 } 2473 } 2474 } 2475 } 2476 reg = ts->reg; 2477 if (tcg_regset_test_reg(arg_ct->u.regs, reg)) { 2478 /* nothing to do : the constraint is satisfied */ 2479 } else { 2480 allocate_in_reg: 2481 /* allocate a new register matching the constraint 2482 and move the temporary register into it */ 2483 reg = tcg_reg_alloc(s, arg_ct->u.regs, i_allocated_regs, 2484 ts->indirect_base); 2485 tcg_out_mov(s, ts->type, reg, ts->reg); 2486 } 2487 new_args[i] = reg; 2488 const_args[i] = 0; 2489 tcg_regset_set_reg(i_allocated_regs, reg); 2490 iarg_end: ; 2491 } 2492 2493 /* mark dead temporaries and free the associated registers */ 2494 for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) { 2495 if (IS_DEAD_ARG(i)) { 2496 temp_dead(s, arg_temp(op->args[i])); 2497 } 2498 } 2499 2500 if (def->flags & TCG_OPF_BB_END) { 2501 tcg_reg_alloc_bb_end(s, i_allocated_regs); 2502 } else { 2503 if (def->flags & TCG_OPF_CALL_CLOBBER) { 2504 /* XXX: permit generic clobber register list ? */ 2505 for (i = 0; i < TCG_TARGET_NB_REGS; i++) { 2506 if (tcg_regset_test_reg(tcg_target_call_clobber_regs, i)) { 2507 tcg_reg_free(s, i, i_allocated_regs); 2508 } 2509 } 2510 } 2511 if (def->flags & TCG_OPF_SIDE_EFFECTS) { 2512 /* sync globals if the op has side effects and might trigger 2513 an exception. */ 2514 sync_globals(s, i_allocated_regs); 2515 } 2516 2517 /* satisfy the output constraints */ 2518 for(k = 0; k < nb_oargs; k++) { 2519 i = def->sorted_args[k]; 2520 arg = op->args[i]; 2521 arg_ct = &def->args_ct[i]; 2522 ts = arg_temp(arg); 2523 if ((arg_ct->ct & TCG_CT_ALIAS) 2524 && !const_args[arg_ct->alias_index]) { 2525 reg = new_args[arg_ct->alias_index]; 2526 } else if (arg_ct->ct & TCG_CT_NEWREG) { 2527 reg = tcg_reg_alloc(s, arg_ct->u.regs, 2528 i_allocated_regs | o_allocated_regs, 2529 ts->indirect_base); 2530 } else { 2531 /* if fixed register, we try to use it */ 2532 reg = ts->reg; 2533 if (ts->fixed_reg && 2534 tcg_regset_test_reg(arg_ct->u.regs, reg)) { 2535 goto oarg_end; 2536 } 2537 reg = tcg_reg_alloc(s, arg_ct->u.regs, o_allocated_regs, 2538 ts->indirect_base); 2539 } 2540 tcg_regset_set_reg(o_allocated_regs, reg); 2541 /* if a fixed register is used, then a move will be done afterwards */ 2542 if (!ts->fixed_reg) { 2543 if (ts->val_type == TEMP_VAL_REG) { 2544 s->reg_to_temp[ts->reg] = NULL; 2545 } 2546 ts->val_type = TEMP_VAL_REG; 2547 ts->reg = reg; 2548 /* temp value is modified, so the value kept in memory is 2549 potentially not the same */ 2550 ts->mem_coherent = 0; 2551 s->reg_to_temp[reg] = ts; 2552 } 2553 oarg_end: 2554 new_args[i] = reg; 2555 } 2556 } 2557 2558 /* emit instruction */ 2559 tcg_out_op(s, op->opc, new_args, const_args); 2560 2561 /* move the outputs in the correct register if needed */ 2562 for(i = 0; i < nb_oargs; i++) { 2563 ts = arg_temp(op->args[i]); 2564 reg = new_args[i]; 2565 if (ts->fixed_reg && ts->reg != reg) { 2566 tcg_out_mov(s, ts->type, ts->reg, reg); 2567 } 2568 if (NEED_SYNC_ARG(i)) { 2569 temp_sync(s, ts, o_allocated_regs, IS_DEAD_ARG(i)); 2570 } else if (IS_DEAD_ARG(i)) { 2571 temp_dead(s, ts); 2572 } 2573 } 2574 } 2575 2576 #ifdef TCG_TARGET_STACK_GROWSUP 2577 #define STACK_DIR(x) (-(x)) 2578 #else 2579 #define STACK_DIR(x) (x) 2580 #endif 2581 2582 static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) 2583 { 2584 const int nb_oargs = op->callo; 2585 const int nb_iargs = op->calli; 2586 const TCGLifeData arg_life = op->life; 2587 int flags, nb_regs, i; 2588 TCGReg reg; 2589 TCGArg arg; 2590 TCGTemp *ts; 2591 intptr_t stack_offset; 2592 size_t call_stack_size; 2593 tcg_insn_unit *func_addr; 2594 int allocate_args; 2595 TCGRegSet allocated_regs; 2596 2597 func_addr = (tcg_insn_unit *)(intptr_t)op->args[nb_oargs + nb_iargs]; 2598 flags = op->args[nb_oargs + nb_iargs + 1]; 2599 2600 nb_regs = ARRAY_SIZE(tcg_target_call_iarg_regs); 2601 if (nb_regs > nb_iargs) { 2602 nb_regs = nb_iargs; 2603 } 2604 2605 /* assign stack slots first */ 2606 call_stack_size = (nb_iargs - nb_regs) * sizeof(tcg_target_long); 2607 call_stack_size = (call_stack_size + TCG_TARGET_STACK_ALIGN - 1) & 2608 ~(TCG_TARGET_STACK_ALIGN - 1); 2609 allocate_args = (call_stack_size > TCG_STATIC_CALL_ARGS_SIZE); 2610 if (allocate_args) { 2611 /* XXX: if more than TCG_STATIC_CALL_ARGS_SIZE is needed, 2612 preallocate call stack */ 2613 tcg_abort(); 2614 } 2615 2616 stack_offset = TCG_TARGET_CALL_STACK_OFFSET; 2617 for (i = nb_regs; i < nb_iargs; i++) { 2618 arg = op->args[nb_oargs + i]; 2619 #ifdef TCG_TARGET_STACK_GROWSUP 2620 stack_offset -= sizeof(tcg_target_long); 2621 #endif 2622 if (arg != TCG_CALL_DUMMY_ARG) { 2623 ts = arg_temp(arg); 2624 temp_load(s, ts, tcg_target_available_regs[ts->type], 2625 s->reserved_regs); 2626 tcg_out_st(s, ts->type, ts->reg, TCG_REG_CALL_STACK, stack_offset); 2627 } 2628 #ifndef TCG_TARGET_STACK_GROWSUP 2629 stack_offset += sizeof(tcg_target_long); 2630 #endif 2631 } 2632 2633 /* assign input registers */ 2634 allocated_regs = s->reserved_regs; 2635 for (i = 0; i < nb_regs; i++) { 2636 arg = op->args[nb_oargs + i]; 2637 if (arg != TCG_CALL_DUMMY_ARG) { 2638 ts = arg_temp(arg); 2639 reg = tcg_target_call_iarg_regs[i]; 2640 tcg_reg_free(s, reg, allocated_regs); 2641 2642 if (ts->val_type == TEMP_VAL_REG) { 2643 if (ts->reg != reg) { 2644 tcg_out_mov(s, ts->type, reg, ts->reg); 2645 } 2646 } else { 2647 TCGRegSet arg_set = 0; 2648 2649 tcg_regset_set_reg(arg_set, reg); 2650 temp_load(s, ts, arg_set, allocated_regs); 2651 } 2652 2653 tcg_regset_set_reg(allocated_regs, reg); 2654 } 2655 } 2656 2657 /* mark dead temporaries and free the associated registers */ 2658 for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) { 2659 if (IS_DEAD_ARG(i)) { 2660 temp_dead(s, arg_temp(op->args[i])); 2661 } 2662 } 2663 2664 /* clobber call registers */ 2665 for (i = 0; i < TCG_TARGET_NB_REGS; i++) { 2666 if (tcg_regset_test_reg(tcg_target_call_clobber_regs, i)) { 2667 tcg_reg_free(s, i, allocated_regs); 2668 } 2669 } 2670 2671 /* Save globals if they might be written by the helper, sync them if 2672 they might be read. */ 2673 if (flags & TCG_CALL_NO_READ_GLOBALS) { 2674 /* Nothing to do */ 2675 } else if (flags & TCG_CALL_NO_WRITE_GLOBALS) { 2676 sync_globals(s, allocated_regs); 2677 } else { 2678 save_globals(s, allocated_regs); 2679 } 2680 2681 tcg_out_call(s, func_addr); 2682 2683 /* assign output registers and emit moves if needed */ 2684 for(i = 0; i < nb_oargs; i++) { 2685 arg = op->args[i]; 2686 ts = arg_temp(arg); 2687 reg = tcg_target_call_oarg_regs[i]; 2688 tcg_debug_assert(s->reg_to_temp[reg] == NULL); 2689 2690 if (ts->fixed_reg) { 2691 if (ts->reg != reg) { 2692 tcg_out_mov(s, ts->type, ts->reg, reg); 2693 } 2694 } else { 2695 if (ts->val_type == TEMP_VAL_REG) { 2696 s->reg_to_temp[ts->reg] = NULL; 2697 } 2698 ts->val_type = TEMP_VAL_REG; 2699 ts->reg = reg; 2700 ts->mem_coherent = 0; 2701 s->reg_to_temp[reg] = ts; 2702 if (NEED_SYNC_ARG(i)) { 2703 temp_sync(s, ts, allocated_regs, IS_DEAD_ARG(i)); 2704 } else if (IS_DEAD_ARG(i)) { 2705 temp_dead(s, ts); 2706 } 2707 } 2708 } 2709 } 2710 2711 #ifdef CONFIG_PROFILER 2712 2713 static int64_t tcg_table_op_count[NB_OPS]; 2714 2715 void tcg_dump_op_count(FILE *f, fprintf_function cpu_fprintf) 2716 { 2717 int i; 2718 2719 for (i = 0; i < NB_OPS; i++) { 2720 cpu_fprintf(f, "%s %" PRId64 "\n", tcg_op_defs[i].name, 2721 tcg_table_op_count[i]); 2722 } 2723 } 2724 #else 2725 void tcg_dump_op_count(FILE *f, fprintf_function cpu_fprintf) 2726 { 2727 cpu_fprintf(f, "[TCG profiler not compiled]\n"); 2728 } 2729 #endif 2730 2731 2732 int tcg_gen_code(TCGContext *s, TranslationBlock *tb) 2733 { 2734 int i, oi, oi_next, num_insns; 2735 2736 #ifdef CONFIG_PROFILER 2737 { 2738 int n; 2739 2740 n = s->gen_op_buf[0].prev + 1; 2741 s->op_count += n; 2742 if (n > s->op_count_max) { 2743 s->op_count_max = n; 2744 } 2745 2746 n = s->nb_temps; 2747 s->temp_count += n; 2748 if (n > s->temp_count_max) { 2749 s->temp_count_max = n; 2750 } 2751 } 2752 #endif 2753 2754 #ifdef DEBUG_DISAS 2755 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP) 2756 && qemu_log_in_addr_range(tb->pc))) { 2757 qemu_log_lock(); 2758 qemu_log("OP:\n"); 2759 tcg_dump_ops(s); 2760 qemu_log("\n"); 2761 qemu_log_unlock(); 2762 } 2763 #endif 2764 2765 #ifdef CONFIG_PROFILER 2766 s->opt_time -= profile_getclock(); 2767 #endif 2768 2769 #ifdef USE_TCG_OPTIMIZATIONS 2770 tcg_optimize(s); 2771 #endif 2772 2773 #ifdef CONFIG_PROFILER 2774 s->opt_time += profile_getclock(); 2775 s->la_time -= profile_getclock(); 2776 #endif 2777 2778 liveness_pass_1(s); 2779 2780 if (s->nb_indirects > 0) { 2781 #ifdef DEBUG_DISAS 2782 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_IND) 2783 && qemu_log_in_addr_range(tb->pc))) { 2784 qemu_log_lock(); 2785 qemu_log("OP before indirect lowering:\n"); 2786 tcg_dump_ops(s); 2787 qemu_log("\n"); 2788 qemu_log_unlock(); 2789 } 2790 #endif 2791 /* Replace indirect temps with direct temps. */ 2792 if (liveness_pass_2(s)) { 2793 /* If changes were made, re-run liveness. */ 2794 liveness_pass_1(s); 2795 } 2796 } 2797 2798 #ifdef CONFIG_PROFILER 2799 s->la_time += profile_getclock(); 2800 #endif 2801 2802 #ifdef DEBUG_DISAS 2803 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT) 2804 && qemu_log_in_addr_range(tb->pc))) { 2805 qemu_log_lock(); 2806 qemu_log("OP after optimization and liveness analysis:\n"); 2807 tcg_dump_ops(s); 2808 qemu_log("\n"); 2809 qemu_log_unlock(); 2810 } 2811 #endif 2812 2813 tcg_reg_alloc_start(s); 2814 2815 s->code_buf = tb->tc.ptr; 2816 s->code_ptr = tb->tc.ptr; 2817 2818 #ifdef TCG_TARGET_NEED_LDST_LABELS 2819 s->ldst_labels = NULL; 2820 #endif 2821 #ifdef TCG_TARGET_NEED_POOL_LABELS 2822 s->pool_labels = NULL; 2823 #endif 2824 2825 num_insns = -1; 2826 for (oi = s->gen_op_buf[0].next; oi != 0; oi = oi_next) { 2827 TCGOp * const op = &s->gen_op_buf[oi]; 2828 TCGOpcode opc = op->opc; 2829 2830 oi_next = op->next; 2831 #ifdef CONFIG_PROFILER 2832 tcg_table_op_count[opc]++; 2833 #endif 2834 2835 switch (opc) { 2836 case INDEX_op_mov_i32: 2837 case INDEX_op_mov_i64: 2838 tcg_reg_alloc_mov(s, op); 2839 break; 2840 case INDEX_op_movi_i32: 2841 case INDEX_op_movi_i64: 2842 tcg_reg_alloc_movi(s, op); 2843 break; 2844 case INDEX_op_insn_start: 2845 if (num_insns >= 0) { 2846 s->gen_insn_end_off[num_insns] = tcg_current_code_size(s); 2847 } 2848 num_insns++; 2849 for (i = 0; i < TARGET_INSN_START_WORDS; ++i) { 2850 target_ulong a; 2851 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS 2852 a = deposit64(op->args[i * 2], 32, 32, op->args[i * 2 + 1]); 2853 #else 2854 a = op->args[i]; 2855 #endif 2856 s->gen_insn_data[num_insns][i] = a; 2857 } 2858 break; 2859 case INDEX_op_discard: 2860 temp_dead(s, arg_temp(op->args[0])); 2861 break; 2862 case INDEX_op_set_label: 2863 tcg_reg_alloc_bb_end(s, s->reserved_regs); 2864 tcg_out_label(s, arg_label(op->args[0]), s->code_ptr); 2865 break; 2866 case INDEX_op_call: 2867 tcg_reg_alloc_call(s, op); 2868 break; 2869 default: 2870 /* Sanity check that we've not introduced any unhandled opcodes. */ 2871 tcg_debug_assert(tcg_op_supported(opc)); 2872 /* Note: in order to speed up the code, it would be much 2873 faster to have specialized register allocator functions for 2874 some common argument patterns */ 2875 tcg_reg_alloc_op(s, op); 2876 break; 2877 } 2878 #ifdef CONFIG_DEBUG_TCG 2879 check_regs(s); 2880 #endif 2881 /* Test for (pending) buffer overflow. The assumption is that any 2882 one operation beginning below the high water mark cannot overrun 2883 the buffer completely. Thus we can test for overflow after 2884 generating code without having to check during generation. */ 2885 if (unlikely((void *)s->code_ptr > s->code_gen_highwater)) { 2886 return -1; 2887 } 2888 } 2889 tcg_debug_assert(num_insns >= 0); 2890 s->gen_insn_end_off[num_insns] = tcg_current_code_size(s); 2891 2892 /* Generate TB finalization at the end of block */ 2893 #ifdef TCG_TARGET_NEED_LDST_LABELS 2894 if (!tcg_out_ldst_finalize(s)) { 2895 return -1; 2896 } 2897 #endif 2898 #ifdef TCG_TARGET_NEED_POOL_LABELS 2899 if (!tcg_out_pool_finalize(s)) { 2900 return -1; 2901 } 2902 #endif 2903 2904 /* flush instruction cache */ 2905 flush_icache_range((uintptr_t)s->code_buf, (uintptr_t)s->code_ptr); 2906 2907 return tcg_current_code_size(s); 2908 } 2909 2910 #ifdef CONFIG_PROFILER 2911 void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf) 2912 { 2913 TCGContext *s = tcg_ctx; 2914 int64_t tb_count = s->tb_count; 2915 int64_t tb_div_count = tb_count ? tb_count : 1; 2916 int64_t tot = s->interm_time + s->code_time; 2917 2918 cpu_fprintf(f, "JIT cycles %" PRId64 " (%0.3f s at 2.4 GHz)\n", 2919 tot, tot / 2.4e9); 2920 cpu_fprintf(f, "translated TBs %" PRId64 " (aborted=%" PRId64 " %0.1f%%)\n", 2921 tb_count, s->tb_count1 - tb_count, 2922 (double)(s->tb_count1 - s->tb_count) 2923 / (s->tb_count1 ? s->tb_count1 : 1) * 100.0); 2924 cpu_fprintf(f, "avg ops/TB %0.1f max=%d\n", 2925 (double)s->op_count / tb_div_count, s->op_count_max); 2926 cpu_fprintf(f, "deleted ops/TB %0.2f\n", 2927 (double)s->del_op_count / tb_div_count); 2928 cpu_fprintf(f, "avg temps/TB %0.2f max=%d\n", 2929 (double)s->temp_count / tb_div_count, s->temp_count_max); 2930 cpu_fprintf(f, "avg host code/TB %0.1f\n", 2931 (double)s->code_out_len / tb_div_count); 2932 cpu_fprintf(f, "avg search data/TB %0.1f\n", 2933 (double)s->search_out_len / tb_div_count); 2934 2935 cpu_fprintf(f, "cycles/op %0.1f\n", 2936 s->op_count ? (double)tot / s->op_count : 0); 2937 cpu_fprintf(f, "cycles/in byte %0.1f\n", 2938 s->code_in_len ? (double)tot / s->code_in_len : 0); 2939 cpu_fprintf(f, "cycles/out byte %0.1f\n", 2940 s->code_out_len ? (double)tot / s->code_out_len : 0); 2941 cpu_fprintf(f, "cycles/search byte %0.1f\n", 2942 s->search_out_len ? (double)tot / s->search_out_len : 0); 2943 if (tot == 0) { 2944 tot = 1; 2945 } 2946 cpu_fprintf(f, " gen_interm time %0.1f%%\n", 2947 (double)s->interm_time / tot * 100.0); 2948 cpu_fprintf(f, " gen_code time %0.1f%%\n", 2949 (double)s->code_time / tot * 100.0); 2950 cpu_fprintf(f, "optim./code time %0.1f%%\n", 2951 (double)s->opt_time / (s->code_time ? s->code_time : 1) 2952 * 100.0); 2953 cpu_fprintf(f, "liveness/code time %0.1f%%\n", 2954 (double)s->la_time / (s->code_time ? s->code_time : 1) * 100.0); 2955 cpu_fprintf(f, "cpu_restore count %" PRId64 "\n", 2956 s->restore_count); 2957 cpu_fprintf(f, " avg cycles %0.1f\n", 2958 s->restore_count ? (double)s->restore_time / s->restore_count : 0); 2959 } 2960 #else 2961 void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf) 2962 { 2963 cpu_fprintf(f, "[TCG profiler not compiled]\n"); 2964 } 2965 #endif 2966 2967 #ifdef ELF_HOST_MACHINE 2968 /* In order to use this feature, the backend needs to do three things: 2969 2970 (1) Define ELF_HOST_MACHINE to indicate both what value to 2971 put into the ELF image and to indicate support for the feature. 2972 2973 (2) Define tcg_register_jit. This should create a buffer containing 2974 the contents of a .debug_frame section that describes the post- 2975 prologue unwind info for the tcg machine. 2976 2977 (3) Call tcg_register_jit_int, with the constructed .debug_frame. 2978 */ 2979 2980 /* Begin GDB interface. THE FOLLOWING MUST MATCH GDB DOCS. */ 2981 typedef enum { 2982 JIT_NOACTION = 0, 2983 JIT_REGISTER_FN, 2984 JIT_UNREGISTER_FN 2985 } jit_actions_t; 2986 2987 struct jit_code_entry { 2988 struct jit_code_entry *next_entry; 2989 struct jit_code_entry *prev_entry; 2990 const void *symfile_addr; 2991 uint64_t symfile_size; 2992 }; 2993 2994 struct jit_descriptor { 2995 uint32_t version; 2996 uint32_t action_flag; 2997 struct jit_code_entry *relevant_entry; 2998 struct jit_code_entry *first_entry; 2999 }; 3000 3001 void __jit_debug_register_code(void) __attribute__((noinline)); 3002 void __jit_debug_register_code(void) 3003 { 3004 asm(""); 3005 } 3006 3007 /* Must statically initialize the version, because GDB may check 3008 the version before we can set it. */ 3009 struct jit_descriptor __jit_debug_descriptor = { 1, 0, 0, 0 }; 3010 3011 /* End GDB interface. */ 3012 3013 static int find_string(const char *strtab, const char *str) 3014 { 3015 const char *p = strtab + 1; 3016 3017 while (1) { 3018 if (strcmp(p, str) == 0) { 3019 return p - strtab; 3020 } 3021 p += strlen(p) + 1; 3022 } 3023 } 3024 3025 static void tcg_register_jit_int(void *buf_ptr, size_t buf_size, 3026 const void *debug_frame, 3027 size_t debug_frame_size) 3028 { 3029 struct __attribute__((packed)) DebugInfo { 3030 uint32_t len; 3031 uint16_t version; 3032 uint32_t abbrev; 3033 uint8_t ptr_size; 3034 uint8_t cu_die; 3035 uint16_t cu_lang; 3036 uintptr_t cu_low_pc; 3037 uintptr_t cu_high_pc; 3038 uint8_t fn_die; 3039 char fn_name[16]; 3040 uintptr_t fn_low_pc; 3041 uintptr_t fn_high_pc; 3042 uint8_t cu_eoc; 3043 }; 3044 3045 struct ElfImage { 3046 ElfW(Ehdr) ehdr; 3047 ElfW(Phdr) phdr; 3048 ElfW(Shdr) shdr[7]; 3049 ElfW(Sym) sym[2]; 3050 struct DebugInfo di; 3051 uint8_t da[24]; 3052 char str[80]; 3053 }; 3054 3055 struct ElfImage *img; 3056 3057 static const struct ElfImage img_template = { 3058 .ehdr = { 3059 .e_ident[EI_MAG0] = ELFMAG0, 3060 .e_ident[EI_MAG1] = ELFMAG1, 3061 .e_ident[EI_MAG2] = ELFMAG2, 3062 .e_ident[EI_MAG3] = ELFMAG3, 3063 .e_ident[EI_CLASS] = ELF_CLASS, 3064 .e_ident[EI_DATA] = ELF_DATA, 3065 .e_ident[EI_VERSION] = EV_CURRENT, 3066 .e_type = ET_EXEC, 3067 .e_machine = ELF_HOST_MACHINE, 3068 .e_version = EV_CURRENT, 3069 .e_phoff = offsetof(struct ElfImage, phdr), 3070 .e_shoff = offsetof(struct ElfImage, shdr), 3071 .e_ehsize = sizeof(ElfW(Shdr)), 3072 .e_phentsize = sizeof(ElfW(Phdr)), 3073 .e_phnum = 1, 3074 .e_shentsize = sizeof(ElfW(Shdr)), 3075 .e_shnum = ARRAY_SIZE(img->shdr), 3076 .e_shstrndx = ARRAY_SIZE(img->shdr) - 1, 3077 #ifdef ELF_HOST_FLAGS 3078 .e_flags = ELF_HOST_FLAGS, 3079 #endif 3080 #ifdef ELF_OSABI 3081 .e_ident[EI_OSABI] = ELF_OSABI, 3082 #endif 3083 }, 3084 .phdr = { 3085 .p_type = PT_LOAD, 3086 .p_flags = PF_X, 3087 }, 3088 .shdr = { 3089 [0] = { .sh_type = SHT_NULL }, 3090 /* Trick: The contents of code_gen_buffer are not present in 3091 this fake ELF file; that got allocated elsewhere. Therefore 3092 we mark .text as SHT_NOBITS (similar to .bss) so that readers 3093 will not look for contents. We can record any address. */ 3094 [1] = { /* .text */ 3095 .sh_type = SHT_NOBITS, 3096 .sh_flags = SHF_EXECINSTR | SHF_ALLOC, 3097 }, 3098 [2] = { /* .debug_info */ 3099 .sh_type = SHT_PROGBITS, 3100 .sh_offset = offsetof(struct ElfImage, di), 3101 .sh_size = sizeof(struct DebugInfo), 3102 }, 3103 [3] = { /* .debug_abbrev */ 3104 .sh_type = SHT_PROGBITS, 3105 .sh_offset = offsetof(struct ElfImage, da), 3106 .sh_size = sizeof(img->da), 3107 }, 3108 [4] = { /* .debug_frame */ 3109 .sh_type = SHT_PROGBITS, 3110 .sh_offset = sizeof(struct ElfImage), 3111 }, 3112 [5] = { /* .symtab */ 3113 .sh_type = SHT_SYMTAB, 3114 .sh_offset = offsetof(struct ElfImage, sym), 3115 .sh_size = sizeof(img->sym), 3116 .sh_info = 1, 3117 .sh_link = ARRAY_SIZE(img->shdr) - 1, 3118 .sh_entsize = sizeof(ElfW(Sym)), 3119 }, 3120 [6] = { /* .strtab */ 3121 .sh_type = SHT_STRTAB, 3122 .sh_offset = offsetof(struct ElfImage, str), 3123 .sh_size = sizeof(img->str), 3124 } 3125 }, 3126 .sym = { 3127 [1] = { /* code_gen_buffer */ 3128 .st_info = ELF_ST_INFO(STB_GLOBAL, STT_FUNC), 3129 .st_shndx = 1, 3130 } 3131 }, 3132 .di = { 3133 .len = sizeof(struct DebugInfo) - 4, 3134 .version = 2, 3135 .ptr_size = sizeof(void *), 3136 .cu_die = 1, 3137 .cu_lang = 0x8001, /* DW_LANG_Mips_Assembler */ 3138 .fn_die = 2, 3139 .fn_name = "code_gen_buffer" 3140 }, 3141 .da = { 3142 1, /* abbrev number (the cu) */ 3143 0x11, 1, /* DW_TAG_compile_unit, has children */ 3144 0x13, 0x5, /* DW_AT_language, DW_FORM_data2 */ 3145 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */ 3146 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */ 3147 0, 0, /* end of abbrev */ 3148 2, /* abbrev number (the fn) */ 3149 0x2e, 0, /* DW_TAG_subprogram, no children */ 3150 0x3, 0x8, /* DW_AT_name, DW_FORM_string */ 3151 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */ 3152 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */ 3153 0, 0, /* end of abbrev */ 3154 0 /* no more abbrev */ 3155 }, 3156 .str = "\0" ".text\0" ".debug_info\0" ".debug_abbrev\0" 3157 ".debug_frame\0" ".symtab\0" ".strtab\0" "code_gen_buffer", 3158 }; 3159 3160 /* We only need a single jit entry; statically allocate it. */ 3161 static struct jit_code_entry one_entry; 3162 3163 uintptr_t buf = (uintptr_t)buf_ptr; 3164 size_t img_size = sizeof(struct ElfImage) + debug_frame_size; 3165 DebugFrameHeader *dfh; 3166 3167 img = g_malloc(img_size); 3168 *img = img_template; 3169 3170 img->phdr.p_vaddr = buf; 3171 img->phdr.p_paddr = buf; 3172 img->phdr.p_memsz = buf_size; 3173 3174 img->shdr[1].sh_name = find_string(img->str, ".text"); 3175 img->shdr[1].sh_addr = buf; 3176 img->shdr[1].sh_size = buf_size; 3177 3178 img->shdr[2].sh_name = find_string(img->str, ".debug_info"); 3179 img->shdr[3].sh_name = find_string(img->str, ".debug_abbrev"); 3180 3181 img->shdr[4].sh_name = find_string(img->str, ".debug_frame"); 3182 img->shdr[4].sh_size = debug_frame_size; 3183 3184 img->shdr[5].sh_name = find_string(img->str, ".symtab"); 3185 img->shdr[6].sh_name = find_string(img->str, ".strtab"); 3186 3187 img->sym[1].st_name = find_string(img->str, "code_gen_buffer"); 3188 img->sym[1].st_value = buf; 3189 img->sym[1].st_size = buf_size; 3190 3191 img->di.cu_low_pc = buf; 3192 img->di.cu_high_pc = buf + buf_size; 3193 img->di.fn_low_pc = buf; 3194 img->di.fn_high_pc = buf + buf_size; 3195 3196 dfh = (DebugFrameHeader *)(img + 1); 3197 memcpy(dfh, debug_frame, debug_frame_size); 3198 dfh->fde.func_start = buf; 3199 dfh->fde.func_len = buf_size; 3200 3201 #ifdef DEBUG_JIT 3202 /* Enable this block to be able to debug the ELF image file creation. 3203 One can use readelf, objdump, or other inspection utilities. */ 3204 { 3205 FILE *f = fopen("/tmp/qemu.jit", "w+b"); 3206 if (f) { 3207 if (fwrite(img, img_size, 1, f) != img_size) { 3208 /* Avoid stupid unused return value warning for fwrite. */ 3209 } 3210 fclose(f); 3211 } 3212 } 3213 #endif 3214 3215 one_entry.symfile_addr = img; 3216 one_entry.symfile_size = img_size; 3217 3218 __jit_debug_descriptor.action_flag = JIT_REGISTER_FN; 3219 __jit_debug_descriptor.relevant_entry = &one_entry; 3220 __jit_debug_descriptor.first_entry = &one_entry; 3221 __jit_debug_register_code(); 3222 } 3223 #else 3224 /* No support for the feature. Provide the entry point expected by exec.c, 3225 and implement the internal function we declared earlier. */ 3226 3227 static void tcg_register_jit_int(void *buf, size_t size, 3228 const void *debug_frame, 3229 size_t debug_frame_size) 3230 { 3231 } 3232 3233 void tcg_register_jit(void *buf, size_t buf_size) 3234 { 3235 } 3236 #endif /* ELF_HOST_MACHINE */ 3237