1 /* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 27 /* Define to jump the ELF file used to communicate with GDB. */ 28 #undef DEBUG_JIT 29 30 #include "qemu/error-report.h" 31 #include "qemu/cutils.h" 32 #include "qemu/host-utils.h" 33 #include "qemu/qemu-print.h" 34 #include "qemu/cacheflush.h" 35 #include "qemu/cacheinfo.h" 36 #include "qemu/timer.h" 37 #include "exec/translation-block.h" 38 #include "exec/tlb-common.h" 39 #include "tcg/startup.h" 40 #include "tcg/tcg-op-common.h" 41 42 #if UINTPTR_MAX == UINT32_MAX 43 # define ELF_CLASS ELFCLASS32 44 #else 45 # define ELF_CLASS ELFCLASS64 46 #endif 47 #if HOST_BIG_ENDIAN 48 # define ELF_DATA ELFDATA2MSB 49 #else 50 # define ELF_DATA ELFDATA2LSB 51 #endif 52 53 #include "elf.h" 54 #include "exec/log.h" 55 #include "tcg/tcg-ldst.h" 56 #include "tcg/tcg-temp-internal.h" 57 #include "tcg-internal.h" 58 #include "tcg/perf.h" 59 #include "tcg-has.h" 60 #ifdef CONFIG_USER_ONLY 61 #include "user/guest-base.h" 62 #endif 63 64 /* Forward declarations for functions declared in tcg-target.c.inc and 65 used here. */ 66 static void tcg_target_init(TCGContext *s); 67 static void tcg_target_qemu_prologue(TCGContext *s); 68 static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 69 intptr_t value, intptr_t addend); 70 static void tcg_out_nop_fill(tcg_insn_unit *p, int count); 71 72 typedef struct TCGLabelQemuLdst TCGLabelQemuLdst; 73 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l); 74 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l); 75 76 /* The CIE and FDE header definitions will be common to all hosts. */ 77 typedef struct { 78 uint32_t len __attribute__((aligned((sizeof(void *))))); 79 uint32_t id; 80 uint8_t version; 81 char augmentation[1]; 82 uint8_t code_align; 83 uint8_t data_align; 84 uint8_t return_column; 85 } DebugFrameCIE; 86 87 typedef struct QEMU_PACKED { 88 uint32_t len __attribute__((aligned((sizeof(void *))))); 89 uint32_t cie_offset; 90 uintptr_t func_start; 91 uintptr_t func_len; 92 } DebugFrameFDEHeader; 93 94 typedef struct QEMU_PACKED { 95 DebugFrameCIE cie; 96 DebugFrameFDEHeader fde; 97 } DebugFrameHeader; 98 99 struct TCGLabelQemuLdst { 100 bool is_ld; /* qemu_ld: true, qemu_st: false */ 101 MemOpIdx oi; 102 TCGType type; /* result type of a load */ 103 TCGReg addr_reg; /* reg index for guest virtual addr */ 104 TCGReg datalo_reg; /* reg index for low word to be loaded or stored */ 105 TCGReg datahi_reg; /* reg index for high word to be loaded or stored */ 106 const tcg_insn_unit *raddr; /* addr of the next IR of qemu_ld/st IR */ 107 tcg_insn_unit *label_ptr[2]; /* label pointers to be updated */ 108 QSIMPLEQ_ENTRY(TCGLabelQemuLdst) next; 109 }; 110 111 static void tcg_register_jit_int(const void *buf, size_t size, 112 const void *debug_frame, 113 size_t debug_frame_size) 114 __attribute__((unused)); 115 116 /* Forward declarations for functions declared and used in tcg-target.c.inc. */ 117 static void tcg_out_tb_start(TCGContext *s); 118 static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1, 119 intptr_t arg2); 120 static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg); 121 static void tcg_out_movi(TCGContext *s, TCGType type, 122 TCGReg ret, tcg_target_long arg); 123 static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg); 124 static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg); 125 static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg); 126 static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg); 127 static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg); 128 static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg); 129 static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg); 130 static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg); 131 static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg ret, TCGReg arg); 132 static void tcg_out_addi_ptr(TCGContext *s, TCGReg, TCGReg, tcg_target_long); 133 static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2); 134 static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg); 135 static void tcg_out_goto_tb(TCGContext *s, int which); 136 static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, 137 const TCGArg args[TCG_MAX_OP_ARGS], 138 const int const_args[TCG_MAX_OP_ARGS]); 139 #if TCG_TARGET_MAYBE_vec 140 static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 141 TCGReg dst, TCGReg src); 142 static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 143 TCGReg dst, TCGReg base, intptr_t offset); 144 static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 145 TCGReg dst, int64_t arg); 146 static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 147 unsigned vecl, unsigned vece, 148 const TCGArg args[TCG_MAX_OP_ARGS], 149 const int const_args[TCG_MAX_OP_ARGS]); 150 #else 151 static inline bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 152 TCGReg dst, TCGReg src) 153 { 154 g_assert_not_reached(); 155 } 156 static inline bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 157 TCGReg dst, TCGReg base, intptr_t offset) 158 { 159 g_assert_not_reached(); 160 } 161 static inline void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 162 TCGReg dst, int64_t arg) 163 { 164 g_assert_not_reached(); 165 } 166 static inline void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 167 unsigned vecl, unsigned vece, 168 const TCGArg args[TCG_MAX_OP_ARGS], 169 const int const_args[TCG_MAX_OP_ARGS]) 170 { 171 g_assert_not_reached(); 172 } 173 int tcg_can_emit_vec_op(TCGOpcode o, TCGType t, unsigned ve) 174 { 175 return 0; 176 } 177 #endif 178 static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1, 179 intptr_t arg2); 180 static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 181 TCGReg base, intptr_t ofs); 182 static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target, 183 const TCGHelperInfo *info); 184 static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot); 185 static bool tcg_target_const_match(int64_t val, int ct, 186 TCGType type, TCGCond cond, int vece); 187 188 #ifndef CONFIG_USER_ONLY 189 #define guest_base ({ qemu_build_not_reached(); (uintptr_t)0; }) 190 #endif 191 192 typedef struct TCGLdstHelperParam { 193 TCGReg (*ra_gen)(TCGContext *s, const TCGLabelQemuLdst *l, int arg_reg); 194 unsigned ntmp; 195 int tmp[3]; 196 } TCGLdstHelperParam; 197 198 static void tcg_out_ld_helper_args(TCGContext *s, const TCGLabelQemuLdst *l, 199 const TCGLdstHelperParam *p) 200 __attribute__((unused)); 201 static void tcg_out_ld_helper_ret(TCGContext *s, const TCGLabelQemuLdst *l, 202 bool load_sign, const TCGLdstHelperParam *p) 203 __attribute__((unused)); 204 static void tcg_out_st_helper_args(TCGContext *s, const TCGLabelQemuLdst *l, 205 const TCGLdstHelperParam *p) 206 __attribute__((unused)); 207 208 static void * const qemu_ld_helpers[MO_SSIZE + 1] __attribute__((unused)) = { 209 [MO_UB] = helper_ldub_mmu, 210 [MO_SB] = helper_ldsb_mmu, 211 [MO_UW] = helper_lduw_mmu, 212 [MO_SW] = helper_ldsw_mmu, 213 [MO_UL] = helper_ldul_mmu, 214 [MO_UQ] = helper_ldq_mmu, 215 #if TCG_TARGET_REG_BITS == 64 216 [MO_SL] = helper_ldsl_mmu, 217 [MO_128] = helper_ld16_mmu, 218 #endif 219 }; 220 221 static void * const qemu_st_helpers[MO_SIZE + 1] __attribute__((unused)) = { 222 [MO_8] = helper_stb_mmu, 223 [MO_16] = helper_stw_mmu, 224 [MO_32] = helper_stl_mmu, 225 [MO_64] = helper_stq_mmu, 226 #if TCG_TARGET_REG_BITS == 64 227 [MO_128] = helper_st16_mmu, 228 #endif 229 }; 230 231 typedef struct { 232 MemOp atom; /* lg2 bits of atomicity required */ 233 MemOp align; /* lg2 bits of alignment to use */ 234 } TCGAtomAlign; 235 236 static TCGAtomAlign atom_and_align_for_opc(TCGContext *s, MemOp opc, 237 MemOp host_atom, bool allow_two_ops) 238 __attribute__((unused)); 239 240 #ifdef CONFIG_USER_ONLY 241 bool tcg_use_softmmu; 242 #endif 243 244 TCGContext tcg_init_ctx; 245 __thread TCGContext *tcg_ctx; 246 247 TCGContext **tcg_ctxs; 248 unsigned int tcg_cur_ctxs; 249 unsigned int tcg_max_ctxs; 250 TCGv_env tcg_env; 251 const void *tcg_code_gen_epilogue; 252 uintptr_t tcg_splitwx_diff; 253 254 #ifndef CONFIG_TCG_INTERPRETER 255 tcg_prologue_fn *tcg_qemu_tb_exec; 256 #endif 257 258 static TCGRegSet tcg_target_available_regs[TCG_TYPE_COUNT]; 259 static TCGRegSet tcg_target_call_clobber_regs; 260 261 #if TCG_TARGET_INSN_UNIT_SIZE == 1 262 static __attribute__((unused)) inline void tcg_out8(TCGContext *s, uint8_t v) 263 { 264 *s->code_ptr++ = v; 265 } 266 267 static __attribute__((unused)) inline void tcg_patch8(tcg_insn_unit *p, 268 uint8_t v) 269 { 270 *p = v; 271 } 272 #endif 273 274 #if TCG_TARGET_INSN_UNIT_SIZE <= 2 275 static __attribute__((unused)) inline void tcg_out16(TCGContext *s, uint16_t v) 276 { 277 if (TCG_TARGET_INSN_UNIT_SIZE == 2) { 278 *s->code_ptr++ = v; 279 } else { 280 tcg_insn_unit *p = s->code_ptr; 281 memcpy(p, &v, sizeof(v)); 282 s->code_ptr = p + (2 / TCG_TARGET_INSN_UNIT_SIZE); 283 } 284 } 285 286 static __attribute__((unused)) inline void tcg_patch16(tcg_insn_unit *p, 287 uint16_t v) 288 { 289 if (TCG_TARGET_INSN_UNIT_SIZE == 2) { 290 *p = v; 291 } else { 292 memcpy(p, &v, sizeof(v)); 293 } 294 } 295 #endif 296 297 #if TCG_TARGET_INSN_UNIT_SIZE <= 4 298 static __attribute__((unused)) inline void tcg_out32(TCGContext *s, uint32_t v) 299 { 300 if (TCG_TARGET_INSN_UNIT_SIZE == 4) { 301 *s->code_ptr++ = v; 302 } else { 303 tcg_insn_unit *p = s->code_ptr; 304 memcpy(p, &v, sizeof(v)); 305 s->code_ptr = p + (4 / TCG_TARGET_INSN_UNIT_SIZE); 306 } 307 } 308 309 static __attribute__((unused)) inline void tcg_patch32(tcg_insn_unit *p, 310 uint32_t v) 311 { 312 if (TCG_TARGET_INSN_UNIT_SIZE == 4) { 313 *p = v; 314 } else { 315 memcpy(p, &v, sizeof(v)); 316 } 317 } 318 #endif 319 320 #if TCG_TARGET_INSN_UNIT_SIZE <= 8 321 static __attribute__((unused)) inline void tcg_out64(TCGContext *s, uint64_t v) 322 { 323 if (TCG_TARGET_INSN_UNIT_SIZE == 8) { 324 *s->code_ptr++ = v; 325 } else { 326 tcg_insn_unit *p = s->code_ptr; 327 memcpy(p, &v, sizeof(v)); 328 s->code_ptr = p + (8 / TCG_TARGET_INSN_UNIT_SIZE); 329 } 330 } 331 332 static __attribute__((unused)) inline void tcg_patch64(tcg_insn_unit *p, 333 uint64_t v) 334 { 335 if (TCG_TARGET_INSN_UNIT_SIZE == 8) { 336 *p = v; 337 } else { 338 memcpy(p, &v, sizeof(v)); 339 } 340 } 341 #endif 342 343 /* label relocation processing */ 344 345 static void tcg_out_reloc(TCGContext *s, tcg_insn_unit *code_ptr, int type, 346 TCGLabel *l, intptr_t addend) 347 { 348 TCGRelocation *r = tcg_malloc(sizeof(TCGRelocation)); 349 350 r->type = type; 351 r->ptr = code_ptr; 352 r->addend = addend; 353 QSIMPLEQ_INSERT_TAIL(&l->relocs, r, next); 354 } 355 356 static void tcg_out_label(TCGContext *s, TCGLabel *l) 357 { 358 tcg_debug_assert(!l->has_value); 359 l->has_value = 1; 360 l->u.value_ptr = tcg_splitwx_to_rx(s->code_ptr); 361 } 362 363 TCGLabel *gen_new_label(void) 364 { 365 TCGContext *s = tcg_ctx; 366 TCGLabel *l = tcg_malloc(sizeof(TCGLabel)); 367 368 memset(l, 0, sizeof(TCGLabel)); 369 l->id = s->nb_labels++; 370 QSIMPLEQ_INIT(&l->branches); 371 QSIMPLEQ_INIT(&l->relocs); 372 373 QSIMPLEQ_INSERT_TAIL(&s->labels, l, next); 374 375 return l; 376 } 377 378 static bool tcg_resolve_relocs(TCGContext *s) 379 { 380 TCGLabel *l; 381 382 QSIMPLEQ_FOREACH(l, &s->labels, next) { 383 TCGRelocation *r; 384 uintptr_t value = l->u.value; 385 386 QSIMPLEQ_FOREACH(r, &l->relocs, next) { 387 if (!patch_reloc(r->ptr, r->type, value, r->addend)) { 388 return false; 389 } 390 } 391 } 392 return true; 393 } 394 395 static void set_jmp_reset_offset(TCGContext *s, int which) 396 { 397 /* 398 * We will check for overflow at the end of the opcode loop in 399 * tcg_gen_code, where we bound tcg_current_code_size to UINT16_MAX. 400 */ 401 s->gen_tb->jmp_reset_offset[which] = tcg_current_code_size(s); 402 } 403 404 static void G_GNUC_UNUSED set_jmp_insn_offset(TCGContext *s, int which) 405 { 406 /* 407 * We will check for overflow at the end of the opcode loop in 408 * tcg_gen_code, where we bound tcg_current_code_size to UINT16_MAX. 409 */ 410 s->gen_tb->jmp_insn_offset[which] = tcg_current_code_size(s); 411 } 412 413 static uintptr_t G_GNUC_UNUSED get_jmp_target_addr(TCGContext *s, int which) 414 { 415 /* 416 * Return the read-execute version of the pointer, for the benefit 417 * of any pc-relative addressing mode. 418 */ 419 return (uintptr_t)tcg_splitwx_to_rx(&s->gen_tb->jmp_target_addr[which]); 420 } 421 422 static int __attribute__((unused)) 423 tlb_mask_table_ofs(TCGContext *s, int which) 424 { 425 return (offsetof(CPUNegativeOffsetState, tlb.f[which]) - 426 sizeof(CPUNegativeOffsetState)); 427 } 428 429 /* Signal overflow, starting over with fewer guest insns. */ 430 static G_NORETURN 431 void tcg_raise_tb_overflow(TCGContext *s) 432 { 433 siglongjmp(s->jmp_trans, -2); 434 } 435 436 /* 437 * Used by tcg_out_movext{1,2} to hold the arguments for tcg_out_movext. 438 * By the time we arrive at tcg_out_movext1, @dst is always a TCGReg. 439 * 440 * However, tcg_out_helper_load_slots reuses this field to hold an 441 * argument slot number (which may designate a argument register or an 442 * argument stack slot), converting to TCGReg once all arguments that 443 * are destined for the stack are processed. 444 */ 445 typedef struct TCGMovExtend { 446 unsigned dst; 447 TCGReg src; 448 TCGType dst_type; 449 TCGType src_type; 450 MemOp src_ext; 451 } TCGMovExtend; 452 453 /** 454 * tcg_out_movext -- move and extend 455 * @s: tcg context 456 * @dst_type: integral type for destination 457 * @dst: destination register 458 * @src_type: integral type for source 459 * @src_ext: extension to apply to source 460 * @src: source register 461 * 462 * Move or extend @src into @dst, depending on @src_ext and the types. 463 */ 464 static void tcg_out_movext(TCGContext *s, TCGType dst_type, TCGReg dst, 465 TCGType src_type, MemOp src_ext, TCGReg src) 466 { 467 switch (src_ext) { 468 case MO_UB: 469 tcg_out_ext8u(s, dst, src); 470 break; 471 case MO_SB: 472 tcg_out_ext8s(s, dst_type, dst, src); 473 break; 474 case MO_UW: 475 tcg_out_ext16u(s, dst, src); 476 break; 477 case MO_SW: 478 tcg_out_ext16s(s, dst_type, dst, src); 479 break; 480 case MO_UL: 481 case MO_SL: 482 if (dst_type == TCG_TYPE_I32) { 483 if (src_type == TCG_TYPE_I32) { 484 tcg_out_mov(s, TCG_TYPE_I32, dst, src); 485 } else { 486 tcg_out_extrl_i64_i32(s, dst, src); 487 } 488 } else if (src_type == TCG_TYPE_I32) { 489 if (src_ext & MO_SIGN) { 490 tcg_out_exts_i32_i64(s, dst, src); 491 } else { 492 tcg_out_extu_i32_i64(s, dst, src); 493 } 494 } else { 495 if (src_ext & MO_SIGN) { 496 tcg_out_ext32s(s, dst, src); 497 } else { 498 tcg_out_ext32u(s, dst, src); 499 } 500 } 501 break; 502 case MO_UQ: 503 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 504 if (dst_type == TCG_TYPE_I32) { 505 tcg_out_extrl_i64_i32(s, dst, src); 506 } else { 507 tcg_out_mov(s, TCG_TYPE_I64, dst, src); 508 } 509 break; 510 default: 511 g_assert_not_reached(); 512 } 513 } 514 515 /* Minor variations on a theme, using a structure. */ 516 static void tcg_out_movext1_new_src(TCGContext *s, const TCGMovExtend *i, 517 TCGReg src) 518 { 519 tcg_out_movext(s, i->dst_type, i->dst, i->src_type, i->src_ext, src); 520 } 521 522 static void tcg_out_movext1(TCGContext *s, const TCGMovExtend *i) 523 { 524 tcg_out_movext1_new_src(s, i, i->src); 525 } 526 527 /** 528 * tcg_out_movext2 -- move and extend two pair 529 * @s: tcg context 530 * @i1: first move description 531 * @i2: second move description 532 * @scratch: temporary register, or -1 for none 533 * 534 * As tcg_out_movext, for both @i1 and @i2, caring for overlap 535 * between the sources and destinations. 536 */ 537 538 static void tcg_out_movext2(TCGContext *s, const TCGMovExtend *i1, 539 const TCGMovExtend *i2, int scratch) 540 { 541 TCGReg src1 = i1->src; 542 TCGReg src2 = i2->src; 543 544 if (i1->dst != src2) { 545 tcg_out_movext1(s, i1); 546 tcg_out_movext1(s, i2); 547 return; 548 } 549 if (i2->dst == src1) { 550 TCGType src1_type = i1->src_type; 551 TCGType src2_type = i2->src_type; 552 553 if (tcg_out_xchg(s, MAX(src1_type, src2_type), src1, src2)) { 554 /* The data is now in the correct registers, now extend. */ 555 src1 = i2->src; 556 src2 = i1->src; 557 } else { 558 tcg_debug_assert(scratch >= 0); 559 tcg_out_mov(s, src1_type, scratch, src1); 560 src1 = scratch; 561 } 562 } 563 tcg_out_movext1_new_src(s, i2, src2); 564 tcg_out_movext1_new_src(s, i1, src1); 565 } 566 567 /** 568 * tcg_out_movext3 -- move and extend three pair 569 * @s: tcg context 570 * @i1: first move description 571 * @i2: second move description 572 * @i3: third move description 573 * @scratch: temporary register, or -1 for none 574 * 575 * As tcg_out_movext, for all of @i1, @i2 and @i3, caring for overlap 576 * between the sources and destinations. 577 */ 578 579 static void tcg_out_movext3(TCGContext *s, const TCGMovExtend *i1, 580 const TCGMovExtend *i2, const TCGMovExtend *i3, 581 int scratch) 582 { 583 TCGReg src1 = i1->src; 584 TCGReg src2 = i2->src; 585 TCGReg src3 = i3->src; 586 587 if (i1->dst != src2 && i1->dst != src3) { 588 tcg_out_movext1(s, i1); 589 tcg_out_movext2(s, i2, i3, scratch); 590 return; 591 } 592 if (i2->dst != src1 && i2->dst != src3) { 593 tcg_out_movext1(s, i2); 594 tcg_out_movext2(s, i1, i3, scratch); 595 return; 596 } 597 if (i3->dst != src1 && i3->dst != src2) { 598 tcg_out_movext1(s, i3); 599 tcg_out_movext2(s, i1, i2, scratch); 600 return; 601 } 602 603 /* 604 * There is a cycle. Since there are only 3 nodes, the cycle is 605 * either "clockwise" or "anti-clockwise", and can be solved with 606 * a single scratch or two xchg. 607 */ 608 if (i1->dst == src2 && i2->dst == src3 && i3->dst == src1) { 609 /* "Clockwise" */ 610 if (tcg_out_xchg(s, MAX(i1->src_type, i2->src_type), src1, src2)) { 611 tcg_out_xchg(s, MAX(i2->src_type, i3->src_type), src2, src3); 612 /* The data is now in the correct registers, now extend. */ 613 tcg_out_movext1_new_src(s, i1, i1->dst); 614 tcg_out_movext1_new_src(s, i2, i2->dst); 615 tcg_out_movext1_new_src(s, i3, i3->dst); 616 } else { 617 tcg_debug_assert(scratch >= 0); 618 tcg_out_mov(s, i1->src_type, scratch, src1); 619 tcg_out_movext1(s, i3); 620 tcg_out_movext1(s, i2); 621 tcg_out_movext1_new_src(s, i1, scratch); 622 } 623 } else if (i1->dst == src3 && i2->dst == src1 && i3->dst == src2) { 624 /* "Anti-clockwise" */ 625 if (tcg_out_xchg(s, MAX(i2->src_type, i3->src_type), src2, src3)) { 626 tcg_out_xchg(s, MAX(i1->src_type, i2->src_type), src1, src2); 627 /* The data is now in the correct registers, now extend. */ 628 tcg_out_movext1_new_src(s, i1, i1->dst); 629 tcg_out_movext1_new_src(s, i2, i2->dst); 630 tcg_out_movext1_new_src(s, i3, i3->dst); 631 } else { 632 tcg_debug_assert(scratch >= 0); 633 tcg_out_mov(s, i1->src_type, scratch, src1); 634 tcg_out_movext1(s, i2); 635 tcg_out_movext1(s, i3); 636 tcg_out_movext1_new_src(s, i1, scratch); 637 } 638 } else { 639 g_assert_not_reached(); 640 } 641 } 642 643 /* 644 * Allocate a new TCGLabelQemuLdst entry. 645 */ 646 647 __attribute__((unused)) 648 static TCGLabelQemuLdst *new_ldst_label(TCGContext *s) 649 { 650 TCGLabelQemuLdst *l = tcg_malloc(sizeof(*l)); 651 652 memset(l, 0, sizeof(*l)); 653 QSIMPLEQ_INSERT_TAIL(&s->ldst_labels, l, next); 654 655 return l; 656 } 657 658 /* 659 * Allocate new constant pool entries. 660 */ 661 662 typedef struct TCGLabelPoolData { 663 struct TCGLabelPoolData *next; 664 tcg_insn_unit *label; 665 intptr_t addend; 666 int rtype; 667 unsigned nlong; 668 tcg_target_ulong data[]; 669 } TCGLabelPoolData; 670 671 static TCGLabelPoolData *new_pool_alloc(TCGContext *s, int nlong, int rtype, 672 tcg_insn_unit *label, intptr_t addend) 673 { 674 TCGLabelPoolData *n = tcg_malloc(sizeof(TCGLabelPoolData) 675 + sizeof(tcg_target_ulong) * nlong); 676 677 n->label = label; 678 n->addend = addend; 679 n->rtype = rtype; 680 n->nlong = nlong; 681 return n; 682 } 683 684 static void new_pool_insert(TCGContext *s, TCGLabelPoolData *n) 685 { 686 TCGLabelPoolData *i, **pp; 687 int nlong = n->nlong; 688 689 /* Insertion sort on the pool. */ 690 for (pp = &s->pool_labels; (i = *pp) != NULL; pp = &i->next) { 691 if (nlong > i->nlong) { 692 break; 693 } 694 if (nlong < i->nlong) { 695 continue; 696 } 697 if (memcmp(n->data, i->data, sizeof(tcg_target_ulong) * nlong) >= 0) { 698 break; 699 } 700 } 701 n->next = *pp; 702 *pp = n; 703 } 704 705 /* The "usual" for generic integer code. */ 706 __attribute__((unused)) 707 static void new_pool_label(TCGContext *s, tcg_target_ulong d, int rtype, 708 tcg_insn_unit *label, intptr_t addend) 709 { 710 TCGLabelPoolData *n = new_pool_alloc(s, 1, rtype, label, addend); 711 n->data[0] = d; 712 new_pool_insert(s, n); 713 } 714 715 /* For v64 or v128, depending on the host. */ 716 __attribute__((unused)) 717 static void new_pool_l2(TCGContext *s, int rtype, tcg_insn_unit *label, 718 intptr_t addend, tcg_target_ulong d0, 719 tcg_target_ulong d1) 720 { 721 TCGLabelPoolData *n = new_pool_alloc(s, 2, rtype, label, addend); 722 n->data[0] = d0; 723 n->data[1] = d1; 724 new_pool_insert(s, n); 725 } 726 727 /* For v128 or v256, depending on the host. */ 728 __attribute__((unused)) 729 static void new_pool_l4(TCGContext *s, int rtype, tcg_insn_unit *label, 730 intptr_t addend, tcg_target_ulong d0, 731 tcg_target_ulong d1, tcg_target_ulong d2, 732 tcg_target_ulong d3) 733 { 734 TCGLabelPoolData *n = new_pool_alloc(s, 4, rtype, label, addend); 735 n->data[0] = d0; 736 n->data[1] = d1; 737 n->data[2] = d2; 738 n->data[3] = d3; 739 new_pool_insert(s, n); 740 } 741 742 /* For v256, for 32-bit host. */ 743 __attribute__((unused)) 744 static void new_pool_l8(TCGContext *s, int rtype, tcg_insn_unit *label, 745 intptr_t addend, tcg_target_ulong d0, 746 tcg_target_ulong d1, tcg_target_ulong d2, 747 tcg_target_ulong d3, tcg_target_ulong d4, 748 tcg_target_ulong d5, tcg_target_ulong d6, 749 tcg_target_ulong d7) 750 { 751 TCGLabelPoolData *n = new_pool_alloc(s, 8, rtype, label, addend); 752 n->data[0] = d0; 753 n->data[1] = d1; 754 n->data[2] = d2; 755 n->data[3] = d3; 756 n->data[4] = d4; 757 n->data[5] = d5; 758 n->data[6] = d6; 759 n->data[7] = d7; 760 new_pool_insert(s, n); 761 } 762 763 /* 764 * Generate TB finalization at the end of block 765 */ 766 767 static int tcg_out_ldst_finalize(TCGContext *s) 768 { 769 TCGLabelQemuLdst *lb; 770 771 /* qemu_ld/st slow paths */ 772 QSIMPLEQ_FOREACH(lb, &s->ldst_labels, next) { 773 if (lb->is_ld 774 ? !tcg_out_qemu_ld_slow_path(s, lb) 775 : !tcg_out_qemu_st_slow_path(s, lb)) { 776 return -2; 777 } 778 779 /* 780 * Test for (pending) buffer overflow. The assumption is that any 781 * one operation beginning below the high water mark cannot overrun 782 * the buffer completely. Thus we can test for overflow after 783 * generating code without having to check during generation. 784 */ 785 if (unlikely((void *)s->code_ptr > s->code_gen_highwater)) { 786 return -1; 787 } 788 } 789 return 0; 790 } 791 792 static int tcg_out_pool_finalize(TCGContext *s) 793 { 794 TCGLabelPoolData *p = s->pool_labels; 795 TCGLabelPoolData *l = NULL; 796 void *a; 797 798 if (p == NULL) { 799 return 0; 800 } 801 802 /* 803 * ??? Round up to qemu_icache_linesize, but then do not round 804 * again when allocating the next TranslationBlock structure. 805 */ 806 a = (void *)ROUND_UP((uintptr_t)s->code_ptr, 807 sizeof(tcg_target_ulong) * p->nlong); 808 tcg_out_nop_fill(s->code_ptr, (tcg_insn_unit *)a - s->code_ptr); 809 s->data_gen_ptr = a; 810 811 for (; p != NULL; p = p->next) { 812 size_t size = sizeof(tcg_target_ulong) * p->nlong; 813 uintptr_t value; 814 815 if (!l || l->nlong != p->nlong || memcmp(l->data, p->data, size)) { 816 if (unlikely(a > s->code_gen_highwater)) { 817 return -1; 818 } 819 memcpy(a, p->data, size); 820 a += size; 821 l = p; 822 } 823 824 value = (uintptr_t)tcg_splitwx_to_rx(a) - size; 825 if (!patch_reloc(p->label, p->rtype, value, p->addend)) { 826 return -2; 827 } 828 } 829 830 s->code_ptr = a; 831 return 0; 832 } 833 834 #define C_PFX1(P, A) P##A 835 #define C_PFX2(P, A, B) P##A##_##B 836 #define C_PFX3(P, A, B, C) P##A##_##B##_##C 837 #define C_PFX4(P, A, B, C, D) P##A##_##B##_##C##_##D 838 #define C_PFX5(P, A, B, C, D, E) P##A##_##B##_##C##_##D##_##E 839 #define C_PFX6(P, A, B, C, D, E, F) P##A##_##B##_##C##_##D##_##E##_##F 840 841 /* Define an enumeration for the various combinations. */ 842 843 #define C_O0_I1(I1) C_PFX1(c_o0_i1_, I1), 844 #define C_O0_I2(I1, I2) C_PFX2(c_o0_i2_, I1, I2), 845 #define C_O0_I3(I1, I2, I3) C_PFX3(c_o0_i3_, I1, I2, I3), 846 #define C_O0_I4(I1, I2, I3, I4) C_PFX4(c_o0_i4_, I1, I2, I3, I4), 847 848 #define C_O1_I1(O1, I1) C_PFX2(c_o1_i1_, O1, I1), 849 #define C_O1_I2(O1, I1, I2) C_PFX3(c_o1_i2_, O1, I1, I2), 850 #define C_O1_I3(O1, I1, I2, I3) C_PFX4(c_o1_i3_, O1, I1, I2, I3), 851 #define C_O1_I4(O1, I1, I2, I3, I4) C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4), 852 853 #define C_N1_I2(O1, I1, I2) C_PFX3(c_n1_i2_, O1, I1, I2), 854 #define C_N1O1_I1(O1, O2, I1) C_PFX3(c_n1o1_i1_, O1, O2, I1), 855 #define C_N2_I1(O1, O2, I1) C_PFX3(c_n2_i1_, O1, O2, I1), 856 857 #define C_O2_I1(O1, O2, I1) C_PFX3(c_o2_i1_, O1, O2, I1), 858 #define C_O2_I2(O1, O2, I1, I2) C_PFX4(c_o2_i2_, O1, O2, I1, I2), 859 #define C_O2_I3(O1, O2, I1, I2, I3) C_PFX5(c_o2_i3_, O1, O2, I1, I2, I3), 860 #define C_O2_I4(O1, O2, I1, I2, I3, I4) C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, I4), 861 #define C_N1_O1_I4(O1, O2, I1, I2, I3, I4) C_PFX6(c_n1_o1_i4_, O1, O2, I1, I2, I3, I4), 862 863 typedef enum { 864 C_Dynamic = -2, 865 C_NotImplemented = -1, 866 #include "tcg-target-con-set.h" 867 } TCGConstraintSetIndex; 868 869 static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode, TCGType, unsigned); 870 871 #undef C_O0_I1 872 #undef C_O0_I2 873 #undef C_O0_I3 874 #undef C_O0_I4 875 #undef C_O1_I1 876 #undef C_O1_I2 877 #undef C_O1_I3 878 #undef C_O1_I4 879 #undef C_N1_I2 880 #undef C_N1O1_I1 881 #undef C_N2_I1 882 #undef C_O2_I1 883 #undef C_O2_I2 884 #undef C_O2_I3 885 #undef C_O2_I4 886 #undef C_N1_O1_I4 887 888 /* Put all of the constraint sets into an array, indexed by the enum. */ 889 890 typedef struct TCGConstraintSet { 891 uint8_t nb_oargs, nb_iargs; 892 const char *args_ct_str[TCG_MAX_OP_ARGS]; 893 } TCGConstraintSet; 894 895 #define C_O0_I1(I1) { 0, 1, { #I1 } }, 896 #define C_O0_I2(I1, I2) { 0, 2, { #I1, #I2 } }, 897 #define C_O0_I3(I1, I2, I3) { 0, 3, { #I1, #I2, #I3 } }, 898 #define C_O0_I4(I1, I2, I3, I4) { 0, 4, { #I1, #I2, #I3, #I4 } }, 899 900 #define C_O1_I1(O1, I1) { 1, 1, { #O1, #I1 } }, 901 #define C_O1_I2(O1, I1, I2) { 1, 2, { #O1, #I1, #I2 } }, 902 #define C_O1_I3(O1, I1, I2, I3) { 1, 3, { #O1, #I1, #I2, #I3 } }, 903 #define C_O1_I4(O1, I1, I2, I3, I4) { 1, 4, { #O1, #I1, #I2, #I3, #I4 } }, 904 905 #define C_N1_I2(O1, I1, I2) { 1, 2, { "&" #O1, #I1, #I2 } }, 906 #define C_N1O1_I1(O1, O2, I1) { 2, 1, { "&" #O1, #O2, #I1 } }, 907 #define C_N2_I1(O1, O2, I1) { 2, 1, { "&" #O1, "&" #O2, #I1 } }, 908 909 #define C_O2_I1(O1, O2, I1) { 2, 1, { #O1, #O2, #I1 } }, 910 #define C_O2_I2(O1, O2, I1, I2) { 2, 2, { #O1, #O2, #I1, #I2 } }, 911 #define C_O2_I3(O1, O2, I1, I2, I3) { 2, 3, { #O1, #O2, #I1, #I2, #I3 } }, 912 #define C_O2_I4(O1, O2, I1, I2, I3, I4) { 2, 4, { #O1, #O2, #I1, #I2, #I3, #I4 } }, 913 #define C_N1_O1_I4(O1, O2, I1, I2, I3, I4) { 2, 4, { "&" #O1, #O2, #I1, #I2, #I3, #I4 } }, 914 915 static const TCGConstraintSet constraint_sets[] = { 916 #include "tcg-target-con-set.h" 917 }; 918 919 #undef C_O0_I1 920 #undef C_O0_I2 921 #undef C_O0_I3 922 #undef C_O0_I4 923 #undef C_O1_I1 924 #undef C_O1_I2 925 #undef C_O1_I3 926 #undef C_O1_I4 927 #undef C_N1_I2 928 #undef C_N1O1_I1 929 #undef C_N2_I1 930 #undef C_O2_I1 931 #undef C_O2_I2 932 #undef C_O2_I3 933 #undef C_O2_I4 934 #undef C_N1_O1_I4 935 936 /* Expand the enumerator to be returned from tcg_target_op_def(). */ 937 938 #define C_O0_I1(I1) C_PFX1(c_o0_i1_, I1) 939 #define C_O0_I2(I1, I2) C_PFX2(c_o0_i2_, I1, I2) 940 #define C_O0_I3(I1, I2, I3) C_PFX3(c_o0_i3_, I1, I2, I3) 941 #define C_O0_I4(I1, I2, I3, I4) C_PFX4(c_o0_i4_, I1, I2, I3, I4) 942 943 #define C_O1_I1(O1, I1) C_PFX2(c_o1_i1_, O1, I1) 944 #define C_O1_I2(O1, I1, I2) C_PFX3(c_o1_i2_, O1, I1, I2) 945 #define C_O1_I3(O1, I1, I2, I3) C_PFX4(c_o1_i3_, O1, I1, I2, I3) 946 #define C_O1_I4(O1, I1, I2, I3, I4) C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4) 947 948 #define C_N1_I2(O1, I1, I2) C_PFX3(c_n1_i2_, O1, I1, I2) 949 #define C_N1O1_I1(O1, O2, I1) C_PFX3(c_n1o1_i1_, O1, O2, I1) 950 #define C_N2_I1(O1, O2, I1) C_PFX3(c_n2_i1_, O1, O2, I1) 951 952 #define C_O2_I1(O1, O2, I1) C_PFX3(c_o2_i1_, O1, O2, I1) 953 #define C_O2_I2(O1, O2, I1, I2) C_PFX4(c_o2_i2_, O1, O2, I1, I2) 954 #define C_O2_I3(O1, O2, I1, I2, I3) C_PFX5(c_o2_i3_, O1, O2, I1, I2, I3) 955 #define C_O2_I4(O1, O2, I1, I2, I3, I4) C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, I4) 956 #define C_N1_O1_I4(O1, O2, I1, I2, I3, I4) C_PFX6(c_n1_o1_i4_, O1, O2, I1, I2, I3, I4) 957 958 /* 959 * TCGOutOp is the base class for a set of structures that describe how 960 * to generate code for a given TCGOpcode. 961 * 962 * @static_constraint: 963 * C_NotImplemented: The TCGOpcode is not supported by the backend. 964 * C_Dynamic: Use @dynamic_constraint to select a constraint set 965 * based on any of @type, @flags, or host isa. 966 * Otherwise: The register allocation constrains for the TCGOpcode. 967 * 968 * Subclasses of TCGOutOp will define a set of output routines that may 969 * be used. Such routines will often be selected by the set of registers 970 * and constants that come out of register allocation. The set of 971 * routines that are provided will guide the set of constraints that are 972 * legal. In particular, assume that tcg_optimize() has done its job in 973 * swapping commutative operands and folding operations for which all 974 * operands are constant. 975 */ 976 typedef struct TCGOutOp { 977 TCGConstraintSetIndex static_constraint; 978 TCGConstraintSetIndex (*dynamic_constraint)(TCGType type, unsigned flags); 979 } TCGOutOp; 980 981 typedef struct TCGOutOpBinary { 982 TCGOutOp base; 983 void (*out_rrr)(TCGContext *s, TCGType type, 984 TCGReg a0, TCGReg a1, TCGReg a2); 985 void (*out_rri)(TCGContext *s, TCGType type, 986 TCGReg a0, TCGReg a1, tcg_target_long a2); 987 } TCGOutOpBinary; 988 989 typedef struct TCGOutOpBrcond { 990 TCGOutOp base; 991 void (*out_rr)(TCGContext *s, TCGType type, TCGCond cond, 992 TCGReg a1, TCGReg a2, TCGLabel *label); 993 void (*out_ri)(TCGContext *s, TCGType type, TCGCond cond, 994 TCGReg a1, tcg_target_long a2, TCGLabel *label); 995 } TCGOutOpBrcond; 996 997 typedef struct TCGOutOpBrcond2 { 998 TCGOutOp base; 999 void (*out)(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, 1000 TCGArg bl, bool const_bl, 1001 TCGArg bh, bool const_bh, TCGLabel *l); 1002 } TCGOutOpBrcond2; 1003 1004 typedef struct TCGOutOpBswap { 1005 TCGOutOp base; 1006 void (*out_rr)(TCGContext *s, TCGType type, 1007 TCGReg a0, TCGReg a1, unsigned flags); 1008 } TCGOutOpBswap; 1009 1010 typedef struct TCGOutOpDeposit { 1011 TCGOutOp base; 1012 void (*out_rrr)(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, 1013 TCGReg a2, unsigned ofs, unsigned len); 1014 void (*out_rri)(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, 1015 tcg_target_long a2, unsigned ofs, unsigned len); 1016 void (*out_rzr)(TCGContext *s, TCGType type, TCGReg a0, 1017 TCGReg a2, unsigned ofs, unsigned len); 1018 } TCGOutOpDeposit; 1019 1020 typedef struct TCGOutOpDivRem { 1021 TCGOutOp base; 1022 void (*out_rr01r)(TCGContext *s, TCGType type, 1023 TCGReg a0, TCGReg a1, TCGReg a4); 1024 } TCGOutOpDivRem; 1025 1026 typedef struct TCGOutOpExtract { 1027 TCGOutOp base; 1028 void (*out_rr)(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, 1029 unsigned ofs, unsigned len); 1030 } TCGOutOpExtract; 1031 1032 typedef struct TCGOutOpExtract2 { 1033 TCGOutOp base; 1034 void (*out_rrr)(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, 1035 TCGReg a2, unsigned shr); 1036 } TCGOutOpExtract2; 1037 1038 typedef struct TCGOutOpMovcond { 1039 TCGOutOp base; 1040 void (*out)(TCGContext *s, TCGType type, TCGCond cond, 1041 TCGReg ret, TCGReg c1, TCGArg c2, bool const_c2, 1042 TCGArg vt, bool const_vt, TCGArg vf, bool consf_vf); 1043 } TCGOutOpMovcond; 1044 1045 typedef struct TCGOutOpMul2 { 1046 TCGOutOp base; 1047 void (*out_rrrr)(TCGContext *s, TCGType type, 1048 TCGReg a0, TCGReg a1, TCGReg a2, TCGReg a3); 1049 } TCGOutOpMul2; 1050 1051 typedef struct TCGOutOpUnary { 1052 TCGOutOp base; 1053 void (*out_rr)(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1); 1054 } TCGOutOpUnary; 1055 1056 typedef struct TCGOutOpSetcond { 1057 TCGOutOp base; 1058 void (*out_rrr)(TCGContext *s, TCGType type, TCGCond cond, 1059 TCGReg ret, TCGReg a1, TCGReg a2); 1060 void (*out_rri)(TCGContext *s, TCGType type, TCGCond cond, 1061 TCGReg ret, TCGReg a1, tcg_target_long a2); 1062 } TCGOutOpSetcond; 1063 1064 typedef struct TCGOutOpSetcond2 { 1065 TCGOutOp base; 1066 void (*out)(TCGContext *s, TCGCond cond, TCGReg ret, TCGReg al, TCGReg ah, 1067 TCGArg bl, bool const_bl, TCGArg bh, bool const_bh); 1068 } TCGOutOpSetcond2; 1069 1070 typedef struct TCGOutOpSubtract { 1071 TCGOutOp base; 1072 void (*out_rrr)(TCGContext *s, TCGType type, 1073 TCGReg a0, TCGReg a1, TCGReg a2); 1074 void (*out_rir)(TCGContext *s, TCGType type, 1075 TCGReg a0, tcg_target_long a1, TCGReg a2); 1076 } TCGOutOpSubtract; 1077 1078 #include "tcg-target.c.inc" 1079 1080 #ifndef CONFIG_TCG_INTERPRETER 1081 /* Validate CPUTLBDescFast placement. */ 1082 QEMU_BUILD_BUG_ON((int)(offsetof(CPUNegativeOffsetState, tlb.f[0]) - 1083 sizeof(CPUNegativeOffsetState)) 1084 < MIN_TLB_MASK_TABLE_OFS); 1085 #endif 1086 1087 #if TCG_TARGET_REG_BITS == 64 1088 /* 1089 * We require these functions for slow-path function calls. 1090 * Adapt them generically for opcode output. 1091 */ 1092 1093 static void tgen_exts_i32_i64(TCGContext *s, TCGType t, TCGReg a0, TCGReg a1) 1094 { 1095 tcg_out_exts_i32_i64(s, a0, a1); 1096 } 1097 1098 static const TCGOutOpUnary outop_exts_i32_i64 = { 1099 .base.static_constraint = C_O1_I1(r, r), 1100 .out_rr = tgen_exts_i32_i64, 1101 }; 1102 1103 static void tgen_extu_i32_i64(TCGContext *s, TCGType t, TCGReg a0, TCGReg a1) 1104 { 1105 tcg_out_extu_i32_i64(s, a0, a1); 1106 } 1107 1108 static const TCGOutOpUnary outop_extu_i32_i64 = { 1109 .base.static_constraint = C_O1_I1(r, r), 1110 .out_rr = tgen_extu_i32_i64, 1111 }; 1112 1113 static void tgen_extrl_i64_i32(TCGContext *s, TCGType t, TCGReg a0, TCGReg a1) 1114 { 1115 tcg_out_extrl_i64_i32(s, a0, a1); 1116 } 1117 1118 static const TCGOutOpUnary outop_extrl_i64_i32 = { 1119 .base.static_constraint = C_O1_I1(r, r), 1120 .out_rr = TCG_TARGET_HAS_extr_i64_i32 ? tgen_extrl_i64_i32 : NULL, 1121 }; 1122 #endif 1123 1124 /* 1125 * Register V as the TCGOutOp for O. 1126 * This verifies that V is of type T, otherwise give a nice compiler error. 1127 * This prevents trivial mistakes within each arch/tcg-target.c.inc. 1128 */ 1129 #define OUTOP(O, T, V) [O] = _Generic(V, T: &V.base) 1130 1131 /* Register allocation descriptions for every TCGOpcode. */ 1132 static const TCGOutOp * const all_outop[NB_OPS] = { 1133 OUTOP(INDEX_op_add, TCGOutOpBinary, outop_add), 1134 OUTOP(INDEX_op_and, TCGOutOpBinary, outop_and), 1135 OUTOP(INDEX_op_andc, TCGOutOpBinary, outop_andc), 1136 OUTOP(INDEX_op_brcond, TCGOutOpBrcond, outop_brcond), 1137 OUTOP(INDEX_op_bswap16, TCGOutOpBswap, outop_bswap16), 1138 OUTOP(INDEX_op_bswap32, TCGOutOpBswap, outop_bswap32), 1139 OUTOP(INDEX_op_clz, TCGOutOpBinary, outop_clz), 1140 OUTOP(INDEX_op_ctpop, TCGOutOpUnary, outop_ctpop), 1141 OUTOP(INDEX_op_ctz, TCGOutOpBinary, outop_ctz), 1142 OUTOP(INDEX_op_deposit, TCGOutOpDeposit, outop_deposit), 1143 OUTOP(INDEX_op_divs, TCGOutOpBinary, outop_divs), 1144 OUTOP(INDEX_op_divu, TCGOutOpBinary, outop_divu), 1145 OUTOP(INDEX_op_divs2, TCGOutOpDivRem, outop_divs2), 1146 OUTOP(INDEX_op_divu2, TCGOutOpDivRem, outop_divu2), 1147 OUTOP(INDEX_op_eqv, TCGOutOpBinary, outop_eqv), 1148 OUTOP(INDEX_op_extract, TCGOutOpExtract, outop_extract), 1149 OUTOP(INDEX_op_extract2, TCGOutOpExtract2, outop_extract2), 1150 OUTOP(INDEX_op_movcond, TCGOutOpMovcond, outop_movcond), 1151 OUTOP(INDEX_op_mul, TCGOutOpBinary, outop_mul), 1152 OUTOP(INDEX_op_muls2, TCGOutOpMul2, outop_muls2), 1153 OUTOP(INDEX_op_mulsh, TCGOutOpBinary, outop_mulsh), 1154 OUTOP(INDEX_op_mulu2, TCGOutOpMul2, outop_mulu2), 1155 OUTOP(INDEX_op_muluh, TCGOutOpBinary, outop_muluh), 1156 OUTOP(INDEX_op_nand, TCGOutOpBinary, outop_nand), 1157 OUTOP(INDEX_op_neg, TCGOutOpUnary, outop_neg), 1158 OUTOP(INDEX_op_negsetcond, TCGOutOpSetcond, outop_negsetcond), 1159 OUTOP(INDEX_op_nor, TCGOutOpBinary, outop_nor), 1160 OUTOP(INDEX_op_not, TCGOutOpUnary, outop_not), 1161 OUTOP(INDEX_op_or, TCGOutOpBinary, outop_or), 1162 OUTOP(INDEX_op_orc, TCGOutOpBinary, outop_orc), 1163 OUTOP(INDEX_op_rems, TCGOutOpBinary, outop_rems), 1164 OUTOP(INDEX_op_remu, TCGOutOpBinary, outop_remu), 1165 OUTOP(INDEX_op_rotl, TCGOutOpBinary, outop_rotl), 1166 OUTOP(INDEX_op_rotr, TCGOutOpBinary, outop_rotr), 1167 OUTOP(INDEX_op_sar, TCGOutOpBinary, outop_sar), 1168 OUTOP(INDEX_op_setcond, TCGOutOpSetcond, outop_setcond), 1169 OUTOP(INDEX_op_sextract, TCGOutOpExtract, outop_sextract), 1170 OUTOP(INDEX_op_shl, TCGOutOpBinary, outop_shl), 1171 OUTOP(INDEX_op_shr, TCGOutOpBinary, outop_shr), 1172 OUTOP(INDEX_op_sub, TCGOutOpSubtract, outop_sub), 1173 OUTOP(INDEX_op_xor, TCGOutOpBinary, outop_xor), 1174 1175 #if TCG_TARGET_REG_BITS == 32 1176 OUTOP(INDEX_op_brcond2_i32, TCGOutOpBrcond2, outop_brcond2), 1177 OUTOP(INDEX_op_setcond2_i32, TCGOutOpSetcond2, outop_setcond2), 1178 #else 1179 OUTOP(INDEX_op_bswap64, TCGOutOpUnary, outop_bswap64), 1180 OUTOP(INDEX_op_ext_i32_i64, TCGOutOpUnary, outop_exts_i32_i64), 1181 OUTOP(INDEX_op_extu_i32_i64, TCGOutOpUnary, outop_extu_i32_i64), 1182 OUTOP(INDEX_op_extrl_i64_i32, TCGOutOpUnary, outop_extrl_i64_i32), 1183 OUTOP(INDEX_op_extrh_i64_i32, TCGOutOpUnary, outop_extrh_i64_i32), 1184 #endif 1185 }; 1186 1187 #undef OUTOP 1188 1189 /* 1190 * All TCG threads except the parent (i.e. the one that called tcg_context_init 1191 * and registered the target's TCG globals) must register with this function 1192 * before initiating translation. 1193 * 1194 * In user-mode we just point tcg_ctx to tcg_init_ctx. See the documentation 1195 * of tcg_region_init() for the reasoning behind this. 1196 * 1197 * In system-mode each caller registers its context in tcg_ctxs[]. Note that in 1198 * system-mode tcg_ctxs[] does not track tcg_ctx_init, since the initial context 1199 * is not used anymore for translation once this function is called. 1200 * 1201 * Not tracking tcg_init_ctx in tcg_ctxs[] in system-mode keeps code that 1202 * iterates over the array (e.g. tcg_code_size() the same for both system/user 1203 * modes. 1204 */ 1205 #ifdef CONFIG_USER_ONLY 1206 void tcg_register_thread(void) 1207 { 1208 tcg_ctx = &tcg_init_ctx; 1209 } 1210 #else 1211 void tcg_register_thread(void) 1212 { 1213 TCGContext *s = g_malloc(sizeof(*s)); 1214 unsigned int i, n; 1215 1216 *s = tcg_init_ctx; 1217 1218 /* Relink mem_base. */ 1219 for (i = 0, n = tcg_init_ctx.nb_globals; i < n; ++i) { 1220 if (tcg_init_ctx.temps[i].mem_base) { 1221 ptrdiff_t b = tcg_init_ctx.temps[i].mem_base - tcg_init_ctx.temps; 1222 tcg_debug_assert(b >= 0 && b < n); 1223 s->temps[i].mem_base = &s->temps[b]; 1224 } 1225 } 1226 1227 /* Claim an entry in tcg_ctxs */ 1228 n = qatomic_fetch_inc(&tcg_cur_ctxs); 1229 g_assert(n < tcg_max_ctxs); 1230 qatomic_set(&tcg_ctxs[n], s); 1231 1232 if (n > 0) { 1233 tcg_region_initial_alloc(s); 1234 } 1235 1236 tcg_ctx = s; 1237 } 1238 #endif /* !CONFIG_USER_ONLY */ 1239 1240 /* pool based memory allocation */ 1241 void *tcg_malloc_internal(TCGContext *s, int size) 1242 { 1243 TCGPool *p; 1244 int pool_size; 1245 1246 if (size > TCG_POOL_CHUNK_SIZE) { 1247 /* big malloc: insert a new pool (XXX: could optimize) */ 1248 p = g_malloc(sizeof(TCGPool) + size); 1249 p->size = size; 1250 p->next = s->pool_first_large; 1251 s->pool_first_large = p; 1252 return p->data; 1253 } else { 1254 p = s->pool_current; 1255 if (!p) { 1256 p = s->pool_first; 1257 if (!p) 1258 goto new_pool; 1259 } else { 1260 if (!p->next) { 1261 new_pool: 1262 pool_size = TCG_POOL_CHUNK_SIZE; 1263 p = g_malloc(sizeof(TCGPool) + pool_size); 1264 p->size = pool_size; 1265 p->next = NULL; 1266 if (s->pool_current) { 1267 s->pool_current->next = p; 1268 } else { 1269 s->pool_first = p; 1270 } 1271 } else { 1272 p = p->next; 1273 } 1274 } 1275 } 1276 s->pool_current = p; 1277 s->pool_cur = p->data + size; 1278 s->pool_end = p->data + p->size; 1279 return p->data; 1280 } 1281 1282 void tcg_pool_reset(TCGContext *s) 1283 { 1284 TCGPool *p, *t; 1285 for (p = s->pool_first_large; p; p = t) { 1286 t = p->next; 1287 g_free(p); 1288 } 1289 s->pool_first_large = NULL; 1290 s->pool_cur = s->pool_end = NULL; 1291 s->pool_current = NULL; 1292 } 1293 1294 /* 1295 * Create TCGHelperInfo structures for "tcg/tcg-ldst.h" functions, 1296 * akin to what "exec/helper-tcg.h" does with DEF_HELPER_FLAGS_N. 1297 * We only use these for layout in tcg_out_ld_helper_ret and 1298 * tcg_out_st_helper_args, and share them between several of 1299 * the helpers, with the end result that it's easier to build manually. 1300 */ 1301 1302 #if TCG_TARGET_REG_BITS == 32 1303 # define dh_typecode_ttl dh_typecode_i32 1304 #else 1305 # define dh_typecode_ttl dh_typecode_i64 1306 #endif 1307 1308 static TCGHelperInfo info_helper_ld32_mmu = { 1309 .flags = TCG_CALL_NO_WG, 1310 .typemask = dh_typemask(ttl, 0) /* return tcg_target_ulong */ 1311 | dh_typemask(env, 1) 1312 | dh_typemask(i64, 2) /* uint64_t addr */ 1313 | dh_typemask(i32, 3) /* unsigned oi */ 1314 | dh_typemask(ptr, 4) /* uintptr_t ra */ 1315 }; 1316 1317 static TCGHelperInfo info_helper_ld64_mmu = { 1318 .flags = TCG_CALL_NO_WG, 1319 .typemask = dh_typemask(i64, 0) /* return uint64_t */ 1320 | dh_typemask(env, 1) 1321 | dh_typemask(i64, 2) /* uint64_t addr */ 1322 | dh_typemask(i32, 3) /* unsigned oi */ 1323 | dh_typemask(ptr, 4) /* uintptr_t ra */ 1324 }; 1325 1326 static TCGHelperInfo info_helper_ld128_mmu = { 1327 .flags = TCG_CALL_NO_WG, 1328 .typemask = dh_typemask(i128, 0) /* return Int128 */ 1329 | dh_typemask(env, 1) 1330 | dh_typemask(i64, 2) /* uint64_t addr */ 1331 | dh_typemask(i32, 3) /* unsigned oi */ 1332 | dh_typemask(ptr, 4) /* uintptr_t ra */ 1333 }; 1334 1335 static TCGHelperInfo info_helper_st32_mmu = { 1336 .flags = TCG_CALL_NO_WG, 1337 .typemask = dh_typemask(void, 0) 1338 | dh_typemask(env, 1) 1339 | dh_typemask(i64, 2) /* uint64_t addr */ 1340 | dh_typemask(i32, 3) /* uint32_t data */ 1341 | dh_typemask(i32, 4) /* unsigned oi */ 1342 | dh_typemask(ptr, 5) /* uintptr_t ra */ 1343 }; 1344 1345 static TCGHelperInfo info_helper_st64_mmu = { 1346 .flags = TCG_CALL_NO_WG, 1347 .typemask = dh_typemask(void, 0) 1348 | dh_typemask(env, 1) 1349 | dh_typemask(i64, 2) /* uint64_t addr */ 1350 | dh_typemask(i64, 3) /* uint64_t data */ 1351 | dh_typemask(i32, 4) /* unsigned oi */ 1352 | dh_typemask(ptr, 5) /* uintptr_t ra */ 1353 }; 1354 1355 static TCGHelperInfo info_helper_st128_mmu = { 1356 .flags = TCG_CALL_NO_WG, 1357 .typemask = dh_typemask(void, 0) 1358 | dh_typemask(env, 1) 1359 | dh_typemask(i64, 2) /* uint64_t addr */ 1360 | dh_typemask(i128, 3) /* Int128 data */ 1361 | dh_typemask(i32, 4) /* unsigned oi */ 1362 | dh_typemask(ptr, 5) /* uintptr_t ra */ 1363 }; 1364 1365 #ifdef CONFIG_TCG_INTERPRETER 1366 static ffi_type *typecode_to_ffi(int argmask) 1367 { 1368 /* 1369 * libffi does not support __int128_t, so we have forced Int128 1370 * to use the structure definition instead of the builtin type. 1371 */ 1372 static ffi_type *ffi_type_i128_elements[3] = { 1373 &ffi_type_uint64, 1374 &ffi_type_uint64, 1375 NULL 1376 }; 1377 static ffi_type ffi_type_i128 = { 1378 .size = 16, 1379 .alignment = __alignof__(Int128), 1380 .type = FFI_TYPE_STRUCT, 1381 .elements = ffi_type_i128_elements, 1382 }; 1383 1384 switch (argmask) { 1385 case dh_typecode_void: 1386 return &ffi_type_void; 1387 case dh_typecode_i32: 1388 return &ffi_type_uint32; 1389 case dh_typecode_s32: 1390 return &ffi_type_sint32; 1391 case dh_typecode_i64: 1392 return &ffi_type_uint64; 1393 case dh_typecode_s64: 1394 return &ffi_type_sint64; 1395 case dh_typecode_ptr: 1396 return &ffi_type_pointer; 1397 case dh_typecode_i128: 1398 return &ffi_type_i128; 1399 } 1400 g_assert_not_reached(); 1401 } 1402 1403 static ffi_cif *init_ffi_layout(TCGHelperInfo *info) 1404 { 1405 unsigned typemask = info->typemask; 1406 struct { 1407 ffi_cif cif; 1408 ffi_type *args[]; 1409 } *ca; 1410 ffi_status status; 1411 int nargs; 1412 1413 /* Ignoring the return type, find the last non-zero field. */ 1414 nargs = 32 - clz32(typemask >> 3); 1415 nargs = DIV_ROUND_UP(nargs, 3); 1416 assert(nargs <= MAX_CALL_IARGS); 1417 1418 ca = g_malloc0(sizeof(*ca) + nargs * sizeof(ffi_type *)); 1419 ca->cif.rtype = typecode_to_ffi(typemask & 7); 1420 ca->cif.nargs = nargs; 1421 1422 if (nargs != 0) { 1423 ca->cif.arg_types = ca->args; 1424 for (int j = 0; j < nargs; ++j) { 1425 int typecode = extract32(typemask, (j + 1) * 3, 3); 1426 ca->args[j] = typecode_to_ffi(typecode); 1427 } 1428 } 1429 1430 status = ffi_prep_cif(&ca->cif, FFI_DEFAULT_ABI, nargs, 1431 ca->cif.rtype, ca->cif.arg_types); 1432 assert(status == FFI_OK); 1433 1434 return &ca->cif; 1435 } 1436 1437 #define HELPER_INFO_INIT(I) (&(I)->cif) 1438 #define HELPER_INFO_INIT_VAL(I) init_ffi_layout(I) 1439 #else 1440 #define HELPER_INFO_INIT(I) (&(I)->init) 1441 #define HELPER_INFO_INIT_VAL(I) 1 1442 #endif /* CONFIG_TCG_INTERPRETER */ 1443 1444 static inline bool arg_slot_reg_p(unsigned arg_slot) 1445 { 1446 /* 1447 * Split the sizeof away from the comparison to avoid Werror from 1448 * "unsigned < 0 is always false", when iarg_regs is empty. 1449 */ 1450 unsigned nreg = ARRAY_SIZE(tcg_target_call_iarg_regs); 1451 return arg_slot < nreg; 1452 } 1453 1454 static inline int arg_slot_stk_ofs(unsigned arg_slot) 1455 { 1456 unsigned max = TCG_STATIC_CALL_ARGS_SIZE / sizeof(tcg_target_long); 1457 unsigned stk_slot = arg_slot - ARRAY_SIZE(tcg_target_call_iarg_regs); 1458 1459 tcg_debug_assert(stk_slot < max); 1460 return TCG_TARGET_CALL_STACK_OFFSET + stk_slot * sizeof(tcg_target_long); 1461 } 1462 1463 typedef struct TCGCumulativeArgs { 1464 int arg_idx; /* tcg_gen_callN args[] */ 1465 int info_in_idx; /* TCGHelperInfo in[] */ 1466 int arg_slot; /* regs+stack slot */ 1467 int ref_slot; /* stack slots for references */ 1468 } TCGCumulativeArgs; 1469 1470 static void layout_arg_even(TCGCumulativeArgs *cum) 1471 { 1472 cum->arg_slot += cum->arg_slot & 1; 1473 } 1474 1475 static void layout_arg_1(TCGCumulativeArgs *cum, TCGHelperInfo *info, 1476 TCGCallArgumentKind kind) 1477 { 1478 TCGCallArgumentLoc *loc = &info->in[cum->info_in_idx]; 1479 1480 *loc = (TCGCallArgumentLoc){ 1481 .kind = kind, 1482 .arg_idx = cum->arg_idx, 1483 .arg_slot = cum->arg_slot, 1484 }; 1485 cum->info_in_idx++; 1486 cum->arg_slot++; 1487 } 1488 1489 static void layout_arg_normal_n(TCGCumulativeArgs *cum, 1490 TCGHelperInfo *info, int n) 1491 { 1492 TCGCallArgumentLoc *loc = &info->in[cum->info_in_idx]; 1493 1494 for (int i = 0; i < n; ++i) { 1495 /* Layout all using the same arg_idx, adjusting the subindex. */ 1496 loc[i] = (TCGCallArgumentLoc){ 1497 .kind = TCG_CALL_ARG_NORMAL, 1498 .arg_idx = cum->arg_idx, 1499 .tmp_subindex = i, 1500 .arg_slot = cum->arg_slot + i, 1501 }; 1502 } 1503 cum->info_in_idx += n; 1504 cum->arg_slot += n; 1505 } 1506 1507 static void layout_arg_by_ref(TCGCumulativeArgs *cum, TCGHelperInfo *info) 1508 { 1509 TCGCallArgumentLoc *loc = &info->in[cum->info_in_idx]; 1510 int n = 128 / TCG_TARGET_REG_BITS; 1511 1512 /* The first subindex carries the pointer. */ 1513 layout_arg_1(cum, info, TCG_CALL_ARG_BY_REF); 1514 1515 /* 1516 * The callee is allowed to clobber memory associated with 1517 * structure pass by-reference. Therefore we must make copies. 1518 * Allocate space from "ref_slot", which will be adjusted to 1519 * follow the parameters on the stack. 1520 */ 1521 loc[0].ref_slot = cum->ref_slot; 1522 1523 /* 1524 * Subsequent words also go into the reference slot, but 1525 * do not accumulate into the regular arguments. 1526 */ 1527 for (int i = 1; i < n; ++i) { 1528 loc[i] = (TCGCallArgumentLoc){ 1529 .kind = TCG_CALL_ARG_BY_REF_N, 1530 .arg_idx = cum->arg_idx, 1531 .tmp_subindex = i, 1532 .ref_slot = cum->ref_slot + i, 1533 }; 1534 } 1535 cum->info_in_idx += n - 1; /* i=0 accounted for in layout_arg_1 */ 1536 cum->ref_slot += n; 1537 } 1538 1539 static void init_call_layout(TCGHelperInfo *info) 1540 { 1541 int max_reg_slots = ARRAY_SIZE(tcg_target_call_iarg_regs); 1542 int max_stk_slots = TCG_STATIC_CALL_ARGS_SIZE / sizeof(tcg_target_long); 1543 unsigned typemask = info->typemask; 1544 unsigned typecode; 1545 TCGCumulativeArgs cum = { }; 1546 1547 /* 1548 * Parse and place any function return value. 1549 */ 1550 typecode = typemask & 7; 1551 switch (typecode) { 1552 case dh_typecode_void: 1553 info->nr_out = 0; 1554 break; 1555 case dh_typecode_i32: 1556 case dh_typecode_s32: 1557 case dh_typecode_ptr: 1558 info->nr_out = 1; 1559 info->out_kind = TCG_CALL_RET_NORMAL; 1560 break; 1561 case dh_typecode_i64: 1562 case dh_typecode_s64: 1563 info->nr_out = 64 / TCG_TARGET_REG_BITS; 1564 info->out_kind = TCG_CALL_RET_NORMAL; 1565 /* Query the last register now to trigger any assert early. */ 1566 tcg_target_call_oarg_reg(info->out_kind, info->nr_out - 1); 1567 break; 1568 case dh_typecode_i128: 1569 info->nr_out = 128 / TCG_TARGET_REG_BITS; 1570 info->out_kind = TCG_TARGET_CALL_RET_I128; 1571 switch (TCG_TARGET_CALL_RET_I128) { 1572 case TCG_CALL_RET_NORMAL: 1573 /* Query the last register now to trigger any assert early. */ 1574 tcg_target_call_oarg_reg(info->out_kind, info->nr_out - 1); 1575 break; 1576 case TCG_CALL_RET_BY_VEC: 1577 /* Query the single register now to trigger any assert early. */ 1578 tcg_target_call_oarg_reg(TCG_CALL_RET_BY_VEC, 0); 1579 break; 1580 case TCG_CALL_RET_BY_REF: 1581 /* 1582 * Allocate the first argument to the output. 1583 * We don't need to store this anywhere, just make it 1584 * unavailable for use in the input loop below. 1585 */ 1586 cum.arg_slot = 1; 1587 break; 1588 default: 1589 qemu_build_not_reached(); 1590 } 1591 break; 1592 default: 1593 g_assert_not_reached(); 1594 } 1595 1596 /* 1597 * Parse and place function arguments. 1598 */ 1599 for (typemask >>= 3; typemask; typemask >>= 3, cum.arg_idx++) { 1600 TCGCallArgumentKind kind; 1601 TCGType type; 1602 1603 typecode = typemask & 7; 1604 switch (typecode) { 1605 case dh_typecode_i32: 1606 case dh_typecode_s32: 1607 type = TCG_TYPE_I32; 1608 break; 1609 case dh_typecode_i64: 1610 case dh_typecode_s64: 1611 type = TCG_TYPE_I64; 1612 break; 1613 case dh_typecode_ptr: 1614 type = TCG_TYPE_PTR; 1615 break; 1616 case dh_typecode_i128: 1617 type = TCG_TYPE_I128; 1618 break; 1619 default: 1620 g_assert_not_reached(); 1621 } 1622 1623 switch (type) { 1624 case TCG_TYPE_I32: 1625 switch (TCG_TARGET_CALL_ARG_I32) { 1626 case TCG_CALL_ARG_EVEN: 1627 layout_arg_even(&cum); 1628 /* fall through */ 1629 case TCG_CALL_ARG_NORMAL: 1630 layout_arg_1(&cum, info, TCG_CALL_ARG_NORMAL); 1631 break; 1632 case TCG_CALL_ARG_EXTEND: 1633 kind = TCG_CALL_ARG_EXTEND_U + (typecode & 1); 1634 layout_arg_1(&cum, info, kind); 1635 break; 1636 default: 1637 qemu_build_not_reached(); 1638 } 1639 break; 1640 1641 case TCG_TYPE_I64: 1642 switch (TCG_TARGET_CALL_ARG_I64) { 1643 case TCG_CALL_ARG_EVEN: 1644 layout_arg_even(&cum); 1645 /* fall through */ 1646 case TCG_CALL_ARG_NORMAL: 1647 if (TCG_TARGET_REG_BITS == 32) { 1648 layout_arg_normal_n(&cum, info, 2); 1649 } else { 1650 layout_arg_1(&cum, info, TCG_CALL_ARG_NORMAL); 1651 } 1652 break; 1653 default: 1654 qemu_build_not_reached(); 1655 } 1656 break; 1657 1658 case TCG_TYPE_I128: 1659 switch (TCG_TARGET_CALL_ARG_I128) { 1660 case TCG_CALL_ARG_EVEN: 1661 layout_arg_even(&cum); 1662 /* fall through */ 1663 case TCG_CALL_ARG_NORMAL: 1664 layout_arg_normal_n(&cum, info, 128 / TCG_TARGET_REG_BITS); 1665 break; 1666 case TCG_CALL_ARG_BY_REF: 1667 layout_arg_by_ref(&cum, info); 1668 break; 1669 default: 1670 qemu_build_not_reached(); 1671 } 1672 break; 1673 1674 default: 1675 g_assert_not_reached(); 1676 } 1677 } 1678 info->nr_in = cum.info_in_idx; 1679 1680 /* Validate that we didn't overrun the input array. */ 1681 assert(cum.info_in_idx <= ARRAY_SIZE(info->in)); 1682 /* Validate the backend has enough argument space. */ 1683 assert(cum.arg_slot <= max_reg_slots + max_stk_slots); 1684 1685 /* 1686 * Relocate the "ref_slot" area to the end of the parameters. 1687 * Minimizing this stack offset helps code size for x86, 1688 * which has a signed 8-bit offset encoding. 1689 */ 1690 if (cum.ref_slot != 0) { 1691 int ref_base = 0; 1692 1693 if (cum.arg_slot > max_reg_slots) { 1694 int align = __alignof(Int128) / sizeof(tcg_target_long); 1695 1696 ref_base = cum.arg_slot - max_reg_slots; 1697 if (align > 1) { 1698 ref_base = ROUND_UP(ref_base, align); 1699 } 1700 } 1701 assert(ref_base + cum.ref_slot <= max_stk_slots); 1702 ref_base += max_reg_slots; 1703 1704 if (ref_base != 0) { 1705 for (int i = cum.info_in_idx - 1; i >= 0; --i) { 1706 TCGCallArgumentLoc *loc = &info->in[i]; 1707 switch (loc->kind) { 1708 case TCG_CALL_ARG_BY_REF: 1709 case TCG_CALL_ARG_BY_REF_N: 1710 loc->ref_slot += ref_base; 1711 break; 1712 default: 1713 break; 1714 } 1715 } 1716 } 1717 } 1718 } 1719 1720 static int indirect_reg_alloc_order[ARRAY_SIZE(tcg_target_reg_alloc_order)]; 1721 static void process_constraint_sets(void); 1722 static TCGTemp *tcg_global_reg_new_internal(TCGContext *s, TCGType type, 1723 TCGReg reg, const char *name); 1724 1725 static void tcg_context_init(unsigned max_threads) 1726 { 1727 TCGContext *s = &tcg_init_ctx; 1728 int n, i; 1729 TCGTemp *ts; 1730 1731 memset(s, 0, sizeof(*s)); 1732 s->nb_globals = 0; 1733 1734 init_call_layout(&info_helper_ld32_mmu); 1735 init_call_layout(&info_helper_ld64_mmu); 1736 init_call_layout(&info_helper_ld128_mmu); 1737 init_call_layout(&info_helper_st32_mmu); 1738 init_call_layout(&info_helper_st64_mmu); 1739 init_call_layout(&info_helper_st128_mmu); 1740 1741 tcg_target_init(s); 1742 process_constraint_sets(); 1743 1744 /* Reverse the order of the saved registers, assuming they're all at 1745 the start of tcg_target_reg_alloc_order. */ 1746 for (n = 0; n < ARRAY_SIZE(tcg_target_reg_alloc_order); ++n) { 1747 int r = tcg_target_reg_alloc_order[n]; 1748 if (tcg_regset_test_reg(tcg_target_call_clobber_regs, r)) { 1749 break; 1750 } 1751 } 1752 for (i = 0; i < n; ++i) { 1753 indirect_reg_alloc_order[i] = tcg_target_reg_alloc_order[n - 1 - i]; 1754 } 1755 for (; i < ARRAY_SIZE(tcg_target_reg_alloc_order); ++i) { 1756 indirect_reg_alloc_order[i] = tcg_target_reg_alloc_order[i]; 1757 } 1758 1759 tcg_ctx = s; 1760 /* 1761 * In user-mode we simply share the init context among threads, since we 1762 * use a single region. See the documentation tcg_region_init() for the 1763 * reasoning behind this. 1764 * In system-mode we will have at most max_threads TCG threads. 1765 */ 1766 #ifdef CONFIG_USER_ONLY 1767 tcg_ctxs = &tcg_ctx; 1768 tcg_cur_ctxs = 1; 1769 tcg_max_ctxs = 1; 1770 #else 1771 tcg_max_ctxs = max_threads; 1772 tcg_ctxs = g_new0(TCGContext *, max_threads); 1773 #endif 1774 1775 tcg_debug_assert(!tcg_regset_test_reg(s->reserved_regs, TCG_AREG0)); 1776 ts = tcg_global_reg_new_internal(s, TCG_TYPE_PTR, TCG_AREG0, "env"); 1777 tcg_env = temp_tcgv_ptr(ts); 1778 } 1779 1780 void tcg_init(size_t tb_size, int splitwx, unsigned max_threads) 1781 { 1782 tcg_context_init(max_threads); 1783 tcg_region_init(tb_size, splitwx, max_threads); 1784 } 1785 1786 /* 1787 * Allocate TBs right before their corresponding translated code, making 1788 * sure that TBs and code are on different cache lines. 1789 */ 1790 TranslationBlock *tcg_tb_alloc(TCGContext *s) 1791 { 1792 uintptr_t align = qemu_icache_linesize; 1793 TranslationBlock *tb; 1794 void *next; 1795 1796 retry: 1797 tb = (void *)ROUND_UP((uintptr_t)s->code_gen_ptr, align); 1798 next = (void *)ROUND_UP((uintptr_t)(tb + 1), align); 1799 1800 if (unlikely(next > s->code_gen_highwater)) { 1801 if (tcg_region_alloc(s)) { 1802 return NULL; 1803 } 1804 goto retry; 1805 } 1806 qatomic_set(&s->code_gen_ptr, next); 1807 return tb; 1808 } 1809 1810 void tcg_prologue_init(void) 1811 { 1812 TCGContext *s = tcg_ctx; 1813 size_t prologue_size; 1814 1815 s->code_ptr = s->code_gen_ptr; 1816 s->code_buf = s->code_gen_ptr; 1817 s->data_gen_ptr = NULL; 1818 1819 #ifndef CONFIG_TCG_INTERPRETER 1820 tcg_qemu_tb_exec = (tcg_prologue_fn *)tcg_splitwx_to_rx(s->code_ptr); 1821 #endif 1822 1823 s->pool_labels = NULL; 1824 1825 qemu_thread_jit_write(); 1826 /* Generate the prologue. */ 1827 tcg_target_qemu_prologue(s); 1828 1829 /* Allow the prologue to put e.g. guest_base into a pool entry. */ 1830 { 1831 int result = tcg_out_pool_finalize(s); 1832 tcg_debug_assert(result == 0); 1833 } 1834 1835 prologue_size = tcg_current_code_size(s); 1836 perf_report_prologue(s->code_gen_ptr, prologue_size); 1837 1838 #ifndef CONFIG_TCG_INTERPRETER 1839 flush_idcache_range((uintptr_t)tcg_splitwx_to_rx(s->code_buf), 1840 (uintptr_t)s->code_buf, prologue_size); 1841 #endif 1842 1843 if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM)) { 1844 FILE *logfile = qemu_log_trylock(); 1845 if (logfile) { 1846 fprintf(logfile, "PROLOGUE: [size=%zu]\n", prologue_size); 1847 if (s->data_gen_ptr) { 1848 size_t code_size = s->data_gen_ptr - s->code_gen_ptr; 1849 size_t data_size = prologue_size - code_size; 1850 size_t i; 1851 1852 disas(logfile, s->code_gen_ptr, code_size); 1853 1854 for (i = 0; i < data_size; i += sizeof(tcg_target_ulong)) { 1855 if (sizeof(tcg_target_ulong) == 8) { 1856 fprintf(logfile, 1857 "0x%08" PRIxPTR ": .quad 0x%016" PRIx64 "\n", 1858 (uintptr_t)s->data_gen_ptr + i, 1859 *(uint64_t *)(s->data_gen_ptr + i)); 1860 } else { 1861 fprintf(logfile, 1862 "0x%08" PRIxPTR ": .long 0x%08x\n", 1863 (uintptr_t)s->data_gen_ptr + i, 1864 *(uint32_t *)(s->data_gen_ptr + i)); 1865 } 1866 } 1867 } else { 1868 disas(logfile, s->code_gen_ptr, prologue_size); 1869 } 1870 fprintf(logfile, "\n"); 1871 qemu_log_unlock(logfile); 1872 } 1873 } 1874 1875 #ifndef CONFIG_TCG_INTERPRETER 1876 /* 1877 * Assert that goto_ptr is implemented completely, setting an epilogue. 1878 * For tci, we use NULL as the signal to return from the interpreter, 1879 * so skip this check. 1880 */ 1881 tcg_debug_assert(tcg_code_gen_epilogue != NULL); 1882 #endif 1883 1884 tcg_region_prologue_set(s); 1885 } 1886 1887 void tcg_func_start(TCGContext *s) 1888 { 1889 tcg_pool_reset(s); 1890 s->nb_temps = s->nb_globals; 1891 1892 /* No temps have been previously allocated for size or locality. */ 1893 tcg_temp_ebb_reset_freed(s); 1894 1895 /* No constant temps have been previously allocated. */ 1896 for (int i = 0; i < TCG_TYPE_COUNT; ++i) { 1897 if (s->const_table[i]) { 1898 g_hash_table_remove_all(s->const_table[i]); 1899 } 1900 } 1901 1902 s->nb_ops = 0; 1903 s->nb_labels = 0; 1904 s->current_frame_offset = s->frame_start; 1905 1906 #ifdef CONFIG_DEBUG_TCG 1907 s->goto_tb_issue_mask = 0; 1908 #endif 1909 1910 QTAILQ_INIT(&s->ops); 1911 QTAILQ_INIT(&s->free_ops); 1912 s->emit_before_op = NULL; 1913 QSIMPLEQ_INIT(&s->labels); 1914 1915 tcg_debug_assert(s->addr_type <= TCG_TYPE_REG); 1916 tcg_debug_assert(s->insn_start_words > 0); 1917 } 1918 1919 static TCGTemp *tcg_temp_alloc(TCGContext *s) 1920 { 1921 int n = s->nb_temps++; 1922 1923 if (n >= TCG_MAX_TEMPS) { 1924 tcg_raise_tb_overflow(s); 1925 } 1926 return memset(&s->temps[n], 0, sizeof(TCGTemp)); 1927 } 1928 1929 static TCGTemp *tcg_global_alloc(TCGContext *s) 1930 { 1931 TCGTemp *ts; 1932 1933 tcg_debug_assert(s->nb_globals == s->nb_temps); 1934 tcg_debug_assert(s->nb_globals < TCG_MAX_TEMPS); 1935 s->nb_globals++; 1936 ts = tcg_temp_alloc(s); 1937 ts->kind = TEMP_GLOBAL; 1938 1939 return ts; 1940 } 1941 1942 static TCGTemp *tcg_global_reg_new_internal(TCGContext *s, TCGType type, 1943 TCGReg reg, const char *name) 1944 { 1945 TCGTemp *ts; 1946 1947 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32); 1948 1949 ts = tcg_global_alloc(s); 1950 ts->base_type = type; 1951 ts->type = type; 1952 ts->kind = TEMP_FIXED; 1953 ts->reg = reg; 1954 ts->name = name; 1955 tcg_regset_set_reg(s->reserved_regs, reg); 1956 1957 return ts; 1958 } 1959 1960 void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size) 1961 { 1962 s->frame_start = start; 1963 s->frame_end = start + size; 1964 s->frame_temp 1965 = tcg_global_reg_new_internal(s, TCG_TYPE_PTR, reg, "_frame"); 1966 } 1967 1968 static TCGTemp *tcg_global_mem_new_internal(TCGv_ptr base, intptr_t offset, 1969 const char *name, TCGType type) 1970 { 1971 TCGContext *s = tcg_ctx; 1972 TCGTemp *base_ts = tcgv_ptr_temp(base); 1973 TCGTemp *ts = tcg_global_alloc(s); 1974 int indirect_reg = 0; 1975 1976 switch (base_ts->kind) { 1977 case TEMP_FIXED: 1978 break; 1979 case TEMP_GLOBAL: 1980 /* We do not support double-indirect registers. */ 1981 tcg_debug_assert(!base_ts->indirect_reg); 1982 base_ts->indirect_base = 1; 1983 s->nb_indirects += (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64 1984 ? 2 : 1); 1985 indirect_reg = 1; 1986 break; 1987 default: 1988 g_assert_not_reached(); 1989 } 1990 1991 if (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64) { 1992 TCGTemp *ts2 = tcg_global_alloc(s); 1993 char buf[64]; 1994 1995 ts->base_type = TCG_TYPE_I64; 1996 ts->type = TCG_TYPE_I32; 1997 ts->indirect_reg = indirect_reg; 1998 ts->mem_allocated = 1; 1999 ts->mem_base = base_ts; 2000 ts->mem_offset = offset; 2001 pstrcpy(buf, sizeof(buf), name); 2002 pstrcat(buf, sizeof(buf), "_0"); 2003 ts->name = strdup(buf); 2004 2005 tcg_debug_assert(ts2 == ts + 1); 2006 ts2->base_type = TCG_TYPE_I64; 2007 ts2->type = TCG_TYPE_I32; 2008 ts2->indirect_reg = indirect_reg; 2009 ts2->mem_allocated = 1; 2010 ts2->mem_base = base_ts; 2011 ts2->mem_offset = offset + 4; 2012 ts2->temp_subindex = 1; 2013 pstrcpy(buf, sizeof(buf), name); 2014 pstrcat(buf, sizeof(buf), "_1"); 2015 ts2->name = strdup(buf); 2016 } else { 2017 ts->base_type = type; 2018 ts->type = type; 2019 ts->indirect_reg = indirect_reg; 2020 ts->mem_allocated = 1; 2021 ts->mem_base = base_ts; 2022 ts->mem_offset = offset; 2023 ts->name = name; 2024 } 2025 return ts; 2026 } 2027 2028 TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t off, const char *name) 2029 { 2030 TCGTemp *ts = tcg_global_mem_new_internal(reg, off, name, TCG_TYPE_I32); 2031 return temp_tcgv_i32(ts); 2032 } 2033 2034 TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t off, const char *name) 2035 { 2036 TCGTemp *ts = tcg_global_mem_new_internal(reg, off, name, TCG_TYPE_I64); 2037 return temp_tcgv_i64(ts); 2038 } 2039 2040 TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t off, const char *name) 2041 { 2042 TCGTemp *ts = tcg_global_mem_new_internal(reg, off, name, TCG_TYPE_PTR); 2043 return temp_tcgv_ptr(ts); 2044 } 2045 2046 TCGTemp *tcg_temp_new_internal(TCGType type, TCGTempKind kind) 2047 { 2048 TCGContext *s = tcg_ctx; 2049 TCGTemp *ts; 2050 int n; 2051 2052 if (kind == TEMP_EBB) { 2053 int idx = find_first_bit(s->free_temps[type].l, TCG_MAX_TEMPS); 2054 2055 if (idx < TCG_MAX_TEMPS) { 2056 /* There is already an available temp with the right type. */ 2057 clear_bit(idx, s->free_temps[type].l); 2058 2059 ts = &s->temps[idx]; 2060 ts->temp_allocated = 1; 2061 tcg_debug_assert(ts->base_type == type); 2062 tcg_debug_assert(ts->kind == kind); 2063 return ts; 2064 } 2065 } else { 2066 tcg_debug_assert(kind == TEMP_TB); 2067 } 2068 2069 switch (type) { 2070 case TCG_TYPE_I32: 2071 case TCG_TYPE_V64: 2072 case TCG_TYPE_V128: 2073 case TCG_TYPE_V256: 2074 n = 1; 2075 break; 2076 case TCG_TYPE_I64: 2077 n = 64 / TCG_TARGET_REG_BITS; 2078 break; 2079 case TCG_TYPE_I128: 2080 n = 128 / TCG_TARGET_REG_BITS; 2081 break; 2082 default: 2083 g_assert_not_reached(); 2084 } 2085 2086 ts = tcg_temp_alloc(s); 2087 ts->base_type = type; 2088 ts->temp_allocated = 1; 2089 ts->kind = kind; 2090 2091 if (n == 1) { 2092 ts->type = type; 2093 } else { 2094 ts->type = TCG_TYPE_REG; 2095 2096 for (int i = 1; i < n; ++i) { 2097 TCGTemp *ts2 = tcg_temp_alloc(s); 2098 2099 tcg_debug_assert(ts2 == ts + i); 2100 ts2->base_type = type; 2101 ts2->type = TCG_TYPE_REG; 2102 ts2->temp_allocated = 1; 2103 ts2->temp_subindex = i; 2104 ts2->kind = kind; 2105 } 2106 } 2107 return ts; 2108 } 2109 2110 TCGv_i32 tcg_temp_new_i32(void) 2111 { 2112 return temp_tcgv_i32(tcg_temp_new_internal(TCG_TYPE_I32, TEMP_TB)); 2113 } 2114 2115 TCGv_i32 tcg_temp_ebb_new_i32(void) 2116 { 2117 return temp_tcgv_i32(tcg_temp_new_internal(TCG_TYPE_I32, TEMP_EBB)); 2118 } 2119 2120 TCGv_i64 tcg_temp_new_i64(void) 2121 { 2122 return temp_tcgv_i64(tcg_temp_new_internal(TCG_TYPE_I64, TEMP_TB)); 2123 } 2124 2125 TCGv_i64 tcg_temp_ebb_new_i64(void) 2126 { 2127 return temp_tcgv_i64(tcg_temp_new_internal(TCG_TYPE_I64, TEMP_EBB)); 2128 } 2129 2130 TCGv_ptr tcg_temp_new_ptr(void) 2131 { 2132 return temp_tcgv_ptr(tcg_temp_new_internal(TCG_TYPE_PTR, TEMP_TB)); 2133 } 2134 2135 TCGv_ptr tcg_temp_ebb_new_ptr(void) 2136 { 2137 return temp_tcgv_ptr(tcg_temp_new_internal(TCG_TYPE_PTR, TEMP_EBB)); 2138 } 2139 2140 TCGv_i128 tcg_temp_new_i128(void) 2141 { 2142 return temp_tcgv_i128(tcg_temp_new_internal(TCG_TYPE_I128, TEMP_TB)); 2143 } 2144 2145 TCGv_i128 tcg_temp_ebb_new_i128(void) 2146 { 2147 return temp_tcgv_i128(tcg_temp_new_internal(TCG_TYPE_I128, TEMP_EBB)); 2148 } 2149 2150 TCGv_vec tcg_temp_new_vec(TCGType type) 2151 { 2152 TCGTemp *t; 2153 2154 #ifdef CONFIG_DEBUG_TCG 2155 switch (type) { 2156 case TCG_TYPE_V64: 2157 assert(TCG_TARGET_HAS_v64); 2158 break; 2159 case TCG_TYPE_V128: 2160 assert(TCG_TARGET_HAS_v128); 2161 break; 2162 case TCG_TYPE_V256: 2163 assert(TCG_TARGET_HAS_v256); 2164 break; 2165 default: 2166 g_assert_not_reached(); 2167 } 2168 #endif 2169 2170 t = tcg_temp_new_internal(type, TEMP_EBB); 2171 return temp_tcgv_vec(t); 2172 } 2173 2174 /* Create a new temp of the same type as an existing temp. */ 2175 TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match) 2176 { 2177 TCGTemp *t = tcgv_vec_temp(match); 2178 2179 tcg_debug_assert(t->temp_allocated != 0); 2180 2181 t = tcg_temp_new_internal(t->base_type, TEMP_EBB); 2182 return temp_tcgv_vec(t); 2183 } 2184 2185 void tcg_temp_free_internal(TCGTemp *ts) 2186 { 2187 TCGContext *s = tcg_ctx; 2188 2189 switch (ts->kind) { 2190 case TEMP_CONST: 2191 case TEMP_TB: 2192 /* Silently ignore free. */ 2193 break; 2194 case TEMP_EBB: 2195 tcg_debug_assert(ts->temp_allocated != 0); 2196 ts->temp_allocated = 0; 2197 set_bit(temp_idx(ts), s->free_temps[ts->base_type].l); 2198 break; 2199 default: 2200 /* It never made sense to free TEMP_FIXED or TEMP_GLOBAL. */ 2201 g_assert_not_reached(); 2202 } 2203 } 2204 2205 void tcg_temp_free_i32(TCGv_i32 arg) 2206 { 2207 tcg_temp_free_internal(tcgv_i32_temp(arg)); 2208 } 2209 2210 void tcg_temp_free_i64(TCGv_i64 arg) 2211 { 2212 tcg_temp_free_internal(tcgv_i64_temp(arg)); 2213 } 2214 2215 void tcg_temp_free_i128(TCGv_i128 arg) 2216 { 2217 tcg_temp_free_internal(tcgv_i128_temp(arg)); 2218 } 2219 2220 void tcg_temp_free_ptr(TCGv_ptr arg) 2221 { 2222 tcg_temp_free_internal(tcgv_ptr_temp(arg)); 2223 } 2224 2225 void tcg_temp_free_vec(TCGv_vec arg) 2226 { 2227 tcg_temp_free_internal(tcgv_vec_temp(arg)); 2228 } 2229 2230 TCGTemp *tcg_constant_internal(TCGType type, int64_t val) 2231 { 2232 TCGContext *s = tcg_ctx; 2233 GHashTable *h = s->const_table[type]; 2234 TCGTemp *ts; 2235 2236 if (h == NULL) { 2237 h = g_hash_table_new(g_int64_hash, g_int64_equal); 2238 s->const_table[type] = h; 2239 } 2240 2241 ts = g_hash_table_lookup(h, &val); 2242 if (ts == NULL) { 2243 int64_t *val_ptr; 2244 2245 ts = tcg_temp_alloc(s); 2246 2247 if (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64) { 2248 TCGTemp *ts2 = tcg_temp_alloc(s); 2249 2250 tcg_debug_assert(ts2 == ts + 1); 2251 2252 ts->base_type = TCG_TYPE_I64; 2253 ts->type = TCG_TYPE_I32; 2254 ts->kind = TEMP_CONST; 2255 ts->temp_allocated = 1; 2256 2257 ts2->base_type = TCG_TYPE_I64; 2258 ts2->type = TCG_TYPE_I32; 2259 ts2->kind = TEMP_CONST; 2260 ts2->temp_allocated = 1; 2261 ts2->temp_subindex = 1; 2262 2263 /* 2264 * Retain the full value of the 64-bit constant in the low 2265 * part, so that the hash table works. Actual uses will 2266 * truncate the value to the low part. 2267 */ 2268 ts[HOST_BIG_ENDIAN].val = val; 2269 ts[!HOST_BIG_ENDIAN].val = val >> 32; 2270 val_ptr = &ts[HOST_BIG_ENDIAN].val; 2271 } else { 2272 ts->base_type = type; 2273 ts->type = type; 2274 ts->kind = TEMP_CONST; 2275 ts->temp_allocated = 1; 2276 ts->val = val; 2277 val_ptr = &ts->val; 2278 } 2279 g_hash_table_insert(h, val_ptr, ts); 2280 } 2281 2282 return ts; 2283 } 2284 2285 TCGv_i32 tcg_constant_i32(int32_t val) 2286 { 2287 return temp_tcgv_i32(tcg_constant_internal(TCG_TYPE_I32, val)); 2288 } 2289 2290 TCGv_i64 tcg_constant_i64(int64_t val) 2291 { 2292 return temp_tcgv_i64(tcg_constant_internal(TCG_TYPE_I64, val)); 2293 } 2294 2295 TCGv_ptr tcg_constant_ptr_int(intptr_t val) 2296 { 2297 return temp_tcgv_ptr(tcg_constant_internal(TCG_TYPE_PTR, val)); 2298 } 2299 2300 TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val) 2301 { 2302 val = dup_const(vece, val); 2303 return temp_tcgv_vec(tcg_constant_internal(type, val)); 2304 } 2305 2306 TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t val) 2307 { 2308 TCGTemp *t = tcgv_vec_temp(match); 2309 2310 tcg_debug_assert(t->temp_allocated != 0); 2311 return tcg_constant_vec(t->base_type, vece, val); 2312 } 2313 2314 #ifdef CONFIG_DEBUG_TCG 2315 size_t temp_idx(TCGTemp *ts) 2316 { 2317 ptrdiff_t n = ts - tcg_ctx->temps; 2318 assert(n >= 0 && n < tcg_ctx->nb_temps); 2319 return n; 2320 } 2321 2322 TCGTemp *tcgv_i32_temp(TCGv_i32 v) 2323 { 2324 uintptr_t o = (uintptr_t)v - offsetof(TCGContext, temps); 2325 2326 assert(o < sizeof(TCGTemp) * tcg_ctx->nb_temps); 2327 assert(o % sizeof(TCGTemp) == 0); 2328 2329 return (void *)tcg_ctx + (uintptr_t)v; 2330 } 2331 #endif /* CONFIG_DEBUG_TCG */ 2332 2333 /* 2334 * Return true if OP may appear in the opcode stream with TYPE. 2335 * Test the runtime variable that controls each opcode. 2336 */ 2337 bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags) 2338 { 2339 bool has_type; 2340 2341 switch (type) { 2342 case TCG_TYPE_I32: 2343 has_type = true; 2344 break; 2345 case TCG_TYPE_I64: 2346 has_type = TCG_TARGET_REG_BITS == 64; 2347 break; 2348 case TCG_TYPE_V64: 2349 has_type = TCG_TARGET_HAS_v64; 2350 break; 2351 case TCG_TYPE_V128: 2352 has_type = TCG_TARGET_HAS_v128; 2353 break; 2354 case TCG_TYPE_V256: 2355 has_type = TCG_TARGET_HAS_v256; 2356 break; 2357 default: 2358 has_type = false; 2359 break; 2360 } 2361 2362 switch (op) { 2363 case INDEX_op_discard: 2364 case INDEX_op_set_label: 2365 case INDEX_op_call: 2366 case INDEX_op_br: 2367 case INDEX_op_mb: 2368 case INDEX_op_insn_start: 2369 case INDEX_op_exit_tb: 2370 case INDEX_op_goto_tb: 2371 case INDEX_op_goto_ptr: 2372 case INDEX_op_qemu_ld_i32: 2373 case INDEX_op_qemu_st_i32: 2374 case INDEX_op_qemu_ld_i64: 2375 case INDEX_op_qemu_st_i64: 2376 return true; 2377 2378 case INDEX_op_qemu_st8_i32: 2379 return TCG_TARGET_HAS_qemu_st8_i32; 2380 2381 case INDEX_op_qemu_ld_i128: 2382 case INDEX_op_qemu_st_i128: 2383 return TCG_TARGET_HAS_qemu_ldst_i128; 2384 2385 case INDEX_op_add: 2386 case INDEX_op_and: 2387 case INDEX_op_brcond: 2388 case INDEX_op_deposit: 2389 case INDEX_op_extract: 2390 case INDEX_op_mov: 2391 case INDEX_op_movcond: 2392 case INDEX_op_negsetcond: 2393 case INDEX_op_or: 2394 case INDEX_op_setcond: 2395 case INDEX_op_sextract: 2396 case INDEX_op_xor: 2397 return has_type; 2398 2399 case INDEX_op_ld8u_i32: 2400 case INDEX_op_ld8s_i32: 2401 case INDEX_op_ld16u_i32: 2402 case INDEX_op_ld16s_i32: 2403 case INDEX_op_ld_i32: 2404 case INDEX_op_st8_i32: 2405 case INDEX_op_st16_i32: 2406 case INDEX_op_st_i32: 2407 return true; 2408 2409 case INDEX_op_add2_i32: 2410 return TCG_TARGET_HAS_add2_i32; 2411 case INDEX_op_sub2_i32: 2412 return TCG_TARGET_HAS_sub2_i32; 2413 2414 case INDEX_op_brcond2_i32: 2415 case INDEX_op_setcond2_i32: 2416 return TCG_TARGET_REG_BITS == 32; 2417 2418 case INDEX_op_ld8u_i64: 2419 case INDEX_op_ld8s_i64: 2420 case INDEX_op_ld16u_i64: 2421 case INDEX_op_ld16s_i64: 2422 case INDEX_op_ld32u_i64: 2423 case INDEX_op_ld32s_i64: 2424 case INDEX_op_ld_i64: 2425 case INDEX_op_st8_i64: 2426 case INDEX_op_st16_i64: 2427 case INDEX_op_st32_i64: 2428 case INDEX_op_st_i64: 2429 case INDEX_op_ext_i32_i64: 2430 case INDEX_op_extu_i32_i64: 2431 case INDEX_op_extrl_i64_i32: 2432 case INDEX_op_extrh_i64_i32: 2433 return TCG_TARGET_REG_BITS == 64; 2434 2435 case INDEX_op_add2_i64: 2436 return TCG_TARGET_HAS_add2_i64; 2437 case INDEX_op_sub2_i64: 2438 return TCG_TARGET_HAS_sub2_i64; 2439 2440 case INDEX_op_mov_vec: 2441 case INDEX_op_dup_vec: 2442 case INDEX_op_dupm_vec: 2443 case INDEX_op_ld_vec: 2444 case INDEX_op_st_vec: 2445 case INDEX_op_add_vec: 2446 case INDEX_op_sub_vec: 2447 case INDEX_op_and_vec: 2448 case INDEX_op_or_vec: 2449 case INDEX_op_xor_vec: 2450 case INDEX_op_cmp_vec: 2451 return has_type; 2452 case INDEX_op_dup2_vec: 2453 return has_type && TCG_TARGET_REG_BITS == 32; 2454 case INDEX_op_not_vec: 2455 return has_type && TCG_TARGET_HAS_not_vec; 2456 case INDEX_op_neg_vec: 2457 return has_type && TCG_TARGET_HAS_neg_vec; 2458 case INDEX_op_abs_vec: 2459 return has_type && TCG_TARGET_HAS_abs_vec; 2460 case INDEX_op_andc_vec: 2461 return has_type && TCG_TARGET_HAS_andc_vec; 2462 case INDEX_op_orc_vec: 2463 return has_type && TCG_TARGET_HAS_orc_vec; 2464 case INDEX_op_nand_vec: 2465 return has_type && TCG_TARGET_HAS_nand_vec; 2466 case INDEX_op_nor_vec: 2467 return has_type && TCG_TARGET_HAS_nor_vec; 2468 case INDEX_op_eqv_vec: 2469 return has_type && TCG_TARGET_HAS_eqv_vec; 2470 case INDEX_op_mul_vec: 2471 return has_type && TCG_TARGET_HAS_mul_vec; 2472 case INDEX_op_shli_vec: 2473 case INDEX_op_shri_vec: 2474 case INDEX_op_sari_vec: 2475 return has_type && TCG_TARGET_HAS_shi_vec; 2476 case INDEX_op_shls_vec: 2477 case INDEX_op_shrs_vec: 2478 case INDEX_op_sars_vec: 2479 return has_type && TCG_TARGET_HAS_shs_vec; 2480 case INDEX_op_shlv_vec: 2481 case INDEX_op_shrv_vec: 2482 case INDEX_op_sarv_vec: 2483 return has_type && TCG_TARGET_HAS_shv_vec; 2484 case INDEX_op_rotli_vec: 2485 return has_type && TCG_TARGET_HAS_roti_vec; 2486 case INDEX_op_rotls_vec: 2487 return has_type && TCG_TARGET_HAS_rots_vec; 2488 case INDEX_op_rotlv_vec: 2489 case INDEX_op_rotrv_vec: 2490 return has_type && TCG_TARGET_HAS_rotv_vec; 2491 case INDEX_op_ssadd_vec: 2492 case INDEX_op_usadd_vec: 2493 case INDEX_op_sssub_vec: 2494 case INDEX_op_ussub_vec: 2495 return has_type && TCG_TARGET_HAS_sat_vec; 2496 case INDEX_op_smin_vec: 2497 case INDEX_op_umin_vec: 2498 case INDEX_op_smax_vec: 2499 case INDEX_op_umax_vec: 2500 return has_type && TCG_TARGET_HAS_minmax_vec; 2501 case INDEX_op_bitsel_vec: 2502 return has_type && TCG_TARGET_HAS_bitsel_vec; 2503 case INDEX_op_cmpsel_vec: 2504 return has_type && TCG_TARGET_HAS_cmpsel_vec; 2505 2506 default: 2507 if (op < INDEX_op_last_generic) { 2508 const TCGOutOp *outop; 2509 TCGConstraintSetIndex con_set; 2510 2511 if (!has_type) { 2512 return false; 2513 } 2514 2515 outop = all_outop[op]; 2516 tcg_debug_assert(outop != NULL); 2517 2518 con_set = outop->static_constraint; 2519 if (con_set == C_Dynamic) { 2520 con_set = outop->dynamic_constraint(type, flags); 2521 } 2522 if (con_set >= 0) { 2523 return true; 2524 } 2525 tcg_debug_assert(con_set == C_NotImplemented); 2526 return false; 2527 } 2528 tcg_debug_assert(op < NB_OPS); 2529 return true; 2530 2531 case INDEX_op_last_generic: 2532 g_assert_not_reached(); 2533 } 2534 } 2535 2536 bool tcg_op_deposit_valid(TCGType type, unsigned ofs, unsigned len) 2537 { 2538 unsigned width; 2539 2540 tcg_debug_assert(type == TCG_TYPE_I32 || type == TCG_TYPE_I64); 2541 width = (type == TCG_TYPE_I32 ? 32 : 64); 2542 2543 tcg_debug_assert(ofs < width); 2544 tcg_debug_assert(len > 0); 2545 tcg_debug_assert(len <= width - ofs); 2546 2547 return TCG_TARGET_deposit_valid(type, ofs, len); 2548 } 2549 2550 static TCGOp *tcg_op_alloc(TCGOpcode opc, unsigned nargs); 2551 2552 static void tcg_gen_callN(void *func, TCGHelperInfo *info, 2553 TCGTemp *ret, TCGTemp **args) 2554 { 2555 TCGv_i64 extend_free[MAX_CALL_IARGS]; 2556 int n_extend = 0; 2557 TCGOp *op; 2558 int i, n, pi = 0, total_args; 2559 2560 if (unlikely(g_once_init_enter(HELPER_INFO_INIT(info)))) { 2561 init_call_layout(info); 2562 g_once_init_leave(HELPER_INFO_INIT(info), HELPER_INFO_INIT_VAL(info)); 2563 } 2564 2565 total_args = info->nr_out + info->nr_in + 2; 2566 op = tcg_op_alloc(INDEX_op_call, total_args); 2567 2568 #ifdef CONFIG_PLUGIN 2569 /* Flag helpers that may affect guest state */ 2570 if (tcg_ctx->plugin_insn && !(info->flags & TCG_CALL_NO_SIDE_EFFECTS)) { 2571 tcg_ctx->plugin_insn->calls_helpers = true; 2572 } 2573 #endif 2574 2575 TCGOP_CALLO(op) = n = info->nr_out; 2576 switch (n) { 2577 case 0: 2578 tcg_debug_assert(ret == NULL); 2579 break; 2580 case 1: 2581 tcg_debug_assert(ret != NULL); 2582 op->args[pi++] = temp_arg(ret); 2583 break; 2584 case 2: 2585 case 4: 2586 tcg_debug_assert(ret != NULL); 2587 tcg_debug_assert(ret->base_type == ret->type + ctz32(n)); 2588 tcg_debug_assert(ret->temp_subindex == 0); 2589 for (i = 0; i < n; ++i) { 2590 op->args[pi++] = temp_arg(ret + i); 2591 } 2592 break; 2593 default: 2594 g_assert_not_reached(); 2595 } 2596 2597 TCGOP_CALLI(op) = n = info->nr_in; 2598 for (i = 0; i < n; i++) { 2599 const TCGCallArgumentLoc *loc = &info->in[i]; 2600 TCGTemp *ts = args[loc->arg_idx] + loc->tmp_subindex; 2601 2602 switch (loc->kind) { 2603 case TCG_CALL_ARG_NORMAL: 2604 case TCG_CALL_ARG_BY_REF: 2605 case TCG_CALL_ARG_BY_REF_N: 2606 op->args[pi++] = temp_arg(ts); 2607 break; 2608 2609 case TCG_CALL_ARG_EXTEND_U: 2610 case TCG_CALL_ARG_EXTEND_S: 2611 { 2612 TCGv_i64 temp = tcg_temp_ebb_new_i64(); 2613 TCGv_i32 orig = temp_tcgv_i32(ts); 2614 2615 if (loc->kind == TCG_CALL_ARG_EXTEND_S) { 2616 tcg_gen_ext_i32_i64(temp, orig); 2617 } else { 2618 tcg_gen_extu_i32_i64(temp, orig); 2619 } 2620 op->args[pi++] = tcgv_i64_arg(temp); 2621 extend_free[n_extend++] = temp; 2622 } 2623 break; 2624 2625 default: 2626 g_assert_not_reached(); 2627 } 2628 } 2629 op->args[pi++] = (uintptr_t)func; 2630 op->args[pi++] = (uintptr_t)info; 2631 tcg_debug_assert(pi == total_args); 2632 2633 if (tcg_ctx->emit_before_op) { 2634 QTAILQ_INSERT_BEFORE(tcg_ctx->emit_before_op, op, link); 2635 } else { 2636 QTAILQ_INSERT_TAIL(&tcg_ctx->ops, op, link); 2637 } 2638 2639 tcg_debug_assert(n_extend < ARRAY_SIZE(extend_free)); 2640 for (i = 0; i < n_extend; ++i) { 2641 tcg_temp_free_i64(extend_free[i]); 2642 } 2643 } 2644 2645 void tcg_gen_call0(void *func, TCGHelperInfo *info, TCGTemp *ret) 2646 { 2647 tcg_gen_callN(func, info, ret, NULL); 2648 } 2649 2650 void tcg_gen_call1(void *func, TCGHelperInfo *info, TCGTemp *ret, TCGTemp *t1) 2651 { 2652 tcg_gen_callN(func, info, ret, &t1); 2653 } 2654 2655 void tcg_gen_call2(void *func, TCGHelperInfo *info, TCGTemp *ret, 2656 TCGTemp *t1, TCGTemp *t2) 2657 { 2658 TCGTemp *args[2] = { t1, t2 }; 2659 tcg_gen_callN(func, info, ret, args); 2660 } 2661 2662 void tcg_gen_call3(void *func, TCGHelperInfo *info, TCGTemp *ret, 2663 TCGTemp *t1, TCGTemp *t2, TCGTemp *t3) 2664 { 2665 TCGTemp *args[3] = { t1, t2, t3 }; 2666 tcg_gen_callN(func, info, ret, args); 2667 } 2668 2669 void tcg_gen_call4(void *func, TCGHelperInfo *info, TCGTemp *ret, 2670 TCGTemp *t1, TCGTemp *t2, TCGTemp *t3, TCGTemp *t4) 2671 { 2672 TCGTemp *args[4] = { t1, t2, t3, t4 }; 2673 tcg_gen_callN(func, info, ret, args); 2674 } 2675 2676 void tcg_gen_call5(void *func, TCGHelperInfo *info, TCGTemp *ret, TCGTemp *t1, 2677 TCGTemp *t2, TCGTemp *t3, TCGTemp *t4, TCGTemp *t5) 2678 { 2679 TCGTemp *args[5] = { t1, t2, t3, t4, t5 }; 2680 tcg_gen_callN(func, info, ret, args); 2681 } 2682 2683 void tcg_gen_call6(void *func, TCGHelperInfo *info, TCGTemp *ret, 2684 TCGTemp *t1, TCGTemp *t2, TCGTemp *t3, 2685 TCGTemp *t4, TCGTemp *t5, TCGTemp *t6) 2686 { 2687 TCGTemp *args[6] = { t1, t2, t3, t4, t5, t6 }; 2688 tcg_gen_callN(func, info, ret, args); 2689 } 2690 2691 void tcg_gen_call7(void *func, TCGHelperInfo *info, TCGTemp *ret, TCGTemp *t1, 2692 TCGTemp *t2, TCGTemp *t3, TCGTemp *t4, 2693 TCGTemp *t5, TCGTemp *t6, TCGTemp *t7) 2694 { 2695 TCGTemp *args[7] = { t1, t2, t3, t4, t5, t6, t7 }; 2696 tcg_gen_callN(func, info, ret, args); 2697 } 2698 2699 static void tcg_reg_alloc_start(TCGContext *s) 2700 { 2701 int i, n; 2702 2703 for (i = 0, n = s->nb_temps; i < n; i++) { 2704 TCGTemp *ts = &s->temps[i]; 2705 TCGTempVal val = TEMP_VAL_MEM; 2706 2707 switch (ts->kind) { 2708 case TEMP_CONST: 2709 val = TEMP_VAL_CONST; 2710 break; 2711 case TEMP_FIXED: 2712 val = TEMP_VAL_REG; 2713 break; 2714 case TEMP_GLOBAL: 2715 break; 2716 case TEMP_EBB: 2717 val = TEMP_VAL_DEAD; 2718 /* fall through */ 2719 case TEMP_TB: 2720 ts->mem_allocated = 0; 2721 break; 2722 default: 2723 g_assert_not_reached(); 2724 } 2725 ts->val_type = val; 2726 } 2727 2728 memset(s->reg_to_temp, 0, sizeof(s->reg_to_temp)); 2729 } 2730 2731 static char *tcg_get_arg_str_ptr(TCGContext *s, char *buf, int buf_size, 2732 TCGTemp *ts) 2733 { 2734 int idx = temp_idx(ts); 2735 2736 switch (ts->kind) { 2737 case TEMP_FIXED: 2738 case TEMP_GLOBAL: 2739 pstrcpy(buf, buf_size, ts->name); 2740 break; 2741 case TEMP_TB: 2742 snprintf(buf, buf_size, "loc%d", idx - s->nb_globals); 2743 break; 2744 case TEMP_EBB: 2745 snprintf(buf, buf_size, "tmp%d", idx - s->nb_globals); 2746 break; 2747 case TEMP_CONST: 2748 switch (ts->type) { 2749 case TCG_TYPE_I32: 2750 snprintf(buf, buf_size, "$0x%x", (int32_t)ts->val); 2751 break; 2752 #if TCG_TARGET_REG_BITS > 32 2753 case TCG_TYPE_I64: 2754 snprintf(buf, buf_size, "$0x%" PRIx64, ts->val); 2755 break; 2756 #endif 2757 case TCG_TYPE_V64: 2758 case TCG_TYPE_V128: 2759 case TCG_TYPE_V256: 2760 snprintf(buf, buf_size, "v%d$0x%" PRIx64, 2761 64 << (ts->type - TCG_TYPE_V64), ts->val); 2762 break; 2763 default: 2764 g_assert_not_reached(); 2765 } 2766 break; 2767 } 2768 return buf; 2769 } 2770 2771 static char *tcg_get_arg_str(TCGContext *s, char *buf, 2772 int buf_size, TCGArg arg) 2773 { 2774 return tcg_get_arg_str_ptr(s, buf, buf_size, arg_temp(arg)); 2775 } 2776 2777 static const char * const cond_name[] = 2778 { 2779 [TCG_COND_NEVER] = "never", 2780 [TCG_COND_ALWAYS] = "always", 2781 [TCG_COND_EQ] = "eq", 2782 [TCG_COND_NE] = "ne", 2783 [TCG_COND_LT] = "lt", 2784 [TCG_COND_GE] = "ge", 2785 [TCG_COND_LE] = "le", 2786 [TCG_COND_GT] = "gt", 2787 [TCG_COND_LTU] = "ltu", 2788 [TCG_COND_GEU] = "geu", 2789 [TCG_COND_LEU] = "leu", 2790 [TCG_COND_GTU] = "gtu", 2791 [TCG_COND_TSTEQ] = "tsteq", 2792 [TCG_COND_TSTNE] = "tstne", 2793 }; 2794 2795 static const char * const ldst_name[(MO_BSWAP | MO_SSIZE) + 1] = 2796 { 2797 [MO_UB] = "ub", 2798 [MO_SB] = "sb", 2799 [MO_LEUW] = "leuw", 2800 [MO_LESW] = "lesw", 2801 [MO_LEUL] = "leul", 2802 [MO_LESL] = "lesl", 2803 [MO_LEUQ] = "leq", 2804 [MO_BEUW] = "beuw", 2805 [MO_BESW] = "besw", 2806 [MO_BEUL] = "beul", 2807 [MO_BESL] = "besl", 2808 [MO_BEUQ] = "beq", 2809 [MO_128 + MO_BE] = "beo", 2810 [MO_128 + MO_LE] = "leo", 2811 }; 2812 2813 static const char * const alignment_name[(MO_AMASK >> MO_ASHIFT) + 1] = { 2814 [MO_UNALN >> MO_ASHIFT] = "un+", 2815 [MO_ALIGN >> MO_ASHIFT] = "al+", 2816 [MO_ALIGN_2 >> MO_ASHIFT] = "al2+", 2817 [MO_ALIGN_4 >> MO_ASHIFT] = "al4+", 2818 [MO_ALIGN_8 >> MO_ASHIFT] = "al8+", 2819 [MO_ALIGN_16 >> MO_ASHIFT] = "al16+", 2820 [MO_ALIGN_32 >> MO_ASHIFT] = "al32+", 2821 [MO_ALIGN_64 >> MO_ASHIFT] = "al64+", 2822 }; 2823 2824 static const char * const atom_name[(MO_ATOM_MASK >> MO_ATOM_SHIFT) + 1] = { 2825 [MO_ATOM_IFALIGN >> MO_ATOM_SHIFT] = "", 2826 [MO_ATOM_IFALIGN_PAIR >> MO_ATOM_SHIFT] = "pair+", 2827 [MO_ATOM_WITHIN16 >> MO_ATOM_SHIFT] = "w16+", 2828 [MO_ATOM_WITHIN16_PAIR >> MO_ATOM_SHIFT] = "w16p+", 2829 [MO_ATOM_SUBALIGN >> MO_ATOM_SHIFT] = "sub+", 2830 [MO_ATOM_NONE >> MO_ATOM_SHIFT] = "noat+", 2831 }; 2832 2833 static const char bswap_flag_name[][6] = { 2834 [TCG_BSWAP_IZ] = "iz", 2835 [TCG_BSWAP_OZ] = "oz", 2836 [TCG_BSWAP_OS] = "os", 2837 [TCG_BSWAP_IZ | TCG_BSWAP_OZ] = "iz,oz", 2838 [TCG_BSWAP_IZ | TCG_BSWAP_OS] = "iz,os", 2839 }; 2840 2841 #ifdef CONFIG_PLUGIN 2842 static const char * const plugin_from_name[] = { 2843 "from-tb", 2844 "from-insn", 2845 "after-insn", 2846 "after-tb", 2847 }; 2848 #endif 2849 2850 static inline bool tcg_regset_single(TCGRegSet d) 2851 { 2852 return (d & (d - 1)) == 0; 2853 } 2854 2855 static inline TCGReg tcg_regset_first(TCGRegSet d) 2856 { 2857 if (TCG_TARGET_NB_REGS <= 32) { 2858 return ctz32(d); 2859 } else { 2860 return ctz64(d); 2861 } 2862 } 2863 2864 /* Return only the number of characters output -- no error return. */ 2865 #define ne_fprintf(...) \ 2866 ({ int ret_ = fprintf(__VA_ARGS__); ret_ >= 0 ? ret_ : 0; }) 2867 2868 void tcg_dump_ops(TCGContext *s, FILE *f, bool have_prefs) 2869 { 2870 char buf[128]; 2871 TCGOp *op; 2872 2873 QTAILQ_FOREACH(op, &s->ops, link) { 2874 int i, k, nb_oargs, nb_iargs, nb_cargs; 2875 const TCGOpDef *def; 2876 TCGOpcode c; 2877 int col = 0; 2878 2879 c = op->opc; 2880 def = &tcg_op_defs[c]; 2881 2882 if (c == INDEX_op_insn_start) { 2883 nb_oargs = 0; 2884 col += ne_fprintf(f, "\n ----"); 2885 2886 for (i = 0, k = s->insn_start_words; i < k; ++i) { 2887 col += ne_fprintf(f, " %016" PRIx64, 2888 tcg_get_insn_start_param(op, i)); 2889 } 2890 } else if (c == INDEX_op_call) { 2891 const TCGHelperInfo *info = tcg_call_info(op); 2892 void *func = tcg_call_func(op); 2893 2894 /* variable number of arguments */ 2895 nb_oargs = TCGOP_CALLO(op); 2896 nb_iargs = TCGOP_CALLI(op); 2897 nb_cargs = def->nb_cargs; 2898 2899 col += ne_fprintf(f, " %s ", def->name); 2900 2901 /* 2902 * Print the function name from TCGHelperInfo, if available. 2903 * Note that plugins have a template function for the info, 2904 * but the actual function pointer comes from the plugin. 2905 */ 2906 if (func == info->func) { 2907 col += ne_fprintf(f, "%s", info->name); 2908 } else { 2909 col += ne_fprintf(f, "plugin(%p)", func); 2910 } 2911 2912 col += ne_fprintf(f, ",$0x%x,$%d", info->flags, nb_oargs); 2913 for (i = 0; i < nb_oargs; i++) { 2914 col += ne_fprintf(f, ",%s", tcg_get_arg_str(s, buf, sizeof(buf), 2915 op->args[i])); 2916 } 2917 for (i = 0; i < nb_iargs; i++) { 2918 TCGArg arg = op->args[nb_oargs + i]; 2919 const char *t = tcg_get_arg_str(s, buf, sizeof(buf), arg); 2920 col += ne_fprintf(f, ",%s", t); 2921 } 2922 } else { 2923 if (def->flags & TCG_OPF_INT) { 2924 col += ne_fprintf(f, " %s_i%d ", 2925 def->name, 2926 8 * tcg_type_size(TCGOP_TYPE(op))); 2927 } else if (def->flags & TCG_OPF_VECTOR) { 2928 col += ne_fprintf(f, "%s v%d,e%d,", 2929 def->name, 2930 8 * tcg_type_size(TCGOP_TYPE(op)), 2931 8 << TCGOP_VECE(op)); 2932 } else { 2933 col += ne_fprintf(f, " %s ", def->name); 2934 } 2935 2936 nb_oargs = def->nb_oargs; 2937 nb_iargs = def->nb_iargs; 2938 nb_cargs = def->nb_cargs; 2939 2940 k = 0; 2941 for (i = 0; i < nb_oargs; i++) { 2942 const char *sep = k ? "," : ""; 2943 col += ne_fprintf(f, "%s%s", sep, 2944 tcg_get_arg_str(s, buf, sizeof(buf), 2945 op->args[k++])); 2946 } 2947 for (i = 0; i < nb_iargs; i++) { 2948 const char *sep = k ? "," : ""; 2949 col += ne_fprintf(f, "%s%s", sep, 2950 tcg_get_arg_str(s, buf, sizeof(buf), 2951 op->args[k++])); 2952 } 2953 switch (c) { 2954 case INDEX_op_brcond: 2955 case INDEX_op_setcond: 2956 case INDEX_op_negsetcond: 2957 case INDEX_op_movcond: 2958 case INDEX_op_brcond2_i32: 2959 case INDEX_op_setcond2_i32: 2960 case INDEX_op_cmp_vec: 2961 case INDEX_op_cmpsel_vec: 2962 if (op->args[k] < ARRAY_SIZE(cond_name) 2963 && cond_name[op->args[k]]) { 2964 col += ne_fprintf(f, ",%s", cond_name[op->args[k++]]); 2965 } else { 2966 col += ne_fprintf(f, ",$0x%" TCG_PRIlx, op->args[k++]); 2967 } 2968 i = 1; 2969 break; 2970 case INDEX_op_qemu_ld_i32: 2971 case INDEX_op_qemu_st_i32: 2972 case INDEX_op_qemu_st8_i32: 2973 case INDEX_op_qemu_ld_i64: 2974 case INDEX_op_qemu_st_i64: 2975 case INDEX_op_qemu_ld_i128: 2976 case INDEX_op_qemu_st_i128: 2977 { 2978 const char *s_al, *s_op, *s_at; 2979 MemOpIdx oi = op->args[k++]; 2980 MemOp mop = get_memop(oi); 2981 unsigned ix = get_mmuidx(oi); 2982 2983 s_al = alignment_name[(mop & MO_AMASK) >> MO_ASHIFT]; 2984 s_op = ldst_name[mop & (MO_BSWAP | MO_SSIZE)]; 2985 s_at = atom_name[(mop & MO_ATOM_MASK) >> MO_ATOM_SHIFT]; 2986 mop &= ~(MO_AMASK | MO_BSWAP | MO_SSIZE | MO_ATOM_MASK); 2987 2988 /* If all fields are accounted for, print symbolically. */ 2989 if (!mop && s_al && s_op && s_at) { 2990 col += ne_fprintf(f, ",%s%s%s,%u", 2991 s_at, s_al, s_op, ix); 2992 } else { 2993 mop = get_memop(oi); 2994 col += ne_fprintf(f, ",$0x%x,%u", mop, ix); 2995 } 2996 i = 1; 2997 } 2998 break; 2999 case INDEX_op_bswap16: 3000 case INDEX_op_bswap32: 3001 case INDEX_op_bswap64: 3002 { 3003 TCGArg flags = op->args[k]; 3004 const char *name = NULL; 3005 3006 if (flags < ARRAY_SIZE(bswap_flag_name)) { 3007 name = bswap_flag_name[flags]; 3008 } 3009 if (name) { 3010 col += ne_fprintf(f, ",%s", name); 3011 } else { 3012 col += ne_fprintf(f, ",$0x%" TCG_PRIlx, flags); 3013 } 3014 i = k = 1; 3015 } 3016 break; 3017 #ifdef CONFIG_PLUGIN 3018 case INDEX_op_plugin_cb: 3019 { 3020 TCGArg from = op->args[k++]; 3021 const char *name = NULL; 3022 3023 if (from < ARRAY_SIZE(plugin_from_name)) { 3024 name = plugin_from_name[from]; 3025 } 3026 if (name) { 3027 col += ne_fprintf(f, "%s", name); 3028 } else { 3029 col += ne_fprintf(f, "$0x%" TCG_PRIlx, from); 3030 } 3031 i = 1; 3032 } 3033 break; 3034 #endif 3035 default: 3036 i = 0; 3037 break; 3038 } 3039 switch (c) { 3040 case INDEX_op_set_label: 3041 case INDEX_op_br: 3042 case INDEX_op_brcond: 3043 case INDEX_op_brcond2_i32: 3044 col += ne_fprintf(f, "%s$L%d", k ? "," : "", 3045 arg_label(op->args[k])->id); 3046 i++, k++; 3047 break; 3048 case INDEX_op_mb: 3049 { 3050 TCGBar membar = op->args[k]; 3051 const char *b_op, *m_op; 3052 3053 switch (membar & TCG_BAR_SC) { 3054 case 0: 3055 b_op = "none"; 3056 break; 3057 case TCG_BAR_LDAQ: 3058 b_op = "acq"; 3059 break; 3060 case TCG_BAR_STRL: 3061 b_op = "rel"; 3062 break; 3063 case TCG_BAR_SC: 3064 b_op = "seq"; 3065 break; 3066 default: 3067 g_assert_not_reached(); 3068 } 3069 3070 switch (membar & TCG_MO_ALL) { 3071 case 0: 3072 m_op = "none"; 3073 break; 3074 case TCG_MO_LD_LD: 3075 m_op = "rr"; 3076 break; 3077 case TCG_MO_LD_ST: 3078 m_op = "rw"; 3079 break; 3080 case TCG_MO_ST_LD: 3081 m_op = "wr"; 3082 break; 3083 case TCG_MO_ST_ST: 3084 m_op = "ww"; 3085 break; 3086 case TCG_MO_LD_LD | TCG_MO_LD_ST: 3087 m_op = "rr+rw"; 3088 break; 3089 case TCG_MO_LD_LD | TCG_MO_ST_LD: 3090 m_op = "rr+wr"; 3091 break; 3092 case TCG_MO_LD_LD | TCG_MO_ST_ST: 3093 m_op = "rr+ww"; 3094 break; 3095 case TCG_MO_LD_ST | TCG_MO_ST_LD: 3096 m_op = "rw+wr"; 3097 break; 3098 case TCG_MO_LD_ST | TCG_MO_ST_ST: 3099 m_op = "rw+ww"; 3100 break; 3101 case TCG_MO_ST_LD | TCG_MO_ST_ST: 3102 m_op = "wr+ww"; 3103 break; 3104 case TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_LD: 3105 m_op = "rr+rw+wr"; 3106 break; 3107 case TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST: 3108 m_op = "rr+rw+ww"; 3109 break; 3110 case TCG_MO_LD_LD | TCG_MO_ST_LD | TCG_MO_ST_ST: 3111 m_op = "rr+wr+ww"; 3112 break; 3113 case TCG_MO_LD_ST | TCG_MO_ST_LD | TCG_MO_ST_ST: 3114 m_op = "rw+wr+ww"; 3115 break; 3116 case TCG_MO_ALL: 3117 m_op = "all"; 3118 break; 3119 default: 3120 g_assert_not_reached(); 3121 } 3122 3123 col += ne_fprintf(f, "%s%s:%s", (k ? "," : ""), b_op, m_op); 3124 i++, k++; 3125 } 3126 break; 3127 default: 3128 break; 3129 } 3130 for (; i < nb_cargs; i++, k++) { 3131 col += ne_fprintf(f, "%s$0x%" TCG_PRIlx, k ? "," : "", 3132 op->args[k]); 3133 } 3134 } 3135 3136 if (have_prefs || op->life) { 3137 for (; col < 40; ++col) { 3138 putc(' ', f); 3139 } 3140 } 3141 3142 if (op->life) { 3143 unsigned life = op->life; 3144 3145 if (life & (SYNC_ARG * 3)) { 3146 ne_fprintf(f, " sync:"); 3147 for (i = 0; i < 2; ++i) { 3148 if (life & (SYNC_ARG << i)) { 3149 ne_fprintf(f, " %d", i); 3150 } 3151 } 3152 } 3153 life /= DEAD_ARG; 3154 if (life) { 3155 ne_fprintf(f, " dead:"); 3156 for (i = 0; life; ++i, life >>= 1) { 3157 if (life & 1) { 3158 ne_fprintf(f, " %d", i); 3159 } 3160 } 3161 } 3162 } 3163 3164 if (have_prefs) { 3165 for (i = 0; i < nb_oargs; ++i) { 3166 TCGRegSet set = output_pref(op, i); 3167 3168 if (i == 0) { 3169 ne_fprintf(f, " pref="); 3170 } else { 3171 ne_fprintf(f, ","); 3172 } 3173 if (set == 0) { 3174 ne_fprintf(f, "none"); 3175 } else if (set == MAKE_64BIT_MASK(0, TCG_TARGET_NB_REGS)) { 3176 ne_fprintf(f, "all"); 3177 #ifdef CONFIG_DEBUG_TCG 3178 } else if (tcg_regset_single(set)) { 3179 TCGReg reg = tcg_regset_first(set); 3180 ne_fprintf(f, "%s", tcg_target_reg_names[reg]); 3181 #endif 3182 } else if (TCG_TARGET_NB_REGS <= 32) { 3183 ne_fprintf(f, "0x%x", (uint32_t)set); 3184 } else { 3185 ne_fprintf(f, "0x%" PRIx64, (uint64_t)set); 3186 } 3187 } 3188 } 3189 3190 putc('\n', f); 3191 } 3192 } 3193 3194 /* we give more priority to constraints with less registers */ 3195 static int get_constraint_priority(const TCGArgConstraint *arg_ct, int k) 3196 { 3197 int n; 3198 3199 arg_ct += k; 3200 n = ctpop64(arg_ct->regs); 3201 3202 /* 3203 * Sort constraints of a single register first, which includes output 3204 * aliases (which must exactly match the input already allocated). 3205 */ 3206 if (n == 1 || arg_ct->oalias) { 3207 return INT_MAX; 3208 } 3209 3210 /* 3211 * Sort register pairs next, first then second immediately after. 3212 * Arbitrarily sort multiple pairs by the index of the first reg; 3213 * there shouldn't be many pairs. 3214 */ 3215 switch (arg_ct->pair) { 3216 case 1: 3217 case 3: 3218 return (k + 1) * 2; 3219 case 2: 3220 return (arg_ct->pair_index + 1) * 2 - 1; 3221 } 3222 3223 /* Finally, sort by decreasing register count. */ 3224 assert(n > 1); 3225 return -n; 3226 } 3227 3228 /* sort from highest priority to lowest */ 3229 static void sort_constraints(TCGArgConstraint *a, int start, int n) 3230 { 3231 int i, j; 3232 3233 for (i = 0; i < n; i++) { 3234 a[start + i].sort_index = start + i; 3235 } 3236 if (n <= 1) { 3237 return; 3238 } 3239 for (i = 0; i < n - 1; i++) { 3240 for (j = i + 1; j < n; j++) { 3241 int p1 = get_constraint_priority(a, a[start + i].sort_index); 3242 int p2 = get_constraint_priority(a, a[start + j].sort_index); 3243 if (p1 < p2) { 3244 int tmp = a[start + i].sort_index; 3245 a[start + i].sort_index = a[start + j].sort_index; 3246 a[start + j].sort_index = tmp; 3247 } 3248 } 3249 } 3250 } 3251 3252 static const TCGArgConstraint empty_cts[TCG_MAX_OP_ARGS]; 3253 static TCGArgConstraint all_cts[ARRAY_SIZE(constraint_sets)][TCG_MAX_OP_ARGS]; 3254 3255 static void process_constraint_sets(void) 3256 { 3257 for (size_t c = 0; c < ARRAY_SIZE(constraint_sets); ++c) { 3258 const TCGConstraintSet *tdefs = &constraint_sets[c]; 3259 TCGArgConstraint *args_ct = all_cts[c]; 3260 int nb_oargs = tdefs->nb_oargs; 3261 int nb_iargs = tdefs->nb_iargs; 3262 int nb_args = nb_oargs + nb_iargs; 3263 bool saw_alias_pair = false; 3264 3265 for (int i = 0; i < nb_args; i++) { 3266 const char *ct_str = tdefs->args_ct_str[i]; 3267 bool input_p = i >= nb_oargs; 3268 int o; 3269 3270 switch (*ct_str) { 3271 case '0' ... '9': 3272 o = *ct_str - '0'; 3273 tcg_debug_assert(input_p); 3274 tcg_debug_assert(o < nb_oargs); 3275 tcg_debug_assert(args_ct[o].regs != 0); 3276 tcg_debug_assert(!args_ct[o].oalias); 3277 args_ct[i] = args_ct[o]; 3278 /* The output sets oalias. */ 3279 args_ct[o].oalias = 1; 3280 args_ct[o].alias_index = i; 3281 /* The input sets ialias. */ 3282 args_ct[i].ialias = 1; 3283 args_ct[i].alias_index = o; 3284 if (args_ct[i].pair) { 3285 saw_alias_pair = true; 3286 } 3287 tcg_debug_assert(ct_str[1] == '\0'); 3288 continue; 3289 3290 case '&': 3291 tcg_debug_assert(!input_p); 3292 args_ct[i].newreg = true; 3293 ct_str++; 3294 break; 3295 3296 case 'p': /* plus */ 3297 /* Allocate to the register after the previous. */ 3298 tcg_debug_assert(i > (input_p ? nb_oargs : 0)); 3299 o = i - 1; 3300 tcg_debug_assert(!args_ct[o].pair); 3301 tcg_debug_assert(!args_ct[o].ct); 3302 args_ct[i] = (TCGArgConstraint){ 3303 .pair = 2, 3304 .pair_index = o, 3305 .regs = args_ct[o].regs << 1, 3306 .newreg = args_ct[o].newreg, 3307 }; 3308 args_ct[o].pair = 1; 3309 args_ct[o].pair_index = i; 3310 tcg_debug_assert(ct_str[1] == '\0'); 3311 continue; 3312 3313 case 'm': /* minus */ 3314 /* Allocate to the register before the previous. */ 3315 tcg_debug_assert(i > (input_p ? nb_oargs : 0)); 3316 o = i - 1; 3317 tcg_debug_assert(!args_ct[o].pair); 3318 tcg_debug_assert(!args_ct[o].ct); 3319 args_ct[i] = (TCGArgConstraint){ 3320 .pair = 1, 3321 .pair_index = o, 3322 .regs = args_ct[o].regs >> 1, 3323 .newreg = args_ct[o].newreg, 3324 }; 3325 args_ct[o].pair = 2; 3326 args_ct[o].pair_index = i; 3327 tcg_debug_assert(ct_str[1] == '\0'); 3328 continue; 3329 } 3330 3331 do { 3332 switch (*ct_str) { 3333 case 'i': 3334 args_ct[i].ct |= TCG_CT_CONST; 3335 break; 3336 #ifdef TCG_REG_ZERO 3337 case 'z': 3338 args_ct[i].ct |= TCG_CT_REG_ZERO; 3339 break; 3340 #endif 3341 3342 /* Include all of the target-specific constraints. */ 3343 3344 #undef CONST 3345 #define CONST(CASE, MASK) \ 3346 case CASE: args_ct[i].ct |= MASK; break; 3347 #define REGS(CASE, MASK) \ 3348 case CASE: args_ct[i].regs |= MASK; break; 3349 3350 #include "tcg-target-con-str.h" 3351 3352 #undef REGS 3353 #undef CONST 3354 default: 3355 case '0' ... '9': 3356 case '&': 3357 case 'p': 3358 case 'm': 3359 /* Typo in TCGConstraintSet constraint. */ 3360 g_assert_not_reached(); 3361 } 3362 } while (*++ct_str != '\0'); 3363 } 3364 3365 /* 3366 * Fix up output pairs that are aliased with inputs. 3367 * When we created the alias, we copied pair from the output. 3368 * There are three cases: 3369 * (1a) Pairs of inputs alias pairs of outputs. 3370 * (1b) One input aliases the first of a pair of outputs. 3371 * (2) One input aliases the second of a pair of outputs. 3372 * 3373 * Case 1a is handled by making sure that the pair_index'es are 3374 * properly updated so that they appear the same as a pair of inputs. 3375 * 3376 * Case 1b is handled by setting the pair_index of the input to 3377 * itself, simply so it doesn't point to an unrelated argument. 3378 * Since we don't encounter the "second" during the input allocation 3379 * phase, nothing happens with the second half of the input pair. 3380 * 3381 * Case 2 is handled by setting the second input to pair=3, the 3382 * first output to pair=3, and the pair_index'es to match. 3383 */ 3384 if (saw_alias_pair) { 3385 for (int i = nb_oargs; i < nb_args; i++) { 3386 int o, o2, i2; 3387 3388 /* 3389 * Since [0-9pm] must be alone in the constraint string, 3390 * the only way they can both be set is if the pair comes 3391 * from the output alias. 3392 */ 3393 if (!args_ct[i].ialias) { 3394 continue; 3395 } 3396 switch (args_ct[i].pair) { 3397 case 0: 3398 break; 3399 case 1: 3400 o = args_ct[i].alias_index; 3401 o2 = args_ct[o].pair_index; 3402 tcg_debug_assert(args_ct[o].pair == 1); 3403 tcg_debug_assert(args_ct[o2].pair == 2); 3404 if (args_ct[o2].oalias) { 3405 /* Case 1a */ 3406 i2 = args_ct[o2].alias_index; 3407 tcg_debug_assert(args_ct[i2].pair == 2); 3408 args_ct[i2].pair_index = i; 3409 args_ct[i].pair_index = i2; 3410 } else { 3411 /* Case 1b */ 3412 args_ct[i].pair_index = i; 3413 } 3414 break; 3415 case 2: 3416 o = args_ct[i].alias_index; 3417 o2 = args_ct[o].pair_index; 3418 tcg_debug_assert(args_ct[o].pair == 2); 3419 tcg_debug_assert(args_ct[o2].pair == 1); 3420 if (args_ct[o2].oalias) { 3421 /* Case 1a */ 3422 i2 = args_ct[o2].alias_index; 3423 tcg_debug_assert(args_ct[i2].pair == 1); 3424 args_ct[i2].pair_index = i; 3425 args_ct[i].pair_index = i2; 3426 } else { 3427 /* Case 2 */ 3428 args_ct[i].pair = 3; 3429 args_ct[o2].pair = 3; 3430 args_ct[i].pair_index = o2; 3431 args_ct[o2].pair_index = i; 3432 } 3433 break; 3434 default: 3435 g_assert_not_reached(); 3436 } 3437 } 3438 } 3439 3440 /* sort the constraints (XXX: this is just an heuristic) */ 3441 sort_constraints(args_ct, 0, nb_oargs); 3442 sort_constraints(args_ct, nb_oargs, nb_iargs); 3443 } 3444 } 3445 3446 static const TCGArgConstraint *opcode_args_ct(const TCGOp *op) 3447 { 3448 TCGOpcode opc = op->opc; 3449 TCGType type = TCGOP_TYPE(op); 3450 unsigned flags = TCGOP_FLAGS(op); 3451 const TCGOpDef *def = &tcg_op_defs[opc]; 3452 const TCGOutOp *outop = all_outop[opc]; 3453 TCGConstraintSetIndex con_set; 3454 3455 if (def->flags & TCG_OPF_NOT_PRESENT) { 3456 return empty_cts; 3457 } 3458 3459 if (outop) { 3460 con_set = outop->static_constraint; 3461 if (con_set == C_Dynamic) { 3462 con_set = outop->dynamic_constraint(type, flags); 3463 } 3464 } else { 3465 con_set = tcg_target_op_def(opc, type, flags); 3466 } 3467 tcg_debug_assert(con_set >= 0); 3468 tcg_debug_assert(con_set < ARRAY_SIZE(constraint_sets)); 3469 3470 /* The constraint arguments must match TCGOpcode arguments. */ 3471 tcg_debug_assert(constraint_sets[con_set].nb_oargs == def->nb_oargs); 3472 tcg_debug_assert(constraint_sets[con_set].nb_iargs == def->nb_iargs); 3473 3474 return all_cts[con_set]; 3475 } 3476 3477 static void remove_label_use(TCGOp *op, int idx) 3478 { 3479 TCGLabel *label = arg_label(op->args[idx]); 3480 TCGLabelUse *use; 3481 3482 QSIMPLEQ_FOREACH(use, &label->branches, next) { 3483 if (use->op == op) { 3484 QSIMPLEQ_REMOVE(&label->branches, use, TCGLabelUse, next); 3485 return; 3486 } 3487 } 3488 g_assert_not_reached(); 3489 } 3490 3491 void tcg_op_remove(TCGContext *s, TCGOp *op) 3492 { 3493 switch (op->opc) { 3494 case INDEX_op_br: 3495 remove_label_use(op, 0); 3496 break; 3497 case INDEX_op_brcond: 3498 remove_label_use(op, 3); 3499 break; 3500 case INDEX_op_brcond2_i32: 3501 remove_label_use(op, 5); 3502 break; 3503 default: 3504 break; 3505 } 3506 3507 QTAILQ_REMOVE(&s->ops, op, link); 3508 QTAILQ_INSERT_TAIL(&s->free_ops, op, link); 3509 s->nb_ops--; 3510 } 3511 3512 void tcg_remove_ops_after(TCGOp *op) 3513 { 3514 TCGContext *s = tcg_ctx; 3515 3516 while (true) { 3517 TCGOp *last = tcg_last_op(); 3518 if (last == op) { 3519 return; 3520 } 3521 tcg_op_remove(s, last); 3522 } 3523 } 3524 3525 static TCGOp *tcg_op_alloc(TCGOpcode opc, unsigned nargs) 3526 { 3527 TCGContext *s = tcg_ctx; 3528 TCGOp *op = NULL; 3529 3530 if (unlikely(!QTAILQ_EMPTY(&s->free_ops))) { 3531 QTAILQ_FOREACH(op, &s->free_ops, link) { 3532 if (nargs <= op->nargs) { 3533 QTAILQ_REMOVE(&s->free_ops, op, link); 3534 nargs = op->nargs; 3535 goto found; 3536 } 3537 } 3538 } 3539 3540 /* Most opcodes have 3 or 4 operands: reduce fragmentation. */ 3541 nargs = MAX(4, nargs); 3542 op = tcg_malloc(sizeof(TCGOp) + sizeof(TCGArg) * nargs); 3543 3544 found: 3545 memset(op, 0, offsetof(TCGOp, link)); 3546 op->opc = opc; 3547 op->nargs = nargs; 3548 3549 /* Check for bitfield overflow. */ 3550 tcg_debug_assert(op->nargs == nargs); 3551 3552 s->nb_ops++; 3553 return op; 3554 } 3555 3556 TCGOp *tcg_emit_op(TCGOpcode opc, unsigned nargs) 3557 { 3558 TCGOp *op = tcg_op_alloc(opc, nargs); 3559 3560 if (tcg_ctx->emit_before_op) { 3561 QTAILQ_INSERT_BEFORE(tcg_ctx->emit_before_op, op, link); 3562 } else { 3563 QTAILQ_INSERT_TAIL(&tcg_ctx->ops, op, link); 3564 } 3565 return op; 3566 } 3567 3568 TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *old_op, 3569 TCGOpcode opc, TCGType type, unsigned nargs) 3570 { 3571 TCGOp *new_op = tcg_op_alloc(opc, nargs); 3572 3573 TCGOP_TYPE(new_op) = type; 3574 QTAILQ_INSERT_BEFORE(old_op, new_op, link); 3575 return new_op; 3576 } 3577 3578 TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *old_op, 3579 TCGOpcode opc, TCGType type, unsigned nargs) 3580 { 3581 TCGOp *new_op = tcg_op_alloc(opc, nargs); 3582 3583 TCGOP_TYPE(new_op) = type; 3584 QTAILQ_INSERT_AFTER(&s->ops, old_op, new_op, link); 3585 return new_op; 3586 } 3587 3588 static void move_label_uses(TCGLabel *to, TCGLabel *from) 3589 { 3590 TCGLabelUse *u; 3591 3592 QSIMPLEQ_FOREACH(u, &from->branches, next) { 3593 TCGOp *op = u->op; 3594 switch (op->opc) { 3595 case INDEX_op_br: 3596 op->args[0] = label_arg(to); 3597 break; 3598 case INDEX_op_brcond: 3599 op->args[3] = label_arg(to); 3600 break; 3601 case INDEX_op_brcond2_i32: 3602 op->args[5] = label_arg(to); 3603 break; 3604 default: 3605 g_assert_not_reached(); 3606 } 3607 } 3608 3609 QSIMPLEQ_CONCAT(&to->branches, &from->branches); 3610 } 3611 3612 /* Reachable analysis : remove unreachable code. */ 3613 static void __attribute__((noinline)) 3614 reachable_code_pass(TCGContext *s) 3615 { 3616 TCGOp *op, *op_next, *op_prev; 3617 bool dead = false; 3618 3619 QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) { 3620 bool remove = dead; 3621 TCGLabel *label; 3622 3623 switch (op->opc) { 3624 case INDEX_op_set_label: 3625 label = arg_label(op->args[0]); 3626 3627 /* 3628 * Note that the first op in the TB is always a load, 3629 * so there is always something before a label. 3630 */ 3631 op_prev = QTAILQ_PREV(op, link); 3632 3633 /* 3634 * If we find two sequential labels, move all branches to 3635 * reference the second label and remove the first label. 3636 * Do this before branch to next optimization, so that the 3637 * middle label is out of the way. 3638 */ 3639 if (op_prev->opc == INDEX_op_set_label) { 3640 move_label_uses(label, arg_label(op_prev->args[0])); 3641 tcg_op_remove(s, op_prev); 3642 op_prev = QTAILQ_PREV(op, link); 3643 } 3644 3645 /* 3646 * Optimization can fold conditional branches to unconditional. 3647 * If we find a label which is preceded by an unconditional 3648 * branch to next, remove the branch. We couldn't do this when 3649 * processing the branch because any dead code between the branch 3650 * and label had not yet been removed. 3651 */ 3652 if (op_prev->opc == INDEX_op_br && 3653 label == arg_label(op_prev->args[0])) { 3654 tcg_op_remove(s, op_prev); 3655 /* Fall through means insns become live again. */ 3656 dead = false; 3657 } 3658 3659 if (QSIMPLEQ_EMPTY(&label->branches)) { 3660 /* 3661 * While there is an occasional backward branch, virtually 3662 * all branches generated by the translators are forward. 3663 * Which means that generally we will have already removed 3664 * all references to the label that will be, and there is 3665 * little to be gained by iterating. 3666 */ 3667 remove = true; 3668 } else { 3669 /* Once we see a label, insns become live again. */ 3670 dead = false; 3671 remove = false; 3672 } 3673 break; 3674 3675 case INDEX_op_br: 3676 case INDEX_op_exit_tb: 3677 case INDEX_op_goto_ptr: 3678 /* Unconditional branches; everything following is dead. */ 3679 dead = true; 3680 break; 3681 3682 case INDEX_op_call: 3683 /* Notice noreturn helper calls, raising exceptions. */ 3684 if (tcg_call_flags(op) & TCG_CALL_NO_RETURN) { 3685 dead = true; 3686 } 3687 break; 3688 3689 case INDEX_op_insn_start: 3690 /* Never remove -- we need to keep these for unwind. */ 3691 remove = false; 3692 break; 3693 3694 default: 3695 break; 3696 } 3697 3698 if (remove) { 3699 tcg_op_remove(s, op); 3700 } 3701 } 3702 } 3703 3704 #define TS_DEAD 1 3705 #define TS_MEM 2 3706 3707 #define IS_DEAD_ARG(n) (arg_life & (DEAD_ARG << (n))) 3708 #define NEED_SYNC_ARG(n) (arg_life & (SYNC_ARG << (n))) 3709 3710 /* For liveness_pass_1, the register preferences for a given temp. */ 3711 static inline TCGRegSet *la_temp_pref(TCGTemp *ts) 3712 { 3713 return ts->state_ptr; 3714 } 3715 3716 /* For liveness_pass_1, reset the preferences for a given temp to the 3717 * maximal regset for its type. 3718 */ 3719 static inline void la_reset_pref(TCGTemp *ts) 3720 { 3721 *la_temp_pref(ts) 3722 = (ts->state == TS_DEAD ? 0 : tcg_target_available_regs[ts->type]); 3723 } 3724 3725 /* liveness analysis: end of function: all temps are dead, and globals 3726 should be in memory. */ 3727 static void la_func_end(TCGContext *s, int ng, int nt) 3728 { 3729 int i; 3730 3731 for (i = 0; i < ng; ++i) { 3732 s->temps[i].state = TS_DEAD | TS_MEM; 3733 la_reset_pref(&s->temps[i]); 3734 } 3735 for (i = ng; i < nt; ++i) { 3736 s->temps[i].state = TS_DEAD; 3737 la_reset_pref(&s->temps[i]); 3738 } 3739 } 3740 3741 /* liveness analysis: end of basic block: all temps are dead, globals 3742 and local temps should be in memory. */ 3743 static void la_bb_end(TCGContext *s, int ng, int nt) 3744 { 3745 int i; 3746 3747 for (i = 0; i < nt; ++i) { 3748 TCGTemp *ts = &s->temps[i]; 3749 int state; 3750 3751 switch (ts->kind) { 3752 case TEMP_FIXED: 3753 case TEMP_GLOBAL: 3754 case TEMP_TB: 3755 state = TS_DEAD | TS_MEM; 3756 break; 3757 case TEMP_EBB: 3758 case TEMP_CONST: 3759 state = TS_DEAD; 3760 break; 3761 default: 3762 g_assert_not_reached(); 3763 } 3764 ts->state = state; 3765 la_reset_pref(ts); 3766 } 3767 } 3768 3769 /* liveness analysis: sync globals back to memory. */ 3770 static void la_global_sync(TCGContext *s, int ng) 3771 { 3772 int i; 3773 3774 for (i = 0; i < ng; ++i) { 3775 int state = s->temps[i].state; 3776 s->temps[i].state = state | TS_MEM; 3777 if (state == TS_DEAD) { 3778 /* If the global was previously dead, reset prefs. */ 3779 la_reset_pref(&s->temps[i]); 3780 } 3781 } 3782 } 3783 3784 /* 3785 * liveness analysis: conditional branch: all temps are dead unless 3786 * explicitly live-across-conditional-branch, globals and local temps 3787 * should be synced. 3788 */ 3789 static void la_bb_sync(TCGContext *s, int ng, int nt) 3790 { 3791 la_global_sync(s, ng); 3792 3793 for (int i = ng; i < nt; ++i) { 3794 TCGTemp *ts = &s->temps[i]; 3795 int state; 3796 3797 switch (ts->kind) { 3798 case TEMP_TB: 3799 state = ts->state; 3800 ts->state = state | TS_MEM; 3801 if (state != TS_DEAD) { 3802 continue; 3803 } 3804 break; 3805 case TEMP_EBB: 3806 case TEMP_CONST: 3807 continue; 3808 default: 3809 g_assert_not_reached(); 3810 } 3811 la_reset_pref(&s->temps[i]); 3812 } 3813 } 3814 3815 /* liveness analysis: sync globals back to memory and kill. */ 3816 static void la_global_kill(TCGContext *s, int ng) 3817 { 3818 int i; 3819 3820 for (i = 0; i < ng; i++) { 3821 s->temps[i].state = TS_DEAD | TS_MEM; 3822 la_reset_pref(&s->temps[i]); 3823 } 3824 } 3825 3826 /* liveness analysis: note live globals crossing calls. */ 3827 static void la_cross_call(TCGContext *s, int nt) 3828 { 3829 TCGRegSet mask = ~tcg_target_call_clobber_regs; 3830 int i; 3831 3832 for (i = 0; i < nt; i++) { 3833 TCGTemp *ts = &s->temps[i]; 3834 if (!(ts->state & TS_DEAD)) { 3835 TCGRegSet *pset = la_temp_pref(ts); 3836 TCGRegSet set = *pset; 3837 3838 set &= mask; 3839 /* If the combination is not possible, restart. */ 3840 if (set == 0) { 3841 set = tcg_target_available_regs[ts->type] & mask; 3842 } 3843 *pset = set; 3844 } 3845 } 3846 } 3847 3848 /* 3849 * Liveness analysis: Verify the lifetime of TEMP_TB, and reduce 3850 * to TEMP_EBB, if possible. 3851 */ 3852 static void __attribute__((noinline)) 3853 liveness_pass_0(TCGContext *s) 3854 { 3855 void * const multiple_ebb = (void *)(uintptr_t)-1; 3856 int nb_temps = s->nb_temps; 3857 TCGOp *op, *ebb; 3858 3859 for (int i = s->nb_globals; i < nb_temps; ++i) { 3860 s->temps[i].state_ptr = NULL; 3861 } 3862 3863 /* 3864 * Represent each EBB by the op at which it begins. In the case of 3865 * the first EBB, this is the first op, otherwise it is a label. 3866 * Collect the uses of each TEMP_TB: NULL for unused, EBB for use 3867 * within a single EBB, else MULTIPLE_EBB. 3868 */ 3869 ebb = QTAILQ_FIRST(&s->ops); 3870 QTAILQ_FOREACH(op, &s->ops, link) { 3871 const TCGOpDef *def; 3872 int nb_oargs, nb_iargs; 3873 3874 switch (op->opc) { 3875 case INDEX_op_set_label: 3876 ebb = op; 3877 continue; 3878 case INDEX_op_discard: 3879 continue; 3880 case INDEX_op_call: 3881 nb_oargs = TCGOP_CALLO(op); 3882 nb_iargs = TCGOP_CALLI(op); 3883 break; 3884 default: 3885 def = &tcg_op_defs[op->opc]; 3886 nb_oargs = def->nb_oargs; 3887 nb_iargs = def->nb_iargs; 3888 break; 3889 } 3890 3891 for (int i = 0; i < nb_oargs + nb_iargs; ++i) { 3892 TCGTemp *ts = arg_temp(op->args[i]); 3893 3894 if (ts->kind != TEMP_TB) { 3895 continue; 3896 } 3897 if (ts->state_ptr == NULL) { 3898 ts->state_ptr = ebb; 3899 } else if (ts->state_ptr != ebb) { 3900 ts->state_ptr = multiple_ebb; 3901 } 3902 } 3903 } 3904 3905 /* 3906 * For TEMP_TB that turned out not to be used beyond one EBB, 3907 * reduce the liveness to TEMP_EBB. 3908 */ 3909 for (int i = s->nb_globals; i < nb_temps; ++i) { 3910 TCGTemp *ts = &s->temps[i]; 3911 if (ts->kind == TEMP_TB && ts->state_ptr != multiple_ebb) { 3912 ts->kind = TEMP_EBB; 3913 } 3914 } 3915 } 3916 3917 /* Liveness analysis : update the opc_arg_life array to tell if a 3918 given input arguments is dead. Instructions updating dead 3919 temporaries are removed. */ 3920 static void __attribute__((noinline)) 3921 liveness_pass_1(TCGContext *s) 3922 { 3923 int nb_globals = s->nb_globals; 3924 int nb_temps = s->nb_temps; 3925 TCGOp *op, *op_prev; 3926 TCGRegSet *prefs; 3927 int i; 3928 3929 prefs = tcg_malloc(sizeof(TCGRegSet) * nb_temps); 3930 for (i = 0; i < nb_temps; ++i) { 3931 s->temps[i].state_ptr = prefs + i; 3932 } 3933 3934 /* ??? Should be redundant with the exit_tb that ends the TB. */ 3935 la_func_end(s, nb_globals, nb_temps); 3936 3937 QTAILQ_FOREACH_REVERSE_SAFE(op, &s->ops, link, op_prev) { 3938 int nb_iargs, nb_oargs; 3939 TCGOpcode opc_new, opc_new2; 3940 TCGLifeData arg_life = 0; 3941 TCGTemp *ts; 3942 TCGOpcode opc = op->opc; 3943 const TCGOpDef *def = &tcg_op_defs[opc]; 3944 const TCGArgConstraint *args_ct; 3945 3946 switch (opc) { 3947 case INDEX_op_call: 3948 { 3949 const TCGHelperInfo *info = tcg_call_info(op); 3950 int call_flags = tcg_call_flags(op); 3951 3952 nb_oargs = TCGOP_CALLO(op); 3953 nb_iargs = TCGOP_CALLI(op); 3954 3955 /* pure functions can be removed if their result is unused */ 3956 if (call_flags & TCG_CALL_NO_SIDE_EFFECTS) { 3957 for (i = 0; i < nb_oargs; i++) { 3958 ts = arg_temp(op->args[i]); 3959 if (ts->state != TS_DEAD) { 3960 goto do_not_remove_call; 3961 } 3962 } 3963 goto do_remove; 3964 } 3965 do_not_remove_call: 3966 3967 /* Output args are dead. */ 3968 for (i = 0; i < nb_oargs; i++) { 3969 ts = arg_temp(op->args[i]); 3970 if (ts->state & TS_DEAD) { 3971 arg_life |= DEAD_ARG << i; 3972 } 3973 if (ts->state & TS_MEM) { 3974 arg_life |= SYNC_ARG << i; 3975 } 3976 ts->state = TS_DEAD; 3977 la_reset_pref(ts); 3978 } 3979 3980 /* Not used -- it will be tcg_target_call_oarg_reg(). */ 3981 memset(op->output_pref, 0, sizeof(op->output_pref)); 3982 3983 if (!(call_flags & (TCG_CALL_NO_WRITE_GLOBALS | 3984 TCG_CALL_NO_READ_GLOBALS))) { 3985 la_global_kill(s, nb_globals); 3986 } else if (!(call_flags & TCG_CALL_NO_READ_GLOBALS)) { 3987 la_global_sync(s, nb_globals); 3988 } 3989 3990 /* Record arguments that die in this helper. */ 3991 for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) { 3992 ts = arg_temp(op->args[i]); 3993 if (ts->state & TS_DEAD) { 3994 arg_life |= DEAD_ARG << i; 3995 } 3996 } 3997 3998 /* For all live registers, remove call-clobbered prefs. */ 3999 la_cross_call(s, nb_temps); 4000 4001 /* 4002 * Input arguments are live for preceding opcodes. 4003 * 4004 * For those arguments that die, and will be allocated in 4005 * registers, clear the register set for that arg, to be 4006 * filled in below. For args that will be on the stack, 4007 * reset to any available reg. Process arguments in reverse 4008 * order so that if a temp is used more than once, the stack 4009 * reset to max happens before the register reset to 0. 4010 */ 4011 for (i = nb_iargs - 1; i >= 0; i--) { 4012 const TCGCallArgumentLoc *loc = &info->in[i]; 4013 ts = arg_temp(op->args[nb_oargs + i]); 4014 4015 if (ts->state & TS_DEAD) { 4016 switch (loc->kind) { 4017 case TCG_CALL_ARG_NORMAL: 4018 case TCG_CALL_ARG_EXTEND_U: 4019 case TCG_CALL_ARG_EXTEND_S: 4020 if (arg_slot_reg_p(loc->arg_slot)) { 4021 *la_temp_pref(ts) = 0; 4022 break; 4023 } 4024 /* fall through */ 4025 default: 4026 *la_temp_pref(ts) = 4027 tcg_target_available_regs[ts->type]; 4028 break; 4029 } 4030 ts->state &= ~TS_DEAD; 4031 } 4032 } 4033 4034 /* 4035 * For each input argument, add its input register to prefs. 4036 * If a temp is used once, this produces a single set bit; 4037 * if a temp is used multiple times, this produces a set. 4038 */ 4039 for (i = 0; i < nb_iargs; i++) { 4040 const TCGCallArgumentLoc *loc = &info->in[i]; 4041 ts = arg_temp(op->args[nb_oargs + i]); 4042 4043 switch (loc->kind) { 4044 case TCG_CALL_ARG_NORMAL: 4045 case TCG_CALL_ARG_EXTEND_U: 4046 case TCG_CALL_ARG_EXTEND_S: 4047 if (arg_slot_reg_p(loc->arg_slot)) { 4048 tcg_regset_set_reg(*la_temp_pref(ts), 4049 tcg_target_call_iarg_regs[loc->arg_slot]); 4050 } 4051 break; 4052 default: 4053 break; 4054 } 4055 } 4056 } 4057 break; 4058 case INDEX_op_insn_start: 4059 break; 4060 case INDEX_op_discard: 4061 /* mark the temporary as dead */ 4062 ts = arg_temp(op->args[0]); 4063 ts->state = TS_DEAD; 4064 la_reset_pref(ts); 4065 break; 4066 4067 case INDEX_op_add2_i32: 4068 case INDEX_op_add2_i64: 4069 opc_new = INDEX_op_add; 4070 goto do_addsub2; 4071 case INDEX_op_sub2_i32: 4072 case INDEX_op_sub2_i64: 4073 opc_new = INDEX_op_sub; 4074 do_addsub2: 4075 nb_iargs = 4; 4076 nb_oargs = 2; 4077 /* Test if the high part of the operation is dead, but not 4078 the low part. The result can be optimized to a simple 4079 add or sub. This happens often for x86_64 guest when the 4080 cpu mode is set to 32 bit. */ 4081 if (arg_temp(op->args[1])->state == TS_DEAD) { 4082 if (arg_temp(op->args[0])->state == TS_DEAD) { 4083 goto do_remove; 4084 } 4085 /* Replace the opcode and adjust the args in place, 4086 leaving 3 unused args at the end. */ 4087 op->opc = opc = opc_new; 4088 op->args[1] = op->args[2]; 4089 op->args[2] = op->args[4]; 4090 /* Fall through and mark the single-word operation live. */ 4091 nb_iargs = 2; 4092 nb_oargs = 1; 4093 } 4094 goto do_not_remove; 4095 4096 case INDEX_op_muls2: 4097 opc_new = INDEX_op_mul; 4098 opc_new2 = INDEX_op_mulsh; 4099 goto do_mul2; 4100 case INDEX_op_mulu2: 4101 opc_new = INDEX_op_mul; 4102 opc_new2 = INDEX_op_muluh; 4103 do_mul2: 4104 nb_iargs = 2; 4105 nb_oargs = 2; 4106 if (arg_temp(op->args[1])->state == TS_DEAD) { 4107 if (arg_temp(op->args[0])->state == TS_DEAD) { 4108 /* Both parts of the operation are dead. */ 4109 goto do_remove; 4110 } 4111 /* The high part of the operation is dead; generate the low. */ 4112 op->opc = opc = opc_new; 4113 op->args[1] = op->args[2]; 4114 op->args[2] = op->args[3]; 4115 } else if (arg_temp(op->args[0])->state == TS_DEAD && 4116 tcg_op_supported(opc_new2, TCGOP_TYPE(op), 0)) { 4117 /* The low part of the operation is dead; generate the high. */ 4118 op->opc = opc = opc_new2; 4119 op->args[0] = op->args[1]; 4120 op->args[1] = op->args[2]; 4121 op->args[2] = op->args[3]; 4122 } else { 4123 goto do_not_remove; 4124 } 4125 /* Mark the single-word operation live. */ 4126 nb_oargs = 1; 4127 goto do_not_remove; 4128 4129 default: 4130 /* XXX: optimize by hardcoding common cases (e.g. triadic ops) */ 4131 nb_iargs = def->nb_iargs; 4132 nb_oargs = def->nb_oargs; 4133 4134 /* Test if the operation can be removed because all 4135 its outputs are dead. We assume that nb_oargs == 0 4136 implies side effects */ 4137 if (!(def->flags & TCG_OPF_SIDE_EFFECTS) && nb_oargs != 0) { 4138 for (i = 0; i < nb_oargs; i++) { 4139 if (arg_temp(op->args[i])->state != TS_DEAD) { 4140 goto do_not_remove; 4141 } 4142 } 4143 goto do_remove; 4144 } 4145 goto do_not_remove; 4146 4147 do_remove: 4148 tcg_op_remove(s, op); 4149 break; 4150 4151 do_not_remove: 4152 for (i = 0; i < nb_oargs; i++) { 4153 ts = arg_temp(op->args[i]); 4154 4155 /* Remember the preference of the uses that followed. */ 4156 if (i < ARRAY_SIZE(op->output_pref)) { 4157 op->output_pref[i] = *la_temp_pref(ts); 4158 } 4159 4160 /* Output args are dead. */ 4161 if (ts->state & TS_DEAD) { 4162 arg_life |= DEAD_ARG << i; 4163 } 4164 if (ts->state & TS_MEM) { 4165 arg_life |= SYNC_ARG << i; 4166 } 4167 ts->state = TS_DEAD; 4168 la_reset_pref(ts); 4169 } 4170 4171 /* If end of basic block, update. */ 4172 if (def->flags & TCG_OPF_BB_EXIT) { 4173 la_func_end(s, nb_globals, nb_temps); 4174 } else if (def->flags & TCG_OPF_COND_BRANCH) { 4175 la_bb_sync(s, nb_globals, nb_temps); 4176 } else if (def->flags & TCG_OPF_BB_END) { 4177 la_bb_end(s, nb_globals, nb_temps); 4178 } else if (def->flags & TCG_OPF_SIDE_EFFECTS) { 4179 la_global_sync(s, nb_globals); 4180 if (def->flags & TCG_OPF_CALL_CLOBBER) { 4181 la_cross_call(s, nb_temps); 4182 } 4183 } 4184 4185 /* Record arguments that die in this opcode. */ 4186 for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) { 4187 ts = arg_temp(op->args[i]); 4188 if (ts->state & TS_DEAD) { 4189 arg_life |= DEAD_ARG << i; 4190 } 4191 } 4192 4193 /* Input arguments are live for preceding opcodes. */ 4194 for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) { 4195 ts = arg_temp(op->args[i]); 4196 if (ts->state & TS_DEAD) { 4197 /* For operands that were dead, initially allow 4198 all regs for the type. */ 4199 *la_temp_pref(ts) = tcg_target_available_regs[ts->type]; 4200 ts->state &= ~TS_DEAD; 4201 } 4202 } 4203 4204 /* Incorporate constraints for this operand. */ 4205 switch (opc) { 4206 case INDEX_op_mov: 4207 /* Note that these are TCG_OPF_NOT_PRESENT and do not 4208 have proper constraints. That said, special case 4209 moves to propagate preferences backward. */ 4210 if (IS_DEAD_ARG(1)) { 4211 *la_temp_pref(arg_temp(op->args[0])) 4212 = *la_temp_pref(arg_temp(op->args[1])); 4213 } 4214 break; 4215 4216 default: 4217 args_ct = opcode_args_ct(op); 4218 for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) { 4219 const TCGArgConstraint *ct = &args_ct[i]; 4220 TCGRegSet set, *pset; 4221 4222 ts = arg_temp(op->args[i]); 4223 pset = la_temp_pref(ts); 4224 set = *pset; 4225 4226 set &= ct->regs; 4227 if (ct->ialias) { 4228 set &= output_pref(op, ct->alias_index); 4229 } 4230 /* If the combination is not possible, restart. */ 4231 if (set == 0) { 4232 set = ct->regs; 4233 } 4234 *pset = set; 4235 } 4236 break; 4237 } 4238 break; 4239 } 4240 op->life = arg_life; 4241 } 4242 } 4243 4244 /* Liveness analysis: Convert indirect regs to direct temporaries. */ 4245 static bool __attribute__((noinline)) 4246 liveness_pass_2(TCGContext *s) 4247 { 4248 int nb_globals = s->nb_globals; 4249 int nb_temps, i; 4250 bool changes = false; 4251 TCGOp *op, *op_next; 4252 4253 /* Create a temporary for each indirect global. */ 4254 for (i = 0; i < nb_globals; ++i) { 4255 TCGTemp *its = &s->temps[i]; 4256 if (its->indirect_reg) { 4257 TCGTemp *dts = tcg_temp_alloc(s); 4258 dts->type = its->type; 4259 dts->base_type = its->base_type; 4260 dts->temp_subindex = its->temp_subindex; 4261 dts->kind = TEMP_EBB; 4262 its->state_ptr = dts; 4263 } else { 4264 its->state_ptr = NULL; 4265 } 4266 /* All globals begin dead. */ 4267 its->state = TS_DEAD; 4268 } 4269 for (nb_temps = s->nb_temps; i < nb_temps; ++i) { 4270 TCGTemp *its = &s->temps[i]; 4271 its->state_ptr = NULL; 4272 its->state = TS_DEAD; 4273 } 4274 4275 QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) { 4276 TCGOpcode opc = op->opc; 4277 const TCGOpDef *def = &tcg_op_defs[opc]; 4278 TCGLifeData arg_life = op->life; 4279 int nb_iargs, nb_oargs, call_flags; 4280 TCGTemp *arg_ts, *dir_ts; 4281 4282 if (opc == INDEX_op_call) { 4283 nb_oargs = TCGOP_CALLO(op); 4284 nb_iargs = TCGOP_CALLI(op); 4285 call_flags = tcg_call_flags(op); 4286 } else { 4287 nb_iargs = def->nb_iargs; 4288 nb_oargs = def->nb_oargs; 4289 4290 /* Set flags similar to how calls require. */ 4291 if (def->flags & TCG_OPF_COND_BRANCH) { 4292 /* Like reading globals: sync_globals */ 4293 call_flags = TCG_CALL_NO_WRITE_GLOBALS; 4294 } else if (def->flags & TCG_OPF_BB_END) { 4295 /* Like writing globals: save_globals */ 4296 call_flags = 0; 4297 } else if (def->flags & TCG_OPF_SIDE_EFFECTS) { 4298 /* Like reading globals: sync_globals */ 4299 call_flags = TCG_CALL_NO_WRITE_GLOBALS; 4300 } else { 4301 /* No effect on globals. */ 4302 call_flags = (TCG_CALL_NO_READ_GLOBALS | 4303 TCG_CALL_NO_WRITE_GLOBALS); 4304 } 4305 } 4306 4307 /* Make sure that input arguments are available. */ 4308 for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) { 4309 arg_ts = arg_temp(op->args[i]); 4310 dir_ts = arg_ts->state_ptr; 4311 if (dir_ts && arg_ts->state == TS_DEAD) { 4312 TCGOpcode lopc = (arg_ts->type == TCG_TYPE_I32 4313 ? INDEX_op_ld_i32 4314 : INDEX_op_ld_i64); 4315 TCGOp *lop = tcg_op_insert_before(s, op, lopc, 4316 arg_ts->type, 3); 4317 4318 lop->args[0] = temp_arg(dir_ts); 4319 lop->args[1] = temp_arg(arg_ts->mem_base); 4320 lop->args[2] = arg_ts->mem_offset; 4321 4322 /* Loaded, but synced with memory. */ 4323 arg_ts->state = TS_MEM; 4324 } 4325 } 4326 4327 /* Perform input replacement, and mark inputs that became dead. 4328 No action is required except keeping temp_state up to date 4329 so that we reload when needed. */ 4330 for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) { 4331 arg_ts = arg_temp(op->args[i]); 4332 dir_ts = arg_ts->state_ptr; 4333 if (dir_ts) { 4334 op->args[i] = temp_arg(dir_ts); 4335 changes = true; 4336 if (IS_DEAD_ARG(i)) { 4337 arg_ts->state = TS_DEAD; 4338 } 4339 } 4340 } 4341 4342 /* Liveness analysis should ensure that the following are 4343 all correct, for call sites and basic block end points. */ 4344 if (call_flags & TCG_CALL_NO_READ_GLOBALS) { 4345 /* Nothing to do */ 4346 } else if (call_flags & TCG_CALL_NO_WRITE_GLOBALS) { 4347 for (i = 0; i < nb_globals; ++i) { 4348 /* Liveness should see that globals are synced back, 4349 that is, either TS_DEAD or TS_MEM. */ 4350 arg_ts = &s->temps[i]; 4351 tcg_debug_assert(arg_ts->state_ptr == 0 4352 || arg_ts->state != 0); 4353 } 4354 } else { 4355 for (i = 0; i < nb_globals; ++i) { 4356 /* Liveness should see that globals are saved back, 4357 that is, TS_DEAD, waiting to be reloaded. */ 4358 arg_ts = &s->temps[i]; 4359 tcg_debug_assert(arg_ts->state_ptr == 0 4360 || arg_ts->state == TS_DEAD); 4361 } 4362 } 4363 4364 /* Outputs become available. */ 4365 if (opc == INDEX_op_mov) { 4366 arg_ts = arg_temp(op->args[0]); 4367 dir_ts = arg_ts->state_ptr; 4368 if (dir_ts) { 4369 op->args[0] = temp_arg(dir_ts); 4370 changes = true; 4371 4372 /* The output is now live and modified. */ 4373 arg_ts->state = 0; 4374 4375 if (NEED_SYNC_ARG(0)) { 4376 TCGOpcode sopc = (arg_ts->type == TCG_TYPE_I32 4377 ? INDEX_op_st_i32 4378 : INDEX_op_st_i64); 4379 TCGOp *sop = tcg_op_insert_after(s, op, sopc, 4380 arg_ts->type, 3); 4381 TCGTemp *out_ts = dir_ts; 4382 4383 if (IS_DEAD_ARG(0)) { 4384 out_ts = arg_temp(op->args[1]); 4385 arg_ts->state = TS_DEAD; 4386 tcg_op_remove(s, op); 4387 } else { 4388 arg_ts->state = TS_MEM; 4389 } 4390 4391 sop->args[0] = temp_arg(out_ts); 4392 sop->args[1] = temp_arg(arg_ts->mem_base); 4393 sop->args[2] = arg_ts->mem_offset; 4394 } else { 4395 tcg_debug_assert(!IS_DEAD_ARG(0)); 4396 } 4397 } 4398 } else { 4399 for (i = 0; i < nb_oargs; i++) { 4400 arg_ts = arg_temp(op->args[i]); 4401 dir_ts = arg_ts->state_ptr; 4402 if (!dir_ts) { 4403 continue; 4404 } 4405 op->args[i] = temp_arg(dir_ts); 4406 changes = true; 4407 4408 /* The output is now live and modified. */ 4409 arg_ts->state = 0; 4410 4411 /* Sync outputs upon their last write. */ 4412 if (NEED_SYNC_ARG(i)) { 4413 TCGOpcode sopc = (arg_ts->type == TCG_TYPE_I32 4414 ? INDEX_op_st_i32 4415 : INDEX_op_st_i64); 4416 TCGOp *sop = tcg_op_insert_after(s, op, sopc, 4417 arg_ts->type, 3); 4418 4419 sop->args[0] = temp_arg(dir_ts); 4420 sop->args[1] = temp_arg(arg_ts->mem_base); 4421 sop->args[2] = arg_ts->mem_offset; 4422 4423 arg_ts->state = TS_MEM; 4424 } 4425 /* Drop outputs that are dead. */ 4426 if (IS_DEAD_ARG(i)) { 4427 arg_ts->state = TS_DEAD; 4428 } 4429 } 4430 } 4431 } 4432 4433 return changes; 4434 } 4435 4436 static void temp_allocate_frame(TCGContext *s, TCGTemp *ts) 4437 { 4438 intptr_t off; 4439 int size, align; 4440 4441 /* When allocating an object, look at the full type. */ 4442 size = tcg_type_size(ts->base_type); 4443 switch (ts->base_type) { 4444 case TCG_TYPE_I32: 4445 align = 4; 4446 break; 4447 case TCG_TYPE_I64: 4448 case TCG_TYPE_V64: 4449 align = 8; 4450 break; 4451 case TCG_TYPE_I128: 4452 case TCG_TYPE_V128: 4453 case TCG_TYPE_V256: 4454 /* 4455 * Note that we do not require aligned storage for V256, 4456 * and that we provide alignment for I128 to match V128, 4457 * even if that's above what the host ABI requires. 4458 */ 4459 align = 16; 4460 break; 4461 default: 4462 g_assert_not_reached(); 4463 } 4464 4465 /* 4466 * Assume the stack is sufficiently aligned. 4467 * This affects e.g. ARM NEON, where we have 8 byte stack alignment 4468 * and do not require 16 byte vector alignment. This seems slightly 4469 * easier than fully parameterizing the above switch statement. 4470 */ 4471 align = MIN(TCG_TARGET_STACK_ALIGN, align); 4472 off = ROUND_UP(s->current_frame_offset, align); 4473 4474 /* If we've exhausted the stack frame, restart with a smaller TB. */ 4475 if (off + size > s->frame_end) { 4476 tcg_raise_tb_overflow(s); 4477 } 4478 s->current_frame_offset = off + size; 4479 #if defined(__sparc__) 4480 off += TCG_TARGET_STACK_BIAS; 4481 #endif 4482 4483 /* If the object was subdivided, assign memory to all the parts. */ 4484 if (ts->base_type != ts->type) { 4485 int part_size = tcg_type_size(ts->type); 4486 int part_count = size / part_size; 4487 4488 /* 4489 * Each part is allocated sequentially in tcg_temp_new_internal. 4490 * Jump back to the first part by subtracting the current index. 4491 */ 4492 ts -= ts->temp_subindex; 4493 for (int i = 0; i < part_count; ++i) { 4494 ts[i].mem_offset = off + i * part_size; 4495 ts[i].mem_base = s->frame_temp; 4496 ts[i].mem_allocated = 1; 4497 } 4498 } else { 4499 ts->mem_offset = off; 4500 ts->mem_base = s->frame_temp; 4501 ts->mem_allocated = 1; 4502 } 4503 } 4504 4505 /* Assign @reg to @ts, and update reg_to_temp[]. */ 4506 static void set_temp_val_reg(TCGContext *s, TCGTemp *ts, TCGReg reg) 4507 { 4508 if (ts->val_type == TEMP_VAL_REG) { 4509 TCGReg old = ts->reg; 4510 tcg_debug_assert(s->reg_to_temp[old] == ts); 4511 if (old == reg) { 4512 return; 4513 } 4514 s->reg_to_temp[old] = NULL; 4515 } 4516 tcg_debug_assert(s->reg_to_temp[reg] == NULL); 4517 s->reg_to_temp[reg] = ts; 4518 ts->val_type = TEMP_VAL_REG; 4519 ts->reg = reg; 4520 } 4521 4522 /* Assign a non-register value type to @ts, and update reg_to_temp[]. */ 4523 static void set_temp_val_nonreg(TCGContext *s, TCGTemp *ts, TCGTempVal type) 4524 { 4525 tcg_debug_assert(type != TEMP_VAL_REG); 4526 if (ts->val_type == TEMP_VAL_REG) { 4527 TCGReg reg = ts->reg; 4528 tcg_debug_assert(s->reg_to_temp[reg] == ts); 4529 s->reg_to_temp[reg] = NULL; 4530 } 4531 ts->val_type = type; 4532 } 4533 4534 static void temp_load(TCGContext *, TCGTemp *, TCGRegSet, TCGRegSet, TCGRegSet); 4535 4536 /* Mark a temporary as free or dead. If 'free_or_dead' is negative, 4537 mark it free; otherwise mark it dead. */ 4538 static void temp_free_or_dead(TCGContext *s, TCGTemp *ts, int free_or_dead) 4539 { 4540 TCGTempVal new_type; 4541 4542 switch (ts->kind) { 4543 case TEMP_FIXED: 4544 return; 4545 case TEMP_GLOBAL: 4546 case TEMP_TB: 4547 new_type = TEMP_VAL_MEM; 4548 break; 4549 case TEMP_EBB: 4550 new_type = free_or_dead < 0 ? TEMP_VAL_MEM : TEMP_VAL_DEAD; 4551 break; 4552 case TEMP_CONST: 4553 new_type = TEMP_VAL_CONST; 4554 break; 4555 default: 4556 g_assert_not_reached(); 4557 } 4558 set_temp_val_nonreg(s, ts, new_type); 4559 } 4560 4561 /* Mark a temporary as dead. */ 4562 static inline void temp_dead(TCGContext *s, TCGTemp *ts) 4563 { 4564 temp_free_or_dead(s, ts, 1); 4565 } 4566 4567 /* Sync a temporary to memory. 'allocated_regs' is used in case a temporary 4568 registers needs to be allocated to store a constant. If 'free_or_dead' 4569 is non-zero, subsequently release the temporary; if it is positive, the 4570 temp is dead; if it is negative, the temp is free. */ 4571 static void temp_sync(TCGContext *s, TCGTemp *ts, TCGRegSet allocated_regs, 4572 TCGRegSet preferred_regs, int free_or_dead) 4573 { 4574 if (!temp_readonly(ts) && !ts->mem_coherent) { 4575 if (!ts->mem_allocated) { 4576 temp_allocate_frame(s, ts); 4577 } 4578 switch (ts->val_type) { 4579 case TEMP_VAL_CONST: 4580 /* If we're going to free the temp immediately, then we won't 4581 require it later in a register, so attempt to store the 4582 constant to memory directly. */ 4583 if (free_or_dead 4584 && tcg_out_sti(s, ts->type, ts->val, 4585 ts->mem_base->reg, ts->mem_offset)) { 4586 break; 4587 } 4588 temp_load(s, ts, tcg_target_available_regs[ts->type], 4589 allocated_regs, preferred_regs); 4590 /* fallthrough */ 4591 4592 case TEMP_VAL_REG: 4593 tcg_out_st(s, ts->type, ts->reg, 4594 ts->mem_base->reg, ts->mem_offset); 4595 break; 4596 4597 case TEMP_VAL_MEM: 4598 break; 4599 4600 case TEMP_VAL_DEAD: 4601 default: 4602 g_assert_not_reached(); 4603 } 4604 ts->mem_coherent = 1; 4605 } 4606 if (free_or_dead) { 4607 temp_free_or_dead(s, ts, free_or_dead); 4608 } 4609 } 4610 4611 /* free register 'reg' by spilling the corresponding temporary if necessary */ 4612 static void tcg_reg_free(TCGContext *s, TCGReg reg, TCGRegSet allocated_regs) 4613 { 4614 TCGTemp *ts = s->reg_to_temp[reg]; 4615 if (ts != NULL) { 4616 temp_sync(s, ts, allocated_regs, 0, -1); 4617 } 4618 } 4619 4620 /** 4621 * tcg_reg_alloc: 4622 * @required_regs: Set of registers in which we must allocate. 4623 * @allocated_regs: Set of registers which must be avoided. 4624 * @preferred_regs: Set of registers we should prefer. 4625 * @rev: True if we search the registers in "indirect" order. 4626 * 4627 * The allocated register must be in @required_regs & ~@allocated_regs, 4628 * but if we can put it in @preferred_regs we may save a move later. 4629 */ 4630 static TCGReg tcg_reg_alloc(TCGContext *s, TCGRegSet required_regs, 4631 TCGRegSet allocated_regs, 4632 TCGRegSet preferred_regs, bool rev) 4633 { 4634 int i, j, f, n = ARRAY_SIZE(tcg_target_reg_alloc_order); 4635 TCGRegSet reg_ct[2]; 4636 const int *order; 4637 4638 reg_ct[1] = required_regs & ~allocated_regs; 4639 tcg_debug_assert(reg_ct[1] != 0); 4640 reg_ct[0] = reg_ct[1] & preferred_regs; 4641 4642 /* Skip the preferred_regs option if it cannot be satisfied, 4643 or if the preference made no difference. */ 4644 f = reg_ct[0] == 0 || reg_ct[0] == reg_ct[1]; 4645 4646 order = rev ? indirect_reg_alloc_order : tcg_target_reg_alloc_order; 4647 4648 /* Try free registers, preferences first. */ 4649 for (j = f; j < 2; j++) { 4650 TCGRegSet set = reg_ct[j]; 4651 4652 if (tcg_regset_single(set)) { 4653 /* One register in the set. */ 4654 TCGReg reg = tcg_regset_first(set); 4655 if (s->reg_to_temp[reg] == NULL) { 4656 return reg; 4657 } 4658 } else { 4659 for (i = 0; i < n; i++) { 4660 TCGReg reg = order[i]; 4661 if (s->reg_to_temp[reg] == NULL && 4662 tcg_regset_test_reg(set, reg)) { 4663 return reg; 4664 } 4665 } 4666 } 4667 } 4668 4669 /* We must spill something. */ 4670 for (j = f; j < 2; j++) { 4671 TCGRegSet set = reg_ct[j]; 4672 4673 if (tcg_regset_single(set)) { 4674 /* One register in the set. */ 4675 TCGReg reg = tcg_regset_first(set); 4676 tcg_reg_free(s, reg, allocated_regs); 4677 return reg; 4678 } else { 4679 for (i = 0; i < n; i++) { 4680 TCGReg reg = order[i]; 4681 if (tcg_regset_test_reg(set, reg)) { 4682 tcg_reg_free(s, reg, allocated_regs); 4683 return reg; 4684 } 4685 } 4686 } 4687 } 4688 4689 g_assert_not_reached(); 4690 } 4691 4692 static TCGReg tcg_reg_alloc_pair(TCGContext *s, TCGRegSet required_regs, 4693 TCGRegSet allocated_regs, 4694 TCGRegSet preferred_regs, bool rev) 4695 { 4696 int i, j, k, fmin, n = ARRAY_SIZE(tcg_target_reg_alloc_order); 4697 TCGRegSet reg_ct[2]; 4698 const int *order; 4699 4700 /* Ensure that if I is not in allocated_regs, I+1 is not either. */ 4701 reg_ct[1] = required_regs & ~(allocated_regs | (allocated_regs >> 1)); 4702 tcg_debug_assert(reg_ct[1] != 0); 4703 reg_ct[0] = reg_ct[1] & preferred_regs; 4704 4705 order = rev ? indirect_reg_alloc_order : tcg_target_reg_alloc_order; 4706 4707 /* 4708 * Skip the preferred_regs option if it cannot be satisfied, 4709 * or if the preference made no difference. 4710 */ 4711 k = reg_ct[0] == 0 || reg_ct[0] == reg_ct[1]; 4712 4713 /* 4714 * Minimize the number of flushes by looking for 2 free registers first, 4715 * then a single flush, then two flushes. 4716 */ 4717 for (fmin = 2; fmin >= 0; fmin--) { 4718 for (j = k; j < 2; j++) { 4719 TCGRegSet set = reg_ct[j]; 4720 4721 for (i = 0; i < n; i++) { 4722 TCGReg reg = order[i]; 4723 4724 if (tcg_regset_test_reg(set, reg)) { 4725 int f = !s->reg_to_temp[reg] + !s->reg_to_temp[reg + 1]; 4726 if (f >= fmin) { 4727 tcg_reg_free(s, reg, allocated_regs); 4728 tcg_reg_free(s, reg + 1, allocated_regs); 4729 return reg; 4730 } 4731 } 4732 } 4733 } 4734 } 4735 g_assert_not_reached(); 4736 } 4737 4738 /* Make sure the temporary is in a register. If needed, allocate the register 4739 from DESIRED while avoiding ALLOCATED. */ 4740 static void temp_load(TCGContext *s, TCGTemp *ts, TCGRegSet desired_regs, 4741 TCGRegSet allocated_regs, TCGRegSet preferred_regs) 4742 { 4743 TCGReg reg; 4744 4745 switch (ts->val_type) { 4746 case TEMP_VAL_REG: 4747 return; 4748 case TEMP_VAL_CONST: 4749 reg = tcg_reg_alloc(s, desired_regs, allocated_regs, 4750 preferred_regs, ts->indirect_base); 4751 if (ts->type <= TCG_TYPE_I64) { 4752 tcg_out_movi(s, ts->type, reg, ts->val); 4753 } else { 4754 uint64_t val = ts->val; 4755 MemOp vece = MO_64; 4756 4757 /* 4758 * Find the minimal vector element that matches the constant. 4759 * The targets will, in general, have to do this search anyway, 4760 * do this generically. 4761 */ 4762 if (val == dup_const(MO_8, val)) { 4763 vece = MO_8; 4764 } else if (val == dup_const(MO_16, val)) { 4765 vece = MO_16; 4766 } else if (val == dup_const(MO_32, val)) { 4767 vece = MO_32; 4768 } 4769 4770 tcg_out_dupi_vec(s, ts->type, vece, reg, ts->val); 4771 } 4772 ts->mem_coherent = 0; 4773 break; 4774 case TEMP_VAL_MEM: 4775 if (!ts->mem_allocated) { 4776 temp_allocate_frame(s, ts); 4777 } 4778 reg = tcg_reg_alloc(s, desired_regs, allocated_regs, 4779 preferred_regs, ts->indirect_base); 4780 tcg_out_ld(s, ts->type, reg, ts->mem_base->reg, ts->mem_offset); 4781 ts->mem_coherent = 1; 4782 break; 4783 case TEMP_VAL_DEAD: 4784 default: 4785 g_assert_not_reached(); 4786 } 4787 set_temp_val_reg(s, ts, reg); 4788 } 4789 4790 /* Save a temporary to memory. 'allocated_regs' is used in case a 4791 temporary registers needs to be allocated to store a constant. */ 4792 static void temp_save(TCGContext *s, TCGTemp *ts, TCGRegSet allocated_regs) 4793 { 4794 /* The liveness analysis already ensures that globals are back 4795 in memory. Keep an tcg_debug_assert for safety. */ 4796 tcg_debug_assert(ts->val_type == TEMP_VAL_MEM || temp_readonly(ts)); 4797 } 4798 4799 /* save globals to their canonical location and assume they can be 4800 modified be the following code. 'allocated_regs' is used in case a 4801 temporary registers needs to be allocated to store a constant. */ 4802 static void save_globals(TCGContext *s, TCGRegSet allocated_regs) 4803 { 4804 int i, n; 4805 4806 for (i = 0, n = s->nb_globals; i < n; i++) { 4807 temp_save(s, &s->temps[i], allocated_regs); 4808 } 4809 } 4810 4811 /* sync globals to their canonical location and assume they can be 4812 read by the following code. 'allocated_regs' is used in case a 4813 temporary registers needs to be allocated to store a constant. */ 4814 static void sync_globals(TCGContext *s, TCGRegSet allocated_regs) 4815 { 4816 int i, n; 4817 4818 for (i = 0, n = s->nb_globals; i < n; i++) { 4819 TCGTemp *ts = &s->temps[i]; 4820 tcg_debug_assert(ts->val_type != TEMP_VAL_REG 4821 || ts->kind == TEMP_FIXED 4822 || ts->mem_coherent); 4823 } 4824 } 4825 4826 /* at the end of a basic block, we assume all temporaries are dead and 4827 all globals are stored at their canonical location. */ 4828 static void tcg_reg_alloc_bb_end(TCGContext *s, TCGRegSet allocated_regs) 4829 { 4830 int i; 4831 4832 for (i = s->nb_globals; i < s->nb_temps; i++) { 4833 TCGTemp *ts = &s->temps[i]; 4834 4835 switch (ts->kind) { 4836 case TEMP_TB: 4837 temp_save(s, ts, allocated_regs); 4838 break; 4839 case TEMP_EBB: 4840 /* The liveness analysis already ensures that temps are dead. 4841 Keep an tcg_debug_assert for safety. */ 4842 tcg_debug_assert(ts->val_type == TEMP_VAL_DEAD); 4843 break; 4844 case TEMP_CONST: 4845 /* Similarly, we should have freed any allocated register. */ 4846 tcg_debug_assert(ts->val_type == TEMP_VAL_CONST); 4847 break; 4848 default: 4849 g_assert_not_reached(); 4850 } 4851 } 4852 4853 save_globals(s, allocated_regs); 4854 } 4855 4856 /* 4857 * At a conditional branch, we assume all temporaries are dead unless 4858 * explicitly live-across-conditional-branch; all globals and local 4859 * temps are synced to their location. 4860 */ 4861 static void tcg_reg_alloc_cbranch(TCGContext *s, TCGRegSet allocated_regs) 4862 { 4863 sync_globals(s, allocated_regs); 4864 4865 for (int i = s->nb_globals; i < s->nb_temps; i++) { 4866 TCGTemp *ts = &s->temps[i]; 4867 /* 4868 * The liveness analysis already ensures that temps are dead. 4869 * Keep tcg_debug_asserts for safety. 4870 */ 4871 switch (ts->kind) { 4872 case TEMP_TB: 4873 tcg_debug_assert(ts->val_type != TEMP_VAL_REG || ts->mem_coherent); 4874 break; 4875 case TEMP_EBB: 4876 case TEMP_CONST: 4877 break; 4878 default: 4879 g_assert_not_reached(); 4880 } 4881 } 4882 } 4883 4884 /* 4885 * Specialized code generation for INDEX_op_mov_* with a constant. 4886 */ 4887 static void tcg_reg_alloc_do_movi(TCGContext *s, TCGTemp *ots, 4888 tcg_target_ulong val, TCGLifeData arg_life, 4889 TCGRegSet preferred_regs) 4890 { 4891 /* ENV should not be modified. */ 4892 tcg_debug_assert(!temp_readonly(ots)); 4893 4894 /* The movi is not explicitly generated here. */ 4895 set_temp_val_nonreg(s, ots, TEMP_VAL_CONST); 4896 ots->val = val; 4897 ots->mem_coherent = 0; 4898 if (NEED_SYNC_ARG(0)) { 4899 temp_sync(s, ots, s->reserved_regs, preferred_regs, IS_DEAD_ARG(0)); 4900 } else if (IS_DEAD_ARG(0)) { 4901 temp_dead(s, ots); 4902 } 4903 } 4904 4905 /* 4906 * Specialized code generation for INDEX_op_mov_*. 4907 */ 4908 static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op) 4909 { 4910 const TCGLifeData arg_life = op->life; 4911 TCGRegSet allocated_regs, preferred_regs; 4912 TCGTemp *ts, *ots; 4913 TCGType otype, itype; 4914 TCGReg oreg, ireg; 4915 4916 allocated_regs = s->reserved_regs; 4917 preferred_regs = output_pref(op, 0); 4918 ots = arg_temp(op->args[0]); 4919 ts = arg_temp(op->args[1]); 4920 4921 /* ENV should not be modified. */ 4922 tcg_debug_assert(!temp_readonly(ots)); 4923 4924 /* Note that otype != itype for no-op truncation. */ 4925 otype = ots->type; 4926 itype = ts->type; 4927 4928 if (ts->val_type == TEMP_VAL_CONST) { 4929 /* propagate constant or generate sti */ 4930 tcg_target_ulong val = ts->val; 4931 if (IS_DEAD_ARG(1)) { 4932 temp_dead(s, ts); 4933 } 4934 tcg_reg_alloc_do_movi(s, ots, val, arg_life, preferred_regs); 4935 return; 4936 } 4937 4938 /* If the source value is in memory we're going to be forced 4939 to have it in a register in order to perform the copy. Copy 4940 the SOURCE value into its own register first, that way we 4941 don't have to reload SOURCE the next time it is used. */ 4942 if (ts->val_type == TEMP_VAL_MEM) { 4943 temp_load(s, ts, tcg_target_available_regs[itype], 4944 allocated_regs, preferred_regs); 4945 } 4946 tcg_debug_assert(ts->val_type == TEMP_VAL_REG); 4947 ireg = ts->reg; 4948 4949 if (IS_DEAD_ARG(0)) { 4950 /* mov to a non-saved dead register makes no sense (even with 4951 liveness analysis disabled). */ 4952 tcg_debug_assert(NEED_SYNC_ARG(0)); 4953 if (!ots->mem_allocated) { 4954 temp_allocate_frame(s, ots); 4955 } 4956 tcg_out_st(s, otype, ireg, ots->mem_base->reg, ots->mem_offset); 4957 if (IS_DEAD_ARG(1)) { 4958 temp_dead(s, ts); 4959 } 4960 temp_dead(s, ots); 4961 return; 4962 } 4963 4964 if (IS_DEAD_ARG(1) && ts->kind != TEMP_FIXED) { 4965 /* 4966 * The mov can be suppressed. Kill input first, so that it 4967 * is unlinked from reg_to_temp, then set the output to the 4968 * reg that we saved from the input. 4969 */ 4970 temp_dead(s, ts); 4971 oreg = ireg; 4972 } else { 4973 if (ots->val_type == TEMP_VAL_REG) { 4974 oreg = ots->reg; 4975 } else { 4976 /* Make sure to not spill the input register during allocation. */ 4977 oreg = tcg_reg_alloc(s, tcg_target_available_regs[otype], 4978 allocated_regs | ((TCGRegSet)1 << ireg), 4979 preferred_regs, ots->indirect_base); 4980 } 4981 if (!tcg_out_mov(s, otype, oreg, ireg)) { 4982 /* 4983 * Cross register class move not supported. 4984 * Store the source register into the destination slot 4985 * and leave the destination temp as TEMP_VAL_MEM. 4986 */ 4987 assert(!temp_readonly(ots)); 4988 if (!ts->mem_allocated) { 4989 temp_allocate_frame(s, ots); 4990 } 4991 tcg_out_st(s, ts->type, ireg, ots->mem_base->reg, ots->mem_offset); 4992 set_temp_val_nonreg(s, ts, TEMP_VAL_MEM); 4993 ots->mem_coherent = 1; 4994 return; 4995 } 4996 } 4997 set_temp_val_reg(s, ots, oreg); 4998 ots->mem_coherent = 0; 4999 5000 if (NEED_SYNC_ARG(0)) { 5001 temp_sync(s, ots, allocated_regs, 0, 0); 5002 } 5003 } 5004 5005 /* 5006 * Specialized code generation for INDEX_op_dup_vec. 5007 */ 5008 static void tcg_reg_alloc_dup(TCGContext *s, const TCGOp *op) 5009 { 5010 const TCGLifeData arg_life = op->life; 5011 TCGRegSet dup_out_regs, dup_in_regs; 5012 const TCGArgConstraint *dup_args_ct; 5013 TCGTemp *its, *ots; 5014 TCGType itype, vtype; 5015 unsigned vece; 5016 int lowpart_ofs; 5017 bool ok; 5018 5019 ots = arg_temp(op->args[0]); 5020 its = arg_temp(op->args[1]); 5021 5022 /* ENV should not be modified. */ 5023 tcg_debug_assert(!temp_readonly(ots)); 5024 5025 itype = its->type; 5026 vece = TCGOP_VECE(op); 5027 vtype = TCGOP_TYPE(op); 5028 5029 if (its->val_type == TEMP_VAL_CONST) { 5030 /* Propagate constant via movi -> dupi. */ 5031 tcg_target_ulong val = its->val; 5032 if (IS_DEAD_ARG(1)) { 5033 temp_dead(s, its); 5034 } 5035 tcg_reg_alloc_do_movi(s, ots, val, arg_life, output_pref(op, 0)); 5036 return; 5037 } 5038 5039 dup_args_ct = opcode_args_ct(op); 5040 dup_out_regs = dup_args_ct[0].regs; 5041 dup_in_regs = dup_args_ct[1].regs; 5042 5043 /* Allocate the output register now. */ 5044 if (ots->val_type != TEMP_VAL_REG) { 5045 TCGRegSet allocated_regs = s->reserved_regs; 5046 TCGReg oreg; 5047 5048 if (!IS_DEAD_ARG(1) && its->val_type == TEMP_VAL_REG) { 5049 /* Make sure to not spill the input register. */ 5050 tcg_regset_set_reg(allocated_regs, its->reg); 5051 } 5052 oreg = tcg_reg_alloc(s, dup_out_regs, allocated_regs, 5053 output_pref(op, 0), ots->indirect_base); 5054 set_temp_val_reg(s, ots, oreg); 5055 } 5056 5057 switch (its->val_type) { 5058 case TEMP_VAL_REG: 5059 /* 5060 * The dup constriaints must be broad, covering all possible VECE. 5061 * However, tcg_op_dup_vec() gets to see the VECE and we allow it 5062 * to fail, indicating that extra moves are required for that case. 5063 */ 5064 if (tcg_regset_test_reg(dup_in_regs, its->reg)) { 5065 if (tcg_out_dup_vec(s, vtype, vece, ots->reg, its->reg)) { 5066 goto done; 5067 } 5068 /* Try again from memory or a vector input register. */ 5069 } 5070 if (!its->mem_coherent) { 5071 /* 5072 * The input register is not synced, and so an extra store 5073 * would be required to use memory. Attempt an integer-vector 5074 * register move first. We do not have a TCGRegSet for this. 5075 */ 5076 if (tcg_out_mov(s, itype, ots->reg, its->reg)) { 5077 break; 5078 } 5079 /* Sync the temp back to its slot and load from there. */ 5080 temp_sync(s, its, s->reserved_regs, 0, 0); 5081 } 5082 /* fall through */ 5083 5084 case TEMP_VAL_MEM: 5085 lowpart_ofs = 0; 5086 if (HOST_BIG_ENDIAN) { 5087 lowpart_ofs = tcg_type_size(itype) - (1 << vece); 5088 } 5089 if (tcg_out_dupm_vec(s, vtype, vece, ots->reg, its->mem_base->reg, 5090 its->mem_offset + lowpart_ofs)) { 5091 goto done; 5092 } 5093 /* Load the input into the destination vector register. */ 5094 tcg_out_ld(s, itype, ots->reg, its->mem_base->reg, its->mem_offset); 5095 break; 5096 5097 default: 5098 g_assert_not_reached(); 5099 } 5100 5101 /* We now have a vector input register, so dup must succeed. */ 5102 ok = tcg_out_dup_vec(s, vtype, vece, ots->reg, ots->reg); 5103 tcg_debug_assert(ok); 5104 5105 done: 5106 ots->mem_coherent = 0; 5107 if (IS_DEAD_ARG(1)) { 5108 temp_dead(s, its); 5109 } 5110 if (NEED_SYNC_ARG(0)) { 5111 temp_sync(s, ots, s->reserved_regs, 0, 0); 5112 } 5113 if (IS_DEAD_ARG(0)) { 5114 temp_dead(s, ots); 5115 } 5116 } 5117 5118 static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) 5119 { 5120 const TCGLifeData arg_life = op->life; 5121 const TCGOpDef * const def = &tcg_op_defs[op->opc]; 5122 TCGRegSet i_allocated_regs; 5123 TCGRegSet o_allocated_regs; 5124 int i, k, nb_iargs, nb_oargs; 5125 TCGReg reg; 5126 TCGArg arg; 5127 const TCGArgConstraint *args_ct; 5128 const TCGArgConstraint *arg_ct; 5129 TCGTemp *ts; 5130 TCGArg new_args[TCG_MAX_OP_ARGS]; 5131 int const_args[TCG_MAX_OP_ARGS]; 5132 TCGCond op_cond; 5133 5134 nb_oargs = def->nb_oargs; 5135 nb_iargs = def->nb_iargs; 5136 5137 /* copy constants */ 5138 memcpy(new_args + nb_oargs + nb_iargs, 5139 op->args + nb_oargs + nb_iargs, 5140 sizeof(TCGArg) * def->nb_cargs); 5141 5142 i_allocated_regs = s->reserved_regs; 5143 o_allocated_regs = s->reserved_regs; 5144 5145 switch (op->opc) { 5146 case INDEX_op_brcond: 5147 op_cond = op->args[2]; 5148 break; 5149 case INDEX_op_setcond: 5150 case INDEX_op_negsetcond: 5151 case INDEX_op_cmp_vec: 5152 op_cond = op->args[3]; 5153 break; 5154 case INDEX_op_brcond2_i32: 5155 op_cond = op->args[4]; 5156 break; 5157 case INDEX_op_movcond: 5158 case INDEX_op_setcond2_i32: 5159 case INDEX_op_cmpsel_vec: 5160 op_cond = op->args[5]; 5161 break; 5162 default: 5163 /* No condition within opcode. */ 5164 op_cond = TCG_COND_ALWAYS; 5165 break; 5166 } 5167 5168 args_ct = opcode_args_ct(op); 5169 5170 /* satisfy input constraints */ 5171 for (k = 0; k < nb_iargs; k++) { 5172 TCGRegSet i_preferred_regs, i_required_regs; 5173 bool allocate_new_reg, copyto_new_reg; 5174 TCGTemp *ts2; 5175 int i1, i2; 5176 5177 i = args_ct[nb_oargs + k].sort_index; 5178 arg = op->args[i]; 5179 arg_ct = &args_ct[i]; 5180 ts = arg_temp(arg); 5181 5182 if (ts->val_type == TEMP_VAL_CONST) { 5183 #ifdef TCG_REG_ZERO 5184 if (ts->val == 0 && (arg_ct->ct & TCG_CT_REG_ZERO)) { 5185 /* Hardware zero register: indicate register via non-const. */ 5186 const_args[i] = 0; 5187 new_args[i] = TCG_REG_ZERO; 5188 continue; 5189 } 5190 #endif 5191 5192 if (tcg_target_const_match(ts->val, arg_ct->ct, ts->type, 5193 op_cond, TCGOP_VECE(op))) { 5194 /* constant is OK for instruction */ 5195 const_args[i] = 1; 5196 new_args[i] = ts->val; 5197 continue; 5198 } 5199 } 5200 5201 reg = ts->reg; 5202 i_preferred_regs = 0; 5203 i_required_regs = arg_ct->regs; 5204 allocate_new_reg = false; 5205 copyto_new_reg = false; 5206 5207 switch (arg_ct->pair) { 5208 case 0: /* not paired */ 5209 if (arg_ct->ialias) { 5210 i_preferred_regs = output_pref(op, arg_ct->alias_index); 5211 5212 /* 5213 * If the input is readonly, then it cannot also be an 5214 * output and aliased to itself. If the input is not 5215 * dead after the instruction, we must allocate a new 5216 * register and move it. 5217 */ 5218 if (temp_readonly(ts) || !IS_DEAD_ARG(i) 5219 || args_ct[arg_ct->alias_index].newreg) { 5220 allocate_new_reg = true; 5221 } else if (ts->val_type == TEMP_VAL_REG) { 5222 /* 5223 * Check if the current register has already been 5224 * allocated for another input. 5225 */ 5226 allocate_new_reg = 5227 tcg_regset_test_reg(i_allocated_regs, reg); 5228 } 5229 } 5230 if (!allocate_new_reg) { 5231 temp_load(s, ts, i_required_regs, i_allocated_regs, 5232 i_preferred_regs); 5233 reg = ts->reg; 5234 allocate_new_reg = !tcg_regset_test_reg(i_required_regs, reg); 5235 } 5236 if (allocate_new_reg) { 5237 /* 5238 * Allocate a new register matching the constraint 5239 * and move the temporary register into it. 5240 */ 5241 temp_load(s, ts, tcg_target_available_regs[ts->type], 5242 i_allocated_regs, 0); 5243 reg = tcg_reg_alloc(s, i_required_regs, i_allocated_regs, 5244 i_preferred_regs, ts->indirect_base); 5245 copyto_new_reg = true; 5246 } 5247 break; 5248 5249 case 1: 5250 /* First of an input pair; if i1 == i2, the second is an output. */ 5251 i1 = i; 5252 i2 = arg_ct->pair_index; 5253 ts2 = i1 != i2 ? arg_temp(op->args[i2]) : NULL; 5254 5255 /* 5256 * It is easier to default to allocating a new pair 5257 * and to identify a few cases where it's not required. 5258 */ 5259 if (arg_ct->ialias) { 5260 i_preferred_regs = output_pref(op, arg_ct->alias_index); 5261 if (IS_DEAD_ARG(i1) && 5262 IS_DEAD_ARG(i2) && 5263 !temp_readonly(ts) && 5264 ts->val_type == TEMP_VAL_REG && 5265 ts->reg < TCG_TARGET_NB_REGS - 1 && 5266 tcg_regset_test_reg(i_required_regs, reg) && 5267 !tcg_regset_test_reg(i_allocated_regs, reg) && 5268 !tcg_regset_test_reg(i_allocated_regs, reg + 1) && 5269 (ts2 5270 ? ts2->val_type == TEMP_VAL_REG && 5271 ts2->reg == reg + 1 && 5272 !temp_readonly(ts2) 5273 : s->reg_to_temp[reg + 1] == NULL)) { 5274 break; 5275 } 5276 } else { 5277 /* Without aliasing, the pair must also be an input. */ 5278 tcg_debug_assert(ts2); 5279 if (ts->val_type == TEMP_VAL_REG && 5280 ts2->val_type == TEMP_VAL_REG && 5281 ts2->reg == reg + 1 && 5282 tcg_regset_test_reg(i_required_regs, reg)) { 5283 break; 5284 } 5285 } 5286 reg = tcg_reg_alloc_pair(s, i_required_regs, i_allocated_regs, 5287 0, ts->indirect_base); 5288 goto do_pair; 5289 5290 case 2: /* pair second */ 5291 reg = new_args[arg_ct->pair_index] + 1; 5292 goto do_pair; 5293 5294 case 3: /* ialias with second output, no first input */ 5295 tcg_debug_assert(arg_ct->ialias); 5296 i_preferred_regs = output_pref(op, arg_ct->alias_index); 5297 5298 if (IS_DEAD_ARG(i) && 5299 !temp_readonly(ts) && 5300 ts->val_type == TEMP_VAL_REG && 5301 reg > 0 && 5302 s->reg_to_temp[reg - 1] == NULL && 5303 tcg_regset_test_reg(i_required_regs, reg) && 5304 !tcg_regset_test_reg(i_allocated_regs, reg) && 5305 !tcg_regset_test_reg(i_allocated_regs, reg - 1)) { 5306 tcg_regset_set_reg(i_allocated_regs, reg - 1); 5307 break; 5308 } 5309 reg = tcg_reg_alloc_pair(s, i_required_regs >> 1, 5310 i_allocated_regs, 0, 5311 ts->indirect_base); 5312 tcg_regset_set_reg(i_allocated_regs, reg); 5313 reg += 1; 5314 goto do_pair; 5315 5316 do_pair: 5317 /* 5318 * If an aliased input is not dead after the instruction, 5319 * we must allocate a new register and move it. 5320 */ 5321 if (arg_ct->ialias && (!IS_DEAD_ARG(i) || temp_readonly(ts))) { 5322 TCGRegSet t_allocated_regs = i_allocated_regs; 5323 5324 /* 5325 * Because of the alias, and the continued life, make sure 5326 * that the temp is somewhere *other* than the reg pair, 5327 * and we get a copy in reg. 5328 */ 5329 tcg_regset_set_reg(t_allocated_regs, reg); 5330 tcg_regset_set_reg(t_allocated_regs, reg + 1); 5331 if (ts->val_type == TEMP_VAL_REG && ts->reg == reg) { 5332 /* If ts was already in reg, copy it somewhere else. */ 5333 TCGReg nr; 5334 bool ok; 5335 5336 tcg_debug_assert(ts->kind != TEMP_FIXED); 5337 nr = tcg_reg_alloc(s, tcg_target_available_regs[ts->type], 5338 t_allocated_regs, 0, ts->indirect_base); 5339 ok = tcg_out_mov(s, ts->type, nr, reg); 5340 tcg_debug_assert(ok); 5341 5342 set_temp_val_reg(s, ts, nr); 5343 } else { 5344 temp_load(s, ts, tcg_target_available_regs[ts->type], 5345 t_allocated_regs, 0); 5346 copyto_new_reg = true; 5347 } 5348 } else { 5349 /* Preferably allocate to reg, otherwise copy. */ 5350 i_required_regs = (TCGRegSet)1 << reg; 5351 temp_load(s, ts, i_required_regs, i_allocated_regs, 5352 i_preferred_regs); 5353 copyto_new_reg = ts->reg != reg; 5354 } 5355 break; 5356 5357 default: 5358 g_assert_not_reached(); 5359 } 5360 5361 if (copyto_new_reg) { 5362 if (!tcg_out_mov(s, ts->type, reg, ts->reg)) { 5363 /* 5364 * Cross register class move not supported. Sync the 5365 * temp back to its slot and load from there. 5366 */ 5367 temp_sync(s, ts, i_allocated_regs, 0, 0); 5368 tcg_out_ld(s, ts->type, reg, 5369 ts->mem_base->reg, ts->mem_offset); 5370 } 5371 } 5372 new_args[i] = reg; 5373 const_args[i] = 0; 5374 tcg_regset_set_reg(i_allocated_regs, reg); 5375 } 5376 5377 /* mark dead temporaries and free the associated registers */ 5378 for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) { 5379 if (IS_DEAD_ARG(i)) { 5380 temp_dead(s, arg_temp(op->args[i])); 5381 } 5382 } 5383 5384 if (def->flags & TCG_OPF_COND_BRANCH) { 5385 tcg_reg_alloc_cbranch(s, i_allocated_regs); 5386 } else if (def->flags & TCG_OPF_BB_END) { 5387 tcg_reg_alloc_bb_end(s, i_allocated_regs); 5388 } else { 5389 if (def->flags & TCG_OPF_CALL_CLOBBER) { 5390 /* XXX: permit generic clobber register list ? */ 5391 for (i = 0; i < TCG_TARGET_NB_REGS; i++) { 5392 if (tcg_regset_test_reg(tcg_target_call_clobber_regs, i)) { 5393 tcg_reg_free(s, i, i_allocated_regs); 5394 } 5395 } 5396 } 5397 if (def->flags & TCG_OPF_SIDE_EFFECTS) { 5398 /* sync globals if the op has side effects and might trigger 5399 an exception. */ 5400 sync_globals(s, i_allocated_regs); 5401 } 5402 5403 /* satisfy the output constraints */ 5404 for (k = 0; k < nb_oargs; k++) { 5405 i = args_ct[k].sort_index; 5406 arg = op->args[i]; 5407 arg_ct = &args_ct[i]; 5408 ts = arg_temp(arg); 5409 5410 /* ENV should not be modified. */ 5411 tcg_debug_assert(!temp_readonly(ts)); 5412 5413 switch (arg_ct->pair) { 5414 case 0: /* not paired */ 5415 if (arg_ct->oalias && !const_args[arg_ct->alias_index]) { 5416 reg = new_args[arg_ct->alias_index]; 5417 } else if (arg_ct->newreg) { 5418 reg = tcg_reg_alloc(s, arg_ct->regs, 5419 i_allocated_regs | o_allocated_regs, 5420 output_pref(op, k), ts->indirect_base); 5421 } else { 5422 reg = tcg_reg_alloc(s, arg_ct->regs, o_allocated_regs, 5423 output_pref(op, k), ts->indirect_base); 5424 } 5425 break; 5426 5427 case 1: /* first of pair */ 5428 if (arg_ct->oalias) { 5429 reg = new_args[arg_ct->alias_index]; 5430 } else if (arg_ct->newreg) { 5431 reg = tcg_reg_alloc_pair(s, arg_ct->regs, 5432 i_allocated_regs | o_allocated_regs, 5433 output_pref(op, k), 5434 ts->indirect_base); 5435 } else { 5436 reg = tcg_reg_alloc_pair(s, arg_ct->regs, o_allocated_regs, 5437 output_pref(op, k), 5438 ts->indirect_base); 5439 } 5440 break; 5441 5442 case 2: /* second of pair */ 5443 if (arg_ct->oalias) { 5444 reg = new_args[arg_ct->alias_index]; 5445 } else { 5446 reg = new_args[arg_ct->pair_index] + 1; 5447 } 5448 break; 5449 5450 case 3: /* first of pair, aliasing with a second input */ 5451 tcg_debug_assert(!arg_ct->newreg); 5452 reg = new_args[arg_ct->pair_index] - 1; 5453 break; 5454 5455 default: 5456 g_assert_not_reached(); 5457 } 5458 tcg_regset_set_reg(o_allocated_regs, reg); 5459 set_temp_val_reg(s, ts, reg); 5460 ts->mem_coherent = 0; 5461 new_args[i] = reg; 5462 } 5463 } 5464 5465 /* emit instruction */ 5466 TCGType type = TCGOP_TYPE(op); 5467 switch (op->opc) { 5468 case INDEX_op_add: 5469 case INDEX_op_and: 5470 case INDEX_op_andc: 5471 case INDEX_op_clz: 5472 case INDEX_op_ctz: 5473 case INDEX_op_divs: 5474 case INDEX_op_divu: 5475 case INDEX_op_eqv: 5476 case INDEX_op_mul: 5477 case INDEX_op_mulsh: 5478 case INDEX_op_muluh: 5479 case INDEX_op_nand: 5480 case INDEX_op_nor: 5481 case INDEX_op_or: 5482 case INDEX_op_orc: 5483 case INDEX_op_rems: 5484 case INDEX_op_remu: 5485 case INDEX_op_rotl: 5486 case INDEX_op_rotr: 5487 case INDEX_op_sar: 5488 case INDEX_op_shl: 5489 case INDEX_op_shr: 5490 case INDEX_op_xor: 5491 { 5492 const TCGOutOpBinary *out = 5493 container_of(all_outop[op->opc], TCGOutOpBinary, base); 5494 5495 /* Constants should never appear in the first source operand. */ 5496 tcg_debug_assert(!const_args[1]); 5497 if (const_args[2]) { 5498 out->out_rri(s, type, new_args[0], new_args[1], new_args[2]); 5499 } else { 5500 out->out_rrr(s, type, new_args[0], new_args[1], new_args[2]); 5501 } 5502 } 5503 break; 5504 5505 case INDEX_op_sub: 5506 { 5507 const TCGOutOpSubtract *out = &outop_sub; 5508 5509 /* 5510 * Constants should never appear in the second source operand. 5511 * These are folded to add with negative constant. 5512 */ 5513 tcg_debug_assert(!const_args[2]); 5514 if (const_args[1]) { 5515 out->out_rir(s, type, new_args[0], new_args[1], new_args[2]); 5516 } else { 5517 out->out_rrr(s, type, new_args[0], new_args[1], new_args[2]); 5518 } 5519 } 5520 break; 5521 5522 case INDEX_op_bswap64: 5523 case INDEX_op_ext_i32_i64: 5524 case INDEX_op_extu_i32_i64: 5525 case INDEX_op_extrl_i64_i32: 5526 case INDEX_op_extrh_i64_i32: 5527 assert(TCG_TARGET_REG_BITS == 64); 5528 /* fall through */ 5529 case INDEX_op_ctpop: 5530 case INDEX_op_neg: 5531 case INDEX_op_not: 5532 { 5533 const TCGOutOpUnary *out = 5534 container_of(all_outop[op->opc], TCGOutOpUnary, base); 5535 5536 /* Constants should have been folded. */ 5537 tcg_debug_assert(!const_args[1]); 5538 out->out_rr(s, type, new_args[0], new_args[1]); 5539 } 5540 break; 5541 5542 case INDEX_op_bswap16: 5543 case INDEX_op_bswap32: 5544 { 5545 const TCGOutOpBswap *out = 5546 container_of(all_outop[op->opc], TCGOutOpBswap, base); 5547 5548 tcg_debug_assert(!const_args[1]); 5549 out->out_rr(s, type, new_args[0], new_args[1], new_args[2]); 5550 } 5551 break; 5552 5553 case INDEX_op_deposit: 5554 { 5555 const TCGOutOpDeposit *out = &outop_deposit; 5556 5557 if (const_args[2]) { 5558 tcg_debug_assert(!const_args[1]); 5559 out->out_rri(s, type, new_args[0], new_args[1], 5560 new_args[2], new_args[3], new_args[4]); 5561 } else if (const_args[1]) { 5562 tcg_debug_assert(new_args[1] == 0); 5563 tcg_debug_assert(!const_args[2]); 5564 out->out_rzr(s, type, new_args[0], new_args[2], 5565 new_args[3], new_args[4]); 5566 } else { 5567 out->out_rrr(s, type, new_args[0], new_args[1], 5568 new_args[2], new_args[3], new_args[4]); 5569 } 5570 } 5571 break; 5572 5573 case INDEX_op_divs2: 5574 case INDEX_op_divu2: 5575 { 5576 const TCGOutOpDivRem *out = 5577 container_of(all_outop[op->opc], TCGOutOpDivRem, base); 5578 5579 /* Only used by x86 and s390x, which use matching constraints. */ 5580 tcg_debug_assert(new_args[0] == new_args[2]); 5581 tcg_debug_assert(new_args[1] == new_args[3]); 5582 tcg_debug_assert(!const_args[4]); 5583 out->out_rr01r(s, type, new_args[0], new_args[1], new_args[4]); 5584 } 5585 break; 5586 5587 case INDEX_op_extract: 5588 case INDEX_op_sextract: 5589 { 5590 const TCGOutOpExtract *out = 5591 container_of(all_outop[op->opc], TCGOutOpExtract, base); 5592 5593 tcg_debug_assert(!const_args[1]); 5594 out->out_rr(s, type, new_args[0], new_args[1], 5595 new_args[2], new_args[3]); 5596 } 5597 break; 5598 5599 case INDEX_op_extract2: 5600 { 5601 const TCGOutOpExtract2 *out = &outop_extract2; 5602 5603 tcg_debug_assert(!const_args[1]); 5604 tcg_debug_assert(!const_args[2]); 5605 out->out_rrr(s, type, new_args[0], new_args[1], 5606 new_args[2], new_args[3]); 5607 } 5608 break; 5609 5610 case INDEX_op_muls2: 5611 case INDEX_op_mulu2: 5612 { 5613 const TCGOutOpMul2 *out = 5614 container_of(all_outop[op->opc], TCGOutOpMul2, base); 5615 5616 tcg_debug_assert(!const_args[2]); 5617 tcg_debug_assert(!const_args[3]); 5618 out->out_rrrr(s, type, new_args[0], new_args[1], 5619 new_args[2], new_args[3]); 5620 } 5621 break; 5622 5623 case INDEX_op_brcond: 5624 { 5625 const TCGOutOpBrcond *out = &outop_brcond; 5626 TCGCond cond = new_args[2]; 5627 TCGLabel *label = arg_label(new_args[3]); 5628 5629 tcg_debug_assert(!const_args[0]); 5630 if (const_args[1]) { 5631 out->out_ri(s, type, cond, new_args[0], new_args[1], label); 5632 } else { 5633 out->out_rr(s, type, cond, new_args[0], new_args[1], label); 5634 } 5635 } 5636 break; 5637 5638 case INDEX_op_movcond: 5639 { 5640 const TCGOutOpMovcond *out = &outop_movcond; 5641 TCGCond cond = new_args[5]; 5642 5643 tcg_debug_assert(!const_args[1]); 5644 out->out(s, type, cond, new_args[0], 5645 new_args[1], new_args[2], const_args[2], 5646 new_args[3], const_args[3], 5647 new_args[4], const_args[4]); 5648 } 5649 break; 5650 5651 case INDEX_op_setcond: 5652 case INDEX_op_negsetcond: 5653 { 5654 const TCGOutOpSetcond *out = 5655 container_of(all_outop[op->opc], TCGOutOpSetcond, base); 5656 TCGCond cond = new_args[3]; 5657 5658 tcg_debug_assert(!const_args[1]); 5659 if (const_args[2]) { 5660 out->out_rri(s, type, cond, 5661 new_args[0], new_args[1], new_args[2]); 5662 } else { 5663 out->out_rrr(s, type, cond, 5664 new_args[0], new_args[1], new_args[2]); 5665 } 5666 } 5667 break; 5668 5669 #if TCG_TARGET_REG_BITS == 32 5670 case INDEX_op_brcond2_i32: 5671 { 5672 const TCGOutOpBrcond2 *out = &outop_brcond2; 5673 TCGCond cond = new_args[4]; 5674 TCGLabel *label = arg_label(new_args[5]); 5675 5676 tcg_debug_assert(!const_args[0]); 5677 tcg_debug_assert(!const_args[1]); 5678 out->out(s, cond, new_args[0], new_args[1], 5679 new_args[2], const_args[2], 5680 new_args[3], const_args[3], label); 5681 } 5682 break; 5683 case INDEX_op_setcond2_i32: 5684 { 5685 const TCGOutOpSetcond2 *out = &outop_setcond2; 5686 TCGCond cond = new_args[5]; 5687 5688 tcg_debug_assert(!const_args[1]); 5689 tcg_debug_assert(!const_args[2]); 5690 out->out(s, cond, new_args[0], new_args[1], new_args[2], 5691 new_args[3], const_args[3], new_args[4], const_args[4]); 5692 } 5693 break; 5694 #else 5695 case INDEX_op_brcond2_i32: 5696 case INDEX_op_setcond2_i32: 5697 g_assert_not_reached(); 5698 #endif 5699 5700 default: 5701 if (def->flags & TCG_OPF_VECTOR) { 5702 tcg_out_vec_op(s, op->opc, type - TCG_TYPE_V64, 5703 TCGOP_VECE(op), new_args, const_args); 5704 } else { 5705 tcg_out_op(s, op->opc, type, new_args, const_args); 5706 } 5707 break; 5708 } 5709 5710 /* move the outputs in the correct register if needed */ 5711 for(i = 0; i < nb_oargs; i++) { 5712 ts = arg_temp(op->args[i]); 5713 5714 /* ENV should not be modified. */ 5715 tcg_debug_assert(!temp_readonly(ts)); 5716 5717 if (NEED_SYNC_ARG(i)) { 5718 temp_sync(s, ts, o_allocated_regs, 0, IS_DEAD_ARG(i)); 5719 } else if (IS_DEAD_ARG(i)) { 5720 temp_dead(s, ts); 5721 } 5722 } 5723 } 5724 5725 static bool tcg_reg_alloc_dup2(TCGContext *s, const TCGOp *op) 5726 { 5727 const TCGLifeData arg_life = op->life; 5728 TCGTemp *ots, *itsl, *itsh; 5729 TCGType vtype = TCGOP_TYPE(op); 5730 5731 /* This opcode is only valid for 32-bit hosts, for 64-bit elements. */ 5732 tcg_debug_assert(TCG_TARGET_REG_BITS == 32); 5733 tcg_debug_assert(TCGOP_VECE(op) == MO_64); 5734 5735 ots = arg_temp(op->args[0]); 5736 itsl = arg_temp(op->args[1]); 5737 itsh = arg_temp(op->args[2]); 5738 5739 /* ENV should not be modified. */ 5740 tcg_debug_assert(!temp_readonly(ots)); 5741 5742 /* Allocate the output register now. */ 5743 if (ots->val_type != TEMP_VAL_REG) { 5744 TCGRegSet allocated_regs = s->reserved_regs; 5745 TCGRegSet dup_out_regs = opcode_args_ct(op)[0].regs; 5746 TCGReg oreg; 5747 5748 /* Make sure to not spill the input registers. */ 5749 if (!IS_DEAD_ARG(1) && itsl->val_type == TEMP_VAL_REG) { 5750 tcg_regset_set_reg(allocated_regs, itsl->reg); 5751 } 5752 if (!IS_DEAD_ARG(2) && itsh->val_type == TEMP_VAL_REG) { 5753 tcg_regset_set_reg(allocated_regs, itsh->reg); 5754 } 5755 5756 oreg = tcg_reg_alloc(s, dup_out_regs, allocated_regs, 5757 output_pref(op, 0), ots->indirect_base); 5758 set_temp_val_reg(s, ots, oreg); 5759 } 5760 5761 /* Promote dup2 of immediates to dupi_vec. */ 5762 if (itsl->val_type == TEMP_VAL_CONST && itsh->val_type == TEMP_VAL_CONST) { 5763 uint64_t val = deposit64(itsl->val, 32, 32, itsh->val); 5764 MemOp vece = MO_64; 5765 5766 if (val == dup_const(MO_8, val)) { 5767 vece = MO_8; 5768 } else if (val == dup_const(MO_16, val)) { 5769 vece = MO_16; 5770 } else if (val == dup_const(MO_32, val)) { 5771 vece = MO_32; 5772 } 5773 5774 tcg_out_dupi_vec(s, vtype, vece, ots->reg, val); 5775 goto done; 5776 } 5777 5778 /* If the two inputs form one 64-bit value, try dupm_vec. */ 5779 if (itsl->temp_subindex == HOST_BIG_ENDIAN && 5780 itsh->temp_subindex == !HOST_BIG_ENDIAN && 5781 itsl == itsh + (HOST_BIG_ENDIAN ? 1 : -1)) { 5782 TCGTemp *its = itsl - HOST_BIG_ENDIAN; 5783 5784 temp_sync(s, its + 0, s->reserved_regs, 0, 0); 5785 temp_sync(s, its + 1, s->reserved_regs, 0, 0); 5786 5787 if (tcg_out_dupm_vec(s, vtype, MO_64, ots->reg, 5788 its->mem_base->reg, its->mem_offset)) { 5789 goto done; 5790 } 5791 } 5792 5793 /* Fall back to generic expansion. */ 5794 return false; 5795 5796 done: 5797 ots->mem_coherent = 0; 5798 if (IS_DEAD_ARG(1)) { 5799 temp_dead(s, itsl); 5800 } 5801 if (IS_DEAD_ARG(2)) { 5802 temp_dead(s, itsh); 5803 } 5804 if (NEED_SYNC_ARG(0)) { 5805 temp_sync(s, ots, s->reserved_regs, 0, IS_DEAD_ARG(0)); 5806 } else if (IS_DEAD_ARG(0)) { 5807 temp_dead(s, ots); 5808 } 5809 return true; 5810 } 5811 5812 static void load_arg_reg(TCGContext *s, TCGReg reg, TCGTemp *ts, 5813 TCGRegSet allocated_regs) 5814 { 5815 if (ts->val_type == TEMP_VAL_REG) { 5816 if (ts->reg != reg) { 5817 tcg_reg_free(s, reg, allocated_regs); 5818 if (!tcg_out_mov(s, ts->type, reg, ts->reg)) { 5819 /* 5820 * Cross register class move not supported. Sync the 5821 * temp back to its slot and load from there. 5822 */ 5823 temp_sync(s, ts, allocated_regs, 0, 0); 5824 tcg_out_ld(s, ts->type, reg, 5825 ts->mem_base->reg, ts->mem_offset); 5826 } 5827 } 5828 } else { 5829 TCGRegSet arg_set = 0; 5830 5831 tcg_reg_free(s, reg, allocated_regs); 5832 tcg_regset_set_reg(arg_set, reg); 5833 temp_load(s, ts, arg_set, allocated_regs, 0); 5834 } 5835 } 5836 5837 static void load_arg_stk(TCGContext *s, unsigned arg_slot, TCGTemp *ts, 5838 TCGRegSet allocated_regs) 5839 { 5840 /* 5841 * When the destination is on the stack, load up the temp and store. 5842 * If there are many call-saved registers, the temp might live to 5843 * see another use; otherwise it'll be discarded. 5844 */ 5845 temp_load(s, ts, tcg_target_available_regs[ts->type], allocated_regs, 0); 5846 tcg_out_st(s, ts->type, ts->reg, TCG_REG_CALL_STACK, 5847 arg_slot_stk_ofs(arg_slot)); 5848 } 5849 5850 static void load_arg_normal(TCGContext *s, const TCGCallArgumentLoc *l, 5851 TCGTemp *ts, TCGRegSet *allocated_regs) 5852 { 5853 if (arg_slot_reg_p(l->arg_slot)) { 5854 TCGReg reg = tcg_target_call_iarg_regs[l->arg_slot]; 5855 load_arg_reg(s, reg, ts, *allocated_regs); 5856 tcg_regset_set_reg(*allocated_regs, reg); 5857 } else { 5858 load_arg_stk(s, l->arg_slot, ts, *allocated_regs); 5859 } 5860 } 5861 5862 static void load_arg_ref(TCGContext *s, unsigned arg_slot, TCGReg ref_base, 5863 intptr_t ref_off, TCGRegSet *allocated_regs) 5864 { 5865 TCGReg reg; 5866 5867 if (arg_slot_reg_p(arg_slot)) { 5868 reg = tcg_target_call_iarg_regs[arg_slot]; 5869 tcg_reg_free(s, reg, *allocated_regs); 5870 tcg_out_addi_ptr(s, reg, ref_base, ref_off); 5871 tcg_regset_set_reg(*allocated_regs, reg); 5872 } else { 5873 reg = tcg_reg_alloc(s, tcg_target_available_regs[TCG_TYPE_PTR], 5874 *allocated_regs, 0, false); 5875 tcg_out_addi_ptr(s, reg, ref_base, ref_off); 5876 tcg_out_st(s, TCG_TYPE_PTR, reg, TCG_REG_CALL_STACK, 5877 arg_slot_stk_ofs(arg_slot)); 5878 } 5879 } 5880 5881 static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) 5882 { 5883 const int nb_oargs = TCGOP_CALLO(op); 5884 const int nb_iargs = TCGOP_CALLI(op); 5885 const TCGLifeData arg_life = op->life; 5886 const TCGHelperInfo *info = tcg_call_info(op); 5887 TCGRegSet allocated_regs = s->reserved_regs; 5888 int i; 5889 5890 /* 5891 * Move inputs into place in reverse order, 5892 * so that we place stacked arguments first. 5893 */ 5894 for (i = nb_iargs - 1; i >= 0; --i) { 5895 const TCGCallArgumentLoc *loc = &info->in[i]; 5896 TCGTemp *ts = arg_temp(op->args[nb_oargs + i]); 5897 5898 switch (loc->kind) { 5899 case TCG_CALL_ARG_NORMAL: 5900 case TCG_CALL_ARG_EXTEND_U: 5901 case TCG_CALL_ARG_EXTEND_S: 5902 load_arg_normal(s, loc, ts, &allocated_regs); 5903 break; 5904 case TCG_CALL_ARG_BY_REF: 5905 load_arg_stk(s, loc->ref_slot, ts, allocated_regs); 5906 load_arg_ref(s, loc->arg_slot, TCG_REG_CALL_STACK, 5907 arg_slot_stk_ofs(loc->ref_slot), 5908 &allocated_regs); 5909 break; 5910 case TCG_CALL_ARG_BY_REF_N: 5911 load_arg_stk(s, loc->ref_slot, ts, allocated_regs); 5912 break; 5913 default: 5914 g_assert_not_reached(); 5915 } 5916 } 5917 5918 /* Mark dead temporaries and free the associated registers. */ 5919 for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) { 5920 if (IS_DEAD_ARG(i)) { 5921 temp_dead(s, arg_temp(op->args[i])); 5922 } 5923 } 5924 5925 /* Clobber call registers. */ 5926 for (i = 0; i < TCG_TARGET_NB_REGS; i++) { 5927 if (tcg_regset_test_reg(tcg_target_call_clobber_regs, i)) { 5928 tcg_reg_free(s, i, allocated_regs); 5929 } 5930 } 5931 5932 /* 5933 * Save globals if they might be written by the helper, 5934 * sync them if they might be read. 5935 */ 5936 if (info->flags & TCG_CALL_NO_READ_GLOBALS) { 5937 /* Nothing to do */ 5938 } else if (info->flags & TCG_CALL_NO_WRITE_GLOBALS) { 5939 sync_globals(s, allocated_regs); 5940 } else { 5941 save_globals(s, allocated_regs); 5942 } 5943 5944 /* 5945 * If the ABI passes a pointer to the returned struct as the first 5946 * argument, load that now. Pass a pointer to the output home slot. 5947 */ 5948 if (info->out_kind == TCG_CALL_RET_BY_REF) { 5949 TCGTemp *ts = arg_temp(op->args[0]); 5950 5951 if (!ts->mem_allocated) { 5952 temp_allocate_frame(s, ts); 5953 } 5954 load_arg_ref(s, 0, ts->mem_base->reg, ts->mem_offset, &allocated_regs); 5955 } 5956 5957 tcg_out_call(s, tcg_call_func(op), info); 5958 5959 /* Assign output registers and emit moves if needed. */ 5960 switch (info->out_kind) { 5961 case TCG_CALL_RET_NORMAL: 5962 for (i = 0; i < nb_oargs; i++) { 5963 TCGTemp *ts = arg_temp(op->args[i]); 5964 TCGReg reg = tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL, i); 5965 5966 /* ENV should not be modified. */ 5967 tcg_debug_assert(!temp_readonly(ts)); 5968 5969 set_temp_val_reg(s, ts, reg); 5970 ts->mem_coherent = 0; 5971 } 5972 break; 5973 5974 case TCG_CALL_RET_BY_VEC: 5975 { 5976 TCGTemp *ts = arg_temp(op->args[0]); 5977 5978 tcg_debug_assert(ts->base_type == TCG_TYPE_I128); 5979 tcg_debug_assert(ts->temp_subindex == 0); 5980 if (!ts->mem_allocated) { 5981 temp_allocate_frame(s, ts); 5982 } 5983 tcg_out_st(s, TCG_TYPE_V128, 5984 tcg_target_call_oarg_reg(TCG_CALL_RET_BY_VEC, 0), 5985 ts->mem_base->reg, ts->mem_offset); 5986 } 5987 /* fall through to mark all parts in memory */ 5988 5989 case TCG_CALL_RET_BY_REF: 5990 /* The callee has performed a write through the reference. */ 5991 for (i = 0; i < nb_oargs; i++) { 5992 TCGTemp *ts = arg_temp(op->args[i]); 5993 ts->val_type = TEMP_VAL_MEM; 5994 } 5995 break; 5996 5997 default: 5998 g_assert_not_reached(); 5999 } 6000 6001 /* Flush or discard output registers as needed. */ 6002 for (i = 0; i < nb_oargs; i++) { 6003 TCGTemp *ts = arg_temp(op->args[i]); 6004 if (NEED_SYNC_ARG(i)) { 6005 temp_sync(s, ts, s->reserved_regs, 0, IS_DEAD_ARG(i)); 6006 } else if (IS_DEAD_ARG(i)) { 6007 temp_dead(s, ts); 6008 } 6009 } 6010 } 6011 6012 /** 6013 * atom_and_align_for_opc: 6014 * @s: tcg context 6015 * @opc: memory operation code 6016 * @host_atom: MO_ATOM_{IFALIGN,WITHIN16,SUBALIGN} for host operations 6017 * @allow_two_ops: true if we are prepared to issue two operations 6018 * 6019 * Return the alignment and atomicity to use for the inline fast path 6020 * for the given memory operation. The alignment may be larger than 6021 * that specified in @opc, and the correct alignment will be diagnosed 6022 * by the slow path helper. 6023 * 6024 * If @allow_two_ops, the host is prepared to test for 2x alignment, 6025 * and issue two loads or stores for subalignment. 6026 */ 6027 static TCGAtomAlign atom_and_align_for_opc(TCGContext *s, MemOp opc, 6028 MemOp host_atom, bool allow_two_ops) 6029 { 6030 MemOp align = memop_alignment_bits(opc); 6031 MemOp size = opc & MO_SIZE; 6032 MemOp half = size ? size - 1 : 0; 6033 MemOp atom = opc & MO_ATOM_MASK; 6034 MemOp atmax; 6035 6036 switch (atom) { 6037 case MO_ATOM_NONE: 6038 /* The operation requires no specific atomicity. */ 6039 atmax = MO_8; 6040 break; 6041 6042 case MO_ATOM_IFALIGN: 6043 atmax = size; 6044 break; 6045 6046 case MO_ATOM_IFALIGN_PAIR: 6047 atmax = half; 6048 break; 6049 6050 case MO_ATOM_WITHIN16: 6051 atmax = size; 6052 if (size == MO_128) { 6053 /* Misalignment implies !within16, and therefore no atomicity. */ 6054 } else if (host_atom != MO_ATOM_WITHIN16) { 6055 /* The host does not implement within16, so require alignment. */ 6056 align = MAX(align, size); 6057 } 6058 break; 6059 6060 case MO_ATOM_WITHIN16_PAIR: 6061 atmax = size; 6062 /* 6063 * Misalignment implies !within16, and therefore half atomicity. 6064 * Any host prepared for two operations can implement this with 6065 * half alignment. 6066 */ 6067 if (host_atom != MO_ATOM_WITHIN16 && allow_two_ops) { 6068 align = MAX(align, half); 6069 } 6070 break; 6071 6072 case MO_ATOM_SUBALIGN: 6073 atmax = size; 6074 if (host_atom != MO_ATOM_SUBALIGN) { 6075 /* If unaligned but not odd, there are subobjects up to half. */ 6076 if (allow_two_ops) { 6077 align = MAX(align, half); 6078 } else { 6079 align = MAX(align, size); 6080 } 6081 } 6082 break; 6083 6084 default: 6085 g_assert_not_reached(); 6086 } 6087 6088 return (TCGAtomAlign){ .atom = atmax, .align = align }; 6089 } 6090 6091 /* 6092 * Similarly for qemu_ld/st slow path helpers. 6093 * We must re-implement tcg_gen_callN and tcg_reg_alloc_call simultaneously, 6094 * using only the provided backend tcg_out_* functions. 6095 */ 6096 6097 static int tcg_out_helper_stk_ofs(TCGType type, unsigned slot) 6098 { 6099 int ofs = arg_slot_stk_ofs(slot); 6100 6101 /* 6102 * Each stack slot is TCG_TARGET_LONG_BITS. If the host does not 6103 * require extension to uint64_t, adjust the address for uint32_t. 6104 */ 6105 if (HOST_BIG_ENDIAN && 6106 TCG_TARGET_REG_BITS == 64 && 6107 type == TCG_TYPE_I32) { 6108 ofs += 4; 6109 } 6110 return ofs; 6111 } 6112 6113 static void tcg_out_helper_load_slots(TCGContext *s, 6114 unsigned nmov, TCGMovExtend *mov, 6115 const TCGLdstHelperParam *parm) 6116 { 6117 unsigned i; 6118 TCGReg dst3; 6119 6120 /* 6121 * Start from the end, storing to the stack first. 6122 * This frees those registers, so we need not consider overlap. 6123 */ 6124 for (i = nmov; i-- > 0; ) { 6125 unsigned slot = mov[i].dst; 6126 6127 if (arg_slot_reg_p(slot)) { 6128 goto found_reg; 6129 } 6130 6131 TCGReg src = mov[i].src; 6132 TCGType dst_type = mov[i].dst_type; 6133 MemOp dst_mo = dst_type == TCG_TYPE_I32 ? MO_32 : MO_64; 6134 6135 /* The argument is going onto the stack; extend into scratch. */ 6136 if ((mov[i].src_ext & MO_SIZE) != dst_mo) { 6137 tcg_debug_assert(parm->ntmp != 0); 6138 mov[i].dst = src = parm->tmp[0]; 6139 tcg_out_movext1(s, &mov[i]); 6140 } 6141 6142 tcg_out_st(s, dst_type, src, TCG_REG_CALL_STACK, 6143 tcg_out_helper_stk_ofs(dst_type, slot)); 6144 } 6145 return; 6146 6147 found_reg: 6148 /* 6149 * The remaining arguments are in registers. 6150 * Convert slot numbers to argument registers. 6151 */ 6152 nmov = i + 1; 6153 for (i = 0; i < nmov; ++i) { 6154 mov[i].dst = tcg_target_call_iarg_regs[mov[i].dst]; 6155 } 6156 6157 switch (nmov) { 6158 case 4: 6159 /* The backend must have provided enough temps for the worst case. */ 6160 tcg_debug_assert(parm->ntmp >= 2); 6161 6162 dst3 = mov[3].dst; 6163 for (unsigned j = 0; j < 3; ++j) { 6164 if (dst3 == mov[j].src) { 6165 /* 6166 * Conflict. Copy the source to a temporary, perform the 6167 * remaining moves, then the extension from our scratch 6168 * on the way out. 6169 */ 6170 TCGReg scratch = parm->tmp[1]; 6171 6172 tcg_out_mov(s, mov[3].src_type, scratch, mov[3].src); 6173 tcg_out_movext3(s, mov, mov + 1, mov + 2, parm->tmp[0]); 6174 tcg_out_movext1_new_src(s, &mov[3], scratch); 6175 break; 6176 } 6177 } 6178 6179 /* No conflicts: perform this move and continue. */ 6180 tcg_out_movext1(s, &mov[3]); 6181 /* fall through */ 6182 6183 case 3: 6184 tcg_out_movext3(s, mov, mov + 1, mov + 2, 6185 parm->ntmp ? parm->tmp[0] : -1); 6186 break; 6187 case 2: 6188 tcg_out_movext2(s, mov, mov + 1, 6189 parm->ntmp ? parm->tmp[0] : -1); 6190 break; 6191 case 1: 6192 tcg_out_movext1(s, mov); 6193 break; 6194 default: 6195 g_assert_not_reached(); 6196 } 6197 } 6198 6199 static void tcg_out_helper_load_imm(TCGContext *s, unsigned slot, 6200 TCGType type, tcg_target_long imm, 6201 const TCGLdstHelperParam *parm) 6202 { 6203 if (arg_slot_reg_p(slot)) { 6204 tcg_out_movi(s, type, tcg_target_call_iarg_regs[slot], imm); 6205 } else { 6206 int ofs = tcg_out_helper_stk_ofs(type, slot); 6207 if (!tcg_out_sti(s, type, imm, TCG_REG_CALL_STACK, ofs)) { 6208 tcg_debug_assert(parm->ntmp != 0); 6209 tcg_out_movi(s, type, parm->tmp[0], imm); 6210 tcg_out_st(s, type, parm->tmp[0], TCG_REG_CALL_STACK, ofs); 6211 } 6212 } 6213 } 6214 6215 static void tcg_out_helper_load_common_args(TCGContext *s, 6216 const TCGLabelQemuLdst *ldst, 6217 const TCGLdstHelperParam *parm, 6218 const TCGHelperInfo *info, 6219 unsigned next_arg) 6220 { 6221 TCGMovExtend ptr_mov = { 6222 .dst_type = TCG_TYPE_PTR, 6223 .src_type = TCG_TYPE_PTR, 6224 .src_ext = sizeof(void *) == 4 ? MO_32 : MO_64 6225 }; 6226 const TCGCallArgumentLoc *loc = &info->in[0]; 6227 TCGType type; 6228 unsigned slot; 6229 tcg_target_ulong imm; 6230 6231 /* 6232 * Handle env, which is always first. 6233 */ 6234 ptr_mov.dst = loc->arg_slot; 6235 ptr_mov.src = TCG_AREG0; 6236 tcg_out_helper_load_slots(s, 1, &ptr_mov, parm); 6237 6238 /* 6239 * Handle oi. 6240 */ 6241 imm = ldst->oi; 6242 loc = &info->in[next_arg]; 6243 type = TCG_TYPE_I32; 6244 switch (loc->kind) { 6245 case TCG_CALL_ARG_NORMAL: 6246 break; 6247 case TCG_CALL_ARG_EXTEND_U: 6248 case TCG_CALL_ARG_EXTEND_S: 6249 /* No extension required for MemOpIdx. */ 6250 tcg_debug_assert(imm <= INT32_MAX); 6251 type = TCG_TYPE_REG; 6252 break; 6253 default: 6254 g_assert_not_reached(); 6255 } 6256 tcg_out_helper_load_imm(s, loc->arg_slot, type, imm, parm); 6257 next_arg++; 6258 6259 /* 6260 * Handle ra. 6261 */ 6262 loc = &info->in[next_arg]; 6263 slot = loc->arg_slot; 6264 if (parm->ra_gen) { 6265 int arg_reg = -1; 6266 TCGReg ra_reg; 6267 6268 if (arg_slot_reg_p(slot)) { 6269 arg_reg = tcg_target_call_iarg_regs[slot]; 6270 } 6271 ra_reg = parm->ra_gen(s, ldst, arg_reg); 6272 6273 ptr_mov.dst = slot; 6274 ptr_mov.src = ra_reg; 6275 tcg_out_helper_load_slots(s, 1, &ptr_mov, parm); 6276 } else { 6277 imm = (uintptr_t)ldst->raddr; 6278 tcg_out_helper_load_imm(s, slot, TCG_TYPE_PTR, imm, parm); 6279 } 6280 } 6281 6282 static unsigned tcg_out_helper_add_mov(TCGMovExtend *mov, 6283 const TCGCallArgumentLoc *loc, 6284 TCGType dst_type, TCGType src_type, 6285 TCGReg lo, TCGReg hi) 6286 { 6287 MemOp reg_mo; 6288 6289 if (dst_type <= TCG_TYPE_REG) { 6290 MemOp src_ext; 6291 6292 switch (loc->kind) { 6293 case TCG_CALL_ARG_NORMAL: 6294 src_ext = src_type == TCG_TYPE_I32 ? MO_32 : MO_64; 6295 break; 6296 case TCG_CALL_ARG_EXTEND_U: 6297 dst_type = TCG_TYPE_REG; 6298 src_ext = MO_UL; 6299 break; 6300 case TCG_CALL_ARG_EXTEND_S: 6301 dst_type = TCG_TYPE_REG; 6302 src_ext = MO_SL; 6303 break; 6304 default: 6305 g_assert_not_reached(); 6306 } 6307 6308 mov[0].dst = loc->arg_slot; 6309 mov[0].dst_type = dst_type; 6310 mov[0].src = lo; 6311 mov[0].src_type = src_type; 6312 mov[0].src_ext = src_ext; 6313 return 1; 6314 } 6315 6316 if (TCG_TARGET_REG_BITS == 32) { 6317 assert(dst_type == TCG_TYPE_I64); 6318 reg_mo = MO_32; 6319 } else { 6320 assert(dst_type == TCG_TYPE_I128); 6321 reg_mo = MO_64; 6322 } 6323 6324 mov[0].dst = loc[HOST_BIG_ENDIAN].arg_slot; 6325 mov[0].src = lo; 6326 mov[0].dst_type = TCG_TYPE_REG; 6327 mov[0].src_type = TCG_TYPE_REG; 6328 mov[0].src_ext = reg_mo; 6329 6330 mov[1].dst = loc[!HOST_BIG_ENDIAN].arg_slot; 6331 mov[1].src = hi; 6332 mov[1].dst_type = TCG_TYPE_REG; 6333 mov[1].src_type = TCG_TYPE_REG; 6334 mov[1].src_ext = reg_mo; 6335 6336 return 2; 6337 } 6338 6339 static void tcg_out_ld_helper_args(TCGContext *s, const TCGLabelQemuLdst *ldst, 6340 const TCGLdstHelperParam *parm) 6341 { 6342 const TCGHelperInfo *info; 6343 const TCGCallArgumentLoc *loc; 6344 TCGMovExtend mov[2]; 6345 unsigned next_arg, nmov; 6346 MemOp mop = get_memop(ldst->oi); 6347 6348 switch (mop & MO_SIZE) { 6349 case MO_8: 6350 case MO_16: 6351 case MO_32: 6352 info = &info_helper_ld32_mmu; 6353 break; 6354 case MO_64: 6355 info = &info_helper_ld64_mmu; 6356 break; 6357 case MO_128: 6358 info = &info_helper_ld128_mmu; 6359 break; 6360 default: 6361 g_assert_not_reached(); 6362 } 6363 6364 /* Defer env argument. */ 6365 next_arg = 1; 6366 6367 loc = &info->in[next_arg]; 6368 if (TCG_TARGET_REG_BITS == 32 && s->addr_type == TCG_TYPE_I32) { 6369 /* 6370 * 32-bit host with 32-bit guest: zero-extend the guest address 6371 * to 64-bits for the helper by storing the low part, then 6372 * load a zero for the high part. 6373 */ 6374 tcg_out_helper_add_mov(mov, loc + HOST_BIG_ENDIAN, 6375 TCG_TYPE_I32, TCG_TYPE_I32, 6376 ldst->addr_reg, -1); 6377 tcg_out_helper_load_slots(s, 1, mov, parm); 6378 6379 tcg_out_helper_load_imm(s, loc[!HOST_BIG_ENDIAN].arg_slot, 6380 TCG_TYPE_I32, 0, parm); 6381 next_arg += 2; 6382 } else { 6383 nmov = tcg_out_helper_add_mov(mov, loc, TCG_TYPE_I64, s->addr_type, 6384 ldst->addr_reg, -1); 6385 tcg_out_helper_load_slots(s, nmov, mov, parm); 6386 next_arg += nmov; 6387 } 6388 6389 switch (info->out_kind) { 6390 case TCG_CALL_RET_NORMAL: 6391 case TCG_CALL_RET_BY_VEC: 6392 break; 6393 case TCG_CALL_RET_BY_REF: 6394 /* 6395 * The return reference is in the first argument slot. 6396 * We need memory in which to return: re-use the top of stack. 6397 */ 6398 { 6399 int ofs_slot0 = TCG_TARGET_CALL_STACK_OFFSET; 6400 6401 if (arg_slot_reg_p(0)) { 6402 tcg_out_addi_ptr(s, tcg_target_call_iarg_regs[0], 6403 TCG_REG_CALL_STACK, ofs_slot0); 6404 } else { 6405 tcg_debug_assert(parm->ntmp != 0); 6406 tcg_out_addi_ptr(s, parm->tmp[0], 6407 TCG_REG_CALL_STACK, ofs_slot0); 6408 tcg_out_st(s, TCG_TYPE_PTR, parm->tmp[0], 6409 TCG_REG_CALL_STACK, ofs_slot0); 6410 } 6411 } 6412 break; 6413 default: 6414 g_assert_not_reached(); 6415 } 6416 6417 tcg_out_helper_load_common_args(s, ldst, parm, info, next_arg); 6418 } 6419 6420 static void tcg_out_ld_helper_ret(TCGContext *s, const TCGLabelQemuLdst *ldst, 6421 bool load_sign, 6422 const TCGLdstHelperParam *parm) 6423 { 6424 MemOp mop = get_memop(ldst->oi); 6425 TCGMovExtend mov[2]; 6426 int ofs_slot0; 6427 6428 switch (ldst->type) { 6429 case TCG_TYPE_I64: 6430 if (TCG_TARGET_REG_BITS == 32) { 6431 break; 6432 } 6433 /* fall through */ 6434 6435 case TCG_TYPE_I32: 6436 mov[0].dst = ldst->datalo_reg; 6437 mov[0].src = tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL, 0); 6438 mov[0].dst_type = ldst->type; 6439 mov[0].src_type = TCG_TYPE_REG; 6440 6441 /* 6442 * If load_sign, then we allowed the helper to perform the 6443 * appropriate sign extension to tcg_target_ulong, and all 6444 * we need now is a plain move. 6445 * 6446 * If they do not, then we expect the relevant extension 6447 * instruction to be no more expensive than a move, and 6448 * we thus save the icache etc by only using one of two 6449 * helper functions. 6450 */ 6451 if (load_sign || !(mop & MO_SIGN)) { 6452 if (TCG_TARGET_REG_BITS == 32 || ldst->type == TCG_TYPE_I32) { 6453 mov[0].src_ext = MO_32; 6454 } else { 6455 mov[0].src_ext = MO_64; 6456 } 6457 } else { 6458 mov[0].src_ext = mop & MO_SSIZE; 6459 } 6460 tcg_out_movext1(s, mov); 6461 return; 6462 6463 case TCG_TYPE_I128: 6464 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 6465 ofs_slot0 = TCG_TARGET_CALL_STACK_OFFSET; 6466 switch (TCG_TARGET_CALL_RET_I128) { 6467 case TCG_CALL_RET_NORMAL: 6468 break; 6469 case TCG_CALL_RET_BY_VEC: 6470 tcg_out_st(s, TCG_TYPE_V128, 6471 tcg_target_call_oarg_reg(TCG_CALL_RET_BY_VEC, 0), 6472 TCG_REG_CALL_STACK, ofs_slot0); 6473 /* fall through */ 6474 case TCG_CALL_RET_BY_REF: 6475 tcg_out_ld(s, TCG_TYPE_I64, ldst->datalo_reg, 6476 TCG_REG_CALL_STACK, ofs_slot0 + 8 * HOST_BIG_ENDIAN); 6477 tcg_out_ld(s, TCG_TYPE_I64, ldst->datahi_reg, 6478 TCG_REG_CALL_STACK, ofs_slot0 + 8 * !HOST_BIG_ENDIAN); 6479 return; 6480 default: 6481 g_assert_not_reached(); 6482 } 6483 break; 6484 6485 default: 6486 g_assert_not_reached(); 6487 } 6488 6489 mov[0].dst = ldst->datalo_reg; 6490 mov[0].src = 6491 tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL, HOST_BIG_ENDIAN); 6492 mov[0].dst_type = TCG_TYPE_REG; 6493 mov[0].src_type = TCG_TYPE_REG; 6494 mov[0].src_ext = TCG_TARGET_REG_BITS == 32 ? MO_32 : MO_64; 6495 6496 mov[1].dst = ldst->datahi_reg; 6497 mov[1].src = 6498 tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL, !HOST_BIG_ENDIAN); 6499 mov[1].dst_type = TCG_TYPE_REG; 6500 mov[1].src_type = TCG_TYPE_REG; 6501 mov[1].src_ext = TCG_TARGET_REG_BITS == 32 ? MO_32 : MO_64; 6502 6503 tcg_out_movext2(s, mov, mov + 1, parm->ntmp ? parm->tmp[0] : -1); 6504 } 6505 6506 static void tcg_out_st_helper_args(TCGContext *s, const TCGLabelQemuLdst *ldst, 6507 const TCGLdstHelperParam *parm) 6508 { 6509 const TCGHelperInfo *info; 6510 const TCGCallArgumentLoc *loc; 6511 TCGMovExtend mov[4]; 6512 TCGType data_type; 6513 unsigned next_arg, nmov, n; 6514 MemOp mop = get_memop(ldst->oi); 6515 6516 switch (mop & MO_SIZE) { 6517 case MO_8: 6518 case MO_16: 6519 case MO_32: 6520 info = &info_helper_st32_mmu; 6521 data_type = TCG_TYPE_I32; 6522 break; 6523 case MO_64: 6524 info = &info_helper_st64_mmu; 6525 data_type = TCG_TYPE_I64; 6526 break; 6527 case MO_128: 6528 info = &info_helper_st128_mmu; 6529 data_type = TCG_TYPE_I128; 6530 break; 6531 default: 6532 g_assert_not_reached(); 6533 } 6534 6535 /* Defer env argument. */ 6536 next_arg = 1; 6537 nmov = 0; 6538 6539 /* Handle addr argument. */ 6540 loc = &info->in[next_arg]; 6541 tcg_debug_assert(s->addr_type <= TCG_TYPE_REG); 6542 if (TCG_TARGET_REG_BITS == 32) { 6543 /* 6544 * 32-bit host (and thus 32-bit guest): zero-extend the guest address 6545 * to 64-bits for the helper by storing the low part. Later, 6546 * after we have processed the register inputs, we will load a 6547 * zero for the high part. 6548 */ 6549 tcg_out_helper_add_mov(mov, loc + HOST_BIG_ENDIAN, 6550 TCG_TYPE_I32, TCG_TYPE_I32, 6551 ldst->addr_reg, -1); 6552 next_arg += 2; 6553 nmov += 1; 6554 } else { 6555 n = tcg_out_helper_add_mov(mov, loc, TCG_TYPE_I64, s->addr_type, 6556 ldst->addr_reg, -1); 6557 next_arg += n; 6558 nmov += n; 6559 } 6560 6561 /* Handle data argument. */ 6562 loc = &info->in[next_arg]; 6563 switch (loc->kind) { 6564 case TCG_CALL_ARG_NORMAL: 6565 case TCG_CALL_ARG_EXTEND_U: 6566 case TCG_CALL_ARG_EXTEND_S: 6567 n = tcg_out_helper_add_mov(mov + nmov, loc, data_type, ldst->type, 6568 ldst->datalo_reg, ldst->datahi_reg); 6569 next_arg += n; 6570 nmov += n; 6571 tcg_out_helper_load_slots(s, nmov, mov, parm); 6572 break; 6573 6574 case TCG_CALL_ARG_BY_REF: 6575 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 6576 tcg_debug_assert(data_type == TCG_TYPE_I128); 6577 tcg_out_st(s, TCG_TYPE_I64, 6578 HOST_BIG_ENDIAN ? ldst->datahi_reg : ldst->datalo_reg, 6579 TCG_REG_CALL_STACK, arg_slot_stk_ofs(loc[0].ref_slot)); 6580 tcg_out_st(s, TCG_TYPE_I64, 6581 HOST_BIG_ENDIAN ? ldst->datalo_reg : ldst->datahi_reg, 6582 TCG_REG_CALL_STACK, arg_slot_stk_ofs(loc[1].ref_slot)); 6583 6584 tcg_out_helper_load_slots(s, nmov, mov, parm); 6585 6586 if (arg_slot_reg_p(loc->arg_slot)) { 6587 tcg_out_addi_ptr(s, tcg_target_call_iarg_regs[loc->arg_slot], 6588 TCG_REG_CALL_STACK, 6589 arg_slot_stk_ofs(loc->ref_slot)); 6590 } else { 6591 tcg_debug_assert(parm->ntmp != 0); 6592 tcg_out_addi_ptr(s, parm->tmp[0], TCG_REG_CALL_STACK, 6593 arg_slot_stk_ofs(loc->ref_slot)); 6594 tcg_out_st(s, TCG_TYPE_PTR, parm->tmp[0], 6595 TCG_REG_CALL_STACK, arg_slot_stk_ofs(loc->arg_slot)); 6596 } 6597 next_arg += 2; 6598 break; 6599 6600 default: 6601 g_assert_not_reached(); 6602 } 6603 6604 if (TCG_TARGET_REG_BITS == 32) { 6605 /* Zero extend the address by loading a zero for the high part. */ 6606 loc = &info->in[1 + !HOST_BIG_ENDIAN]; 6607 tcg_out_helper_load_imm(s, loc->arg_slot, TCG_TYPE_I32, 0, parm); 6608 } 6609 6610 tcg_out_helper_load_common_args(s, ldst, parm, info, next_arg); 6611 } 6612 6613 int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start) 6614 { 6615 int i, start_words, num_insns; 6616 TCGOp *op; 6617 6618 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP) 6619 && qemu_log_in_addr_range(pc_start))) { 6620 FILE *logfile = qemu_log_trylock(); 6621 if (logfile) { 6622 fprintf(logfile, "OP:\n"); 6623 tcg_dump_ops(s, logfile, false); 6624 fprintf(logfile, "\n"); 6625 qemu_log_unlock(logfile); 6626 } 6627 } 6628 6629 #ifdef CONFIG_DEBUG_TCG 6630 /* Ensure all labels referenced have been emitted. */ 6631 { 6632 TCGLabel *l; 6633 bool error = false; 6634 6635 QSIMPLEQ_FOREACH(l, &s->labels, next) { 6636 if (unlikely(!l->present) && !QSIMPLEQ_EMPTY(&l->branches)) { 6637 qemu_log_mask(CPU_LOG_TB_OP, 6638 "$L%d referenced but not present.\n", l->id); 6639 error = true; 6640 } 6641 } 6642 assert(!error); 6643 } 6644 #endif 6645 6646 /* Do not reuse any EBB that may be allocated within the TB. */ 6647 tcg_temp_ebb_reset_freed(s); 6648 6649 tcg_optimize(s); 6650 6651 reachable_code_pass(s); 6652 liveness_pass_0(s); 6653 liveness_pass_1(s); 6654 6655 if (s->nb_indirects > 0) { 6656 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_IND) 6657 && qemu_log_in_addr_range(pc_start))) { 6658 FILE *logfile = qemu_log_trylock(); 6659 if (logfile) { 6660 fprintf(logfile, "OP before indirect lowering:\n"); 6661 tcg_dump_ops(s, logfile, false); 6662 fprintf(logfile, "\n"); 6663 qemu_log_unlock(logfile); 6664 } 6665 } 6666 6667 /* Replace indirect temps with direct temps. */ 6668 if (liveness_pass_2(s)) { 6669 /* If changes were made, re-run liveness. */ 6670 liveness_pass_1(s); 6671 } 6672 } 6673 6674 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT) 6675 && qemu_log_in_addr_range(pc_start))) { 6676 FILE *logfile = qemu_log_trylock(); 6677 if (logfile) { 6678 fprintf(logfile, "OP after optimization and liveness analysis:\n"); 6679 tcg_dump_ops(s, logfile, true); 6680 fprintf(logfile, "\n"); 6681 qemu_log_unlock(logfile); 6682 } 6683 } 6684 6685 /* Initialize goto_tb jump offsets. */ 6686 tb->jmp_reset_offset[0] = TB_JMP_OFFSET_INVALID; 6687 tb->jmp_reset_offset[1] = TB_JMP_OFFSET_INVALID; 6688 tb->jmp_insn_offset[0] = TB_JMP_OFFSET_INVALID; 6689 tb->jmp_insn_offset[1] = TB_JMP_OFFSET_INVALID; 6690 6691 tcg_reg_alloc_start(s); 6692 6693 /* 6694 * Reset the buffer pointers when restarting after overflow. 6695 * TODO: Move this into translate-all.c with the rest of the 6696 * buffer management. Having only this done here is confusing. 6697 */ 6698 s->code_buf = tcg_splitwx_to_rw(tb->tc.ptr); 6699 s->code_ptr = s->code_buf; 6700 s->data_gen_ptr = NULL; 6701 6702 QSIMPLEQ_INIT(&s->ldst_labels); 6703 s->pool_labels = NULL; 6704 6705 start_words = s->insn_start_words; 6706 s->gen_insn_data = 6707 tcg_malloc(sizeof(uint64_t) * s->gen_tb->icount * start_words); 6708 6709 tcg_out_tb_start(s); 6710 6711 num_insns = -1; 6712 QTAILQ_FOREACH(op, &s->ops, link) { 6713 TCGOpcode opc = op->opc; 6714 6715 switch (opc) { 6716 case INDEX_op_extrl_i64_i32: 6717 assert(TCG_TARGET_REG_BITS == 64); 6718 /* 6719 * If TCG_TYPE_I32 is represented in some canonical form, 6720 * e.g. zero or sign-extended, then emit as a unary op. 6721 * Otherwise we can treat this as a plain move. 6722 * If the output dies, treat this as a plain move, because 6723 * this will be implemented with a store. 6724 */ 6725 if (TCG_TARGET_HAS_extr_i64_i32) { 6726 TCGLifeData arg_life = op->life; 6727 if (!IS_DEAD_ARG(0)) { 6728 goto do_default; 6729 } 6730 } 6731 /* fall through */ 6732 case INDEX_op_mov: 6733 case INDEX_op_mov_vec: 6734 tcg_reg_alloc_mov(s, op); 6735 break; 6736 case INDEX_op_dup_vec: 6737 tcg_reg_alloc_dup(s, op); 6738 break; 6739 case INDEX_op_insn_start: 6740 if (num_insns >= 0) { 6741 size_t off = tcg_current_code_size(s); 6742 s->gen_insn_end_off[num_insns] = off; 6743 /* Assert that we do not overflow our stored offset. */ 6744 assert(s->gen_insn_end_off[num_insns] == off); 6745 } 6746 num_insns++; 6747 for (i = 0; i < start_words; ++i) { 6748 s->gen_insn_data[num_insns * start_words + i] = 6749 tcg_get_insn_start_param(op, i); 6750 } 6751 break; 6752 case INDEX_op_discard: 6753 temp_dead(s, arg_temp(op->args[0])); 6754 break; 6755 case INDEX_op_set_label: 6756 tcg_reg_alloc_bb_end(s, s->reserved_regs); 6757 tcg_out_label(s, arg_label(op->args[0])); 6758 break; 6759 case INDEX_op_call: 6760 tcg_reg_alloc_call(s, op); 6761 break; 6762 case INDEX_op_exit_tb: 6763 tcg_out_exit_tb(s, op->args[0]); 6764 break; 6765 case INDEX_op_goto_tb: 6766 tcg_out_goto_tb(s, op->args[0]); 6767 break; 6768 case INDEX_op_dup2_vec: 6769 if (tcg_reg_alloc_dup2(s, op)) { 6770 break; 6771 } 6772 /* fall through */ 6773 default: 6774 do_default: 6775 /* Sanity check that we've not introduced any unhandled opcodes. */ 6776 tcg_debug_assert(tcg_op_supported(opc, TCGOP_TYPE(op), 6777 TCGOP_FLAGS(op))); 6778 /* Note: in order to speed up the code, it would be much 6779 faster to have specialized register allocator functions for 6780 some common argument patterns */ 6781 tcg_reg_alloc_op(s, op); 6782 break; 6783 } 6784 /* Test for (pending) buffer overflow. The assumption is that any 6785 one operation beginning below the high water mark cannot overrun 6786 the buffer completely. Thus we can test for overflow after 6787 generating code without having to check during generation. */ 6788 if (unlikely((void *)s->code_ptr > s->code_gen_highwater)) { 6789 return -1; 6790 } 6791 /* Test for TB overflow, as seen by gen_insn_end_off. */ 6792 if (unlikely(tcg_current_code_size(s) > UINT16_MAX)) { 6793 return -2; 6794 } 6795 } 6796 tcg_debug_assert(num_insns + 1 == s->gen_tb->icount); 6797 s->gen_insn_end_off[num_insns] = tcg_current_code_size(s); 6798 6799 /* Generate TB finalization at the end of block */ 6800 i = tcg_out_ldst_finalize(s); 6801 if (i < 0) { 6802 return i; 6803 } 6804 i = tcg_out_pool_finalize(s); 6805 if (i < 0) { 6806 return i; 6807 } 6808 if (!tcg_resolve_relocs(s)) { 6809 return -2; 6810 } 6811 6812 #ifndef CONFIG_TCG_INTERPRETER 6813 /* flush instruction cache */ 6814 flush_idcache_range((uintptr_t)tcg_splitwx_to_rx(s->code_buf), 6815 (uintptr_t)s->code_buf, 6816 tcg_ptr_byte_diff(s->code_ptr, s->code_buf)); 6817 #endif 6818 6819 return tcg_current_code_size(s); 6820 } 6821 6822 #ifdef ELF_HOST_MACHINE 6823 /* In order to use this feature, the backend needs to do three things: 6824 6825 (1) Define ELF_HOST_MACHINE to indicate both what value to 6826 put into the ELF image and to indicate support for the feature. 6827 6828 (2) Define tcg_register_jit. This should create a buffer containing 6829 the contents of a .debug_frame section that describes the post- 6830 prologue unwind info for the tcg machine. 6831 6832 (3) Call tcg_register_jit_int, with the constructed .debug_frame. 6833 */ 6834 6835 /* Begin GDB interface. THE FOLLOWING MUST MATCH GDB DOCS. */ 6836 typedef enum { 6837 JIT_NOACTION = 0, 6838 JIT_REGISTER_FN, 6839 JIT_UNREGISTER_FN 6840 } jit_actions_t; 6841 6842 struct jit_code_entry { 6843 struct jit_code_entry *next_entry; 6844 struct jit_code_entry *prev_entry; 6845 const void *symfile_addr; 6846 uint64_t symfile_size; 6847 }; 6848 6849 struct jit_descriptor { 6850 uint32_t version; 6851 uint32_t action_flag; 6852 struct jit_code_entry *relevant_entry; 6853 struct jit_code_entry *first_entry; 6854 }; 6855 6856 void __jit_debug_register_code(void) __attribute__((noinline)); 6857 void __jit_debug_register_code(void) 6858 { 6859 asm(""); 6860 } 6861 6862 /* Must statically initialize the version, because GDB may check 6863 the version before we can set it. */ 6864 struct jit_descriptor __jit_debug_descriptor = { 1, 0, 0, 0 }; 6865 6866 /* End GDB interface. */ 6867 6868 static int find_string(const char *strtab, const char *str) 6869 { 6870 const char *p = strtab + 1; 6871 6872 while (1) { 6873 if (strcmp(p, str) == 0) { 6874 return p - strtab; 6875 } 6876 p += strlen(p) + 1; 6877 } 6878 } 6879 6880 static void tcg_register_jit_int(const void *buf_ptr, size_t buf_size, 6881 const void *debug_frame, 6882 size_t debug_frame_size) 6883 { 6884 struct __attribute__((packed)) DebugInfo { 6885 uint32_t len; 6886 uint16_t version; 6887 uint32_t abbrev; 6888 uint8_t ptr_size; 6889 uint8_t cu_die; 6890 uint16_t cu_lang; 6891 uintptr_t cu_low_pc; 6892 uintptr_t cu_high_pc; 6893 uint8_t fn_die; 6894 char fn_name[16]; 6895 uintptr_t fn_low_pc; 6896 uintptr_t fn_high_pc; 6897 uint8_t cu_eoc; 6898 }; 6899 6900 struct ElfImage { 6901 ElfW(Ehdr) ehdr; 6902 ElfW(Phdr) phdr; 6903 ElfW(Shdr) shdr[7]; 6904 ElfW(Sym) sym[2]; 6905 struct DebugInfo di; 6906 uint8_t da[24]; 6907 char str[80]; 6908 }; 6909 6910 struct ElfImage *img; 6911 6912 static const struct ElfImage img_template = { 6913 .ehdr = { 6914 .e_ident[EI_MAG0] = ELFMAG0, 6915 .e_ident[EI_MAG1] = ELFMAG1, 6916 .e_ident[EI_MAG2] = ELFMAG2, 6917 .e_ident[EI_MAG3] = ELFMAG3, 6918 .e_ident[EI_CLASS] = ELF_CLASS, 6919 .e_ident[EI_DATA] = ELF_DATA, 6920 .e_ident[EI_VERSION] = EV_CURRENT, 6921 .e_type = ET_EXEC, 6922 .e_machine = ELF_HOST_MACHINE, 6923 .e_version = EV_CURRENT, 6924 .e_phoff = offsetof(struct ElfImage, phdr), 6925 .e_shoff = offsetof(struct ElfImage, shdr), 6926 .e_ehsize = sizeof(ElfW(Shdr)), 6927 .e_phentsize = sizeof(ElfW(Phdr)), 6928 .e_phnum = 1, 6929 .e_shentsize = sizeof(ElfW(Shdr)), 6930 .e_shnum = ARRAY_SIZE(img->shdr), 6931 .e_shstrndx = ARRAY_SIZE(img->shdr) - 1, 6932 #ifdef ELF_HOST_FLAGS 6933 .e_flags = ELF_HOST_FLAGS, 6934 #endif 6935 #ifdef ELF_OSABI 6936 .e_ident[EI_OSABI] = ELF_OSABI, 6937 #endif 6938 }, 6939 .phdr = { 6940 .p_type = PT_LOAD, 6941 .p_flags = PF_X, 6942 }, 6943 .shdr = { 6944 [0] = { .sh_type = SHT_NULL }, 6945 /* Trick: The contents of code_gen_buffer are not present in 6946 this fake ELF file; that got allocated elsewhere. Therefore 6947 we mark .text as SHT_NOBITS (similar to .bss) so that readers 6948 will not look for contents. We can record any address. */ 6949 [1] = { /* .text */ 6950 .sh_type = SHT_NOBITS, 6951 .sh_flags = SHF_EXECINSTR | SHF_ALLOC, 6952 }, 6953 [2] = { /* .debug_info */ 6954 .sh_type = SHT_PROGBITS, 6955 .sh_offset = offsetof(struct ElfImage, di), 6956 .sh_size = sizeof(struct DebugInfo), 6957 }, 6958 [3] = { /* .debug_abbrev */ 6959 .sh_type = SHT_PROGBITS, 6960 .sh_offset = offsetof(struct ElfImage, da), 6961 .sh_size = sizeof(img->da), 6962 }, 6963 [4] = { /* .debug_frame */ 6964 .sh_type = SHT_PROGBITS, 6965 .sh_offset = sizeof(struct ElfImage), 6966 }, 6967 [5] = { /* .symtab */ 6968 .sh_type = SHT_SYMTAB, 6969 .sh_offset = offsetof(struct ElfImage, sym), 6970 .sh_size = sizeof(img->sym), 6971 .sh_info = 1, 6972 .sh_link = ARRAY_SIZE(img->shdr) - 1, 6973 .sh_entsize = sizeof(ElfW(Sym)), 6974 }, 6975 [6] = { /* .strtab */ 6976 .sh_type = SHT_STRTAB, 6977 .sh_offset = offsetof(struct ElfImage, str), 6978 .sh_size = sizeof(img->str), 6979 } 6980 }, 6981 .sym = { 6982 [1] = { /* code_gen_buffer */ 6983 .st_info = ELF_ST_INFO(STB_GLOBAL, STT_FUNC), 6984 .st_shndx = 1, 6985 } 6986 }, 6987 .di = { 6988 .len = sizeof(struct DebugInfo) - 4, 6989 .version = 2, 6990 .ptr_size = sizeof(void *), 6991 .cu_die = 1, 6992 .cu_lang = 0x8001, /* DW_LANG_Mips_Assembler */ 6993 .fn_die = 2, 6994 .fn_name = "code_gen_buffer" 6995 }, 6996 .da = { 6997 1, /* abbrev number (the cu) */ 6998 0x11, 1, /* DW_TAG_compile_unit, has children */ 6999 0x13, 0x5, /* DW_AT_language, DW_FORM_data2 */ 7000 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */ 7001 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */ 7002 0, 0, /* end of abbrev */ 7003 2, /* abbrev number (the fn) */ 7004 0x2e, 0, /* DW_TAG_subprogram, no children */ 7005 0x3, 0x8, /* DW_AT_name, DW_FORM_string */ 7006 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */ 7007 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */ 7008 0, 0, /* end of abbrev */ 7009 0 /* no more abbrev */ 7010 }, 7011 .str = "\0" ".text\0" ".debug_info\0" ".debug_abbrev\0" 7012 ".debug_frame\0" ".symtab\0" ".strtab\0" "code_gen_buffer", 7013 }; 7014 7015 /* We only need a single jit entry; statically allocate it. */ 7016 static struct jit_code_entry one_entry; 7017 7018 uintptr_t buf = (uintptr_t)buf_ptr; 7019 size_t img_size = sizeof(struct ElfImage) + debug_frame_size; 7020 DebugFrameHeader *dfh; 7021 7022 img = g_malloc(img_size); 7023 *img = img_template; 7024 7025 img->phdr.p_vaddr = buf; 7026 img->phdr.p_paddr = buf; 7027 img->phdr.p_memsz = buf_size; 7028 7029 img->shdr[1].sh_name = find_string(img->str, ".text"); 7030 img->shdr[1].sh_addr = buf; 7031 img->shdr[1].sh_size = buf_size; 7032 7033 img->shdr[2].sh_name = find_string(img->str, ".debug_info"); 7034 img->shdr[3].sh_name = find_string(img->str, ".debug_abbrev"); 7035 7036 img->shdr[4].sh_name = find_string(img->str, ".debug_frame"); 7037 img->shdr[4].sh_size = debug_frame_size; 7038 7039 img->shdr[5].sh_name = find_string(img->str, ".symtab"); 7040 img->shdr[6].sh_name = find_string(img->str, ".strtab"); 7041 7042 img->sym[1].st_name = find_string(img->str, "code_gen_buffer"); 7043 img->sym[1].st_value = buf; 7044 img->sym[1].st_size = buf_size; 7045 7046 img->di.cu_low_pc = buf; 7047 img->di.cu_high_pc = buf + buf_size; 7048 img->di.fn_low_pc = buf; 7049 img->di.fn_high_pc = buf + buf_size; 7050 7051 dfh = (DebugFrameHeader *)(img + 1); 7052 memcpy(dfh, debug_frame, debug_frame_size); 7053 dfh->fde.func_start = buf; 7054 dfh->fde.func_len = buf_size; 7055 7056 #ifdef DEBUG_JIT 7057 /* Enable this block to be able to debug the ELF image file creation. 7058 One can use readelf, objdump, or other inspection utilities. */ 7059 { 7060 g_autofree char *jit = g_strdup_printf("%s/qemu.jit", g_get_tmp_dir()); 7061 FILE *f = fopen(jit, "w+b"); 7062 if (f) { 7063 if (fwrite(img, img_size, 1, f) != img_size) { 7064 /* Avoid stupid unused return value warning for fwrite. */ 7065 } 7066 fclose(f); 7067 } 7068 } 7069 #endif 7070 7071 one_entry.symfile_addr = img; 7072 one_entry.symfile_size = img_size; 7073 7074 __jit_debug_descriptor.action_flag = JIT_REGISTER_FN; 7075 __jit_debug_descriptor.relevant_entry = &one_entry; 7076 __jit_debug_descriptor.first_entry = &one_entry; 7077 __jit_debug_register_code(); 7078 } 7079 #else 7080 /* No support for the feature. Provide the entry point expected by exec.c, 7081 and implement the internal function we declared earlier. */ 7082 7083 static void tcg_register_jit_int(const void *buf, size_t size, 7084 const void *debug_frame, 7085 size_t debug_frame_size) 7086 { 7087 } 7088 7089 void tcg_register_jit(const void *buf, size_t buf_size) 7090 { 7091 } 7092 #endif /* ELF_HOST_MACHINE */ 7093 7094 #if !TCG_TARGET_MAYBE_vec 7095 void tcg_expand_vec_op(TCGOpcode o, TCGType t, unsigned e, TCGArg a0, ...) 7096 { 7097 g_assert_not_reached(); 7098 } 7099 #endif 7100