1 /* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 /* define it to use liveness analysis (better code) */ 26 #define USE_TCG_OPTIMIZATIONS 27 28 #include "qemu/osdep.h" 29 30 /* Define to jump the ELF file used to communicate with GDB. */ 31 #undef DEBUG_JIT 32 33 #include "qemu/cutils.h" 34 #include "qemu/host-utils.h" 35 #include "qemu/timer.h" 36 37 /* Note: the long term plan is to reduce the dependencies on the QEMU 38 CPU definitions. Currently they are used for qemu_ld/st 39 instructions */ 40 #define NO_CPU_IO_DEFS 41 #include "cpu.h" 42 43 #include "exec/cpu-common.h" 44 #include "exec/exec-all.h" 45 46 #include "tcg-op.h" 47 48 #if UINTPTR_MAX == UINT32_MAX 49 # define ELF_CLASS ELFCLASS32 50 #else 51 # define ELF_CLASS ELFCLASS64 52 #endif 53 #ifdef HOST_WORDS_BIGENDIAN 54 # define ELF_DATA ELFDATA2MSB 55 #else 56 # define ELF_DATA ELFDATA2LSB 57 #endif 58 59 #include "elf.h" 60 #include "exec/log.h" 61 #include "sysemu/sysemu.h" 62 63 /* Forward declarations for functions declared in tcg-target.inc.c and 64 used here. */ 65 static void tcg_target_init(TCGContext *s); 66 static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode); 67 static void tcg_target_qemu_prologue(TCGContext *s); 68 static void patch_reloc(tcg_insn_unit *code_ptr, int type, 69 intptr_t value, intptr_t addend); 70 71 /* The CIE and FDE header definitions will be common to all hosts. */ 72 typedef struct { 73 uint32_t len __attribute__((aligned((sizeof(void *))))); 74 uint32_t id; 75 uint8_t version; 76 char augmentation[1]; 77 uint8_t code_align; 78 uint8_t data_align; 79 uint8_t return_column; 80 } DebugFrameCIE; 81 82 typedef struct QEMU_PACKED { 83 uint32_t len __attribute__((aligned((sizeof(void *))))); 84 uint32_t cie_offset; 85 uintptr_t func_start; 86 uintptr_t func_len; 87 } DebugFrameFDEHeader; 88 89 typedef struct QEMU_PACKED { 90 DebugFrameCIE cie; 91 DebugFrameFDEHeader fde; 92 } DebugFrameHeader; 93 94 static void tcg_register_jit_int(void *buf, size_t size, 95 const void *debug_frame, 96 size_t debug_frame_size) 97 __attribute__((unused)); 98 99 /* Forward declarations for functions declared and used in tcg-target.inc.c. */ 100 static const char *target_parse_constraint(TCGArgConstraint *ct, 101 const char *ct_str, TCGType type); 102 static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1, 103 intptr_t arg2); 104 static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg); 105 static void tcg_out_movi(TCGContext *s, TCGType type, 106 TCGReg ret, tcg_target_long arg); 107 static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, 108 const int *const_args); 109 #if TCG_TARGET_MAYBE_vec 110 static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, 111 unsigned vece, const TCGArg *args, 112 const int *const_args); 113 #else 114 static inline void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, 115 unsigned vece, const TCGArg *args, 116 const int *const_args) 117 { 118 g_assert_not_reached(); 119 } 120 #endif 121 static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1, 122 intptr_t arg2); 123 static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 124 TCGReg base, intptr_t ofs); 125 static void tcg_out_call(TCGContext *s, tcg_insn_unit *target); 126 static int tcg_target_const_match(tcg_target_long val, TCGType type, 127 const TCGArgConstraint *arg_ct); 128 #ifdef TCG_TARGET_NEED_LDST_LABELS 129 static bool tcg_out_ldst_finalize(TCGContext *s); 130 #endif 131 132 #define TCG_HIGHWATER 1024 133 134 static TCGContext **tcg_ctxs; 135 static unsigned int n_tcg_ctxs; 136 TCGv_env cpu_env = 0; 137 138 /* 139 * We divide code_gen_buffer into equally-sized "regions" that TCG threads 140 * dynamically allocate from as demand dictates. Given appropriate region 141 * sizing, this minimizes flushes even when some TCG threads generate a lot 142 * more code than others. 143 */ 144 struct tcg_region_state { 145 QemuMutex lock; 146 147 /* fields set at init time */ 148 void *start; 149 void *start_aligned; 150 void *end; 151 size_t n; 152 size_t size; /* size of one region */ 153 size_t stride; /* .size + guard size */ 154 155 /* fields protected by the lock */ 156 size_t current; /* current region index */ 157 size_t agg_size_full; /* aggregate size of full regions */ 158 }; 159 160 static struct tcg_region_state region; 161 static TCGRegSet tcg_target_available_regs[TCG_TYPE_COUNT]; 162 static TCGRegSet tcg_target_call_clobber_regs; 163 164 #if TCG_TARGET_INSN_UNIT_SIZE == 1 165 static __attribute__((unused)) inline void tcg_out8(TCGContext *s, uint8_t v) 166 { 167 *s->code_ptr++ = v; 168 } 169 170 static __attribute__((unused)) inline void tcg_patch8(tcg_insn_unit *p, 171 uint8_t v) 172 { 173 *p = v; 174 } 175 #endif 176 177 #if TCG_TARGET_INSN_UNIT_SIZE <= 2 178 static __attribute__((unused)) inline void tcg_out16(TCGContext *s, uint16_t v) 179 { 180 if (TCG_TARGET_INSN_UNIT_SIZE == 2) { 181 *s->code_ptr++ = v; 182 } else { 183 tcg_insn_unit *p = s->code_ptr; 184 memcpy(p, &v, sizeof(v)); 185 s->code_ptr = p + (2 / TCG_TARGET_INSN_UNIT_SIZE); 186 } 187 } 188 189 static __attribute__((unused)) inline void tcg_patch16(tcg_insn_unit *p, 190 uint16_t v) 191 { 192 if (TCG_TARGET_INSN_UNIT_SIZE == 2) { 193 *p = v; 194 } else { 195 memcpy(p, &v, sizeof(v)); 196 } 197 } 198 #endif 199 200 #if TCG_TARGET_INSN_UNIT_SIZE <= 4 201 static __attribute__((unused)) inline void tcg_out32(TCGContext *s, uint32_t v) 202 { 203 if (TCG_TARGET_INSN_UNIT_SIZE == 4) { 204 *s->code_ptr++ = v; 205 } else { 206 tcg_insn_unit *p = s->code_ptr; 207 memcpy(p, &v, sizeof(v)); 208 s->code_ptr = p + (4 / TCG_TARGET_INSN_UNIT_SIZE); 209 } 210 } 211 212 static __attribute__((unused)) inline void tcg_patch32(tcg_insn_unit *p, 213 uint32_t v) 214 { 215 if (TCG_TARGET_INSN_UNIT_SIZE == 4) { 216 *p = v; 217 } else { 218 memcpy(p, &v, sizeof(v)); 219 } 220 } 221 #endif 222 223 #if TCG_TARGET_INSN_UNIT_SIZE <= 8 224 static __attribute__((unused)) inline void tcg_out64(TCGContext *s, uint64_t v) 225 { 226 if (TCG_TARGET_INSN_UNIT_SIZE == 8) { 227 *s->code_ptr++ = v; 228 } else { 229 tcg_insn_unit *p = s->code_ptr; 230 memcpy(p, &v, sizeof(v)); 231 s->code_ptr = p + (8 / TCG_TARGET_INSN_UNIT_SIZE); 232 } 233 } 234 235 static __attribute__((unused)) inline void tcg_patch64(tcg_insn_unit *p, 236 uint64_t v) 237 { 238 if (TCG_TARGET_INSN_UNIT_SIZE == 8) { 239 *p = v; 240 } else { 241 memcpy(p, &v, sizeof(v)); 242 } 243 } 244 #endif 245 246 /* label relocation processing */ 247 248 static void tcg_out_reloc(TCGContext *s, tcg_insn_unit *code_ptr, int type, 249 TCGLabel *l, intptr_t addend) 250 { 251 TCGRelocation *r; 252 253 if (l->has_value) { 254 /* FIXME: This may break relocations on RISC targets that 255 modify instruction fields in place. The caller may not have 256 written the initial value. */ 257 patch_reloc(code_ptr, type, l->u.value, addend); 258 } else { 259 /* add a new relocation entry */ 260 r = tcg_malloc(sizeof(TCGRelocation)); 261 r->type = type; 262 r->ptr = code_ptr; 263 r->addend = addend; 264 r->next = l->u.first_reloc; 265 l->u.first_reloc = r; 266 } 267 } 268 269 static void tcg_out_label(TCGContext *s, TCGLabel *l, tcg_insn_unit *ptr) 270 { 271 intptr_t value = (intptr_t)ptr; 272 TCGRelocation *r; 273 274 tcg_debug_assert(!l->has_value); 275 276 for (r = l->u.first_reloc; r != NULL; r = r->next) { 277 patch_reloc(r->ptr, r->type, value, r->addend); 278 } 279 280 l->has_value = 1; 281 l->u.value_ptr = ptr; 282 } 283 284 TCGLabel *gen_new_label(void) 285 { 286 TCGContext *s = tcg_ctx; 287 TCGLabel *l = tcg_malloc(sizeof(TCGLabel)); 288 289 *l = (TCGLabel){ 290 .id = s->nb_labels++ 291 }; 292 293 return l; 294 } 295 296 #include "tcg-target.inc.c" 297 298 static void tcg_region_bounds(size_t curr_region, void **pstart, void **pend) 299 { 300 void *start, *end; 301 302 start = region.start_aligned + curr_region * region.stride; 303 end = start + region.size; 304 305 if (curr_region == 0) { 306 start = region.start; 307 } 308 if (curr_region == region.n - 1) { 309 end = region.end; 310 } 311 312 *pstart = start; 313 *pend = end; 314 } 315 316 static void tcg_region_assign(TCGContext *s, size_t curr_region) 317 { 318 void *start, *end; 319 320 tcg_region_bounds(curr_region, &start, &end); 321 322 s->code_gen_buffer = start; 323 s->code_gen_ptr = start; 324 s->code_gen_buffer_size = end - start; 325 s->code_gen_highwater = end - TCG_HIGHWATER; 326 } 327 328 static bool tcg_region_alloc__locked(TCGContext *s) 329 { 330 if (region.current == region.n) { 331 return true; 332 } 333 tcg_region_assign(s, region.current); 334 region.current++; 335 return false; 336 } 337 338 /* 339 * Request a new region once the one in use has filled up. 340 * Returns true on error. 341 */ 342 static bool tcg_region_alloc(TCGContext *s) 343 { 344 bool err; 345 /* read the region size now; alloc__locked will overwrite it on success */ 346 size_t size_full = s->code_gen_buffer_size; 347 348 qemu_mutex_lock(®ion.lock); 349 err = tcg_region_alloc__locked(s); 350 if (!err) { 351 region.agg_size_full += size_full - TCG_HIGHWATER; 352 } 353 qemu_mutex_unlock(®ion.lock); 354 return err; 355 } 356 357 /* 358 * Perform a context's first region allocation. 359 * This function does _not_ increment region.agg_size_full. 360 */ 361 static inline bool tcg_region_initial_alloc__locked(TCGContext *s) 362 { 363 return tcg_region_alloc__locked(s); 364 } 365 366 /* Call from a safe-work context */ 367 void tcg_region_reset_all(void) 368 { 369 unsigned int n_ctxs = atomic_read(&n_tcg_ctxs); 370 unsigned int i; 371 372 qemu_mutex_lock(®ion.lock); 373 region.current = 0; 374 region.agg_size_full = 0; 375 376 for (i = 0; i < n_ctxs; i++) { 377 TCGContext *s = atomic_read(&tcg_ctxs[i]); 378 bool err = tcg_region_initial_alloc__locked(s); 379 380 g_assert(!err); 381 } 382 qemu_mutex_unlock(®ion.lock); 383 } 384 385 #ifdef CONFIG_USER_ONLY 386 static size_t tcg_n_regions(void) 387 { 388 return 1; 389 } 390 #else 391 /* 392 * It is likely that some vCPUs will translate more code than others, so we 393 * first try to set more regions than max_cpus, with those regions being of 394 * reasonable size. If that's not possible we make do by evenly dividing 395 * the code_gen_buffer among the vCPUs. 396 */ 397 static size_t tcg_n_regions(void) 398 { 399 size_t i; 400 401 /* Use a single region if all we have is one vCPU thread */ 402 if (max_cpus == 1 || !qemu_tcg_mttcg_enabled()) { 403 return 1; 404 } 405 406 /* Try to have more regions than max_cpus, with each region being >= 2 MB */ 407 for (i = 8; i > 0; i--) { 408 size_t regions_per_thread = i; 409 size_t region_size; 410 411 region_size = tcg_init_ctx.code_gen_buffer_size; 412 region_size /= max_cpus * regions_per_thread; 413 414 if (region_size >= 2 * 1024u * 1024) { 415 return max_cpus * regions_per_thread; 416 } 417 } 418 /* If we can't, then just allocate one region per vCPU thread */ 419 return max_cpus; 420 } 421 #endif 422 423 /* 424 * Initializes region partitioning. 425 * 426 * Called at init time from the parent thread (i.e. the one calling 427 * tcg_context_init), after the target's TCG globals have been set. 428 * 429 * Region partitioning works by splitting code_gen_buffer into separate regions, 430 * and then assigning regions to TCG threads so that the threads can translate 431 * code in parallel without synchronization. 432 * 433 * In softmmu the number of TCG threads is bounded by max_cpus, so we use at 434 * least max_cpus regions in MTTCG. In !MTTCG we use a single region. 435 * Note that the TCG options from the command-line (i.e. -accel accel=tcg,[...]) 436 * must have been parsed before calling this function, since it calls 437 * qemu_tcg_mttcg_enabled(). 438 * 439 * In user-mode we use a single region. Having multiple regions in user-mode 440 * is not supported, because the number of vCPU threads (recall that each thread 441 * spawned by the guest corresponds to a vCPU thread) is only bounded by the 442 * OS, and usually this number is huge (tens of thousands is not uncommon). 443 * Thus, given this large bound on the number of vCPU threads and the fact 444 * that code_gen_buffer is allocated at compile-time, we cannot guarantee 445 * that the availability of at least one region per vCPU thread. 446 * 447 * However, this user-mode limitation is unlikely to be a significant problem 448 * in practice. Multi-threaded guests share most if not all of their translated 449 * code, which makes parallel code generation less appealing than in softmmu. 450 */ 451 void tcg_region_init(void) 452 { 453 void *buf = tcg_init_ctx.code_gen_buffer; 454 void *aligned; 455 size_t size = tcg_init_ctx.code_gen_buffer_size; 456 size_t page_size = qemu_real_host_page_size; 457 size_t region_size; 458 size_t n_regions; 459 size_t i; 460 461 n_regions = tcg_n_regions(); 462 463 /* The first region will be 'aligned - buf' bytes larger than the others */ 464 aligned = QEMU_ALIGN_PTR_UP(buf, page_size); 465 g_assert(aligned < tcg_init_ctx.code_gen_buffer + size); 466 /* 467 * Make region_size a multiple of page_size, using aligned as the start. 468 * As a result of this we might end up with a few extra pages at the end of 469 * the buffer; we will assign those to the last region. 470 */ 471 region_size = (size - (aligned - buf)) / n_regions; 472 region_size = QEMU_ALIGN_DOWN(region_size, page_size); 473 474 /* A region must have at least 2 pages; one code, one guard */ 475 g_assert(region_size >= 2 * page_size); 476 477 /* init the region struct */ 478 qemu_mutex_init(®ion.lock); 479 region.n = n_regions; 480 region.size = region_size - page_size; 481 region.stride = region_size; 482 region.start = buf; 483 region.start_aligned = aligned; 484 /* page-align the end, since its last page will be a guard page */ 485 region.end = QEMU_ALIGN_PTR_DOWN(buf + size, page_size); 486 /* account for that last guard page */ 487 region.end -= page_size; 488 489 /* set guard pages */ 490 for (i = 0; i < region.n; i++) { 491 void *start, *end; 492 int rc; 493 494 tcg_region_bounds(i, &start, &end); 495 rc = qemu_mprotect_none(end, page_size); 496 g_assert(!rc); 497 } 498 499 /* In user-mode we support only one ctx, so do the initial allocation now */ 500 #ifdef CONFIG_USER_ONLY 501 { 502 bool err = tcg_region_initial_alloc__locked(tcg_ctx); 503 504 g_assert(!err); 505 } 506 #endif 507 } 508 509 /* 510 * All TCG threads except the parent (i.e. the one that called tcg_context_init 511 * and registered the target's TCG globals) must register with this function 512 * before initiating translation. 513 * 514 * In user-mode we just point tcg_ctx to tcg_init_ctx. See the documentation 515 * of tcg_region_init() for the reasoning behind this. 516 * 517 * In softmmu each caller registers its context in tcg_ctxs[]. Note that in 518 * softmmu tcg_ctxs[] does not track tcg_ctx_init, since the initial context 519 * is not used anymore for translation once this function is called. 520 * 521 * Not tracking tcg_init_ctx in tcg_ctxs[] in softmmu keeps code that iterates 522 * over the array (e.g. tcg_code_size() the same for both softmmu and user-mode. 523 */ 524 #ifdef CONFIG_USER_ONLY 525 void tcg_register_thread(void) 526 { 527 tcg_ctx = &tcg_init_ctx; 528 } 529 #else 530 void tcg_register_thread(void) 531 { 532 TCGContext *s = g_malloc(sizeof(*s)); 533 unsigned int i, n; 534 bool err; 535 536 *s = tcg_init_ctx; 537 538 /* Relink mem_base. */ 539 for (i = 0, n = tcg_init_ctx.nb_globals; i < n; ++i) { 540 if (tcg_init_ctx.temps[i].mem_base) { 541 ptrdiff_t b = tcg_init_ctx.temps[i].mem_base - tcg_init_ctx.temps; 542 tcg_debug_assert(b >= 0 && b < n); 543 s->temps[i].mem_base = &s->temps[b]; 544 } 545 } 546 547 /* Claim an entry in tcg_ctxs */ 548 n = atomic_fetch_inc(&n_tcg_ctxs); 549 g_assert(n < max_cpus); 550 atomic_set(&tcg_ctxs[n], s); 551 552 tcg_ctx = s; 553 qemu_mutex_lock(®ion.lock); 554 err = tcg_region_initial_alloc__locked(tcg_ctx); 555 g_assert(!err); 556 qemu_mutex_unlock(®ion.lock); 557 } 558 #endif /* !CONFIG_USER_ONLY */ 559 560 /* 561 * Returns the size (in bytes) of all translated code (i.e. from all regions) 562 * currently in the cache. 563 * See also: tcg_code_capacity() 564 * Do not confuse with tcg_current_code_size(); that one applies to a single 565 * TCG context. 566 */ 567 size_t tcg_code_size(void) 568 { 569 unsigned int n_ctxs = atomic_read(&n_tcg_ctxs); 570 unsigned int i; 571 size_t total; 572 573 qemu_mutex_lock(®ion.lock); 574 total = region.agg_size_full; 575 for (i = 0; i < n_ctxs; i++) { 576 const TCGContext *s = atomic_read(&tcg_ctxs[i]); 577 size_t size; 578 579 size = atomic_read(&s->code_gen_ptr) - s->code_gen_buffer; 580 g_assert(size <= s->code_gen_buffer_size); 581 total += size; 582 } 583 qemu_mutex_unlock(®ion.lock); 584 return total; 585 } 586 587 /* 588 * Returns the code capacity (in bytes) of the entire cache, i.e. including all 589 * regions. 590 * See also: tcg_code_size() 591 */ 592 size_t tcg_code_capacity(void) 593 { 594 size_t guard_size, capacity; 595 596 /* no need for synchronization; these variables are set at init time */ 597 guard_size = region.stride - region.size; 598 capacity = region.end + guard_size - region.start; 599 capacity -= region.n * (guard_size + TCG_HIGHWATER); 600 return capacity; 601 } 602 603 /* pool based memory allocation */ 604 void *tcg_malloc_internal(TCGContext *s, int size) 605 { 606 TCGPool *p; 607 int pool_size; 608 609 if (size > TCG_POOL_CHUNK_SIZE) { 610 /* big malloc: insert a new pool (XXX: could optimize) */ 611 p = g_malloc(sizeof(TCGPool) + size); 612 p->size = size; 613 p->next = s->pool_first_large; 614 s->pool_first_large = p; 615 return p->data; 616 } else { 617 p = s->pool_current; 618 if (!p) { 619 p = s->pool_first; 620 if (!p) 621 goto new_pool; 622 } else { 623 if (!p->next) { 624 new_pool: 625 pool_size = TCG_POOL_CHUNK_SIZE; 626 p = g_malloc(sizeof(TCGPool) + pool_size); 627 p->size = pool_size; 628 p->next = NULL; 629 if (s->pool_current) 630 s->pool_current->next = p; 631 else 632 s->pool_first = p; 633 } else { 634 p = p->next; 635 } 636 } 637 } 638 s->pool_current = p; 639 s->pool_cur = p->data + size; 640 s->pool_end = p->data + p->size; 641 return p->data; 642 } 643 644 void tcg_pool_reset(TCGContext *s) 645 { 646 TCGPool *p, *t; 647 for (p = s->pool_first_large; p; p = t) { 648 t = p->next; 649 g_free(p); 650 } 651 s->pool_first_large = NULL; 652 s->pool_cur = s->pool_end = NULL; 653 s->pool_current = NULL; 654 } 655 656 typedef struct TCGHelperInfo { 657 void *func; 658 const char *name; 659 unsigned flags; 660 unsigned sizemask; 661 } TCGHelperInfo; 662 663 #include "exec/helper-proto.h" 664 665 static const TCGHelperInfo all_helpers[] = { 666 #include "exec/helper-tcg.h" 667 }; 668 static GHashTable *helper_table; 669 670 static int indirect_reg_alloc_order[ARRAY_SIZE(tcg_target_reg_alloc_order)]; 671 static void process_op_defs(TCGContext *s); 672 static TCGTemp *tcg_global_reg_new_internal(TCGContext *s, TCGType type, 673 TCGReg reg, const char *name); 674 675 void tcg_context_init(TCGContext *s) 676 { 677 int op, total_args, n, i; 678 TCGOpDef *def; 679 TCGArgConstraint *args_ct; 680 int *sorted_args; 681 TCGTemp *ts; 682 683 memset(s, 0, sizeof(*s)); 684 s->nb_globals = 0; 685 686 /* Count total number of arguments and allocate the corresponding 687 space */ 688 total_args = 0; 689 for(op = 0; op < NB_OPS; op++) { 690 def = &tcg_op_defs[op]; 691 n = def->nb_iargs + def->nb_oargs; 692 total_args += n; 693 } 694 695 args_ct = g_malloc(sizeof(TCGArgConstraint) * total_args); 696 sorted_args = g_malloc(sizeof(int) * total_args); 697 698 for(op = 0; op < NB_OPS; op++) { 699 def = &tcg_op_defs[op]; 700 def->args_ct = args_ct; 701 def->sorted_args = sorted_args; 702 n = def->nb_iargs + def->nb_oargs; 703 sorted_args += n; 704 args_ct += n; 705 } 706 707 /* Register helpers. */ 708 /* Use g_direct_hash/equal for direct pointer comparisons on func. */ 709 helper_table = g_hash_table_new(NULL, NULL); 710 711 for (i = 0; i < ARRAY_SIZE(all_helpers); ++i) { 712 g_hash_table_insert(helper_table, (gpointer)all_helpers[i].func, 713 (gpointer)&all_helpers[i]); 714 } 715 716 tcg_target_init(s); 717 process_op_defs(s); 718 719 /* Reverse the order of the saved registers, assuming they're all at 720 the start of tcg_target_reg_alloc_order. */ 721 for (n = 0; n < ARRAY_SIZE(tcg_target_reg_alloc_order); ++n) { 722 int r = tcg_target_reg_alloc_order[n]; 723 if (tcg_regset_test_reg(tcg_target_call_clobber_regs, r)) { 724 break; 725 } 726 } 727 for (i = 0; i < n; ++i) { 728 indirect_reg_alloc_order[i] = tcg_target_reg_alloc_order[n - 1 - i]; 729 } 730 for (; i < ARRAY_SIZE(tcg_target_reg_alloc_order); ++i) { 731 indirect_reg_alloc_order[i] = tcg_target_reg_alloc_order[i]; 732 } 733 734 tcg_ctx = s; 735 /* 736 * In user-mode we simply share the init context among threads, since we 737 * use a single region. See the documentation tcg_region_init() for the 738 * reasoning behind this. 739 * In softmmu we will have at most max_cpus TCG threads. 740 */ 741 #ifdef CONFIG_USER_ONLY 742 tcg_ctxs = &tcg_ctx; 743 n_tcg_ctxs = 1; 744 #else 745 tcg_ctxs = g_new(TCGContext *, max_cpus); 746 #endif 747 748 tcg_debug_assert(!tcg_regset_test_reg(s->reserved_regs, TCG_AREG0)); 749 ts = tcg_global_reg_new_internal(s, TCG_TYPE_PTR, TCG_AREG0, "env"); 750 cpu_env = temp_tcgv_ptr(ts); 751 } 752 753 /* 754 * Allocate TBs right before their corresponding translated code, making 755 * sure that TBs and code are on different cache lines. 756 */ 757 TranslationBlock *tcg_tb_alloc(TCGContext *s) 758 { 759 uintptr_t align = qemu_icache_linesize; 760 TranslationBlock *tb; 761 void *next; 762 763 retry: 764 tb = (void *)ROUND_UP((uintptr_t)s->code_gen_ptr, align); 765 next = (void *)ROUND_UP((uintptr_t)(tb + 1), align); 766 767 if (unlikely(next > s->code_gen_highwater)) { 768 if (tcg_region_alloc(s)) { 769 return NULL; 770 } 771 goto retry; 772 } 773 atomic_set(&s->code_gen_ptr, next); 774 s->data_gen_ptr = NULL; 775 return tb; 776 } 777 778 void tcg_prologue_init(TCGContext *s) 779 { 780 size_t prologue_size, total_size; 781 void *buf0, *buf1; 782 783 /* Put the prologue at the beginning of code_gen_buffer. */ 784 buf0 = s->code_gen_buffer; 785 total_size = s->code_gen_buffer_size; 786 s->code_ptr = buf0; 787 s->code_buf = buf0; 788 s->data_gen_ptr = NULL; 789 s->code_gen_prologue = buf0; 790 791 /* Compute a high-water mark, at which we voluntarily flush the buffer 792 and start over. The size here is arbitrary, significantly larger 793 than we expect the code generation for any one opcode to require. */ 794 s->code_gen_highwater = s->code_gen_buffer + (total_size - TCG_HIGHWATER); 795 796 #ifdef TCG_TARGET_NEED_POOL_LABELS 797 s->pool_labels = NULL; 798 #endif 799 800 /* Generate the prologue. */ 801 tcg_target_qemu_prologue(s); 802 803 #ifdef TCG_TARGET_NEED_POOL_LABELS 804 /* Allow the prologue to put e.g. guest_base into a pool entry. */ 805 { 806 bool ok = tcg_out_pool_finalize(s); 807 tcg_debug_assert(ok); 808 } 809 #endif 810 811 buf1 = s->code_ptr; 812 flush_icache_range((uintptr_t)buf0, (uintptr_t)buf1); 813 814 /* Deduct the prologue from the buffer. */ 815 prologue_size = tcg_current_code_size(s); 816 s->code_gen_ptr = buf1; 817 s->code_gen_buffer = buf1; 818 s->code_buf = buf1; 819 total_size -= prologue_size; 820 s->code_gen_buffer_size = total_size; 821 822 tcg_register_jit(s->code_gen_buffer, total_size); 823 824 #ifdef DEBUG_DISAS 825 if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM)) { 826 qemu_log_lock(); 827 qemu_log("PROLOGUE: [size=%zu]\n", prologue_size); 828 if (s->data_gen_ptr) { 829 size_t code_size = s->data_gen_ptr - buf0; 830 size_t data_size = prologue_size - code_size; 831 size_t i; 832 833 log_disas(buf0, code_size); 834 835 for (i = 0; i < data_size; i += sizeof(tcg_target_ulong)) { 836 if (sizeof(tcg_target_ulong) == 8) { 837 qemu_log("0x%08" PRIxPTR ": .quad 0x%016" PRIx64 "\n", 838 (uintptr_t)s->data_gen_ptr + i, 839 *(uint64_t *)(s->data_gen_ptr + i)); 840 } else { 841 qemu_log("0x%08" PRIxPTR ": .long 0x%08x\n", 842 (uintptr_t)s->data_gen_ptr + i, 843 *(uint32_t *)(s->data_gen_ptr + i)); 844 } 845 } 846 } else { 847 log_disas(buf0, prologue_size); 848 } 849 qemu_log("\n"); 850 qemu_log_flush(); 851 qemu_log_unlock(); 852 } 853 #endif 854 855 /* Assert that goto_ptr is implemented completely. */ 856 if (TCG_TARGET_HAS_goto_ptr) { 857 tcg_debug_assert(s->code_gen_epilogue != NULL); 858 } 859 } 860 861 void tcg_func_start(TCGContext *s) 862 { 863 tcg_pool_reset(s); 864 s->nb_temps = s->nb_globals; 865 866 /* No temps have been previously allocated for size or locality. */ 867 memset(s->free_temps, 0, sizeof(s->free_temps)); 868 869 s->nb_labels = 0; 870 s->current_frame_offset = s->frame_start; 871 872 #ifdef CONFIG_DEBUG_TCG 873 s->goto_tb_issue_mask = 0; 874 #endif 875 876 QTAILQ_INIT(&s->ops); 877 QTAILQ_INIT(&s->free_ops); 878 } 879 880 static inline TCGTemp *tcg_temp_alloc(TCGContext *s) 881 { 882 int n = s->nb_temps++; 883 tcg_debug_assert(n < TCG_MAX_TEMPS); 884 return memset(&s->temps[n], 0, sizeof(TCGTemp)); 885 } 886 887 static inline TCGTemp *tcg_global_alloc(TCGContext *s) 888 { 889 TCGTemp *ts; 890 891 tcg_debug_assert(s->nb_globals == s->nb_temps); 892 s->nb_globals++; 893 ts = tcg_temp_alloc(s); 894 ts->temp_global = 1; 895 896 return ts; 897 } 898 899 static TCGTemp *tcg_global_reg_new_internal(TCGContext *s, TCGType type, 900 TCGReg reg, const char *name) 901 { 902 TCGTemp *ts; 903 904 if (TCG_TARGET_REG_BITS == 32 && type != TCG_TYPE_I32) { 905 tcg_abort(); 906 } 907 908 ts = tcg_global_alloc(s); 909 ts->base_type = type; 910 ts->type = type; 911 ts->fixed_reg = 1; 912 ts->reg = reg; 913 ts->name = name; 914 tcg_regset_set_reg(s->reserved_regs, reg); 915 916 return ts; 917 } 918 919 void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size) 920 { 921 s->frame_start = start; 922 s->frame_end = start + size; 923 s->frame_temp 924 = tcg_global_reg_new_internal(s, TCG_TYPE_PTR, reg, "_frame"); 925 } 926 927 TCGTemp *tcg_global_mem_new_internal(TCGType type, TCGv_ptr base, 928 intptr_t offset, const char *name) 929 { 930 TCGContext *s = tcg_ctx; 931 TCGTemp *base_ts = tcgv_ptr_temp(base); 932 TCGTemp *ts = tcg_global_alloc(s); 933 int indirect_reg = 0, bigendian = 0; 934 #ifdef HOST_WORDS_BIGENDIAN 935 bigendian = 1; 936 #endif 937 938 if (!base_ts->fixed_reg) { 939 /* We do not support double-indirect registers. */ 940 tcg_debug_assert(!base_ts->indirect_reg); 941 base_ts->indirect_base = 1; 942 s->nb_indirects += (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64 943 ? 2 : 1); 944 indirect_reg = 1; 945 } 946 947 if (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64) { 948 TCGTemp *ts2 = tcg_global_alloc(s); 949 char buf[64]; 950 951 ts->base_type = TCG_TYPE_I64; 952 ts->type = TCG_TYPE_I32; 953 ts->indirect_reg = indirect_reg; 954 ts->mem_allocated = 1; 955 ts->mem_base = base_ts; 956 ts->mem_offset = offset + bigendian * 4; 957 pstrcpy(buf, sizeof(buf), name); 958 pstrcat(buf, sizeof(buf), "_0"); 959 ts->name = strdup(buf); 960 961 tcg_debug_assert(ts2 == ts + 1); 962 ts2->base_type = TCG_TYPE_I64; 963 ts2->type = TCG_TYPE_I32; 964 ts2->indirect_reg = indirect_reg; 965 ts2->mem_allocated = 1; 966 ts2->mem_base = base_ts; 967 ts2->mem_offset = offset + (1 - bigendian) * 4; 968 pstrcpy(buf, sizeof(buf), name); 969 pstrcat(buf, sizeof(buf), "_1"); 970 ts2->name = strdup(buf); 971 } else { 972 ts->base_type = type; 973 ts->type = type; 974 ts->indirect_reg = indirect_reg; 975 ts->mem_allocated = 1; 976 ts->mem_base = base_ts; 977 ts->mem_offset = offset; 978 ts->name = name; 979 } 980 return ts; 981 } 982 983 static TCGTemp *tcg_temp_new_internal(TCGType type, int temp_local) 984 { 985 TCGContext *s = tcg_ctx; 986 TCGTemp *ts; 987 int idx, k; 988 989 k = type + (temp_local ? TCG_TYPE_COUNT : 0); 990 idx = find_first_bit(s->free_temps[k].l, TCG_MAX_TEMPS); 991 if (idx < TCG_MAX_TEMPS) { 992 /* There is already an available temp with the right type. */ 993 clear_bit(idx, s->free_temps[k].l); 994 995 ts = &s->temps[idx]; 996 ts->temp_allocated = 1; 997 tcg_debug_assert(ts->base_type == type); 998 tcg_debug_assert(ts->temp_local == temp_local); 999 } else { 1000 ts = tcg_temp_alloc(s); 1001 if (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64) { 1002 TCGTemp *ts2 = tcg_temp_alloc(s); 1003 1004 ts->base_type = type; 1005 ts->type = TCG_TYPE_I32; 1006 ts->temp_allocated = 1; 1007 ts->temp_local = temp_local; 1008 1009 tcg_debug_assert(ts2 == ts + 1); 1010 ts2->base_type = TCG_TYPE_I64; 1011 ts2->type = TCG_TYPE_I32; 1012 ts2->temp_allocated = 1; 1013 ts2->temp_local = temp_local; 1014 } else { 1015 ts->base_type = type; 1016 ts->type = type; 1017 ts->temp_allocated = 1; 1018 ts->temp_local = temp_local; 1019 } 1020 } 1021 1022 #if defined(CONFIG_DEBUG_TCG) 1023 s->temps_in_use++; 1024 #endif 1025 return ts; 1026 } 1027 1028 TCGv_i32 tcg_temp_new_internal_i32(int temp_local) 1029 { 1030 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, temp_local); 1031 return temp_tcgv_i32(t); 1032 } 1033 1034 TCGv_i64 tcg_temp_new_internal_i64(int temp_local) 1035 { 1036 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, temp_local); 1037 return temp_tcgv_i64(t); 1038 } 1039 1040 TCGv_vec tcg_temp_new_vec(TCGType type) 1041 { 1042 TCGTemp *t; 1043 1044 #ifdef CONFIG_DEBUG_TCG 1045 switch (type) { 1046 case TCG_TYPE_V64: 1047 assert(TCG_TARGET_HAS_v64); 1048 break; 1049 case TCG_TYPE_V128: 1050 assert(TCG_TARGET_HAS_v128); 1051 break; 1052 case TCG_TYPE_V256: 1053 assert(TCG_TARGET_HAS_v256); 1054 break; 1055 default: 1056 g_assert_not_reached(); 1057 } 1058 #endif 1059 1060 t = tcg_temp_new_internal(type, 0); 1061 return temp_tcgv_vec(t); 1062 } 1063 1064 /* Create a new temp of the same type as an existing temp. */ 1065 TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match) 1066 { 1067 TCGTemp *t = tcgv_vec_temp(match); 1068 1069 tcg_debug_assert(t->temp_allocated != 0); 1070 1071 t = tcg_temp_new_internal(t->base_type, 0); 1072 return temp_tcgv_vec(t); 1073 } 1074 1075 static void tcg_temp_free_internal(TCGTemp *ts) 1076 { 1077 TCGContext *s = tcg_ctx; 1078 int k, idx; 1079 1080 #if defined(CONFIG_DEBUG_TCG) 1081 s->temps_in_use--; 1082 if (s->temps_in_use < 0) { 1083 fprintf(stderr, "More temporaries freed than allocated!\n"); 1084 } 1085 #endif 1086 1087 tcg_debug_assert(ts->temp_global == 0); 1088 tcg_debug_assert(ts->temp_allocated != 0); 1089 ts->temp_allocated = 0; 1090 1091 idx = temp_idx(ts); 1092 k = ts->base_type + (ts->temp_local ? TCG_TYPE_COUNT : 0); 1093 set_bit(idx, s->free_temps[k].l); 1094 } 1095 1096 void tcg_temp_free_i32(TCGv_i32 arg) 1097 { 1098 tcg_temp_free_internal(tcgv_i32_temp(arg)); 1099 } 1100 1101 void tcg_temp_free_i64(TCGv_i64 arg) 1102 { 1103 tcg_temp_free_internal(tcgv_i64_temp(arg)); 1104 } 1105 1106 void tcg_temp_free_vec(TCGv_vec arg) 1107 { 1108 tcg_temp_free_internal(tcgv_vec_temp(arg)); 1109 } 1110 1111 TCGv_i32 tcg_const_i32(int32_t val) 1112 { 1113 TCGv_i32 t0; 1114 t0 = tcg_temp_new_i32(); 1115 tcg_gen_movi_i32(t0, val); 1116 return t0; 1117 } 1118 1119 TCGv_i64 tcg_const_i64(int64_t val) 1120 { 1121 TCGv_i64 t0; 1122 t0 = tcg_temp_new_i64(); 1123 tcg_gen_movi_i64(t0, val); 1124 return t0; 1125 } 1126 1127 TCGv_i32 tcg_const_local_i32(int32_t val) 1128 { 1129 TCGv_i32 t0; 1130 t0 = tcg_temp_local_new_i32(); 1131 tcg_gen_movi_i32(t0, val); 1132 return t0; 1133 } 1134 1135 TCGv_i64 tcg_const_local_i64(int64_t val) 1136 { 1137 TCGv_i64 t0; 1138 t0 = tcg_temp_local_new_i64(); 1139 tcg_gen_movi_i64(t0, val); 1140 return t0; 1141 } 1142 1143 #if defined(CONFIG_DEBUG_TCG) 1144 void tcg_clear_temp_count(void) 1145 { 1146 TCGContext *s = tcg_ctx; 1147 s->temps_in_use = 0; 1148 } 1149 1150 int tcg_check_temp_count(void) 1151 { 1152 TCGContext *s = tcg_ctx; 1153 if (s->temps_in_use) { 1154 /* Clear the count so that we don't give another 1155 * warning immediately next time around. 1156 */ 1157 s->temps_in_use = 0; 1158 return 1; 1159 } 1160 return 0; 1161 } 1162 #endif 1163 1164 /* Return true if OP may appear in the opcode stream. 1165 Test the runtime variable that controls each opcode. */ 1166 bool tcg_op_supported(TCGOpcode op) 1167 { 1168 const bool have_vec 1169 = TCG_TARGET_HAS_v64 | TCG_TARGET_HAS_v128 | TCG_TARGET_HAS_v256; 1170 1171 switch (op) { 1172 case INDEX_op_discard: 1173 case INDEX_op_set_label: 1174 case INDEX_op_call: 1175 case INDEX_op_br: 1176 case INDEX_op_mb: 1177 case INDEX_op_insn_start: 1178 case INDEX_op_exit_tb: 1179 case INDEX_op_goto_tb: 1180 case INDEX_op_qemu_ld_i32: 1181 case INDEX_op_qemu_st_i32: 1182 case INDEX_op_qemu_ld_i64: 1183 case INDEX_op_qemu_st_i64: 1184 return true; 1185 1186 case INDEX_op_goto_ptr: 1187 return TCG_TARGET_HAS_goto_ptr; 1188 1189 case INDEX_op_mov_i32: 1190 case INDEX_op_movi_i32: 1191 case INDEX_op_setcond_i32: 1192 case INDEX_op_brcond_i32: 1193 case INDEX_op_ld8u_i32: 1194 case INDEX_op_ld8s_i32: 1195 case INDEX_op_ld16u_i32: 1196 case INDEX_op_ld16s_i32: 1197 case INDEX_op_ld_i32: 1198 case INDEX_op_st8_i32: 1199 case INDEX_op_st16_i32: 1200 case INDEX_op_st_i32: 1201 case INDEX_op_add_i32: 1202 case INDEX_op_sub_i32: 1203 case INDEX_op_mul_i32: 1204 case INDEX_op_and_i32: 1205 case INDEX_op_or_i32: 1206 case INDEX_op_xor_i32: 1207 case INDEX_op_shl_i32: 1208 case INDEX_op_shr_i32: 1209 case INDEX_op_sar_i32: 1210 return true; 1211 1212 case INDEX_op_movcond_i32: 1213 return TCG_TARGET_HAS_movcond_i32; 1214 case INDEX_op_div_i32: 1215 case INDEX_op_divu_i32: 1216 return TCG_TARGET_HAS_div_i32; 1217 case INDEX_op_rem_i32: 1218 case INDEX_op_remu_i32: 1219 return TCG_TARGET_HAS_rem_i32; 1220 case INDEX_op_div2_i32: 1221 case INDEX_op_divu2_i32: 1222 return TCG_TARGET_HAS_div2_i32; 1223 case INDEX_op_rotl_i32: 1224 case INDEX_op_rotr_i32: 1225 return TCG_TARGET_HAS_rot_i32; 1226 case INDEX_op_deposit_i32: 1227 return TCG_TARGET_HAS_deposit_i32; 1228 case INDEX_op_extract_i32: 1229 return TCG_TARGET_HAS_extract_i32; 1230 case INDEX_op_sextract_i32: 1231 return TCG_TARGET_HAS_sextract_i32; 1232 case INDEX_op_add2_i32: 1233 return TCG_TARGET_HAS_add2_i32; 1234 case INDEX_op_sub2_i32: 1235 return TCG_TARGET_HAS_sub2_i32; 1236 case INDEX_op_mulu2_i32: 1237 return TCG_TARGET_HAS_mulu2_i32; 1238 case INDEX_op_muls2_i32: 1239 return TCG_TARGET_HAS_muls2_i32; 1240 case INDEX_op_muluh_i32: 1241 return TCG_TARGET_HAS_muluh_i32; 1242 case INDEX_op_mulsh_i32: 1243 return TCG_TARGET_HAS_mulsh_i32; 1244 case INDEX_op_ext8s_i32: 1245 return TCG_TARGET_HAS_ext8s_i32; 1246 case INDEX_op_ext16s_i32: 1247 return TCG_TARGET_HAS_ext16s_i32; 1248 case INDEX_op_ext8u_i32: 1249 return TCG_TARGET_HAS_ext8u_i32; 1250 case INDEX_op_ext16u_i32: 1251 return TCG_TARGET_HAS_ext16u_i32; 1252 case INDEX_op_bswap16_i32: 1253 return TCG_TARGET_HAS_bswap16_i32; 1254 case INDEX_op_bswap32_i32: 1255 return TCG_TARGET_HAS_bswap32_i32; 1256 case INDEX_op_not_i32: 1257 return TCG_TARGET_HAS_not_i32; 1258 case INDEX_op_neg_i32: 1259 return TCG_TARGET_HAS_neg_i32; 1260 case INDEX_op_andc_i32: 1261 return TCG_TARGET_HAS_andc_i32; 1262 case INDEX_op_orc_i32: 1263 return TCG_TARGET_HAS_orc_i32; 1264 case INDEX_op_eqv_i32: 1265 return TCG_TARGET_HAS_eqv_i32; 1266 case INDEX_op_nand_i32: 1267 return TCG_TARGET_HAS_nand_i32; 1268 case INDEX_op_nor_i32: 1269 return TCG_TARGET_HAS_nor_i32; 1270 case INDEX_op_clz_i32: 1271 return TCG_TARGET_HAS_clz_i32; 1272 case INDEX_op_ctz_i32: 1273 return TCG_TARGET_HAS_ctz_i32; 1274 case INDEX_op_ctpop_i32: 1275 return TCG_TARGET_HAS_ctpop_i32; 1276 1277 case INDEX_op_brcond2_i32: 1278 case INDEX_op_setcond2_i32: 1279 return TCG_TARGET_REG_BITS == 32; 1280 1281 case INDEX_op_mov_i64: 1282 case INDEX_op_movi_i64: 1283 case INDEX_op_setcond_i64: 1284 case INDEX_op_brcond_i64: 1285 case INDEX_op_ld8u_i64: 1286 case INDEX_op_ld8s_i64: 1287 case INDEX_op_ld16u_i64: 1288 case INDEX_op_ld16s_i64: 1289 case INDEX_op_ld32u_i64: 1290 case INDEX_op_ld32s_i64: 1291 case INDEX_op_ld_i64: 1292 case INDEX_op_st8_i64: 1293 case INDEX_op_st16_i64: 1294 case INDEX_op_st32_i64: 1295 case INDEX_op_st_i64: 1296 case INDEX_op_add_i64: 1297 case INDEX_op_sub_i64: 1298 case INDEX_op_mul_i64: 1299 case INDEX_op_and_i64: 1300 case INDEX_op_or_i64: 1301 case INDEX_op_xor_i64: 1302 case INDEX_op_shl_i64: 1303 case INDEX_op_shr_i64: 1304 case INDEX_op_sar_i64: 1305 case INDEX_op_ext_i32_i64: 1306 case INDEX_op_extu_i32_i64: 1307 return TCG_TARGET_REG_BITS == 64; 1308 1309 case INDEX_op_movcond_i64: 1310 return TCG_TARGET_HAS_movcond_i64; 1311 case INDEX_op_div_i64: 1312 case INDEX_op_divu_i64: 1313 return TCG_TARGET_HAS_div_i64; 1314 case INDEX_op_rem_i64: 1315 case INDEX_op_remu_i64: 1316 return TCG_TARGET_HAS_rem_i64; 1317 case INDEX_op_div2_i64: 1318 case INDEX_op_divu2_i64: 1319 return TCG_TARGET_HAS_div2_i64; 1320 case INDEX_op_rotl_i64: 1321 case INDEX_op_rotr_i64: 1322 return TCG_TARGET_HAS_rot_i64; 1323 case INDEX_op_deposit_i64: 1324 return TCG_TARGET_HAS_deposit_i64; 1325 case INDEX_op_extract_i64: 1326 return TCG_TARGET_HAS_extract_i64; 1327 case INDEX_op_sextract_i64: 1328 return TCG_TARGET_HAS_sextract_i64; 1329 case INDEX_op_extrl_i64_i32: 1330 return TCG_TARGET_HAS_extrl_i64_i32; 1331 case INDEX_op_extrh_i64_i32: 1332 return TCG_TARGET_HAS_extrh_i64_i32; 1333 case INDEX_op_ext8s_i64: 1334 return TCG_TARGET_HAS_ext8s_i64; 1335 case INDEX_op_ext16s_i64: 1336 return TCG_TARGET_HAS_ext16s_i64; 1337 case INDEX_op_ext32s_i64: 1338 return TCG_TARGET_HAS_ext32s_i64; 1339 case INDEX_op_ext8u_i64: 1340 return TCG_TARGET_HAS_ext8u_i64; 1341 case INDEX_op_ext16u_i64: 1342 return TCG_TARGET_HAS_ext16u_i64; 1343 case INDEX_op_ext32u_i64: 1344 return TCG_TARGET_HAS_ext32u_i64; 1345 case INDEX_op_bswap16_i64: 1346 return TCG_TARGET_HAS_bswap16_i64; 1347 case INDEX_op_bswap32_i64: 1348 return TCG_TARGET_HAS_bswap32_i64; 1349 case INDEX_op_bswap64_i64: 1350 return TCG_TARGET_HAS_bswap64_i64; 1351 case INDEX_op_not_i64: 1352 return TCG_TARGET_HAS_not_i64; 1353 case INDEX_op_neg_i64: 1354 return TCG_TARGET_HAS_neg_i64; 1355 case INDEX_op_andc_i64: 1356 return TCG_TARGET_HAS_andc_i64; 1357 case INDEX_op_orc_i64: 1358 return TCG_TARGET_HAS_orc_i64; 1359 case INDEX_op_eqv_i64: 1360 return TCG_TARGET_HAS_eqv_i64; 1361 case INDEX_op_nand_i64: 1362 return TCG_TARGET_HAS_nand_i64; 1363 case INDEX_op_nor_i64: 1364 return TCG_TARGET_HAS_nor_i64; 1365 case INDEX_op_clz_i64: 1366 return TCG_TARGET_HAS_clz_i64; 1367 case INDEX_op_ctz_i64: 1368 return TCG_TARGET_HAS_ctz_i64; 1369 case INDEX_op_ctpop_i64: 1370 return TCG_TARGET_HAS_ctpop_i64; 1371 case INDEX_op_add2_i64: 1372 return TCG_TARGET_HAS_add2_i64; 1373 case INDEX_op_sub2_i64: 1374 return TCG_TARGET_HAS_sub2_i64; 1375 case INDEX_op_mulu2_i64: 1376 return TCG_TARGET_HAS_mulu2_i64; 1377 case INDEX_op_muls2_i64: 1378 return TCG_TARGET_HAS_muls2_i64; 1379 case INDEX_op_muluh_i64: 1380 return TCG_TARGET_HAS_muluh_i64; 1381 case INDEX_op_mulsh_i64: 1382 return TCG_TARGET_HAS_mulsh_i64; 1383 1384 case INDEX_op_mov_vec: 1385 case INDEX_op_dup_vec: 1386 case INDEX_op_dupi_vec: 1387 case INDEX_op_ld_vec: 1388 case INDEX_op_st_vec: 1389 case INDEX_op_add_vec: 1390 case INDEX_op_sub_vec: 1391 case INDEX_op_and_vec: 1392 case INDEX_op_or_vec: 1393 case INDEX_op_xor_vec: 1394 case INDEX_op_cmp_vec: 1395 return have_vec; 1396 case INDEX_op_dup2_vec: 1397 return have_vec && TCG_TARGET_REG_BITS == 32; 1398 case INDEX_op_not_vec: 1399 return have_vec && TCG_TARGET_HAS_not_vec; 1400 case INDEX_op_neg_vec: 1401 return have_vec && TCG_TARGET_HAS_neg_vec; 1402 case INDEX_op_andc_vec: 1403 return have_vec && TCG_TARGET_HAS_andc_vec; 1404 case INDEX_op_orc_vec: 1405 return have_vec && TCG_TARGET_HAS_orc_vec; 1406 case INDEX_op_shli_vec: 1407 case INDEX_op_shri_vec: 1408 case INDEX_op_sari_vec: 1409 return have_vec && TCG_TARGET_HAS_shi_vec; 1410 case INDEX_op_shls_vec: 1411 case INDEX_op_shrs_vec: 1412 case INDEX_op_sars_vec: 1413 return have_vec && TCG_TARGET_HAS_shs_vec; 1414 case INDEX_op_shlv_vec: 1415 case INDEX_op_shrv_vec: 1416 case INDEX_op_sarv_vec: 1417 return have_vec && TCG_TARGET_HAS_shv_vec; 1418 1419 default: 1420 tcg_debug_assert(op > INDEX_op_last_generic && op < NB_OPS); 1421 return true; 1422 } 1423 } 1424 1425 /* Note: we convert the 64 bit args to 32 bit and do some alignment 1426 and endian swap. Maybe it would be better to do the alignment 1427 and endian swap in tcg_reg_alloc_call(). */ 1428 void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) 1429 { 1430 int i, real_args, nb_rets, pi; 1431 unsigned sizemask, flags; 1432 TCGHelperInfo *info; 1433 TCGOp *op; 1434 1435 info = g_hash_table_lookup(helper_table, (gpointer)func); 1436 flags = info->flags; 1437 sizemask = info->sizemask; 1438 1439 #if defined(__sparc__) && !defined(__arch64__) \ 1440 && !defined(CONFIG_TCG_INTERPRETER) 1441 /* We have 64-bit values in one register, but need to pass as two 1442 separate parameters. Split them. */ 1443 int orig_sizemask = sizemask; 1444 int orig_nargs = nargs; 1445 TCGv_i64 retl, reth; 1446 TCGTemp *split_args[MAX_OPC_PARAM]; 1447 1448 retl = NULL; 1449 reth = NULL; 1450 if (sizemask != 0) { 1451 for (i = real_args = 0; i < nargs; ++i) { 1452 int is_64bit = sizemask & (1 << (i+1)*2); 1453 if (is_64bit) { 1454 TCGv_i64 orig = temp_tcgv_i64(args[i]); 1455 TCGv_i32 h = tcg_temp_new_i32(); 1456 TCGv_i32 l = tcg_temp_new_i32(); 1457 tcg_gen_extr_i64_i32(l, h, orig); 1458 split_args[real_args++] = tcgv_i32_temp(h); 1459 split_args[real_args++] = tcgv_i32_temp(l); 1460 } else { 1461 split_args[real_args++] = args[i]; 1462 } 1463 } 1464 nargs = real_args; 1465 args = split_args; 1466 sizemask = 0; 1467 } 1468 #elif defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS == 64 1469 for (i = 0; i < nargs; ++i) { 1470 int is_64bit = sizemask & (1 << (i+1)*2); 1471 int is_signed = sizemask & (2 << (i+1)*2); 1472 if (!is_64bit) { 1473 TCGv_i64 temp = tcg_temp_new_i64(); 1474 TCGv_i64 orig = temp_tcgv_i64(args[i]); 1475 if (is_signed) { 1476 tcg_gen_ext32s_i64(temp, orig); 1477 } else { 1478 tcg_gen_ext32u_i64(temp, orig); 1479 } 1480 args[i] = tcgv_i64_temp(temp); 1481 } 1482 } 1483 #endif /* TCG_TARGET_EXTEND_ARGS */ 1484 1485 op = tcg_emit_op(INDEX_op_call); 1486 1487 pi = 0; 1488 if (ret != NULL) { 1489 #if defined(__sparc__) && !defined(__arch64__) \ 1490 && !defined(CONFIG_TCG_INTERPRETER) 1491 if (orig_sizemask & 1) { 1492 /* The 32-bit ABI is going to return the 64-bit value in 1493 the %o0/%o1 register pair. Prepare for this by using 1494 two return temporaries, and reassemble below. */ 1495 retl = tcg_temp_new_i64(); 1496 reth = tcg_temp_new_i64(); 1497 op->args[pi++] = tcgv_i64_arg(reth); 1498 op->args[pi++] = tcgv_i64_arg(retl); 1499 nb_rets = 2; 1500 } else { 1501 op->args[pi++] = temp_arg(ret); 1502 nb_rets = 1; 1503 } 1504 #else 1505 if (TCG_TARGET_REG_BITS < 64 && (sizemask & 1)) { 1506 #ifdef HOST_WORDS_BIGENDIAN 1507 op->args[pi++] = temp_arg(ret + 1); 1508 op->args[pi++] = temp_arg(ret); 1509 #else 1510 op->args[pi++] = temp_arg(ret); 1511 op->args[pi++] = temp_arg(ret + 1); 1512 #endif 1513 nb_rets = 2; 1514 } else { 1515 op->args[pi++] = temp_arg(ret); 1516 nb_rets = 1; 1517 } 1518 #endif 1519 } else { 1520 nb_rets = 0; 1521 } 1522 TCGOP_CALLO(op) = nb_rets; 1523 1524 real_args = 0; 1525 for (i = 0; i < nargs; i++) { 1526 int is_64bit = sizemask & (1 << (i+1)*2); 1527 if (TCG_TARGET_REG_BITS < 64 && is_64bit) { 1528 #ifdef TCG_TARGET_CALL_ALIGN_ARGS 1529 /* some targets want aligned 64 bit args */ 1530 if (real_args & 1) { 1531 op->args[pi++] = TCG_CALL_DUMMY_ARG; 1532 real_args++; 1533 } 1534 #endif 1535 /* If stack grows up, then we will be placing successive 1536 arguments at lower addresses, which means we need to 1537 reverse the order compared to how we would normally 1538 treat either big or little-endian. For those arguments 1539 that will wind up in registers, this still works for 1540 HPPA (the only current STACK_GROWSUP target) since the 1541 argument registers are *also* allocated in decreasing 1542 order. If another such target is added, this logic may 1543 have to get more complicated to differentiate between 1544 stack arguments and register arguments. */ 1545 #if defined(HOST_WORDS_BIGENDIAN) != defined(TCG_TARGET_STACK_GROWSUP) 1546 op->args[pi++] = temp_arg(args[i] + 1); 1547 op->args[pi++] = temp_arg(args[i]); 1548 #else 1549 op->args[pi++] = temp_arg(args[i]); 1550 op->args[pi++] = temp_arg(args[i] + 1); 1551 #endif 1552 real_args += 2; 1553 continue; 1554 } 1555 1556 op->args[pi++] = temp_arg(args[i]); 1557 real_args++; 1558 } 1559 op->args[pi++] = (uintptr_t)func; 1560 op->args[pi++] = flags; 1561 TCGOP_CALLI(op) = real_args; 1562 1563 /* Make sure the fields didn't overflow. */ 1564 tcg_debug_assert(TCGOP_CALLI(op) == real_args); 1565 tcg_debug_assert(pi <= ARRAY_SIZE(op->args)); 1566 1567 #if defined(__sparc__) && !defined(__arch64__) \ 1568 && !defined(CONFIG_TCG_INTERPRETER) 1569 /* Free all of the parts we allocated above. */ 1570 for (i = real_args = 0; i < orig_nargs; ++i) { 1571 int is_64bit = orig_sizemask & (1 << (i+1)*2); 1572 if (is_64bit) { 1573 tcg_temp_free_internal(args[real_args++]); 1574 tcg_temp_free_internal(args[real_args++]); 1575 } else { 1576 real_args++; 1577 } 1578 } 1579 if (orig_sizemask & 1) { 1580 /* The 32-bit ABI returned two 32-bit pieces. Re-assemble them. 1581 Note that describing these as TCGv_i64 eliminates an unnecessary 1582 zero-extension that tcg_gen_concat_i32_i64 would create. */ 1583 tcg_gen_concat32_i64(temp_tcgv_i64(ret), retl, reth); 1584 tcg_temp_free_i64(retl); 1585 tcg_temp_free_i64(reth); 1586 } 1587 #elif defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS == 64 1588 for (i = 0; i < nargs; ++i) { 1589 int is_64bit = sizemask & (1 << (i+1)*2); 1590 if (!is_64bit) { 1591 tcg_temp_free_internal(args[i]); 1592 } 1593 } 1594 #endif /* TCG_TARGET_EXTEND_ARGS */ 1595 } 1596 1597 static void tcg_reg_alloc_start(TCGContext *s) 1598 { 1599 int i, n; 1600 TCGTemp *ts; 1601 1602 for (i = 0, n = s->nb_globals; i < n; i++) { 1603 ts = &s->temps[i]; 1604 ts->val_type = (ts->fixed_reg ? TEMP_VAL_REG : TEMP_VAL_MEM); 1605 } 1606 for (n = s->nb_temps; i < n; i++) { 1607 ts = &s->temps[i]; 1608 ts->val_type = (ts->temp_local ? TEMP_VAL_MEM : TEMP_VAL_DEAD); 1609 ts->mem_allocated = 0; 1610 ts->fixed_reg = 0; 1611 } 1612 1613 memset(s->reg_to_temp, 0, sizeof(s->reg_to_temp)); 1614 } 1615 1616 static char *tcg_get_arg_str_ptr(TCGContext *s, char *buf, int buf_size, 1617 TCGTemp *ts) 1618 { 1619 int idx = temp_idx(ts); 1620 1621 if (ts->temp_global) { 1622 pstrcpy(buf, buf_size, ts->name); 1623 } else if (ts->temp_local) { 1624 snprintf(buf, buf_size, "loc%d", idx - s->nb_globals); 1625 } else { 1626 snprintf(buf, buf_size, "tmp%d", idx - s->nb_globals); 1627 } 1628 return buf; 1629 } 1630 1631 static char *tcg_get_arg_str(TCGContext *s, char *buf, 1632 int buf_size, TCGArg arg) 1633 { 1634 return tcg_get_arg_str_ptr(s, buf, buf_size, arg_temp(arg)); 1635 } 1636 1637 /* Find helper name. */ 1638 static inline const char *tcg_find_helper(TCGContext *s, uintptr_t val) 1639 { 1640 const char *ret = NULL; 1641 if (helper_table) { 1642 TCGHelperInfo *info = g_hash_table_lookup(helper_table, (gpointer)val); 1643 if (info) { 1644 ret = info->name; 1645 } 1646 } 1647 return ret; 1648 } 1649 1650 static const char * const cond_name[] = 1651 { 1652 [TCG_COND_NEVER] = "never", 1653 [TCG_COND_ALWAYS] = "always", 1654 [TCG_COND_EQ] = "eq", 1655 [TCG_COND_NE] = "ne", 1656 [TCG_COND_LT] = "lt", 1657 [TCG_COND_GE] = "ge", 1658 [TCG_COND_LE] = "le", 1659 [TCG_COND_GT] = "gt", 1660 [TCG_COND_LTU] = "ltu", 1661 [TCG_COND_GEU] = "geu", 1662 [TCG_COND_LEU] = "leu", 1663 [TCG_COND_GTU] = "gtu" 1664 }; 1665 1666 static const char * const ldst_name[] = 1667 { 1668 [MO_UB] = "ub", 1669 [MO_SB] = "sb", 1670 [MO_LEUW] = "leuw", 1671 [MO_LESW] = "lesw", 1672 [MO_LEUL] = "leul", 1673 [MO_LESL] = "lesl", 1674 [MO_LEQ] = "leq", 1675 [MO_BEUW] = "beuw", 1676 [MO_BESW] = "besw", 1677 [MO_BEUL] = "beul", 1678 [MO_BESL] = "besl", 1679 [MO_BEQ] = "beq", 1680 }; 1681 1682 static const char * const alignment_name[(MO_AMASK >> MO_ASHIFT) + 1] = { 1683 #ifdef ALIGNED_ONLY 1684 [MO_UNALN >> MO_ASHIFT] = "un+", 1685 [MO_ALIGN >> MO_ASHIFT] = "", 1686 #else 1687 [MO_UNALN >> MO_ASHIFT] = "", 1688 [MO_ALIGN >> MO_ASHIFT] = "al+", 1689 #endif 1690 [MO_ALIGN_2 >> MO_ASHIFT] = "al2+", 1691 [MO_ALIGN_4 >> MO_ASHIFT] = "al4+", 1692 [MO_ALIGN_8 >> MO_ASHIFT] = "al8+", 1693 [MO_ALIGN_16 >> MO_ASHIFT] = "al16+", 1694 [MO_ALIGN_32 >> MO_ASHIFT] = "al32+", 1695 [MO_ALIGN_64 >> MO_ASHIFT] = "al64+", 1696 }; 1697 1698 void tcg_dump_ops(TCGContext *s) 1699 { 1700 char buf[128]; 1701 TCGOp *op; 1702 1703 QTAILQ_FOREACH(op, &s->ops, link) { 1704 int i, k, nb_oargs, nb_iargs, nb_cargs; 1705 const TCGOpDef *def; 1706 TCGOpcode c; 1707 int col = 0; 1708 1709 c = op->opc; 1710 def = &tcg_op_defs[c]; 1711 1712 if (c == INDEX_op_insn_start) { 1713 col += qemu_log("\n ----"); 1714 1715 for (i = 0; i < TARGET_INSN_START_WORDS; ++i) { 1716 target_ulong a; 1717 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS 1718 a = deposit64(op->args[i * 2], 32, 32, op->args[i * 2 + 1]); 1719 #else 1720 a = op->args[i]; 1721 #endif 1722 col += qemu_log(" " TARGET_FMT_lx, a); 1723 } 1724 } else if (c == INDEX_op_call) { 1725 /* variable number of arguments */ 1726 nb_oargs = TCGOP_CALLO(op); 1727 nb_iargs = TCGOP_CALLI(op); 1728 nb_cargs = def->nb_cargs; 1729 1730 /* function name, flags, out args */ 1731 col += qemu_log(" %s %s,$0x%" TCG_PRIlx ",$%d", def->name, 1732 tcg_find_helper(s, op->args[nb_oargs + nb_iargs]), 1733 op->args[nb_oargs + nb_iargs + 1], nb_oargs); 1734 for (i = 0; i < nb_oargs; i++) { 1735 col += qemu_log(",%s", tcg_get_arg_str(s, buf, sizeof(buf), 1736 op->args[i])); 1737 } 1738 for (i = 0; i < nb_iargs; i++) { 1739 TCGArg arg = op->args[nb_oargs + i]; 1740 const char *t = "<dummy>"; 1741 if (arg != TCG_CALL_DUMMY_ARG) { 1742 t = tcg_get_arg_str(s, buf, sizeof(buf), arg); 1743 } 1744 col += qemu_log(",%s", t); 1745 } 1746 } else { 1747 col += qemu_log(" %s ", def->name); 1748 1749 nb_oargs = def->nb_oargs; 1750 nb_iargs = def->nb_iargs; 1751 nb_cargs = def->nb_cargs; 1752 1753 if (def->flags & TCG_OPF_VECTOR) { 1754 col += qemu_log("v%d,e%d,", 64 << TCGOP_VECL(op), 1755 8 << TCGOP_VECE(op)); 1756 } 1757 1758 k = 0; 1759 for (i = 0; i < nb_oargs; i++) { 1760 if (k != 0) { 1761 col += qemu_log(","); 1762 } 1763 col += qemu_log("%s", tcg_get_arg_str(s, buf, sizeof(buf), 1764 op->args[k++])); 1765 } 1766 for (i = 0; i < nb_iargs; i++) { 1767 if (k != 0) { 1768 col += qemu_log(","); 1769 } 1770 col += qemu_log("%s", tcg_get_arg_str(s, buf, sizeof(buf), 1771 op->args[k++])); 1772 } 1773 switch (c) { 1774 case INDEX_op_brcond_i32: 1775 case INDEX_op_setcond_i32: 1776 case INDEX_op_movcond_i32: 1777 case INDEX_op_brcond2_i32: 1778 case INDEX_op_setcond2_i32: 1779 case INDEX_op_brcond_i64: 1780 case INDEX_op_setcond_i64: 1781 case INDEX_op_movcond_i64: 1782 case INDEX_op_cmp_vec: 1783 if (op->args[k] < ARRAY_SIZE(cond_name) 1784 && cond_name[op->args[k]]) { 1785 col += qemu_log(",%s", cond_name[op->args[k++]]); 1786 } else { 1787 col += qemu_log(",$0x%" TCG_PRIlx, op->args[k++]); 1788 } 1789 i = 1; 1790 break; 1791 case INDEX_op_qemu_ld_i32: 1792 case INDEX_op_qemu_st_i32: 1793 case INDEX_op_qemu_ld_i64: 1794 case INDEX_op_qemu_st_i64: 1795 { 1796 TCGMemOpIdx oi = op->args[k++]; 1797 TCGMemOp op = get_memop(oi); 1798 unsigned ix = get_mmuidx(oi); 1799 1800 if (op & ~(MO_AMASK | MO_BSWAP | MO_SSIZE)) { 1801 col += qemu_log(",$0x%x,%u", op, ix); 1802 } else { 1803 const char *s_al, *s_op; 1804 s_al = alignment_name[(op & MO_AMASK) >> MO_ASHIFT]; 1805 s_op = ldst_name[op & (MO_BSWAP | MO_SSIZE)]; 1806 col += qemu_log(",%s%s,%u", s_al, s_op, ix); 1807 } 1808 i = 1; 1809 } 1810 break; 1811 default: 1812 i = 0; 1813 break; 1814 } 1815 switch (c) { 1816 case INDEX_op_set_label: 1817 case INDEX_op_br: 1818 case INDEX_op_brcond_i32: 1819 case INDEX_op_brcond_i64: 1820 case INDEX_op_brcond2_i32: 1821 col += qemu_log("%s$L%d", k ? "," : "", 1822 arg_label(op->args[k])->id); 1823 i++, k++; 1824 break; 1825 default: 1826 break; 1827 } 1828 for (; i < nb_cargs; i++, k++) { 1829 col += qemu_log("%s$0x%" TCG_PRIlx, k ? "," : "", op->args[k]); 1830 } 1831 } 1832 if (op->life) { 1833 unsigned life = op->life; 1834 1835 for (; col < 48; ++col) { 1836 putc(' ', qemu_logfile); 1837 } 1838 1839 if (life & (SYNC_ARG * 3)) { 1840 qemu_log(" sync:"); 1841 for (i = 0; i < 2; ++i) { 1842 if (life & (SYNC_ARG << i)) { 1843 qemu_log(" %d", i); 1844 } 1845 } 1846 } 1847 life /= DEAD_ARG; 1848 if (life) { 1849 qemu_log(" dead:"); 1850 for (i = 0; life; ++i, life >>= 1) { 1851 if (life & 1) { 1852 qemu_log(" %d", i); 1853 } 1854 } 1855 } 1856 } 1857 qemu_log("\n"); 1858 } 1859 } 1860 1861 /* we give more priority to constraints with less registers */ 1862 static int get_constraint_priority(const TCGOpDef *def, int k) 1863 { 1864 const TCGArgConstraint *arg_ct; 1865 1866 int i, n; 1867 arg_ct = &def->args_ct[k]; 1868 if (arg_ct->ct & TCG_CT_ALIAS) { 1869 /* an alias is equivalent to a single register */ 1870 n = 1; 1871 } else { 1872 if (!(arg_ct->ct & TCG_CT_REG)) 1873 return 0; 1874 n = 0; 1875 for(i = 0; i < TCG_TARGET_NB_REGS; i++) { 1876 if (tcg_regset_test_reg(arg_ct->u.regs, i)) 1877 n++; 1878 } 1879 } 1880 return TCG_TARGET_NB_REGS - n + 1; 1881 } 1882 1883 /* sort from highest priority to lowest */ 1884 static void sort_constraints(TCGOpDef *def, int start, int n) 1885 { 1886 int i, j, p1, p2, tmp; 1887 1888 for(i = 0; i < n; i++) 1889 def->sorted_args[start + i] = start + i; 1890 if (n <= 1) 1891 return; 1892 for(i = 0; i < n - 1; i++) { 1893 for(j = i + 1; j < n; j++) { 1894 p1 = get_constraint_priority(def, def->sorted_args[start + i]); 1895 p2 = get_constraint_priority(def, def->sorted_args[start + j]); 1896 if (p1 < p2) { 1897 tmp = def->sorted_args[start + i]; 1898 def->sorted_args[start + i] = def->sorted_args[start + j]; 1899 def->sorted_args[start + j] = tmp; 1900 } 1901 } 1902 } 1903 } 1904 1905 static void process_op_defs(TCGContext *s) 1906 { 1907 TCGOpcode op; 1908 1909 for (op = 0; op < NB_OPS; op++) { 1910 TCGOpDef *def = &tcg_op_defs[op]; 1911 const TCGTargetOpDef *tdefs; 1912 TCGType type; 1913 int i, nb_args; 1914 1915 if (def->flags & TCG_OPF_NOT_PRESENT) { 1916 continue; 1917 } 1918 1919 nb_args = def->nb_iargs + def->nb_oargs; 1920 if (nb_args == 0) { 1921 continue; 1922 } 1923 1924 tdefs = tcg_target_op_def(op); 1925 /* Missing TCGTargetOpDef entry. */ 1926 tcg_debug_assert(tdefs != NULL); 1927 1928 type = (def->flags & TCG_OPF_64BIT ? TCG_TYPE_I64 : TCG_TYPE_I32); 1929 for (i = 0; i < nb_args; i++) { 1930 const char *ct_str = tdefs->args_ct_str[i]; 1931 /* Incomplete TCGTargetOpDef entry. */ 1932 tcg_debug_assert(ct_str != NULL); 1933 1934 def->args_ct[i].u.regs = 0; 1935 def->args_ct[i].ct = 0; 1936 while (*ct_str != '\0') { 1937 switch(*ct_str) { 1938 case '0' ... '9': 1939 { 1940 int oarg = *ct_str - '0'; 1941 tcg_debug_assert(ct_str == tdefs->args_ct_str[i]); 1942 tcg_debug_assert(oarg < def->nb_oargs); 1943 tcg_debug_assert(def->args_ct[oarg].ct & TCG_CT_REG); 1944 /* TCG_CT_ALIAS is for the output arguments. 1945 The input is tagged with TCG_CT_IALIAS. */ 1946 def->args_ct[i] = def->args_ct[oarg]; 1947 def->args_ct[oarg].ct |= TCG_CT_ALIAS; 1948 def->args_ct[oarg].alias_index = i; 1949 def->args_ct[i].ct |= TCG_CT_IALIAS; 1950 def->args_ct[i].alias_index = oarg; 1951 } 1952 ct_str++; 1953 break; 1954 case '&': 1955 def->args_ct[i].ct |= TCG_CT_NEWREG; 1956 ct_str++; 1957 break; 1958 case 'i': 1959 def->args_ct[i].ct |= TCG_CT_CONST; 1960 ct_str++; 1961 break; 1962 default: 1963 ct_str = target_parse_constraint(&def->args_ct[i], 1964 ct_str, type); 1965 /* Typo in TCGTargetOpDef constraint. */ 1966 tcg_debug_assert(ct_str != NULL); 1967 } 1968 } 1969 } 1970 1971 /* TCGTargetOpDef entry with too much information? */ 1972 tcg_debug_assert(i == TCG_MAX_OP_ARGS || tdefs->args_ct_str[i] == NULL); 1973 1974 /* sort the constraints (XXX: this is just an heuristic) */ 1975 sort_constraints(def, 0, def->nb_oargs); 1976 sort_constraints(def, def->nb_oargs, def->nb_iargs); 1977 } 1978 } 1979 1980 void tcg_op_remove(TCGContext *s, TCGOp *op) 1981 { 1982 QTAILQ_REMOVE(&s->ops, op, link); 1983 QTAILQ_INSERT_TAIL(&s->free_ops, op, link); 1984 1985 #ifdef CONFIG_PROFILER 1986 atomic_set(&s->prof.del_op_count, s->prof.del_op_count + 1); 1987 #endif 1988 } 1989 1990 static TCGOp *tcg_op_alloc(TCGOpcode opc) 1991 { 1992 TCGContext *s = tcg_ctx; 1993 TCGOp *op; 1994 1995 if (likely(QTAILQ_EMPTY(&s->free_ops))) { 1996 op = tcg_malloc(sizeof(TCGOp)); 1997 } else { 1998 op = QTAILQ_FIRST(&s->free_ops); 1999 QTAILQ_REMOVE(&s->free_ops, op, link); 2000 } 2001 memset(op, 0, offsetof(TCGOp, link)); 2002 op->opc = opc; 2003 2004 return op; 2005 } 2006 2007 TCGOp *tcg_emit_op(TCGOpcode opc) 2008 { 2009 TCGOp *op = tcg_op_alloc(opc); 2010 QTAILQ_INSERT_TAIL(&tcg_ctx->ops, op, link); 2011 return op; 2012 } 2013 2014 TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *old_op, 2015 TCGOpcode opc, int nargs) 2016 { 2017 TCGOp *new_op = tcg_op_alloc(opc); 2018 QTAILQ_INSERT_BEFORE(old_op, new_op, link); 2019 return new_op; 2020 } 2021 2022 TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *old_op, 2023 TCGOpcode opc, int nargs) 2024 { 2025 TCGOp *new_op = tcg_op_alloc(opc); 2026 QTAILQ_INSERT_AFTER(&s->ops, old_op, new_op, link); 2027 return new_op; 2028 } 2029 2030 #define TS_DEAD 1 2031 #define TS_MEM 2 2032 2033 #define IS_DEAD_ARG(n) (arg_life & (DEAD_ARG << (n))) 2034 #define NEED_SYNC_ARG(n) (arg_life & (SYNC_ARG << (n))) 2035 2036 /* liveness analysis: end of function: all temps are dead, and globals 2037 should be in memory. */ 2038 static void tcg_la_func_end(TCGContext *s) 2039 { 2040 int ng = s->nb_globals; 2041 int nt = s->nb_temps; 2042 int i; 2043 2044 for (i = 0; i < ng; ++i) { 2045 s->temps[i].state = TS_DEAD | TS_MEM; 2046 } 2047 for (i = ng; i < nt; ++i) { 2048 s->temps[i].state = TS_DEAD; 2049 } 2050 } 2051 2052 /* liveness analysis: end of basic block: all temps are dead, globals 2053 and local temps should be in memory. */ 2054 static void tcg_la_bb_end(TCGContext *s) 2055 { 2056 int ng = s->nb_globals; 2057 int nt = s->nb_temps; 2058 int i; 2059 2060 for (i = 0; i < ng; ++i) { 2061 s->temps[i].state = TS_DEAD | TS_MEM; 2062 } 2063 for (i = ng; i < nt; ++i) { 2064 s->temps[i].state = (s->temps[i].temp_local 2065 ? TS_DEAD | TS_MEM 2066 : TS_DEAD); 2067 } 2068 } 2069 2070 /* Liveness analysis : update the opc_arg_life array to tell if a 2071 given input arguments is dead. Instructions updating dead 2072 temporaries are removed. */ 2073 static void liveness_pass_1(TCGContext *s) 2074 { 2075 int nb_globals = s->nb_globals; 2076 TCGOp *op, *op_prev; 2077 2078 tcg_la_func_end(s); 2079 2080 QTAILQ_FOREACH_REVERSE_SAFE(op, &s->ops, TCGOpHead, link, op_prev) { 2081 int i, nb_iargs, nb_oargs; 2082 TCGOpcode opc_new, opc_new2; 2083 bool have_opc_new2; 2084 TCGLifeData arg_life = 0; 2085 TCGTemp *arg_ts; 2086 TCGOpcode opc = op->opc; 2087 const TCGOpDef *def = &tcg_op_defs[opc]; 2088 2089 switch (opc) { 2090 case INDEX_op_call: 2091 { 2092 int call_flags; 2093 2094 nb_oargs = TCGOP_CALLO(op); 2095 nb_iargs = TCGOP_CALLI(op); 2096 call_flags = op->args[nb_oargs + nb_iargs + 1]; 2097 2098 /* pure functions can be removed if their result is unused */ 2099 if (call_flags & TCG_CALL_NO_SIDE_EFFECTS) { 2100 for (i = 0; i < nb_oargs; i++) { 2101 arg_ts = arg_temp(op->args[i]); 2102 if (arg_ts->state != TS_DEAD) { 2103 goto do_not_remove_call; 2104 } 2105 } 2106 goto do_remove; 2107 } else { 2108 do_not_remove_call: 2109 2110 /* output args are dead */ 2111 for (i = 0; i < nb_oargs; i++) { 2112 arg_ts = arg_temp(op->args[i]); 2113 if (arg_ts->state & TS_DEAD) { 2114 arg_life |= DEAD_ARG << i; 2115 } 2116 if (arg_ts->state & TS_MEM) { 2117 arg_life |= SYNC_ARG << i; 2118 } 2119 arg_ts->state = TS_DEAD; 2120 } 2121 2122 if (!(call_flags & (TCG_CALL_NO_WRITE_GLOBALS | 2123 TCG_CALL_NO_READ_GLOBALS))) { 2124 /* globals should go back to memory */ 2125 for (i = 0; i < nb_globals; i++) { 2126 s->temps[i].state = TS_DEAD | TS_MEM; 2127 } 2128 } else if (!(call_flags & TCG_CALL_NO_READ_GLOBALS)) { 2129 /* globals should be synced to memory */ 2130 for (i = 0; i < nb_globals; i++) { 2131 s->temps[i].state |= TS_MEM; 2132 } 2133 } 2134 2135 /* record arguments that die in this helper */ 2136 for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) { 2137 arg_ts = arg_temp(op->args[i]); 2138 if (arg_ts && arg_ts->state & TS_DEAD) { 2139 arg_life |= DEAD_ARG << i; 2140 } 2141 } 2142 /* input arguments are live for preceding opcodes */ 2143 for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) { 2144 arg_ts = arg_temp(op->args[i]); 2145 if (arg_ts) { 2146 arg_ts->state &= ~TS_DEAD; 2147 } 2148 } 2149 } 2150 } 2151 break; 2152 case INDEX_op_insn_start: 2153 break; 2154 case INDEX_op_discard: 2155 /* mark the temporary as dead */ 2156 arg_temp(op->args[0])->state = TS_DEAD; 2157 break; 2158 2159 case INDEX_op_add2_i32: 2160 opc_new = INDEX_op_add_i32; 2161 goto do_addsub2; 2162 case INDEX_op_sub2_i32: 2163 opc_new = INDEX_op_sub_i32; 2164 goto do_addsub2; 2165 case INDEX_op_add2_i64: 2166 opc_new = INDEX_op_add_i64; 2167 goto do_addsub2; 2168 case INDEX_op_sub2_i64: 2169 opc_new = INDEX_op_sub_i64; 2170 do_addsub2: 2171 nb_iargs = 4; 2172 nb_oargs = 2; 2173 /* Test if the high part of the operation is dead, but not 2174 the low part. The result can be optimized to a simple 2175 add or sub. This happens often for x86_64 guest when the 2176 cpu mode is set to 32 bit. */ 2177 if (arg_temp(op->args[1])->state == TS_DEAD) { 2178 if (arg_temp(op->args[0])->state == TS_DEAD) { 2179 goto do_remove; 2180 } 2181 /* Replace the opcode and adjust the args in place, 2182 leaving 3 unused args at the end. */ 2183 op->opc = opc = opc_new; 2184 op->args[1] = op->args[2]; 2185 op->args[2] = op->args[4]; 2186 /* Fall through and mark the single-word operation live. */ 2187 nb_iargs = 2; 2188 nb_oargs = 1; 2189 } 2190 goto do_not_remove; 2191 2192 case INDEX_op_mulu2_i32: 2193 opc_new = INDEX_op_mul_i32; 2194 opc_new2 = INDEX_op_muluh_i32; 2195 have_opc_new2 = TCG_TARGET_HAS_muluh_i32; 2196 goto do_mul2; 2197 case INDEX_op_muls2_i32: 2198 opc_new = INDEX_op_mul_i32; 2199 opc_new2 = INDEX_op_mulsh_i32; 2200 have_opc_new2 = TCG_TARGET_HAS_mulsh_i32; 2201 goto do_mul2; 2202 case INDEX_op_mulu2_i64: 2203 opc_new = INDEX_op_mul_i64; 2204 opc_new2 = INDEX_op_muluh_i64; 2205 have_opc_new2 = TCG_TARGET_HAS_muluh_i64; 2206 goto do_mul2; 2207 case INDEX_op_muls2_i64: 2208 opc_new = INDEX_op_mul_i64; 2209 opc_new2 = INDEX_op_mulsh_i64; 2210 have_opc_new2 = TCG_TARGET_HAS_mulsh_i64; 2211 goto do_mul2; 2212 do_mul2: 2213 nb_iargs = 2; 2214 nb_oargs = 2; 2215 if (arg_temp(op->args[1])->state == TS_DEAD) { 2216 if (arg_temp(op->args[0])->state == TS_DEAD) { 2217 /* Both parts of the operation are dead. */ 2218 goto do_remove; 2219 } 2220 /* The high part of the operation is dead; generate the low. */ 2221 op->opc = opc = opc_new; 2222 op->args[1] = op->args[2]; 2223 op->args[2] = op->args[3]; 2224 } else if (arg_temp(op->args[0])->state == TS_DEAD && have_opc_new2) { 2225 /* The low part of the operation is dead; generate the high. */ 2226 op->opc = opc = opc_new2; 2227 op->args[0] = op->args[1]; 2228 op->args[1] = op->args[2]; 2229 op->args[2] = op->args[3]; 2230 } else { 2231 goto do_not_remove; 2232 } 2233 /* Mark the single-word operation live. */ 2234 nb_oargs = 1; 2235 goto do_not_remove; 2236 2237 default: 2238 /* XXX: optimize by hardcoding common cases (e.g. triadic ops) */ 2239 nb_iargs = def->nb_iargs; 2240 nb_oargs = def->nb_oargs; 2241 2242 /* Test if the operation can be removed because all 2243 its outputs are dead. We assume that nb_oargs == 0 2244 implies side effects */ 2245 if (!(def->flags & TCG_OPF_SIDE_EFFECTS) && nb_oargs != 0) { 2246 for (i = 0; i < nb_oargs; i++) { 2247 if (arg_temp(op->args[i])->state != TS_DEAD) { 2248 goto do_not_remove; 2249 } 2250 } 2251 do_remove: 2252 tcg_op_remove(s, op); 2253 } else { 2254 do_not_remove: 2255 /* output args are dead */ 2256 for (i = 0; i < nb_oargs; i++) { 2257 arg_ts = arg_temp(op->args[i]); 2258 if (arg_ts->state & TS_DEAD) { 2259 arg_life |= DEAD_ARG << i; 2260 } 2261 if (arg_ts->state & TS_MEM) { 2262 arg_life |= SYNC_ARG << i; 2263 } 2264 arg_ts->state = TS_DEAD; 2265 } 2266 2267 /* if end of basic block, update */ 2268 if (def->flags & TCG_OPF_BB_END) { 2269 tcg_la_bb_end(s); 2270 } else if (def->flags & TCG_OPF_SIDE_EFFECTS) { 2271 /* globals should be synced to memory */ 2272 for (i = 0; i < nb_globals; i++) { 2273 s->temps[i].state |= TS_MEM; 2274 } 2275 } 2276 2277 /* record arguments that die in this opcode */ 2278 for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) { 2279 arg_ts = arg_temp(op->args[i]); 2280 if (arg_ts->state & TS_DEAD) { 2281 arg_life |= DEAD_ARG << i; 2282 } 2283 } 2284 /* input arguments are live for preceding opcodes */ 2285 for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) { 2286 arg_temp(op->args[i])->state &= ~TS_DEAD; 2287 } 2288 } 2289 break; 2290 } 2291 op->life = arg_life; 2292 } 2293 } 2294 2295 /* Liveness analysis: Convert indirect regs to direct temporaries. */ 2296 static bool liveness_pass_2(TCGContext *s) 2297 { 2298 int nb_globals = s->nb_globals; 2299 int nb_temps, i; 2300 bool changes = false; 2301 TCGOp *op, *op_next; 2302 2303 /* Create a temporary for each indirect global. */ 2304 for (i = 0; i < nb_globals; ++i) { 2305 TCGTemp *its = &s->temps[i]; 2306 if (its->indirect_reg) { 2307 TCGTemp *dts = tcg_temp_alloc(s); 2308 dts->type = its->type; 2309 dts->base_type = its->base_type; 2310 its->state_ptr = dts; 2311 } else { 2312 its->state_ptr = NULL; 2313 } 2314 /* All globals begin dead. */ 2315 its->state = TS_DEAD; 2316 } 2317 for (nb_temps = s->nb_temps; i < nb_temps; ++i) { 2318 TCGTemp *its = &s->temps[i]; 2319 its->state_ptr = NULL; 2320 its->state = TS_DEAD; 2321 } 2322 2323 QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) { 2324 TCGOpcode opc = op->opc; 2325 const TCGOpDef *def = &tcg_op_defs[opc]; 2326 TCGLifeData arg_life = op->life; 2327 int nb_iargs, nb_oargs, call_flags; 2328 TCGTemp *arg_ts, *dir_ts; 2329 2330 if (opc == INDEX_op_call) { 2331 nb_oargs = TCGOP_CALLO(op); 2332 nb_iargs = TCGOP_CALLI(op); 2333 call_flags = op->args[nb_oargs + nb_iargs + 1]; 2334 } else { 2335 nb_iargs = def->nb_iargs; 2336 nb_oargs = def->nb_oargs; 2337 2338 /* Set flags similar to how calls require. */ 2339 if (def->flags & TCG_OPF_BB_END) { 2340 /* Like writing globals: save_globals */ 2341 call_flags = 0; 2342 } else if (def->flags & TCG_OPF_SIDE_EFFECTS) { 2343 /* Like reading globals: sync_globals */ 2344 call_flags = TCG_CALL_NO_WRITE_GLOBALS; 2345 } else { 2346 /* No effect on globals. */ 2347 call_flags = (TCG_CALL_NO_READ_GLOBALS | 2348 TCG_CALL_NO_WRITE_GLOBALS); 2349 } 2350 } 2351 2352 /* Make sure that input arguments are available. */ 2353 for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) { 2354 arg_ts = arg_temp(op->args[i]); 2355 if (arg_ts) { 2356 dir_ts = arg_ts->state_ptr; 2357 if (dir_ts && arg_ts->state == TS_DEAD) { 2358 TCGOpcode lopc = (arg_ts->type == TCG_TYPE_I32 2359 ? INDEX_op_ld_i32 2360 : INDEX_op_ld_i64); 2361 TCGOp *lop = tcg_op_insert_before(s, op, lopc, 3); 2362 2363 lop->args[0] = temp_arg(dir_ts); 2364 lop->args[1] = temp_arg(arg_ts->mem_base); 2365 lop->args[2] = arg_ts->mem_offset; 2366 2367 /* Loaded, but synced with memory. */ 2368 arg_ts->state = TS_MEM; 2369 } 2370 } 2371 } 2372 2373 /* Perform input replacement, and mark inputs that became dead. 2374 No action is required except keeping temp_state up to date 2375 so that we reload when needed. */ 2376 for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) { 2377 arg_ts = arg_temp(op->args[i]); 2378 if (arg_ts) { 2379 dir_ts = arg_ts->state_ptr; 2380 if (dir_ts) { 2381 op->args[i] = temp_arg(dir_ts); 2382 changes = true; 2383 if (IS_DEAD_ARG(i)) { 2384 arg_ts->state = TS_DEAD; 2385 } 2386 } 2387 } 2388 } 2389 2390 /* Liveness analysis should ensure that the following are 2391 all correct, for call sites and basic block end points. */ 2392 if (call_flags & TCG_CALL_NO_READ_GLOBALS) { 2393 /* Nothing to do */ 2394 } else if (call_flags & TCG_CALL_NO_WRITE_GLOBALS) { 2395 for (i = 0; i < nb_globals; ++i) { 2396 /* Liveness should see that globals are synced back, 2397 that is, either TS_DEAD or TS_MEM. */ 2398 arg_ts = &s->temps[i]; 2399 tcg_debug_assert(arg_ts->state_ptr == 0 2400 || arg_ts->state != 0); 2401 } 2402 } else { 2403 for (i = 0; i < nb_globals; ++i) { 2404 /* Liveness should see that globals are saved back, 2405 that is, TS_DEAD, waiting to be reloaded. */ 2406 arg_ts = &s->temps[i]; 2407 tcg_debug_assert(arg_ts->state_ptr == 0 2408 || arg_ts->state == TS_DEAD); 2409 } 2410 } 2411 2412 /* Outputs become available. */ 2413 for (i = 0; i < nb_oargs; i++) { 2414 arg_ts = arg_temp(op->args[i]); 2415 dir_ts = arg_ts->state_ptr; 2416 if (!dir_ts) { 2417 continue; 2418 } 2419 op->args[i] = temp_arg(dir_ts); 2420 changes = true; 2421 2422 /* The output is now live and modified. */ 2423 arg_ts->state = 0; 2424 2425 /* Sync outputs upon their last write. */ 2426 if (NEED_SYNC_ARG(i)) { 2427 TCGOpcode sopc = (arg_ts->type == TCG_TYPE_I32 2428 ? INDEX_op_st_i32 2429 : INDEX_op_st_i64); 2430 TCGOp *sop = tcg_op_insert_after(s, op, sopc, 3); 2431 2432 sop->args[0] = temp_arg(dir_ts); 2433 sop->args[1] = temp_arg(arg_ts->mem_base); 2434 sop->args[2] = arg_ts->mem_offset; 2435 2436 arg_ts->state = TS_MEM; 2437 } 2438 /* Drop outputs that are dead. */ 2439 if (IS_DEAD_ARG(i)) { 2440 arg_ts->state = TS_DEAD; 2441 } 2442 } 2443 } 2444 2445 return changes; 2446 } 2447 2448 #ifdef CONFIG_DEBUG_TCG 2449 static void dump_regs(TCGContext *s) 2450 { 2451 TCGTemp *ts; 2452 int i; 2453 char buf[64]; 2454 2455 for(i = 0; i < s->nb_temps; i++) { 2456 ts = &s->temps[i]; 2457 printf(" %10s: ", tcg_get_arg_str_ptr(s, buf, sizeof(buf), ts)); 2458 switch(ts->val_type) { 2459 case TEMP_VAL_REG: 2460 printf("%s", tcg_target_reg_names[ts->reg]); 2461 break; 2462 case TEMP_VAL_MEM: 2463 printf("%d(%s)", (int)ts->mem_offset, 2464 tcg_target_reg_names[ts->mem_base->reg]); 2465 break; 2466 case TEMP_VAL_CONST: 2467 printf("$0x%" TCG_PRIlx, ts->val); 2468 break; 2469 case TEMP_VAL_DEAD: 2470 printf("D"); 2471 break; 2472 default: 2473 printf("???"); 2474 break; 2475 } 2476 printf("\n"); 2477 } 2478 2479 for(i = 0; i < TCG_TARGET_NB_REGS; i++) { 2480 if (s->reg_to_temp[i] != NULL) { 2481 printf("%s: %s\n", 2482 tcg_target_reg_names[i], 2483 tcg_get_arg_str_ptr(s, buf, sizeof(buf), s->reg_to_temp[i])); 2484 } 2485 } 2486 } 2487 2488 static void check_regs(TCGContext *s) 2489 { 2490 int reg; 2491 int k; 2492 TCGTemp *ts; 2493 char buf[64]; 2494 2495 for (reg = 0; reg < TCG_TARGET_NB_REGS; reg++) { 2496 ts = s->reg_to_temp[reg]; 2497 if (ts != NULL) { 2498 if (ts->val_type != TEMP_VAL_REG || ts->reg != reg) { 2499 printf("Inconsistency for register %s:\n", 2500 tcg_target_reg_names[reg]); 2501 goto fail; 2502 } 2503 } 2504 } 2505 for (k = 0; k < s->nb_temps; k++) { 2506 ts = &s->temps[k]; 2507 if (ts->val_type == TEMP_VAL_REG && !ts->fixed_reg 2508 && s->reg_to_temp[ts->reg] != ts) { 2509 printf("Inconsistency for temp %s:\n", 2510 tcg_get_arg_str_ptr(s, buf, sizeof(buf), ts)); 2511 fail: 2512 printf("reg state:\n"); 2513 dump_regs(s); 2514 tcg_abort(); 2515 } 2516 } 2517 } 2518 #endif 2519 2520 static void temp_allocate_frame(TCGContext *s, TCGTemp *ts) 2521 { 2522 #if !(defined(__sparc__) && TCG_TARGET_REG_BITS == 64) 2523 /* Sparc64 stack is accessed with offset of 2047 */ 2524 s->current_frame_offset = (s->current_frame_offset + 2525 (tcg_target_long)sizeof(tcg_target_long) - 1) & 2526 ~(sizeof(tcg_target_long) - 1); 2527 #endif 2528 if (s->current_frame_offset + (tcg_target_long)sizeof(tcg_target_long) > 2529 s->frame_end) { 2530 tcg_abort(); 2531 } 2532 ts->mem_offset = s->current_frame_offset; 2533 ts->mem_base = s->frame_temp; 2534 ts->mem_allocated = 1; 2535 s->current_frame_offset += sizeof(tcg_target_long); 2536 } 2537 2538 static void temp_load(TCGContext *, TCGTemp *, TCGRegSet, TCGRegSet); 2539 2540 /* Mark a temporary as free or dead. If 'free_or_dead' is negative, 2541 mark it free; otherwise mark it dead. */ 2542 static void temp_free_or_dead(TCGContext *s, TCGTemp *ts, int free_or_dead) 2543 { 2544 if (ts->fixed_reg) { 2545 return; 2546 } 2547 if (ts->val_type == TEMP_VAL_REG) { 2548 s->reg_to_temp[ts->reg] = NULL; 2549 } 2550 ts->val_type = (free_or_dead < 0 2551 || ts->temp_local 2552 || ts->temp_global 2553 ? TEMP_VAL_MEM : TEMP_VAL_DEAD); 2554 } 2555 2556 /* Mark a temporary as dead. */ 2557 static inline void temp_dead(TCGContext *s, TCGTemp *ts) 2558 { 2559 temp_free_or_dead(s, ts, 1); 2560 } 2561 2562 /* Sync a temporary to memory. 'allocated_regs' is used in case a temporary 2563 registers needs to be allocated to store a constant. If 'free_or_dead' 2564 is non-zero, subsequently release the temporary; if it is positive, the 2565 temp is dead; if it is negative, the temp is free. */ 2566 static void temp_sync(TCGContext *s, TCGTemp *ts, 2567 TCGRegSet allocated_regs, int free_or_dead) 2568 { 2569 if (ts->fixed_reg) { 2570 return; 2571 } 2572 if (!ts->mem_coherent) { 2573 if (!ts->mem_allocated) { 2574 temp_allocate_frame(s, ts); 2575 } 2576 switch (ts->val_type) { 2577 case TEMP_VAL_CONST: 2578 /* If we're going to free the temp immediately, then we won't 2579 require it later in a register, so attempt to store the 2580 constant to memory directly. */ 2581 if (free_or_dead 2582 && tcg_out_sti(s, ts->type, ts->val, 2583 ts->mem_base->reg, ts->mem_offset)) { 2584 break; 2585 } 2586 temp_load(s, ts, tcg_target_available_regs[ts->type], 2587 allocated_regs); 2588 /* fallthrough */ 2589 2590 case TEMP_VAL_REG: 2591 tcg_out_st(s, ts->type, ts->reg, 2592 ts->mem_base->reg, ts->mem_offset); 2593 break; 2594 2595 case TEMP_VAL_MEM: 2596 break; 2597 2598 case TEMP_VAL_DEAD: 2599 default: 2600 tcg_abort(); 2601 } 2602 ts->mem_coherent = 1; 2603 } 2604 if (free_or_dead) { 2605 temp_free_or_dead(s, ts, free_or_dead); 2606 } 2607 } 2608 2609 /* free register 'reg' by spilling the corresponding temporary if necessary */ 2610 static void tcg_reg_free(TCGContext *s, TCGReg reg, TCGRegSet allocated_regs) 2611 { 2612 TCGTemp *ts = s->reg_to_temp[reg]; 2613 if (ts != NULL) { 2614 temp_sync(s, ts, allocated_regs, -1); 2615 } 2616 } 2617 2618 /* Allocate a register belonging to reg1 & ~reg2 */ 2619 static TCGReg tcg_reg_alloc(TCGContext *s, TCGRegSet desired_regs, 2620 TCGRegSet allocated_regs, bool rev) 2621 { 2622 int i, n = ARRAY_SIZE(tcg_target_reg_alloc_order); 2623 const int *order; 2624 TCGReg reg; 2625 TCGRegSet reg_ct; 2626 2627 reg_ct = desired_regs & ~allocated_regs; 2628 order = rev ? indirect_reg_alloc_order : tcg_target_reg_alloc_order; 2629 2630 /* first try free registers */ 2631 for(i = 0; i < n; i++) { 2632 reg = order[i]; 2633 if (tcg_regset_test_reg(reg_ct, reg) && s->reg_to_temp[reg] == NULL) 2634 return reg; 2635 } 2636 2637 /* XXX: do better spill choice */ 2638 for(i = 0; i < n; i++) { 2639 reg = order[i]; 2640 if (tcg_regset_test_reg(reg_ct, reg)) { 2641 tcg_reg_free(s, reg, allocated_regs); 2642 return reg; 2643 } 2644 } 2645 2646 tcg_abort(); 2647 } 2648 2649 /* Make sure the temporary is in a register. If needed, allocate the register 2650 from DESIRED while avoiding ALLOCATED. */ 2651 static void temp_load(TCGContext *s, TCGTemp *ts, TCGRegSet desired_regs, 2652 TCGRegSet allocated_regs) 2653 { 2654 TCGReg reg; 2655 2656 switch (ts->val_type) { 2657 case TEMP_VAL_REG: 2658 return; 2659 case TEMP_VAL_CONST: 2660 reg = tcg_reg_alloc(s, desired_regs, allocated_regs, ts->indirect_base); 2661 tcg_out_movi(s, ts->type, reg, ts->val); 2662 ts->mem_coherent = 0; 2663 break; 2664 case TEMP_VAL_MEM: 2665 reg = tcg_reg_alloc(s, desired_regs, allocated_regs, ts->indirect_base); 2666 tcg_out_ld(s, ts->type, reg, ts->mem_base->reg, ts->mem_offset); 2667 ts->mem_coherent = 1; 2668 break; 2669 case TEMP_VAL_DEAD: 2670 default: 2671 tcg_abort(); 2672 } 2673 ts->reg = reg; 2674 ts->val_type = TEMP_VAL_REG; 2675 s->reg_to_temp[reg] = ts; 2676 } 2677 2678 /* Save a temporary to memory. 'allocated_regs' is used in case a 2679 temporary registers needs to be allocated to store a constant. */ 2680 static void temp_save(TCGContext *s, TCGTemp *ts, TCGRegSet allocated_regs) 2681 { 2682 /* The liveness analysis already ensures that globals are back 2683 in memory. Keep an tcg_debug_assert for safety. */ 2684 tcg_debug_assert(ts->val_type == TEMP_VAL_MEM || ts->fixed_reg); 2685 } 2686 2687 /* save globals to their canonical location and assume they can be 2688 modified be the following code. 'allocated_regs' is used in case a 2689 temporary registers needs to be allocated to store a constant. */ 2690 static void save_globals(TCGContext *s, TCGRegSet allocated_regs) 2691 { 2692 int i, n; 2693 2694 for (i = 0, n = s->nb_globals; i < n; i++) { 2695 temp_save(s, &s->temps[i], allocated_regs); 2696 } 2697 } 2698 2699 /* sync globals to their canonical location and assume they can be 2700 read by the following code. 'allocated_regs' is used in case a 2701 temporary registers needs to be allocated to store a constant. */ 2702 static void sync_globals(TCGContext *s, TCGRegSet allocated_regs) 2703 { 2704 int i, n; 2705 2706 for (i = 0, n = s->nb_globals; i < n; i++) { 2707 TCGTemp *ts = &s->temps[i]; 2708 tcg_debug_assert(ts->val_type != TEMP_VAL_REG 2709 || ts->fixed_reg 2710 || ts->mem_coherent); 2711 } 2712 } 2713 2714 /* at the end of a basic block, we assume all temporaries are dead and 2715 all globals are stored at their canonical location. */ 2716 static void tcg_reg_alloc_bb_end(TCGContext *s, TCGRegSet allocated_regs) 2717 { 2718 int i; 2719 2720 for (i = s->nb_globals; i < s->nb_temps; i++) { 2721 TCGTemp *ts = &s->temps[i]; 2722 if (ts->temp_local) { 2723 temp_save(s, ts, allocated_regs); 2724 } else { 2725 /* The liveness analysis already ensures that temps are dead. 2726 Keep an tcg_debug_assert for safety. */ 2727 tcg_debug_assert(ts->val_type == TEMP_VAL_DEAD); 2728 } 2729 } 2730 2731 save_globals(s, allocated_regs); 2732 } 2733 2734 static void tcg_reg_alloc_do_movi(TCGContext *s, TCGTemp *ots, 2735 tcg_target_ulong val, TCGLifeData arg_life) 2736 { 2737 if (ots->fixed_reg) { 2738 /* For fixed registers, we do not do any constant propagation. */ 2739 tcg_out_movi(s, ots->type, ots->reg, val); 2740 return; 2741 } 2742 2743 /* The movi is not explicitly generated here. */ 2744 if (ots->val_type == TEMP_VAL_REG) { 2745 s->reg_to_temp[ots->reg] = NULL; 2746 } 2747 ots->val_type = TEMP_VAL_CONST; 2748 ots->val = val; 2749 ots->mem_coherent = 0; 2750 if (NEED_SYNC_ARG(0)) { 2751 temp_sync(s, ots, s->reserved_regs, IS_DEAD_ARG(0)); 2752 } else if (IS_DEAD_ARG(0)) { 2753 temp_dead(s, ots); 2754 } 2755 } 2756 2757 static void tcg_reg_alloc_movi(TCGContext *s, const TCGOp *op) 2758 { 2759 TCGTemp *ots = arg_temp(op->args[0]); 2760 tcg_target_ulong val = op->args[1]; 2761 2762 tcg_reg_alloc_do_movi(s, ots, val, op->life); 2763 } 2764 2765 static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op) 2766 { 2767 const TCGLifeData arg_life = op->life; 2768 TCGRegSet allocated_regs; 2769 TCGTemp *ts, *ots; 2770 TCGType otype, itype; 2771 2772 allocated_regs = s->reserved_regs; 2773 ots = arg_temp(op->args[0]); 2774 ts = arg_temp(op->args[1]); 2775 2776 /* Note that otype != itype for no-op truncation. */ 2777 otype = ots->type; 2778 itype = ts->type; 2779 2780 if (ts->val_type == TEMP_VAL_CONST) { 2781 /* propagate constant or generate sti */ 2782 tcg_target_ulong val = ts->val; 2783 if (IS_DEAD_ARG(1)) { 2784 temp_dead(s, ts); 2785 } 2786 tcg_reg_alloc_do_movi(s, ots, val, arg_life); 2787 return; 2788 } 2789 2790 /* If the source value is in memory we're going to be forced 2791 to have it in a register in order to perform the copy. Copy 2792 the SOURCE value into its own register first, that way we 2793 don't have to reload SOURCE the next time it is used. */ 2794 if (ts->val_type == TEMP_VAL_MEM) { 2795 temp_load(s, ts, tcg_target_available_regs[itype], allocated_regs); 2796 } 2797 2798 tcg_debug_assert(ts->val_type == TEMP_VAL_REG); 2799 if (IS_DEAD_ARG(0) && !ots->fixed_reg) { 2800 /* mov to a non-saved dead register makes no sense (even with 2801 liveness analysis disabled). */ 2802 tcg_debug_assert(NEED_SYNC_ARG(0)); 2803 if (!ots->mem_allocated) { 2804 temp_allocate_frame(s, ots); 2805 } 2806 tcg_out_st(s, otype, ts->reg, ots->mem_base->reg, ots->mem_offset); 2807 if (IS_DEAD_ARG(1)) { 2808 temp_dead(s, ts); 2809 } 2810 temp_dead(s, ots); 2811 } else { 2812 if (IS_DEAD_ARG(1) && !ts->fixed_reg && !ots->fixed_reg) { 2813 /* the mov can be suppressed */ 2814 if (ots->val_type == TEMP_VAL_REG) { 2815 s->reg_to_temp[ots->reg] = NULL; 2816 } 2817 ots->reg = ts->reg; 2818 temp_dead(s, ts); 2819 } else { 2820 if (ots->val_type != TEMP_VAL_REG) { 2821 /* When allocating a new register, make sure to not spill the 2822 input one. */ 2823 tcg_regset_set_reg(allocated_regs, ts->reg); 2824 ots->reg = tcg_reg_alloc(s, tcg_target_available_regs[otype], 2825 allocated_regs, ots->indirect_base); 2826 } 2827 tcg_out_mov(s, otype, ots->reg, ts->reg); 2828 } 2829 ots->val_type = TEMP_VAL_REG; 2830 ots->mem_coherent = 0; 2831 s->reg_to_temp[ots->reg] = ots; 2832 if (NEED_SYNC_ARG(0)) { 2833 temp_sync(s, ots, allocated_regs, 0); 2834 } 2835 } 2836 } 2837 2838 static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) 2839 { 2840 const TCGLifeData arg_life = op->life; 2841 const TCGOpDef * const def = &tcg_op_defs[op->opc]; 2842 TCGRegSet i_allocated_regs; 2843 TCGRegSet o_allocated_regs; 2844 int i, k, nb_iargs, nb_oargs; 2845 TCGReg reg; 2846 TCGArg arg; 2847 const TCGArgConstraint *arg_ct; 2848 TCGTemp *ts; 2849 TCGArg new_args[TCG_MAX_OP_ARGS]; 2850 int const_args[TCG_MAX_OP_ARGS]; 2851 2852 nb_oargs = def->nb_oargs; 2853 nb_iargs = def->nb_iargs; 2854 2855 /* copy constants */ 2856 memcpy(new_args + nb_oargs + nb_iargs, 2857 op->args + nb_oargs + nb_iargs, 2858 sizeof(TCGArg) * def->nb_cargs); 2859 2860 i_allocated_regs = s->reserved_regs; 2861 o_allocated_regs = s->reserved_regs; 2862 2863 /* satisfy input constraints */ 2864 for (k = 0; k < nb_iargs; k++) { 2865 i = def->sorted_args[nb_oargs + k]; 2866 arg = op->args[i]; 2867 arg_ct = &def->args_ct[i]; 2868 ts = arg_temp(arg); 2869 2870 if (ts->val_type == TEMP_VAL_CONST 2871 && tcg_target_const_match(ts->val, ts->type, arg_ct)) { 2872 /* constant is OK for instruction */ 2873 const_args[i] = 1; 2874 new_args[i] = ts->val; 2875 goto iarg_end; 2876 } 2877 2878 temp_load(s, ts, arg_ct->u.regs, i_allocated_regs); 2879 2880 if (arg_ct->ct & TCG_CT_IALIAS) { 2881 if (ts->fixed_reg) { 2882 /* if fixed register, we must allocate a new register 2883 if the alias is not the same register */ 2884 if (arg != op->args[arg_ct->alias_index]) 2885 goto allocate_in_reg; 2886 } else { 2887 /* if the input is aliased to an output and if it is 2888 not dead after the instruction, we must allocate 2889 a new register and move it */ 2890 if (!IS_DEAD_ARG(i)) { 2891 goto allocate_in_reg; 2892 } 2893 /* check if the current register has already been allocated 2894 for another input aliased to an output */ 2895 int k2, i2; 2896 for (k2 = 0 ; k2 < k ; k2++) { 2897 i2 = def->sorted_args[nb_oargs + k2]; 2898 if ((def->args_ct[i2].ct & TCG_CT_IALIAS) && 2899 (new_args[i2] == ts->reg)) { 2900 goto allocate_in_reg; 2901 } 2902 } 2903 } 2904 } 2905 reg = ts->reg; 2906 if (tcg_regset_test_reg(arg_ct->u.regs, reg)) { 2907 /* nothing to do : the constraint is satisfied */ 2908 } else { 2909 allocate_in_reg: 2910 /* allocate a new register matching the constraint 2911 and move the temporary register into it */ 2912 reg = tcg_reg_alloc(s, arg_ct->u.regs, i_allocated_regs, 2913 ts->indirect_base); 2914 tcg_out_mov(s, ts->type, reg, ts->reg); 2915 } 2916 new_args[i] = reg; 2917 const_args[i] = 0; 2918 tcg_regset_set_reg(i_allocated_regs, reg); 2919 iarg_end: ; 2920 } 2921 2922 /* mark dead temporaries and free the associated registers */ 2923 for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) { 2924 if (IS_DEAD_ARG(i)) { 2925 temp_dead(s, arg_temp(op->args[i])); 2926 } 2927 } 2928 2929 if (def->flags & TCG_OPF_BB_END) { 2930 tcg_reg_alloc_bb_end(s, i_allocated_regs); 2931 } else { 2932 if (def->flags & TCG_OPF_CALL_CLOBBER) { 2933 /* XXX: permit generic clobber register list ? */ 2934 for (i = 0; i < TCG_TARGET_NB_REGS; i++) { 2935 if (tcg_regset_test_reg(tcg_target_call_clobber_regs, i)) { 2936 tcg_reg_free(s, i, i_allocated_regs); 2937 } 2938 } 2939 } 2940 if (def->flags & TCG_OPF_SIDE_EFFECTS) { 2941 /* sync globals if the op has side effects and might trigger 2942 an exception. */ 2943 sync_globals(s, i_allocated_regs); 2944 } 2945 2946 /* satisfy the output constraints */ 2947 for(k = 0; k < nb_oargs; k++) { 2948 i = def->sorted_args[k]; 2949 arg = op->args[i]; 2950 arg_ct = &def->args_ct[i]; 2951 ts = arg_temp(arg); 2952 if ((arg_ct->ct & TCG_CT_ALIAS) 2953 && !const_args[arg_ct->alias_index]) { 2954 reg = new_args[arg_ct->alias_index]; 2955 } else if (arg_ct->ct & TCG_CT_NEWREG) { 2956 reg = tcg_reg_alloc(s, arg_ct->u.regs, 2957 i_allocated_regs | o_allocated_regs, 2958 ts->indirect_base); 2959 } else { 2960 /* if fixed register, we try to use it */ 2961 reg = ts->reg; 2962 if (ts->fixed_reg && 2963 tcg_regset_test_reg(arg_ct->u.regs, reg)) { 2964 goto oarg_end; 2965 } 2966 reg = tcg_reg_alloc(s, arg_ct->u.regs, o_allocated_regs, 2967 ts->indirect_base); 2968 } 2969 tcg_regset_set_reg(o_allocated_regs, reg); 2970 /* if a fixed register is used, then a move will be done afterwards */ 2971 if (!ts->fixed_reg) { 2972 if (ts->val_type == TEMP_VAL_REG) { 2973 s->reg_to_temp[ts->reg] = NULL; 2974 } 2975 ts->val_type = TEMP_VAL_REG; 2976 ts->reg = reg; 2977 /* temp value is modified, so the value kept in memory is 2978 potentially not the same */ 2979 ts->mem_coherent = 0; 2980 s->reg_to_temp[reg] = ts; 2981 } 2982 oarg_end: 2983 new_args[i] = reg; 2984 } 2985 } 2986 2987 /* emit instruction */ 2988 if (def->flags & TCG_OPF_VECTOR) { 2989 tcg_out_vec_op(s, op->opc, TCGOP_VECL(op), TCGOP_VECE(op), 2990 new_args, const_args); 2991 } else { 2992 tcg_out_op(s, op->opc, new_args, const_args); 2993 } 2994 2995 /* move the outputs in the correct register if needed */ 2996 for(i = 0; i < nb_oargs; i++) { 2997 ts = arg_temp(op->args[i]); 2998 reg = new_args[i]; 2999 if (ts->fixed_reg && ts->reg != reg) { 3000 tcg_out_mov(s, ts->type, ts->reg, reg); 3001 } 3002 if (NEED_SYNC_ARG(i)) { 3003 temp_sync(s, ts, o_allocated_regs, IS_DEAD_ARG(i)); 3004 } else if (IS_DEAD_ARG(i)) { 3005 temp_dead(s, ts); 3006 } 3007 } 3008 } 3009 3010 #ifdef TCG_TARGET_STACK_GROWSUP 3011 #define STACK_DIR(x) (-(x)) 3012 #else 3013 #define STACK_DIR(x) (x) 3014 #endif 3015 3016 static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) 3017 { 3018 const int nb_oargs = TCGOP_CALLO(op); 3019 const int nb_iargs = TCGOP_CALLI(op); 3020 const TCGLifeData arg_life = op->life; 3021 int flags, nb_regs, i; 3022 TCGReg reg; 3023 TCGArg arg; 3024 TCGTemp *ts; 3025 intptr_t stack_offset; 3026 size_t call_stack_size; 3027 tcg_insn_unit *func_addr; 3028 int allocate_args; 3029 TCGRegSet allocated_regs; 3030 3031 func_addr = (tcg_insn_unit *)(intptr_t)op->args[nb_oargs + nb_iargs]; 3032 flags = op->args[nb_oargs + nb_iargs + 1]; 3033 3034 nb_regs = ARRAY_SIZE(tcg_target_call_iarg_regs); 3035 if (nb_regs > nb_iargs) { 3036 nb_regs = nb_iargs; 3037 } 3038 3039 /* assign stack slots first */ 3040 call_stack_size = (nb_iargs - nb_regs) * sizeof(tcg_target_long); 3041 call_stack_size = (call_stack_size + TCG_TARGET_STACK_ALIGN - 1) & 3042 ~(TCG_TARGET_STACK_ALIGN - 1); 3043 allocate_args = (call_stack_size > TCG_STATIC_CALL_ARGS_SIZE); 3044 if (allocate_args) { 3045 /* XXX: if more than TCG_STATIC_CALL_ARGS_SIZE is needed, 3046 preallocate call stack */ 3047 tcg_abort(); 3048 } 3049 3050 stack_offset = TCG_TARGET_CALL_STACK_OFFSET; 3051 for (i = nb_regs; i < nb_iargs; i++) { 3052 arg = op->args[nb_oargs + i]; 3053 #ifdef TCG_TARGET_STACK_GROWSUP 3054 stack_offset -= sizeof(tcg_target_long); 3055 #endif 3056 if (arg != TCG_CALL_DUMMY_ARG) { 3057 ts = arg_temp(arg); 3058 temp_load(s, ts, tcg_target_available_regs[ts->type], 3059 s->reserved_regs); 3060 tcg_out_st(s, ts->type, ts->reg, TCG_REG_CALL_STACK, stack_offset); 3061 } 3062 #ifndef TCG_TARGET_STACK_GROWSUP 3063 stack_offset += sizeof(tcg_target_long); 3064 #endif 3065 } 3066 3067 /* assign input registers */ 3068 allocated_regs = s->reserved_regs; 3069 for (i = 0; i < nb_regs; i++) { 3070 arg = op->args[nb_oargs + i]; 3071 if (arg != TCG_CALL_DUMMY_ARG) { 3072 ts = arg_temp(arg); 3073 reg = tcg_target_call_iarg_regs[i]; 3074 tcg_reg_free(s, reg, allocated_regs); 3075 3076 if (ts->val_type == TEMP_VAL_REG) { 3077 if (ts->reg != reg) { 3078 tcg_out_mov(s, ts->type, reg, ts->reg); 3079 } 3080 } else { 3081 TCGRegSet arg_set = 0; 3082 3083 tcg_regset_set_reg(arg_set, reg); 3084 temp_load(s, ts, arg_set, allocated_regs); 3085 } 3086 3087 tcg_regset_set_reg(allocated_regs, reg); 3088 } 3089 } 3090 3091 /* mark dead temporaries and free the associated registers */ 3092 for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) { 3093 if (IS_DEAD_ARG(i)) { 3094 temp_dead(s, arg_temp(op->args[i])); 3095 } 3096 } 3097 3098 /* clobber call registers */ 3099 for (i = 0; i < TCG_TARGET_NB_REGS; i++) { 3100 if (tcg_regset_test_reg(tcg_target_call_clobber_regs, i)) { 3101 tcg_reg_free(s, i, allocated_regs); 3102 } 3103 } 3104 3105 /* Save globals if they might be written by the helper, sync them if 3106 they might be read. */ 3107 if (flags & TCG_CALL_NO_READ_GLOBALS) { 3108 /* Nothing to do */ 3109 } else if (flags & TCG_CALL_NO_WRITE_GLOBALS) { 3110 sync_globals(s, allocated_regs); 3111 } else { 3112 save_globals(s, allocated_regs); 3113 } 3114 3115 tcg_out_call(s, func_addr); 3116 3117 /* assign output registers and emit moves if needed */ 3118 for(i = 0; i < nb_oargs; i++) { 3119 arg = op->args[i]; 3120 ts = arg_temp(arg); 3121 reg = tcg_target_call_oarg_regs[i]; 3122 tcg_debug_assert(s->reg_to_temp[reg] == NULL); 3123 3124 if (ts->fixed_reg) { 3125 if (ts->reg != reg) { 3126 tcg_out_mov(s, ts->type, ts->reg, reg); 3127 } 3128 } else { 3129 if (ts->val_type == TEMP_VAL_REG) { 3130 s->reg_to_temp[ts->reg] = NULL; 3131 } 3132 ts->val_type = TEMP_VAL_REG; 3133 ts->reg = reg; 3134 ts->mem_coherent = 0; 3135 s->reg_to_temp[reg] = ts; 3136 if (NEED_SYNC_ARG(i)) { 3137 temp_sync(s, ts, allocated_regs, IS_DEAD_ARG(i)); 3138 } else if (IS_DEAD_ARG(i)) { 3139 temp_dead(s, ts); 3140 } 3141 } 3142 } 3143 } 3144 3145 #ifdef CONFIG_PROFILER 3146 3147 /* avoid copy/paste errors */ 3148 #define PROF_ADD(to, from, field) \ 3149 do { \ 3150 (to)->field += atomic_read(&((from)->field)); \ 3151 } while (0) 3152 3153 #define PROF_MAX(to, from, field) \ 3154 do { \ 3155 typeof((from)->field) val__ = atomic_read(&((from)->field)); \ 3156 if (val__ > (to)->field) { \ 3157 (to)->field = val__; \ 3158 } \ 3159 } while (0) 3160 3161 /* Pass in a zero'ed @prof */ 3162 static inline 3163 void tcg_profile_snapshot(TCGProfile *prof, bool counters, bool table) 3164 { 3165 unsigned int n_ctxs = atomic_read(&n_tcg_ctxs); 3166 unsigned int i; 3167 3168 for (i = 0; i < n_ctxs; i++) { 3169 TCGContext *s = atomic_read(&tcg_ctxs[i]); 3170 const TCGProfile *orig = &s->prof; 3171 3172 if (counters) { 3173 PROF_ADD(prof, orig, tb_count1); 3174 PROF_ADD(prof, orig, tb_count); 3175 PROF_ADD(prof, orig, op_count); 3176 PROF_MAX(prof, orig, op_count_max); 3177 PROF_ADD(prof, orig, temp_count); 3178 PROF_MAX(prof, orig, temp_count_max); 3179 PROF_ADD(prof, orig, del_op_count); 3180 PROF_ADD(prof, orig, code_in_len); 3181 PROF_ADD(prof, orig, code_out_len); 3182 PROF_ADD(prof, orig, search_out_len); 3183 PROF_ADD(prof, orig, interm_time); 3184 PROF_ADD(prof, orig, code_time); 3185 PROF_ADD(prof, orig, la_time); 3186 PROF_ADD(prof, orig, opt_time); 3187 PROF_ADD(prof, orig, restore_count); 3188 PROF_ADD(prof, orig, restore_time); 3189 } 3190 if (table) { 3191 int i; 3192 3193 for (i = 0; i < NB_OPS; i++) { 3194 PROF_ADD(prof, orig, table_op_count[i]); 3195 } 3196 } 3197 } 3198 } 3199 3200 #undef PROF_ADD 3201 #undef PROF_MAX 3202 3203 static void tcg_profile_snapshot_counters(TCGProfile *prof) 3204 { 3205 tcg_profile_snapshot(prof, true, false); 3206 } 3207 3208 static void tcg_profile_snapshot_table(TCGProfile *prof) 3209 { 3210 tcg_profile_snapshot(prof, false, true); 3211 } 3212 3213 void tcg_dump_op_count(FILE *f, fprintf_function cpu_fprintf) 3214 { 3215 TCGProfile prof = {}; 3216 int i; 3217 3218 tcg_profile_snapshot_table(&prof); 3219 for (i = 0; i < NB_OPS; i++) { 3220 cpu_fprintf(f, "%s %" PRId64 "\n", tcg_op_defs[i].name, 3221 prof.table_op_count[i]); 3222 } 3223 } 3224 #else 3225 void tcg_dump_op_count(FILE *f, fprintf_function cpu_fprintf) 3226 { 3227 cpu_fprintf(f, "[TCG profiler not compiled]\n"); 3228 } 3229 #endif 3230 3231 3232 int tcg_gen_code(TCGContext *s, TranslationBlock *tb) 3233 { 3234 #ifdef CONFIG_PROFILER 3235 TCGProfile *prof = &s->prof; 3236 #endif 3237 int i, num_insns; 3238 TCGOp *op; 3239 3240 #ifdef CONFIG_PROFILER 3241 { 3242 int n; 3243 3244 QTAILQ_FOREACH(op, &s->ops, link) { 3245 n++; 3246 } 3247 atomic_set(&prof->op_count, prof->op_count + n); 3248 if (n > prof->op_count_max) { 3249 atomic_set(&prof->op_count_max, n); 3250 } 3251 3252 n = s->nb_temps; 3253 atomic_set(&prof->temp_count, prof->temp_count + n); 3254 if (n > prof->temp_count_max) { 3255 atomic_set(&prof->temp_count_max, n); 3256 } 3257 } 3258 #endif 3259 3260 #ifdef DEBUG_DISAS 3261 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP) 3262 && qemu_log_in_addr_range(tb->pc))) { 3263 qemu_log_lock(); 3264 qemu_log("OP:\n"); 3265 tcg_dump_ops(s); 3266 qemu_log("\n"); 3267 qemu_log_unlock(); 3268 } 3269 #endif 3270 3271 #ifdef CONFIG_PROFILER 3272 atomic_set(&prof->opt_time, prof->opt_time - profile_getclock()); 3273 #endif 3274 3275 #ifdef USE_TCG_OPTIMIZATIONS 3276 tcg_optimize(s); 3277 #endif 3278 3279 #ifdef CONFIG_PROFILER 3280 atomic_set(&prof->opt_time, prof->opt_time + profile_getclock()); 3281 atomic_set(&prof->la_time, prof->la_time - profile_getclock()); 3282 #endif 3283 3284 liveness_pass_1(s); 3285 3286 if (s->nb_indirects > 0) { 3287 #ifdef DEBUG_DISAS 3288 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_IND) 3289 && qemu_log_in_addr_range(tb->pc))) { 3290 qemu_log_lock(); 3291 qemu_log("OP before indirect lowering:\n"); 3292 tcg_dump_ops(s); 3293 qemu_log("\n"); 3294 qemu_log_unlock(); 3295 } 3296 #endif 3297 /* Replace indirect temps with direct temps. */ 3298 if (liveness_pass_2(s)) { 3299 /* If changes were made, re-run liveness. */ 3300 liveness_pass_1(s); 3301 } 3302 } 3303 3304 #ifdef CONFIG_PROFILER 3305 atomic_set(&prof->la_time, prof->la_time + profile_getclock()); 3306 #endif 3307 3308 #ifdef DEBUG_DISAS 3309 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT) 3310 && qemu_log_in_addr_range(tb->pc))) { 3311 qemu_log_lock(); 3312 qemu_log("OP after optimization and liveness analysis:\n"); 3313 tcg_dump_ops(s); 3314 qemu_log("\n"); 3315 qemu_log_unlock(); 3316 } 3317 #endif 3318 3319 tcg_reg_alloc_start(s); 3320 3321 s->code_buf = tb->tc.ptr; 3322 s->code_ptr = tb->tc.ptr; 3323 3324 #ifdef TCG_TARGET_NEED_LDST_LABELS 3325 s->ldst_labels = NULL; 3326 #endif 3327 #ifdef TCG_TARGET_NEED_POOL_LABELS 3328 s->pool_labels = NULL; 3329 #endif 3330 3331 num_insns = -1; 3332 QTAILQ_FOREACH(op, &s->ops, link) { 3333 TCGOpcode opc = op->opc; 3334 3335 #ifdef CONFIG_PROFILER 3336 atomic_set(&prof->table_op_count[opc], prof->table_op_count[opc] + 1); 3337 #endif 3338 3339 switch (opc) { 3340 case INDEX_op_mov_i32: 3341 case INDEX_op_mov_i64: 3342 case INDEX_op_mov_vec: 3343 tcg_reg_alloc_mov(s, op); 3344 break; 3345 case INDEX_op_movi_i32: 3346 case INDEX_op_movi_i64: 3347 case INDEX_op_dupi_vec: 3348 tcg_reg_alloc_movi(s, op); 3349 break; 3350 case INDEX_op_insn_start: 3351 if (num_insns >= 0) { 3352 s->gen_insn_end_off[num_insns] = tcg_current_code_size(s); 3353 } 3354 num_insns++; 3355 for (i = 0; i < TARGET_INSN_START_WORDS; ++i) { 3356 target_ulong a; 3357 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS 3358 a = deposit64(op->args[i * 2], 32, 32, op->args[i * 2 + 1]); 3359 #else 3360 a = op->args[i]; 3361 #endif 3362 s->gen_insn_data[num_insns][i] = a; 3363 } 3364 break; 3365 case INDEX_op_discard: 3366 temp_dead(s, arg_temp(op->args[0])); 3367 break; 3368 case INDEX_op_set_label: 3369 tcg_reg_alloc_bb_end(s, s->reserved_regs); 3370 tcg_out_label(s, arg_label(op->args[0]), s->code_ptr); 3371 break; 3372 case INDEX_op_call: 3373 tcg_reg_alloc_call(s, op); 3374 break; 3375 default: 3376 /* Sanity check that we've not introduced any unhandled opcodes. */ 3377 tcg_debug_assert(tcg_op_supported(opc)); 3378 /* Note: in order to speed up the code, it would be much 3379 faster to have specialized register allocator functions for 3380 some common argument patterns */ 3381 tcg_reg_alloc_op(s, op); 3382 break; 3383 } 3384 #ifdef CONFIG_DEBUG_TCG 3385 check_regs(s); 3386 #endif 3387 /* Test for (pending) buffer overflow. The assumption is that any 3388 one operation beginning below the high water mark cannot overrun 3389 the buffer completely. Thus we can test for overflow after 3390 generating code without having to check during generation. */ 3391 if (unlikely((void *)s->code_ptr > s->code_gen_highwater)) { 3392 return -1; 3393 } 3394 } 3395 tcg_debug_assert(num_insns >= 0); 3396 s->gen_insn_end_off[num_insns] = tcg_current_code_size(s); 3397 3398 /* Generate TB finalization at the end of block */ 3399 #ifdef TCG_TARGET_NEED_LDST_LABELS 3400 if (!tcg_out_ldst_finalize(s)) { 3401 return -1; 3402 } 3403 #endif 3404 #ifdef TCG_TARGET_NEED_POOL_LABELS 3405 if (!tcg_out_pool_finalize(s)) { 3406 return -1; 3407 } 3408 #endif 3409 3410 /* flush instruction cache */ 3411 flush_icache_range((uintptr_t)s->code_buf, (uintptr_t)s->code_ptr); 3412 3413 return tcg_current_code_size(s); 3414 } 3415 3416 #ifdef CONFIG_PROFILER 3417 void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf) 3418 { 3419 TCGProfile prof = {}; 3420 const TCGProfile *s; 3421 int64_t tb_count; 3422 int64_t tb_div_count; 3423 int64_t tot; 3424 3425 tcg_profile_snapshot_counters(&prof); 3426 s = &prof; 3427 tb_count = s->tb_count; 3428 tb_div_count = tb_count ? tb_count : 1; 3429 tot = s->interm_time + s->code_time; 3430 3431 cpu_fprintf(f, "JIT cycles %" PRId64 " (%0.3f s at 2.4 GHz)\n", 3432 tot, tot / 2.4e9); 3433 cpu_fprintf(f, "translated TBs %" PRId64 " (aborted=%" PRId64 " %0.1f%%)\n", 3434 tb_count, s->tb_count1 - tb_count, 3435 (double)(s->tb_count1 - s->tb_count) 3436 / (s->tb_count1 ? s->tb_count1 : 1) * 100.0); 3437 cpu_fprintf(f, "avg ops/TB %0.1f max=%d\n", 3438 (double)s->op_count / tb_div_count, s->op_count_max); 3439 cpu_fprintf(f, "deleted ops/TB %0.2f\n", 3440 (double)s->del_op_count / tb_div_count); 3441 cpu_fprintf(f, "avg temps/TB %0.2f max=%d\n", 3442 (double)s->temp_count / tb_div_count, s->temp_count_max); 3443 cpu_fprintf(f, "avg host code/TB %0.1f\n", 3444 (double)s->code_out_len / tb_div_count); 3445 cpu_fprintf(f, "avg search data/TB %0.1f\n", 3446 (double)s->search_out_len / tb_div_count); 3447 3448 cpu_fprintf(f, "cycles/op %0.1f\n", 3449 s->op_count ? (double)tot / s->op_count : 0); 3450 cpu_fprintf(f, "cycles/in byte %0.1f\n", 3451 s->code_in_len ? (double)tot / s->code_in_len : 0); 3452 cpu_fprintf(f, "cycles/out byte %0.1f\n", 3453 s->code_out_len ? (double)tot / s->code_out_len : 0); 3454 cpu_fprintf(f, "cycles/search byte %0.1f\n", 3455 s->search_out_len ? (double)tot / s->search_out_len : 0); 3456 if (tot == 0) { 3457 tot = 1; 3458 } 3459 cpu_fprintf(f, " gen_interm time %0.1f%%\n", 3460 (double)s->interm_time / tot * 100.0); 3461 cpu_fprintf(f, " gen_code time %0.1f%%\n", 3462 (double)s->code_time / tot * 100.0); 3463 cpu_fprintf(f, "optim./code time %0.1f%%\n", 3464 (double)s->opt_time / (s->code_time ? s->code_time : 1) 3465 * 100.0); 3466 cpu_fprintf(f, "liveness/code time %0.1f%%\n", 3467 (double)s->la_time / (s->code_time ? s->code_time : 1) * 100.0); 3468 cpu_fprintf(f, "cpu_restore count %" PRId64 "\n", 3469 s->restore_count); 3470 cpu_fprintf(f, " avg cycles %0.1f\n", 3471 s->restore_count ? (double)s->restore_time / s->restore_count : 0); 3472 } 3473 #else 3474 void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf) 3475 { 3476 cpu_fprintf(f, "[TCG profiler not compiled]\n"); 3477 } 3478 #endif 3479 3480 #ifdef ELF_HOST_MACHINE 3481 /* In order to use this feature, the backend needs to do three things: 3482 3483 (1) Define ELF_HOST_MACHINE to indicate both what value to 3484 put into the ELF image and to indicate support for the feature. 3485 3486 (2) Define tcg_register_jit. This should create a buffer containing 3487 the contents of a .debug_frame section that describes the post- 3488 prologue unwind info for the tcg machine. 3489 3490 (3) Call tcg_register_jit_int, with the constructed .debug_frame. 3491 */ 3492 3493 /* Begin GDB interface. THE FOLLOWING MUST MATCH GDB DOCS. */ 3494 typedef enum { 3495 JIT_NOACTION = 0, 3496 JIT_REGISTER_FN, 3497 JIT_UNREGISTER_FN 3498 } jit_actions_t; 3499 3500 struct jit_code_entry { 3501 struct jit_code_entry *next_entry; 3502 struct jit_code_entry *prev_entry; 3503 const void *symfile_addr; 3504 uint64_t symfile_size; 3505 }; 3506 3507 struct jit_descriptor { 3508 uint32_t version; 3509 uint32_t action_flag; 3510 struct jit_code_entry *relevant_entry; 3511 struct jit_code_entry *first_entry; 3512 }; 3513 3514 void __jit_debug_register_code(void) __attribute__((noinline)); 3515 void __jit_debug_register_code(void) 3516 { 3517 asm(""); 3518 } 3519 3520 /* Must statically initialize the version, because GDB may check 3521 the version before we can set it. */ 3522 struct jit_descriptor __jit_debug_descriptor = { 1, 0, 0, 0 }; 3523 3524 /* End GDB interface. */ 3525 3526 static int find_string(const char *strtab, const char *str) 3527 { 3528 const char *p = strtab + 1; 3529 3530 while (1) { 3531 if (strcmp(p, str) == 0) { 3532 return p - strtab; 3533 } 3534 p += strlen(p) + 1; 3535 } 3536 } 3537 3538 static void tcg_register_jit_int(void *buf_ptr, size_t buf_size, 3539 const void *debug_frame, 3540 size_t debug_frame_size) 3541 { 3542 struct __attribute__((packed)) DebugInfo { 3543 uint32_t len; 3544 uint16_t version; 3545 uint32_t abbrev; 3546 uint8_t ptr_size; 3547 uint8_t cu_die; 3548 uint16_t cu_lang; 3549 uintptr_t cu_low_pc; 3550 uintptr_t cu_high_pc; 3551 uint8_t fn_die; 3552 char fn_name[16]; 3553 uintptr_t fn_low_pc; 3554 uintptr_t fn_high_pc; 3555 uint8_t cu_eoc; 3556 }; 3557 3558 struct ElfImage { 3559 ElfW(Ehdr) ehdr; 3560 ElfW(Phdr) phdr; 3561 ElfW(Shdr) shdr[7]; 3562 ElfW(Sym) sym[2]; 3563 struct DebugInfo di; 3564 uint8_t da[24]; 3565 char str[80]; 3566 }; 3567 3568 struct ElfImage *img; 3569 3570 static const struct ElfImage img_template = { 3571 .ehdr = { 3572 .e_ident[EI_MAG0] = ELFMAG0, 3573 .e_ident[EI_MAG1] = ELFMAG1, 3574 .e_ident[EI_MAG2] = ELFMAG2, 3575 .e_ident[EI_MAG3] = ELFMAG3, 3576 .e_ident[EI_CLASS] = ELF_CLASS, 3577 .e_ident[EI_DATA] = ELF_DATA, 3578 .e_ident[EI_VERSION] = EV_CURRENT, 3579 .e_type = ET_EXEC, 3580 .e_machine = ELF_HOST_MACHINE, 3581 .e_version = EV_CURRENT, 3582 .e_phoff = offsetof(struct ElfImage, phdr), 3583 .e_shoff = offsetof(struct ElfImage, shdr), 3584 .e_ehsize = sizeof(ElfW(Shdr)), 3585 .e_phentsize = sizeof(ElfW(Phdr)), 3586 .e_phnum = 1, 3587 .e_shentsize = sizeof(ElfW(Shdr)), 3588 .e_shnum = ARRAY_SIZE(img->shdr), 3589 .e_shstrndx = ARRAY_SIZE(img->shdr) - 1, 3590 #ifdef ELF_HOST_FLAGS 3591 .e_flags = ELF_HOST_FLAGS, 3592 #endif 3593 #ifdef ELF_OSABI 3594 .e_ident[EI_OSABI] = ELF_OSABI, 3595 #endif 3596 }, 3597 .phdr = { 3598 .p_type = PT_LOAD, 3599 .p_flags = PF_X, 3600 }, 3601 .shdr = { 3602 [0] = { .sh_type = SHT_NULL }, 3603 /* Trick: The contents of code_gen_buffer are not present in 3604 this fake ELF file; that got allocated elsewhere. Therefore 3605 we mark .text as SHT_NOBITS (similar to .bss) so that readers 3606 will not look for contents. We can record any address. */ 3607 [1] = { /* .text */ 3608 .sh_type = SHT_NOBITS, 3609 .sh_flags = SHF_EXECINSTR | SHF_ALLOC, 3610 }, 3611 [2] = { /* .debug_info */ 3612 .sh_type = SHT_PROGBITS, 3613 .sh_offset = offsetof(struct ElfImage, di), 3614 .sh_size = sizeof(struct DebugInfo), 3615 }, 3616 [3] = { /* .debug_abbrev */ 3617 .sh_type = SHT_PROGBITS, 3618 .sh_offset = offsetof(struct ElfImage, da), 3619 .sh_size = sizeof(img->da), 3620 }, 3621 [4] = { /* .debug_frame */ 3622 .sh_type = SHT_PROGBITS, 3623 .sh_offset = sizeof(struct ElfImage), 3624 }, 3625 [5] = { /* .symtab */ 3626 .sh_type = SHT_SYMTAB, 3627 .sh_offset = offsetof(struct ElfImage, sym), 3628 .sh_size = sizeof(img->sym), 3629 .sh_info = 1, 3630 .sh_link = ARRAY_SIZE(img->shdr) - 1, 3631 .sh_entsize = sizeof(ElfW(Sym)), 3632 }, 3633 [6] = { /* .strtab */ 3634 .sh_type = SHT_STRTAB, 3635 .sh_offset = offsetof(struct ElfImage, str), 3636 .sh_size = sizeof(img->str), 3637 } 3638 }, 3639 .sym = { 3640 [1] = { /* code_gen_buffer */ 3641 .st_info = ELF_ST_INFO(STB_GLOBAL, STT_FUNC), 3642 .st_shndx = 1, 3643 } 3644 }, 3645 .di = { 3646 .len = sizeof(struct DebugInfo) - 4, 3647 .version = 2, 3648 .ptr_size = sizeof(void *), 3649 .cu_die = 1, 3650 .cu_lang = 0x8001, /* DW_LANG_Mips_Assembler */ 3651 .fn_die = 2, 3652 .fn_name = "code_gen_buffer" 3653 }, 3654 .da = { 3655 1, /* abbrev number (the cu) */ 3656 0x11, 1, /* DW_TAG_compile_unit, has children */ 3657 0x13, 0x5, /* DW_AT_language, DW_FORM_data2 */ 3658 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */ 3659 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */ 3660 0, 0, /* end of abbrev */ 3661 2, /* abbrev number (the fn) */ 3662 0x2e, 0, /* DW_TAG_subprogram, no children */ 3663 0x3, 0x8, /* DW_AT_name, DW_FORM_string */ 3664 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */ 3665 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */ 3666 0, 0, /* end of abbrev */ 3667 0 /* no more abbrev */ 3668 }, 3669 .str = "\0" ".text\0" ".debug_info\0" ".debug_abbrev\0" 3670 ".debug_frame\0" ".symtab\0" ".strtab\0" "code_gen_buffer", 3671 }; 3672 3673 /* We only need a single jit entry; statically allocate it. */ 3674 static struct jit_code_entry one_entry; 3675 3676 uintptr_t buf = (uintptr_t)buf_ptr; 3677 size_t img_size = sizeof(struct ElfImage) + debug_frame_size; 3678 DebugFrameHeader *dfh; 3679 3680 img = g_malloc(img_size); 3681 *img = img_template; 3682 3683 img->phdr.p_vaddr = buf; 3684 img->phdr.p_paddr = buf; 3685 img->phdr.p_memsz = buf_size; 3686 3687 img->shdr[1].sh_name = find_string(img->str, ".text"); 3688 img->shdr[1].sh_addr = buf; 3689 img->shdr[1].sh_size = buf_size; 3690 3691 img->shdr[2].sh_name = find_string(img->str, ".debug_info"); 3692 img->shdr[3].sh_name = find_string(img->str, ".debug_abbrev"); 3693 3694 img->shdr[4].sh_name = find_string(img->str, ".debug_frame"); 3695 img->shdr[4].sh_size = debug_frame_size; 3696 3697 img->shdr[5].sh_name = find_string(img->str, ".symtab"); 3698 img->shdr[6].sh_name = find_string(img->str, ".strtab"); 3699 3700 img->sym[1].st_name = find_string(img->str, "code_gen_buffer"); 3701 img->sym[1].st_value = buf; 3702 img->sym[1].st_size = buf_size; 3703 3704 img->di.cu_low_pc = buf; 3705 img->di.cu_high_pc = buf + buf_size; 3706 img->di.fn_low_pc = buf; 3707 img->di.fn_high_pc = buf + buf_size; 3708 3709 dfh = (DebugFrameHeader *)(img + 1); 3710 memcpy(dfh, debug_frame, debug_frame_size); 3711 dfh->fde.func_start = buf; 3712 dfh->fde.func_len = buf_size; 3713 3714 #ifdef DEBUG_JIT 3715 /* Enable this block to be able to debug the ELF image file creation. 3716 One can use readelf, objdump, or other inspection utilities. */ 3717 { 3718 FILE *f = fopen("/tmp/qemu.jit", "w+b"); 3719 if (f) { 3720 if (fwrite(img, img_size, 1, f) != img_size) { 3721 /* Avoid stupid unused return value warning for fwrite. */ 3722 } 3723 fclose(f); 3724 } 3725 } 3726 #endif 3727 3728 one_entry.symfile_addr = img; 3729 one_entry.symfile_size = img_size; 3730 3731 __jit_debug_descriptor.action_flag = JIT_REGISTER_FN; 3732 __jit_debug_descriptor.relevant_entry = &one_entry; 3733 __jit_debug_descriptor.first_entry = &one_entry; 3734 __jit_debug_register_code(); 3735 } 3736 #else 3737 /* No support for the feature. Provide the entry point expected by exec.c, 3738 and implement the internal function we declared earlier. */ 3739 3740 static void tcg_register_jit_int(void *buf, size_t size, 3741 const void *debug_frame, 3742 size_t debug_frame_size) 3743 { 3744 } 3745 3746 void tcg_register_jit(void *buf, size_t buf_size) 3747 { 3748 } 3749 #endif /* ELF_HOST_MACHINE */ 3750 3751 #if !TCG_TARGET_MAYBE_vec 3752 void tcg_expand_vec_op(TCGOpcode o, TCGType t, unsigned e, TCGArg a0, ...) 3753 { 3754 g_assert_not_reached(); 3755 } 3756 #endif 3757