1 /* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "tcg/tcg.h" 27 #include "tcg/tcg-temp-internal.h" 28 #include "tcg/tcg-op-common.h" 29 #include "exec/translation-block.h" 30 #include "exec/plugin-gen.h" 31 #include "tcg-internal.h" 32 #include "tcg-has.h" 33 34 /* 35 * Encourage the compiler to tail-call to a function, rather than inlining. 36 * Minimizes code size across 99 bottles of beer on the wall. 37 */ 38 #define NI __attribute__((noinline)) 39 40 TCGOp * NI tcg_gen_op1(TCGOpcode opc, TCGType type, TCGArg a1) 41 { 42 TCGOp *op = tcg_emit_op(opc, 1); 43 TCGOP_TYPE(op) = type; 44 op->args[0] = a1; 45 return op; 46 } 47 48 TCGOp * NI tcg_gen_op2(TCGOpcode opc, TCGType type, TCGArg a1, TCGArg a2) 49 { 50 TCGOp *op = tcg_emit_op(opc, 2); 51 TCGOP_TYPE(op) = type; 52 op->args[0] = a1; 53 op->args[1] = a2; 54 return op; 55 } 56 57 TCGOp * NI tcg_gen_op3(TCGOpcode opc, TCGType type, TCGArg a1, 58 TCGArg a2, TCGArg a3) 59 { 60 TCGOp *op = tcg_emit_op(opc, 3); 61 TCGOP_TYPE(op) = type; 62 op->args[0] = a1; 63 op->args[1] = a2; 64 op->args[2] = a3; 65 return op; 66 } 67 68 TCGOp * NI tcg_gen_op4(TCGOpcode opc, TCGType type, TCGArg a1, TCGArg a2, 69 TCGArg a3, TCGArg a4) 70 { 71 TCGOp *op = tcg_emit_op(opc, 4); 72 TCGOP_TYPE(op) = type; 73 op->args[0] = a1; 74 op->args[1] = a2; 75 op->args[2] = a3; 76 op->args[3] = a4; 77 return op; 78 } 79 80 TCGOp * NI tcg_gen_op5(TCGOpcode opc, TCGType type, TCGArg a1, TCGArg a2, 81 TCGArg a3, TCGArg a4, TCGArg a5) 82 { 83 TCGOp *op = tcg_emit_op(opc, 5); 84 TCGOP_TYPE(op) = type; 85 op->args[0] = a1; 86 op->args[1] = a2; 87 op->args[2] = a3; 88 op->args[3] = a4; 89 op->args[4] = a5; 90 return op; 91 } 92 93 TCGOp * NI tcg_gen_op6(TCGOpcode opc, TCGType type, TCGArg a1, TCGArg a2, 94 TCGArg a3, TCGArg a4, TCGArg a5, TCGArg a6) 95 { 96 TCGOp *op = tcg_emit_op(opc, 6); 97 TCGOP_TYPE(op) = type; 98 op->args[0] = a1; 99 op->args[1] = a2; 100 op->args[2] = a3; 101 op->args[3] = a4; 102 op->args[4] = a5; 103 op->args[5] = a6; 104 return op; 105 } 106 107 /* 108 * With CONFIG_DEBUG_TCG, tcgv_*_tmp via tcgv_*_arg, is an out-of-line 109 * assertion check. Force tail calls to avoid too much code expansion. 110 */ 111 #ifdef CONFIG_DEBUG_TCG 112 # define DNI NI 113 #else 114 # define DNI 115 #endif 116 117 static void DNI tcg_gen_op1_i32(TCGOpcode opc, TCGType type, TCGv_i32 a1) 118 { 119 tcg_gen_op1(opc, type, tcgv_i32_arg(a1)); 120 } 121 122 static void DNI tcg_gen_op1_i64(TCGOpcode opc, TCGType type, TCGv_i64 a1) 123 { 124 tcg_gen_op1(opc, type, tcgv_i64_arg(a1)); 125 } 126 127 static TCGOp * DNI tcg_gen_op1i(TCGOpcode opc, TCGType type, TCGArg a1) 128 { 129 return tcg_gen_op1(opc, type, a1); 130 } 131 132 static void DNI tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2) 133 { 134 tcg_gen_op2(opc, TCG_TYPE_I32, tcgv_i32_arg(a1), tcgv_i32_arg(a2)); 135 } 136 137 static void DNI tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2) 138 { 139 tcg_gen_op2(opc, TCG_TYPE_I64, tcgv_i64_arg(a1), tcgv_i64_arg(a2)); 140 } 141 142 static void DNI tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 a1, 143 TCGv_i32 a2, TCGv_i32 a3) 144 { 145 tcg_gen_op3(opc, TCG_TYPE_I32, tcgv_i32_arg(a1), 146 tcgv_i32_arg(a2), tcgv_i32_arg(a3)); 147 } 148 149 static void DNI tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 a1, 150 TCGv_i64 a2, TCGv_i64 a3) 151 { 152 tcg_gen_op3(opc, TCG_TYPE_I64, tcgv_i64_arg(a1), 153 tcgv_i64_arg(a2), tcgv_i64_arg(a3)); 154 } 155 156 static void DNI tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 a1, 157 TCGv_i32 a2, TCGArg a3) 158 { 159 tcg_gen_op3(opc, TCG_TYPE_I32, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3); 160 } 161 162 static void DNI tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 a1, 163 TCGv_i64 a2, TCGArg a3) 164 { 165 tcg_gen_op3(opc, TCG_TYPE_I64, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3); 166 } 167 168 static void DNI tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val, 169 TCGv_ptr base, TCGArg offset) 170 { 171 tcg_gen_op3(opc, TCG_TYPE_I32, tcgv_i32_arg(val), 172 tcgv_ptr_arg(base), offset); 173 } 174 175 static void DNI tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val, 176 TCGv_ptr base, TCGArg offset) 177 { 178 tcg_gen_op3(opc, TCG_TYPE_I64, tcgv_i64_arg(val), 179 tcgv_ptr_arg(base), offset); 180 } 181 182 static void DNI tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, 183 TCGv_i32 a3, TCGv_i32 a4) 184 { 185 tcg_gen_op4(opc, TCG_TYPE_I32, tcgv_i32_arg(a1), tcgv_i32_arg(a2), 186 tcgv_i32_arg(a3), tcgv_i32_arg(a4)); 187 } 188 189 static void DNI tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, 190 TCGv_i64 a3, TCGv_i64 a4) 191 { 192 tcg_gen_op4(opc, TCG_TYPE_I64, tcgv_i64_arg(a1), tcgv_i64_arg(a2), 193 tcgv_i64_arg(a3), tcgv_i64_arg(a4)); 194 } 195 196 static void DNI tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, 197 TCGv_i32 a3, TCGArg a4) 198 { 199 tcg_gen_op4(opc, TCG_TYPE_I32, tcgv_i32_arg(a1), tcgv_i32_arg(a2), 200 tcgv_i32_arg(a3), a4); 201 } 202 203 static void DNI tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, 204 TCGv_i64 a3, TCGArg a4) 205 { 206 tcg_gen_op4(opc, TCG_TYPE_I64, tcgv_i64_arg(a1), tcgv_i64_arg(a2), 207 tcgv_i64_arg(a3), a4); 208 } 209 210 static TCGOp * DNI tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, 211 TCGArg a3, TCGArg a4) 212 { 213 return tcg_gen_op4(opc, TCG_TYPE_I32, 214 tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3, a4); 215 } 216 217 static TCGOp * DNI tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, 218 TCGArg a3, TCGArg a4) 219 { 220 return tcg_gen_op4(opc, TCG_TYPE_I64, 221 tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3, a4); 222 } 223 224 static void DNI tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, 225 TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5) 226 { 227 tcg_gen_op5(opc, TCG_TYPE_I32, tcgv_i32_arg(a1), tcgv_i32_arg(a2), 228 tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5)); 229 } 230 231 static void DNI tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, 232 TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5) 233 { 234 tcg_gen_op5(opc, TCG_TYPE_I64, tcgv_i64_arg(a1), tcgv_i64_arg(a2), 235 tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5)); 236 } 237 238 static void DNI tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, 239 TCGv_i32 a3, TCGArg a4, TCGArg a5) 240 { 241 tcg_gen_op5(opc, TCG_TYPE_I32, tcgv_i32_arg(a1), tcgv_i32_arg(a2), 242 tcgv_i32_arg(a3), a4, a5); 243 } 244 245 static void DNI tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, 246 TCGv_i64 a3, TCGArg a4, TCGArg a5) 247 { 248 tcg_gen_op5(opc, TCG_TYPE_I64, tcgv_i64_arg(a1), tcgv_i64_arg(a2), 249 tcgv_i64_arg(a3), a4, a5); 250 } 251 252 static void DNI tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, 253 TCGv_i32 a3, TCGv_i32 a4, 254 TCGv_i32 a5, TCGv_i32 a6) 255 { 256 tcg_gen_op6(opc, TCG_TYPE_I32, tcgv_i32_arg(a1), tcgv_i32_arg(a2), 257 tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5), 258 tcgv_i32_arg(a6)); 259 } 260 261 static void DNI tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, 262 TCGv_i64 a3, TCGv_i64 a4, 263 TCGv_i64 a5, TCGv_i64 a6) 264 { 265 tcg_gen_op6(opc, TCG_TYPE_I64, tcgv_i64_arg(a1), tcgv_i64_arg(a2), 266 tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5), 267 tcgv_i64_arg(a6)); 268 } 269 270 static void DNI tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, 271 TCGv_i32 a3, TCGv_i32 a4, 272 TCGv_i32 a5, TCGArg a6) 273 { 274 tcg_gen_op6(opc, TCG_TYPE_I32, tcgv_i32_arg(a1), tcgv_i32_arg(a2), 275 tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5), a6); 276 } 277 278 static void DNI tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, 279 TCGv_i64 a3, TCGv_i64 a4, 280 TCGv_i64 a5, TCGArg a6) 281 { 282 tcg_gen_op6(opc, TCG_TYPE_I64, tcgv_i64_arg(a1), tcgv_i64_arg(a2), 283 tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5), a6); 284 } 285 286 static TCGOp * DNI tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, 287 TCGv_i32 a3, TCGv_i32 a4, 288 TCGArg a5, TCGArg a6) 289 { 290 return tcg_gen_op6(opc, TCG_TYPE_I32, tcgv_i32_arg(a1), tcgv_i32_arg(a2), 291 tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5, a6); 292 } 293 294 /* Generic ops. */ 295 296 void gen_set_label(TCGLabel *l) 297 { 298 l->present = 1; 299 tcg_gen_op1(INDEX_op_set_label, 0, label_arg(l)); 300 } 301 302 static void add_as_label_use(TCGLabel *l, TCGOp *op) 303 { 304 TCGLabelUse *u = tcg_malloc(sizeof(TCGLabelUse)); 305 306 u->op = op; 307 QSIMPLEQ_INSERT_TAIL(&l->branches, u, next); 308 } 309 310 void tcg_gen_br(TCGLabel *l) 311 { 312 add_as_label_use(l, tcg_gen_op1(INDEX_op_br, 0, label_arg(l))); 313 } 314 315 void tcg_gen_mb(TCGBar mb_type) 316 { 317 #ifdef CONFIG_USER_ONLY 318 bool parallel = tcg_ctx->gen_tb->cflags & CF_PARALLEL; 319 #else 320 /* 321 * It is tempting to elide the barrier in a uniprocessor context. 322 * However, even with a single cpu we have i/o threads running in 323 * parallel, and lack of memory order can result in e.g. virtio 324 * queue entries being read incorrectly. 325 */ 326 bool parallel = true; 327 #endif 328 329 if (parallel) { 330 tcg_gen_op1(INDEX_op_mb, 0, mb_type); 331 } 332 } 333 334 void tcg_gen_plugin_cb(unsigned from) 335 { 336 tcg_gen_op1(INDEX_op_plugin_cb, 0, from); 337 } 338 339 void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned meminfo) 340 { 341 tcg_gen_op2(INDEX_op_plugin_mem_cb, 0, tcgv_i64_arg(addr), meminfo); 342 } 343 344 /* 32 bit ops */ 345 346 void tcg_gen_discard_i32(TCGv_i32 arg) 347 { 348 tcg_gen_op1_i32(INDEX_op_discard, TCG_TYPE_I32, arg); 349 } 350 351 void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg) 352 { 353 if (ret != arg) { 354 tcg_gen_op2_i32(INDEX_op_mov, ret, arg); 355 } 356 } 357 358 void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg) 359 { 360 tcg_gen_mov_i32(ret, tcg_constant_i32(arg)); 361 } 362 363 void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) 364 { 365 tcg_gen_op3_i32(INDEX_op_add, ret, arg1, arg2); 366 } 367 368 void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) 369 { 370 /* some cases can be optimized here */ 371 if (arg2 == 0) { 372 tcg_gen_mov_i32(ret, arg1); 373 } else { 374 tcg_gen_add_i32(ret, arg1, tcg_constant_i32(arg2)); 375 } 376 } 377 378 void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) 379 { 380 tcg_gen_op3_i32(INDEX_op_sub, ret, arg1, arg2); 381 } 382 383 void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2) 384 { 385 if (arg1 == 0) { 386 tcg_gen_neg_i32(ret, arg2); 387 } else { 388 tcg_gen_sub_i32(ret, tcg_constant_i32(arg1), arg2); 389 } 390 } 391 392 void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) 393 { 394 tcg_gen_addi_i32(ret, arg1, -arg2); 395 } 396 397 void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg) 398 { 399 tcg_gen_op2_i32(INDEX_op_neg, ret, arg); 400 } 401 402 void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) 403 { 404 tcg_gen_op3_i32(INDEX_op_and, ret, arg1, arg2); 405 } 406 407 void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) 408 { 409 /* Some cases can be optimized here. */ 410 switch (arg2) { 411 case 0: 412 tcg_gen_movi_i32(ret, 0); 413 return; 414 case -1: 415 tcg_gen_mov_i32(ret, arg1); 416 return; 417 default: 418 /* 419 * Canonicalize on extract, if valid. This aids x86 with its 420 * 2 operand MOVZBL and 2 operand AND, selecting the TCGOpcode 421 * which does not require matching operands. Other backends can 422 * trivially expand the extract to AND during code generation. 423 */ 424 if (!(arg2 & (arg2 + 1))) { 425 unsigned len = ctz32(~arg2); 426 if (TCG_TARGET_extract_valid(TCG_TYPE_I32, 0, len)) { 427 tcg_gen_extract_i32(ret, arg1, 0, len); 428 return; 429 } 430 } 431 break; 432 } 433 434 tcg_gen_and_i32(ret, arg1, tcg_constant_i32(arg2)); 435 } 436 437 void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) 438 { 439 tcg_gen_op3_i32(INDEX_op_or, ret, arg1, arg2); 440 } 441 442 void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) 443 { 444 /* Some cases can be optimized here. */ 445 if (arg2 == -1) { 446 tcg_gen_movi_i32(ret, -1); 447 } else if (arg2 == 0) { 448 tcg_gen_mov_i32(ret, arg1); 449 } else { 450 tcg_gen_or_i32(ret, arg1, tcg_constant_i32(arg2)); 451 } 452 } 453 454 void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) 455 { 456 tcg_gen_op3_i32(INDEX_op_xor, ret, arg1, arg2); 457 } 458 459 void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) 460 { 461 /* Some cases can be optimized here. */ 462 if (arg2 == 0) { 463 tcg_gen_mov_i32(ret, arg1); 464 } else if (arg2 == -1 && 465 tcg_op_supported(INDEX_op_not, TCG_TYPE_I32, 0)) { 466 /* Don't recurse with tcg_gen_not_i32. */ 467 tcg_gen_op2_i32(INDEX_op_not, ret, arg1); 468 } else { 469 tcg_gen_xor_i32(ret, arg1, tcg_constant_i32(arg2)); 470 } 471 } 472 473 void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg) 474 { 475 if (tcg_op_supported(INDEX_op_not, TCG_TYPE_I32, 0)) { 476 tcg_gen_op2_i32(INDEX_op_not, ret, arg); 477 } else { 478 tcg_gen_xori_i32(ret, arg, -1); 479 } 480 } 481 482 void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) 483 { 484 tcg_gen_op3_i32(INDEX_op_shl, ret, arg1, arg2); 485 } 486 487 void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) 488 { 489 tcg_debug_assert(arg2 >= 0 && arg2 < 32); 490 if (arg2 == 0) { 491 tcg_gen_mov_i32(ret, arg1); 492 } else { 493 tcg_gen_shl_i32(ret, arg1, tcg_constant_i32(arg2)); 494 } 495 } 496 497 void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) 498 { 499 tcg_gen_op3_i32(INDEX_op_shr, ret, arg1, arg2); 500 } 501 502 void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) 503 { 504 tcg_debug_assert(arg2 >= 0 && arg2 < 32); 505 if (arg2 == 0) { 506 tcg_gen_mov_i32(ret, arg1); 507 } else { 508 tcg_gen_shr_i32(ret, arg1, tcg_constant_i32(arg2)); 509 } 510 } 511 512 void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) 513 { 514 tcg_gen_op3_i32(INDEX_op_sar, ret, arg1, arg2); 515 } 516 517 void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) 518 { 519 tcg_debug_assert(arg2 >= 0 && arg2 < 32); 520 if (arg2 == 0) { 521 tcg_gen_mov_i32(ret, arg1); 522 } else { 523 tcg_gen_sar_i32(ret, arg1, tcg_constant_i32(arg2)); 524 } 525 } 526 527 void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLabel *l) 528 { 529 if (cond == TCG_COND_ALWAYS) { 530 tcg_gen_br(l); 531 } else if (cond != TCG_COND_NEVER) { 532 TCGOp *op = tcg_gen_op4ii_i32(INDEX_op_brcond, 533 arg1, arg2, cond, label_arg(l)); 534 add_as_label_use(l, op); 535 } 536 } 537 538 void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLabel *l) 539 { 540 if (cond == TCG_COND_ALWAYS) { 541 tcg_gen_br(l); 542 } else if (cond != TCG_COND_NEVER) { 543 tcg_gen_brcond_i32(cond, arg1, tcg_constant_i32(arg2), l); 544 } 545 } 546 547 void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret, 548 TCGv_i32 arg1, TCGv_i32 arg2) 549 { 550 if (cond == TCG_COND_ALWAYS) { 551 tcg_gen_movi_i32(ret, 1); 552 } else if (cond == TCG_COND_NEVER) { 553 tcg_gen_movi_i32(ret, 0); 554 } else { 555 tcg_gen_op4i_i32(INDEX_op_setcond, ret, arg1, arg2, cond); 556 } 557 } 558 559 void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret, 560 TCGv_i32 arg1, int32_t arg2) 561 { 562 tcg_gen_setcond_i32(cond, ret, arg1, tcg_constant_i32(arg2)); 563 } 564 565 void tcg_gen_negsetcond_i32(TCGCond cond, TCGv_i32 ret, 566 TCGv_i32 arg1, TCGv_i32 arg2) 567 { 568 if (cond == TCG_COND_ALWAYS) { 569 tcg_gen_movi_i32(ret, -1); 570 } else if (cond == TCG_COND_NEVER) { 571 tcg_gen_movi_i32(ret, 0); 572 } else { 573 tcg_gen_op4i_i32(INDEX_op_negsetcond, ret, arg1, arg2, cond); 574 } 575 } 576 577 void tcg_gen_negsetcondi_i32(TCGCond cond, TCGv_i32 ret, 578 TCGv_i32 arg1, int32_t arg2) 579 { 580 tcg_gen_negsetcond_i32(cond, ret, arg1, tcg_constant_i32(arg2)); 581 } 582 583 void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) 584 { 585 tcg_gen_op3_i32(INDEX_op_mul, ret, arg1, arg2); 586 } 587 588 void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) 589 { 590 if (arg2 == 0) { 591 tcg_gen_movi_i32(ret, 0); 592 } else if (is_power_of_2(arg2)) { 593 tcg_gen_shli_i32(ret, arg1, ctz32(arg2)); 594 } else { 595 tcg_gen_mul_i32(ret, arg1, tcg_constant_i32(arg2)); 596 } 597 } 598 599 void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) 600 { 601 if (tcg_op_supported(INDEX_op_divs, TCG_TYPE_I32, 0)) { 602 tcg_gen_op3_i32(INDEX_op_divs, ret, arg1, arg2); 603 } else if (tcg_op_supported(INDEX_op_divs2, TCG_TYPE_I32, 0)) { 604 TCGv_i32 t0 = tcg_temp_ebb_new_i32(); 605 tcg_gen_sari_i32(t0, arg1, 31); 606 tcg_gen_op5_i32(INDEX_op_divs2, ret, t0, arg1, t0, arg2); 607 tcg_temp_free_i32(t0); 608 } else { 609 gen_helper_div_i32(ret, arg1, arg2); 610 } 611 } 612 613 void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) 614 { 615 if (tcg_op_supported(INDEX_op_rems, TCG_TYPE_I32, 0)) { 616 tcg_gen_op3_i32(INDEX_op_rems, ret, arg1, arg2); 617 } else if (tcg_op_supported(INDEX_op_divs, TCG_TYPE_I32, 0)) { 618 TCGv_i32 t0 = tcg_temp_ebb_new_i32(); 619 tcg_gen_op3_i32(INDEX_op_divs, t0, arg1, arg2); 620 tcg_gen_mul_i32(t0, t0, arg2); 621 tcg_gen_sub_i32(ret, arg1, t0); 622 tcg_temp_free_i32(t0); 623 } else if (tcg_op_supported(INDEX_op_divs2, TCG_TYPE_I32, 0)) { 624 TCGv_i32 t0 = tcg_temp_ebb_new_i32(); 625 tcg_gen_sari_i32(t0, arg1, 31); 626 tcg_gen_op5_i32(INDEX_op_divs2, t0, ret, arg1, t0, arg2); 627 tcg_temp_free_i32(t0); 628 } else { 629 gen_helper_rem_i32(ret, arg1, arg2); 630 } 631 } 632 633 void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) 634 { 635 if (tcg_op_supported(INDEX_op_divu, TCG_TYPE_I32, 0)) { 636 tcg_gen_op3_i32(INDEX_op_divu, ret, arg1, arg2); 637 } else if (tcg_op_supported(INDEX_op_divu2, TCG_TYPE_I32, 0)) { 638 TCGv_i32 t0 = tcg_temp_ebb_new_i32(); 639 TCGv_i32 zero = tcg_constant_i32(0); 640 tcg_gen_op5_i32(INDEX_op_divu2, ret, t0, arg1, zero, arg2); 641 tcg_temp_free_i32(t0); 642 } else { 643 gen_helper_divu_i32(ret, arg1, arg2); 644 } 645 } 646 647 void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) 648 { 649 if (tcg_op_supported(INDEX_op_remu, TCG_TYPE_I32, 0)) { 650 tcg_gen_op3_i32(INDEX_op_remu, ret, arg1, arg2); 651 } else if (tcg_op_supported(INDEX_op_divu, TCG_TYPE_I32, 0)) { 652 TCGv_i32 t0 = tcg_temp_ebb_new_i32(); 653 tcg_gen_op3_i32(INDEX_op_divu, t0, arg1, arg2); 654 tcg_gen_mul_i32(t0, t0, arg2); 655 tcg_gen_sub_i32(ret, arg1, t0); 656 tcg_temp_free_i32(t0); 657 } else if (tcg_op_supported(INDEX_op_divu2, TCG_TYPE_I32, 0)) { 658 TCGv_i32 t0 = tcg_temp_ebb_new_i32(); 659 TCGv_i32 zero = tcg_constant_i32(0); 660 tcg_gen_op5_i32(INDEX_op_divu2, t0, ret, arg1, zero, arg2); 661 tcg_temp_free_i32(t0); 662 } else { 663 gen_helper_remu_i32(ret, arg1, arg2); 664 } 665 } 666 667 void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) 668 { 669 if (tcg_op_supported(INDEX_op_andc, TCG_TYPE_I32, 0)) { 670 tcg_gen_op3_i32(INDEX_op_andc, ret, arg1, arg2); 671 } else { 672 TCGv_i32 t0 = tcg_temp_ebb_new_i32(); 673 tcg_gen_not_i32(t0, arg2); 674 tcg_gen_and_i32(ret, arg1, t0); 675 tcg_temp_free_i32(t0); 676 } 677 } 678 679 void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) 680 { 681 if (tcg_op_supported(INDEX_op_eqv, TCG_TYPE_I32, 0)) { 682 tcg_gen_op3_i32(INDEX_op_eqv, ret, arg1, arg2); 683 } else { 684 tcg_gen_xor_i32(ret, arg1, arg2); 685 tcg_gen_not_i32(ret, ret); 686 } 687 } 688 689 void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) 690 { 691 if (tcg_op_supported(INDEX_op_nand, TCG_TYPE_I32, 0)) { 692 tcg_gen_op3_i32(INDEX_op_nand, ret, arg1, arg2); 693 } else { 694 tcg_gen_and_i32(ret, arg1, arg2); 695 tcg_gen_not_i32(ret, ret); 696 } 697 } 698 699 void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) 700 { 701 if (tcg_op_supported(INDEX_op_nor, TCG_TYPE_I32, 0)) { 702 tcg_gen_op3_i32(INDEX_op_nor, ret, arg1, arg2); 703 } else { 704 tcg_gen_or_i32(ret, arg1, arg2); 705 tcg_gen_not_i32(ret, ret); 706 } 707 } 708 709 void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) 710 { 711 if (tcg_op_supported(INDEX_op_orc, TCG_TYPE_I32, 0)) { 712 tcg_gen_op3_i32(INDEX_op_orc, ret, arg1, arg2); 713 } else { 714 TCGv_i32 t0 = tcg_temp_ebb_new_i32(); 715 tcg_gen_not_i32(t0, arg2); 716 tcg_gen_or_i32(ret, arg1, t0); 717 tcg_temp_free_i32(t0); 718 } 719 } 720 721 void tcg_gen_clz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) 722 { 723 if (tcg_op_supported(INDEX_op_clz, TCG_TYPE_I32, 0)) { 724 tcg_gen_op3_i32(INDEX_op_clz, ret, arg1, arg2); 725 } else if (tcg_op_supported(INDEX_op_clz, TCG_TYPE_I64, 0)) { 726 TCGv_i64 t1 = tcg_temp_ebb_new_i64(); 727 TCGv_i64 t2 = tcg_temp_ebb_new_i64(); 728 tcg_gen_extu_i32_i64(t1, arg1); 729 tcg_gen_extu_i32_i64(t2, arg2); 730 tcg_gen_addi_i64(t2, t2, 32); 731 tcg_gen_clz_i64(t1, t1, t2); 732 tcg_gen_extrl_i64_i32(ret, t1); 733 tcg_temp_free_i64(t1); 734 tcg_temp_free_i64(t2); 735 tcg_gen_subi_i32(ret, ret, 32); 736 } else { 737 gen_helper_clz_i32(ret, arg1, arg2); 738 } 739 } 740 741 void tcg_gen_clzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2) 742 { 743 tcg_gen_clz_i32(ret, arg1, tcg_constant_i32(arg2)); 744 } 745 746 void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) 747 { 748 TCGv_i32 z, t; 749 750 if (tcg_op_supported(INDEX_op_ctz, TCG_TYPE_I32, 0)) { 751 tcg_gen_op3_i32(INDEX_op_ctz, ret, arg1, arg2); 752 return; 753 } 754 if (tcg_op_supported(INDEX_op_ctz, TCG_TYPE_I64, 0)) { 755 TCGv_i64 t1 = tcg_temp_ebb_new_i64(); 756 TCGv_i64 t2 = tcg_temp_ebb_new_i64(); 757 tcg_gen_extu_i32_i64(t1, arg1); 758 tcg_gen_extu_i32_i64(t2, arg2); 759 tcg_gen_ctz_i64(t1, t1, t2); 760 tcg_gen_extrl_i64_i32(ret, t1); 761 tcg_temp_free_i64(t1); 762 tcg_temp_free_i64(t2); 763 return; 764 } 765 if (tcg_op_supported(INDEX_op_ctpop, TCG_TYPE_REG, 0)) { 766 t = tcg_temp_ebb_new_i32(); 767 tcg_gen_subi_i32(t, arg1, 1); 768 tcg_gen_andc_i32(t, t, arg1); 769 tcg_gen_ctpop_i32(t, t); 770 } else if (tcg_op_supported(INDEX_op_clz, TCG_TYPE_REG, 0)) { 771 t = tcg_temp_ebb_new_i32(); 772 tcg_gen_neg_i32(t, arg1); 773 tcg_gen_and_i32(t, t, arg1); 774 tcg_gen_clzi_i32(t, t, 32); 775 tcg_gen_xori_i32(t, t, 31); 776 } else { 777 gen_helper_ctz_i32(ret, arg1, arg2); 778 return; 779 } 780 781 z = tcg_constant_i32(0); 782 tcg_gen_movcond_i32(TCG_COND_EQ, ret, arg1, z, arg2, t); 783 tcg_temp_free_i32(t); 784 } 785 786 void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2) 787 { 788 if (arg2 == 32 789 && !tcg_op_supported(INDEX_op_ctz, TCG_TYPE_I32, 0) 790 && tcg_op_supported(INDEX_op_ctpop, TCG_TYPE_REG, 0)) { 791 /* This equivalence has the advantage of not requiring a fixup. */ 792 TCGv_i32 t = tcg_temp_ebb_new_i32(); 793 tcg_gen_subi_i32(t, arg1, 1); 794 tcg_gen_andc_i32(t, t, arg1); 795 tcg_gen_ctpop_i32(ret, t); 796 tcg_temp_free_i32(t); 797 } else { 798 tcg_gen_ctz_i32(ret, arg1, tcg_constant_i32(arg2)); 799 } 800 } 801 802 void tcg_gen_clrsb_i32(TCGv_i32 ret, TCGv_i32 arg) 803 { 804 if (tcg_op_supported(INDEX_op_clz, TCG_TYPE_REG, 0)) { 805 TCGv_i32 t = tcg_temp_ebb_new_i32(); 806 tcg_gen_sari_i32(t, arg, 31); 807 tcg_gen_xor_i32(t, t, arg); 808 tcg_gen_clzi_i32(t, t, 32); 809 tcg_gen_subi_i32(ret, t, 1); 810 tcg_temp_free_i32(t); 811 } else { 812 gen_helper_clrsb_i32(ret, arg); 813 } 814 } 815 816 void tcg_gen_ctpop_i32(TCGv_i32 ret, TCGv_i32 arg1) 817 { 818 if (tcg_op_supported(INDEX_op_ctpop, TCG_TYPE_I32, 0)) { 819 tcg_gen_op2_i32(INDEX_op_ctpop, ret, arg1); 820 } else if (tcg_op_supported(INDEX_op_ctpop, TCG_TYPE_I64, 0)) { 821 TCGv_i64 t = tcg_temp_ebb_new_i64(); 822 tcg_gen_extu_i32_i64(t, arg1); 823 tcg_gen_ctpop_i64(t, t); 824 tcg_gen_extrl_i64_i32(ret, t); 825 tcg_temp_free_i64(t); 826 } else { 827 gen_helper_ctpop_i32(ret, arg1); 828 } 829 } 830 831 void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) 832 { 833 if (tcg_op_supported(INDEX_op_rotl, TCG_TYPE_I32, 0)) { 834 tcg_gen_op3_i32(INDEX_op_rotl, ret, arg1, arg2); 835 } else if (tcg_op_supported(INDEX_op_rotr, TCG_TYPE_I32, 0)) { 836 TCGv_i32 t0 = tcg_temp_ebb_new_i32(); 837 tcg_gen_neg_i32(t0, arg2); 838 tcg_gen_op3_i32(INDEX_op_rotr, ret, arg1, t0); 839 tcg_temp_free_i32(t0); 840 } else { 841 TCGv_i32 t0 = tcg_temp_ebb_new_i32(); 842 TCGv_i32 t1 = tcg_temp_ebb_new_i32(); 843 tcg_gen_shl_i32(t0, arg1, arg2); 844 tcg_gen_neg_i32(t1, arg2); 845 tcg_gen_shr_i32(t1, arg1, t1); 846 tcg_gen_or_i32(ret, t0, t1); 847 tcg_temp_free_i32(t0); 848 tcg_temp_free_i32(t1); 849 } 850 } 851 852 void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) 853 { 854 tcg_debug_assert(arg2 >= 0 && arg2 < 32); 855 /* some cases can be optimized here */ 856 if (arg2 == 0) { 857 tcg_gen_mov_i32(ret, arg1); 858 } else if (tcg_op_supported(INDEX_op_rotl, TCG_TYPE_I32, 0)) { 859 TCGv_i32 t0 = tcg_constant_i32(arg2); 860 tcg_gen_op3_i32(INDEX_op_rotl, ret, arg1, t0); 861 } else if (tcg_op_supported(INDEX_op_rotr, TCG_TYPE_I32, 0)) { 862 TCGv_i32 t0 = tcg_constant_i32(32 - arg2); 863 tcg_gen_op3_i32(INDEX_op_rotr, ret, arg1, t0); 864 } else { 865 TCGv_i32 t0 = tcg_temp_ebb_new_i32(); 866 TCGv_i32 t1 = tcg_temp_ebb_new_i32(); 867 tcg_gen_shli_i32(t0, arg1, arg2); 868 tcg_gen_shri_i32(t1, arg1, 32 - arg2); 869 tcg_gen_or_i32(ret, t0, t1); 870 tcg_temp_free_i32(t0); 871 tcg_temp_free_i32(t1); 872 } 873 } 874 875 void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) 876 { 877 if (tcg_op_supported(INDEX_op_rotr, TCG_TYPE_I32, 0)) { 878 tcg_gen_op3_i32(INDEX_op_rotr, ret, arg1, arg2); 879 } else if (tcg_op_supported(INDEX_op_rotl, TCG_TYPE_I32, 0)) { 880 TCGv_i32 t0 = tcg_temp_ebb_new_i32(); 881 tcg_gen_neg_i32(t0, arg2); 882 tcg_gen_op3_i32(INDEX_op_rotl, ret, arg1, t0); 883 tcg_temp_free_i32(t0); 884 } else { 885 TCGv_i32 t0 = tcg_temp_ebb_new_i32(); 886 TCGv_i32 t1 = tcg_temp_ebb_new_i32(); 887 tcg_gen_shr_i32(t0, arg1, arg2); 888 tcg_gen_neg_i32(t1, arg2); 889 tcg_gen_shl_i32(t1, arg1, t1); 890 tcg_gen_or_i32(ret, t0, t1); 891 tcg_temp_free_i32(t0); 892 tcg_temp_free_i32(t1); 893 } 894 } 895 896 void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) 897 { 898 tcg_debug_assert(arg2 >= 0 && arg2 < 32); 899 tcg_gen_rotli_i32(ret, arg1, -arg2 & 31); 900 } 901 902 void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2, 903 unsigned int ofs, unsigned int len) 904 { 905 uint32_t mask; 906 TCGv_i32 t1; 907 908 tcg_debug_assert(ofs < 32); 909 tcg_debug_assert(len > 0); 910 tcg_debug_assert(len <= 32); 911 tcg_debug_assert(ofs + len <= 32); 912 913 if (len == 32) { 914 tcg_gen_mov_i32(ret, arg2); 915 return; 916 } 917 if (TCG_TARGET_deposit_valid(TCG_TYPE_I32, ofs, len)) { 918 tcg_gen_op5ii_i32(INDEX_op_deposit, ret, arg1, arg2, ofs, len); 919 return; 920 } 921 922 t1 = tcg_temp_ebb_new_i32(); 923 924 if (tcg_op_supported(INDEX_op_extract2, TCG_TYPE_I32, 0)) { 925 if (ofs + len == 32) { 926 tcg_gen_shli_i32(t1, arg1, len); 927 tcg_gen_extract2_i32(ret, t1, arg2, len); 928 goto done; 929 } 930 if (ofs == 0) { 931 tcg_gen_extract2_i32(ret, arg1, arg2, len); 932 tcg_gen_rotli_i32(ret, ret, len); 933 goto done; 934 } 935 } 936 937 mask = (1u << len) - 1; 938 if (ofs + len < 32) { 939 tcg_gen_andi_i32(t1, arg2, mask); 940 tcg_gen_shli_i32(t1, t1, ofs); 941 } else { 942 tcg_gen_shli_i32(t1, arg2, ofs); 943 } 944 tcg_gen_andi_i32(ret, arg1, ~(mask << ofs)); 945 tcg_gen_or_i32(ret, ret, t1); 946 done: 947 tcg_temp_free_i32(t1); 948 } 949 950 void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg, 951 unsigned int ofs, unsigned int len) 952 { 953 tcg_debug_assert(ofs < 32); 954 tcg_debug_assert(len > 0); 955 tcg_debug_assert(len <= 32); 956 tcg_debug_assert(ofs + len <= 32); 957 958 if (ofs + len == 32) { 959 tcg_gen_shli_i32(ret, arg, ofs); 960 } else if (ofs == 0) { 961 tcg_gen_andi_i32(ret, arg, (1u << len) - 1); 962 } else if (TCG_TARGET_deposit_valid(TCG_TYPE_I32, ofs, len)) { 963 TCGv_i32 zero = tcg_constant_i32(0); 964 tcg_gen_op5ii_i32(INDEX_op_deposit, ret, zero, arg, ofs, len); 965 } else { 966 /* 967 * To help two-operand hosts we prefer to zero-extend first, 968 * which allows ARG to stay live. 969 */ 970 if (TCG_TARGET_extract_valid(TCG_TYPE_I32, 0, len)) { 971 tcg_gen_extract_i32(ret, arg, 0, len); 972 tcg_gen_shli_i32(ret, ret, ofs); 973 return; 974 } 975 /* Otherwise prefer zero-extension over AND for code size. */ 976 if (TCG_TARGET_extract_valid(TCG_TYPE_I32, 0, ofs + len)) { 977 tcg_gen_shli_i32(ret, arg, ofs); 978 tcg_gen_extract_i32(ret, ret, 0, ofs + len); 979 return; 980 } 981 tcg_gen_andi_i32(ret, arg, (1u << len) - 1); 982 tcg_gen_shli_i32(ret, ret, ofs); 983 } 984 } 985 986 void tcg_gen_extract_i32(TCGv_i32 ret, TCGv_i32 arg, 987 unsigned int ofs, unsigned int len) 988 { 989 tcg_debug_assert(ofs < 32); 990 tcg_debug_assert(len > 0); 991 tcg_debug_assert(len <= 32); 992 tcg_debug_assert(ofs + len <= 32); 993 994 /* Canonicalize certain special cases, even if extract is supported. */ 995 if (ofs + len == 32) { 996 tcg_gen_shri_i32(ret, arg, 32 - len); 997 return; 998 } 999 1000 if (TCG_TARGET_extract_valid(TCG_TYPE_I32, ofs, len)) { 1001 tcg_gen_op4ii_i32(INDEX_op_extract, ret, arg, ofs, len); 1002 return; 1003 } 1004 if (ofs == 0) { 1005 tcg_gen_andi_i32(ret, arg, (1u << len) - 1); 1006 return; 1007 } 1008 1009 /* Assume that zero-extension, if available, is cheaper than a shift. */ 1010 if (TCG_TARGET_extract_valid(TCG_TYPE_I32, 0, ofs + len)) { 1011 tcg_gen_op4ii_i32(INDEX_op_extract, ret, arg, 0, ofs + len); 1012 tcg_gen_shri_i32(ret, ret, ofs); 1013 return; 1014 } 1015 1016 /* ??? Ideally we'd know what values are available for immediate AND. 1017 Assume that 8 bits are available, plus the special case of 16, 1018 so that we get ext8u, ext16u. */ 1019 switch (len) { 1020 case 1 ... 8: case 16: 1021 tcg_gen_shri_i32(ret, arg, ofs); 1022 tcg_gen_andi_i32(ret, ret, (1u << len) - 1); 1023 break; 1024 default: 1025 tcg_gen_shli_i32(ret, arg, 32 - len - ofs); 1026 tcg_gen_shri_i32(ret, ret, 32 - len); 1027 break; 1028 } 1029 } 1030 1031 void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg, 1032 unsigned int ofs, unsigned int len) 1033 { 1034 tcg_debug_assert(ofs < 32); 1035 tcg_debug_assert(len > 0); 1036 tcg_debug_assert(len <= 32); 1037 tcg_debug_assert(ofs + len <= 32); 1038 1039 /* Canonicalize certain special cases, even if extract is supported. */ 1040 if (ofs + len == 32) { 1041 tcg_gen_sari_i32(ret, arg, 32 - len); 1042 return; 1043 } 1044 1045 if (TCG_TARGET_sextract_valid(TCG_TYPE_I32, ofs, len)) { 1046 tcg_gen_op4ii_i32(INDEX_op_sextract, ret, arg, ofs, len); 1047 return; 1048 } 1049 1050 /* Assume that sign-extension, if available, is cheaper than a shift. */ 1051 if (TCG_TARGET_sextract_valid(TCG_TYPE_I32, 0, ofs + len)) { 1052 tcg_gen_op4ii_i32(INDEX_op_sextract, ret, arg, 0, ofs + len); 1053 tcg_gen_sari_i32(ret, ret, ofs); 1054 return; 1055 } 1056 if (TCG_TARGET_sextract_valid(TCG_TYPE_I32, 0, len)) { 1057 tcg_gen_shri_i32(ret, arg, ofs); 1058 tcg_gen_op4ii_i32(INDEX_op_sextract, ret, ret, 0, len); 1059 return; 1060 } 1061 1062 tcg_gen_shli_i32(ret, arg, 32 - len - ofs); 1063 tcg_gen_sari_i32(ret, ret, 32 - len); 1064 } 1065 1066 /* 1067 * Extract 32-bits from a 64-bit input, ah:al, starting from ofs. 1068 * Unlike tcg_gen_extract_i32 above, len is fixed at 32. 1069 */ 1070 void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah, 1071 unsigned int ofs) 1072 { 1073 tcg_debug_assert(ofs <= 32); 1074 if (ofs == 0) { 1075 tcg_gen_mov_i32(ret, al); 1076 } else if (ofs == 32) { 1077 tcg_gen_mov_i32(ret, ah); 1078 } else if (al == ah) { 1079 tcg_gen_rotri_i32(ret, al, ofs); 1080 } else if (tcg_op_supported(INDEX_op_extract2, TCG_TYPE_I32, 0)) { 1081 tcg_gen_op4i_i32(INDEX_op_extract2, ret, al, ah, ofs); 1082 } else { 1083 TCGv_i32 t0 = tcg_temp_ebb_new_i32(); 1084 tcg_gen_shri_i32(t0, al, ofs); 1085 tcg_gen_deposit_i32(ret, t0, ah, 32 - ofs, ofs); 1086 tcg_temp_free_i32(t0); 1087 } 1088 } 1089 1090 void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1, 1091 TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2) 1092 { 1093 if (cond == TCG_COND_ALWAYS) { 1094 tcg_gen_mov_i32(ret, v1); 1095 } else if (cond == TCG_COND_NEVER) { 1096 tcg_gen_mov_i32(ret, v2); 1097 } else { 1098 tcg_gen_op6i_i32(INDEX_op_movcond, ret, c1, c2, v1, v2, cond); 1099 } 1100 } 1101 1102 void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, 1103 TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh) 1104 { 1105 if (TCG_TARGET_HAS_add2_i32) { 1106 tcg_gen_op6_i32(INDEX_op_add2_i32, rl, rh, al, ah, bl, bh); 1107 } else { 1108 TCGv_i32 t0 = tcg_temp_ebb_new_i32(); 1109 TCGv_i32 t1 = tcg_temp_ebb_new_i32(); 1110 tcg_gen_add_i32(t0, al, bl); 1111 tcg_gen_setcond_i32(TCG_COND_LTU, t1, t0, al); 1112 tcg_gen_add_i32(rh, ah, bh); 1113 tcg_gen_add_i32(rh, rh, t1); 1114 tcg_gen_mov_i32(rl, t0); 1115 tcg_temp_free_i32(t0); 1116 tcg_temp_free_i32(t1); 1117 } 1118 } 1119 1120 void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, 1121 TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh) 1122 { 1123 if (TCG_TARGET_HAS_sub2_i32) { 1124 tcg_gen_op6_i32(INDEX_op_sub2_i32, rl, rh, al, ah, bl, bh); 1125 } else { 1126 TCGv_i32 t0 = tcg_temp_ebb_new_i32(); 1127 TCGv_i32 t1 = tcg_temp_ebb_new_i32(); 1128 tcg_gen_sub_i32(t0, al, bl); 1129 tcg_gen_setcond_i32(TCG_COND_LTU, t1, al, bl); 1130 tcg_gen_sub_i32(rh, ah, bh); 1131 tcg_gen_sub_i32(rh, rh, t1); 1132 tcg_gen_mov_i32(rl, t0); 1133 tcg_temp_free_i32(t0); 1134 tcg_temp_free_i32(t1); 1135 } 1136 } 1137 1138 void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2) 1139 { 1140 if (tcg_op_supported(INDEX_op_mulu2, TCG_TYPE_I32, 0)) { 1141 tcg_gen_op4_i32(INDEX_op_mulu2, rl, rh, arg1, arg2); 1142 } else if (tcg_op_supported(INDEX_op_muluh, TCG_TYPE_I32, 0)) { 1143 TCGv_i32 t = tcg_temp_ebb_new_i32(); 1144 tcg_gen_op3_i32(INDEX_op_mul, t, arg1, arg2); 1145 tcg_gen_op3_i32(INDEX_op_muluh, rh, arg1, arg2); 1146 tcg_gen_mov_i32(rl, t); 1147 tcg_temp_free_i32(t); 1148 } else if (TCG_TARGET_REG_BITS == 64) { 1149 TCGv_i64 t0 = tcg_temp_ebb_new_i64(); 1150 TCGv_i64 t1 = tcg_temp_ebb_new_i64(); 1151 tcg_gen_extu_i32_i64(t0, arg1); 1152 tcg_gen_extu_i32_i64(t1, arg2); 1153 tcg_gen_mul_i64(t0, t0, t1); 1154 tcg_gen_extr_i64_i32(rl, rh, t0); 1155 tcg_temp_free_i64(t0); 1156 tcg_temp_free_i64(t1); 1157 } else { 1158 g_assert_not_reached(); 1159 } 1160 } 1161 1162 void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2) 1163 { 1164 if (tcg_op_supported(INDEX_op_muls2, TCG_TYPE_I32, 0)) { 1165 tcg_gen_op4_i32(INDEX_op_muls2, rl, rh, arg1, arg2); 1166 } else if (tcg_op_supported(INDEX_op_mulsh, TCG_TYPE_I32, 0)) { 1167 TCGv_i32 t = tcg_temp_ebb_new_i32(); 1168 tcg_gen_op3_i32(INDEX_op_mul, t, arg1, arg2); 1169 tcg_gen_op3_i32(INDEX_op_mulsh, rh, arg1, arg2); 1170 tcg_gen_mov_i32(rl, t); 1171 tcg_temp_free_i32(t); 1172 } else if (TCG_TARGET_REG_BITS == 32) { 1173 TCGv_i32 t0 = tcg_temp_ebb_new_i32(); 1174 TCGv_i32 t1 = tcg_temp_ebb_new_i32(); 1175 TCGv_i32 t2 = tcg_temp_ebb_new_i32(); 1176 TCGv_i32 t3 = tcg_temp_ebb_new_i32(); 1177 tcg_gen_mulu2_i32(t0, t1, arg1, arg2); 1178 /* Adjust for negative inputs. */ 1179 tcg_gen_sari_i32(t2, arg1, 31); 1180 tcg_gen_sari_i32(t3, arg2, 31); 1181 tcg_gen_and_i32(t2, t2, arg2); 1182 tcg_gen_and_i32(t3, t3, arg1); 1183 tcg_gen_sub_i32(rh, t1, t2); 1184 tcg_gen_sub_i32(rh, rh, t3); 1185 tcg_gen_mov_i32(rl, t0); 1186 tcg_temp_free_i32(t0); 1187 tcg_temp_free_i32(t1); 1188 tcg_temp_free_i32(t2); 1189 tcg_temp_free_i32(t3); 1190 } else { 1191 TCGv_i64 t0 = tcg_temp_ebb_new_i64(); 1192 TCGv_i64 t1 = tcg_temp_ebb_new_i64(); 1193 tcg_gen_ext_i32_i64(t0, arg1); 1194 tcg_gen_ext_i32_i64(t1, arg2); 1195 tcg_gen_mul_i64(t0, t0, t1); 1196 tcg_gen_extr_i64_i32(rl, rh, t0); 1197 tcg_temp_free_i64(t0); 1198 tcg_temp_free_i64(t1); 1199 } 1200 } 1201 1202 void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2) 1203 { 1204 if (TCG_TARGET_REG_BITS == 32) { 1205 TCGv_i32 t0 = tcg_temp_ebb_new_i32(); 1206 TCGv_i32 t1 = tcg_temp_ebb_new_i32(); 1207 TCGv_i32 t2 = tcg_temp_ebb_new_i32(); 1208 tcg_gen_mulu2_i32(t0, t1, arg1, arg2); 1209 /* Adjust for negative input for the signed arg1. */ 1210 tcg_gen_sari_i32(t2, arg1, 31); 1211 tcg_gen_and_i32(t2, t2, arg2); 1212 tcg_gen_sub_i32(rh, t1, t2); 1213 tcg_gen_mov_i32(rl, t0); 1214 tcg_temp_free_i32(t0); 1215 tcg_temp_free_i32(t1); 1216 tcg_temp_free_i32(t2); 1217 } else { 1218 TCGv_i64 t0 = tcg_temp_ebb_new_i64(); 1219 TCGv_i64 t1 = tcg_temp_ebb_new_i64(); 1220 tcg_gen_ext_i32_i64(t0, arg1); 1221 tcg_gen_extu_i32_i64(t1, arg2); 1222 tcg_gen_mul_i64(t0, t0, t1); 1223 tcg_gen_extr_i64_i32(rl, rh, t0); 1224 tcg_temp_free_i64(t0); 1225 tcg_temp_free_i64(t1); 1226 } 1227 } 1228 1229 void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg) 1230 { 1231 tcg_gen_sextract_i32(ret, arg, 0, 8); 1232 } 1233 1234 void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg) 1235 { 1236 tcg_gen_sextract_i32(ret, arg, 0, 16); 1237 } 1238 1239 void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg) 1240 { 1241 tcg_gen_extract_i32(ret, arg, 0, 8); 1242 } 1243 1244 void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg) 1245 { 1246 tcg_gen_extract_i32(ret, arg, 0, 16); 1247 } 1248 1249 /* 1250 * bswap16_i32: 16-bit byte swap on the low bits of a 32-bit value. 1251 * 1252 * Byte pattern: xxab -> yyba 1253 * 1254 * With TCG_BSWAP_IZ, x == zero, else undefined. 1255 * With TCG_BSWAP_OZ, y == zero, with TCG_BSWAP_OS y == sign, else undefined. 1256 */ 1257 void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg, int flags) 1258 { 1259 /* Only one extension flag may be present. */ 1260 tcg_debug_assert(!(flags & TCG_BSWAP_OS) || !(flags & TCG_BSWAP_OZ)); 1261 1262 if (tcg_op_supported(INDEX_op_bswap16, TCG_TYPE_I32, 0)) { 1263 tcg_gen_op3i_i32(INDEX_op_bswap16, ret, arg, flags); 1264 } else { 1265 TCGv_i32 t0 = tcg_temp_ebb_new_i32(); 1266 TCGv_i32 t1 = tcg_temp_ebb_new_i32(); 1267 1268 /* arg = ..ab (IZ) xxab (!IZ) */ 1269 tcg_gen_shri_i32(t0, arg, 8); /* t0 = ...a (IZ) .xxa (!IZ) */ 1270 if (!(flags & TCG_BSWAP_IZ)) { 1271 tcg_gen_ext8u_i32(t0, t0); /* t0 = ...a */ 1272 } 1273 1274 if (flags & TCG_BSWAP_OS) { 1275 tcg_gen_shli_i32(t1, arg, 24); /* t1 = b... */ 1276 tcg_gen_sari_i32(t1, t1, 16); /* t1 = ssb. */ 1277 } else if (flags & TCG_BSWAP_OZ) { 1278 tcg_gen_ext8u_i32(t1, arg); /* t1 = ...b */ 1279 tcg_gen_shli_i32(t1, t1, 8); /* t1 = ..b. */ 1280 } else { 1281 tcg_gen_shli_i32(t1, arg, 8); /* t1 = xab. */ 1282 } 1283 1284 tcg_gen_or_i32(ret, t0, t1); /* ret = ..ba (OZ) */ 1285 /* = ssba (OS) */ 1286 /* = xaba (no flag) */ 1287 tcg_temp_free_i32(t0); 1288 tcg_temp_free_i32(t1); 1289 } 1290 } 1291 1292 /* 1293 * bswap32_i32: 32-bit byte swap on a 32-bit value. 1294 * 1295 * Byte pattern: abcd -> dcba 1296 */ 1297 void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg) 1298 { 1299 if (tcg_op_supported(INDEX_op_bswap32, TCG_TYPE_I32, 0)) { 1300 tcg_gen_op3i_i32(INDEX_op_bswap32, ret, arg, 0); 1301 } else { 1302 TCGv_i32 t0 = tcg_temp_ebb_new_i32(); 1303 TCGv_i32 t1 = tcg_temp_ebb_new_i32(); 1304 TCGv_i32 t2 = tcg_constant_i32(0x00ff00ff); 1305 1306 /* arg = abcd */ 1307 tcg_gen_shri_i32(t0, arg, 8); /* t0 = .abc */ 1308 tcg_gen_and_i32(t1, arg, t2); /* t1 = .b.d */ 1309 tcg_gen_and_i32(t0, t0, t2); /* t0 = .a.c */ 1310 tcg_gen_shli_i32(t1, t1, 8); /* t1 = b.d. */ 1311 tcg_gen_or_i32(ret, t0, t1); /* ret = badc */ 1312 1313 tcg_gen_shri_i32(t0, ret, 16); /* t0 = ..ba */ 1314 tcg_gen_shli_i32(t1, ret, 16); /* t1 = dc.. */ 1315 tcg_gen_or_i32(ret, t0, t1); /* ret = dcba */ 1316 1317 tcg_temp_free_i32(t0); 1318 tcg_temp_free_i32(t1); 1319 } 1320 } 1321 1322 /* 1323 * hswap_i32: Swap 16-bit halfwords within a 32-bit value. 1324 * 1325 * Byte pattern: abcd -> cdab 1326 */ 1327 void tcg_gen_hswap_i32(TCGv_i32 ret, TCGv_i32 arg) 1328 { 1329 /* Swapping 2 16-bit elements is a rotate. */ 1330 tcg_gen_rotli_i32(ret, arg, 16); 1331 } 1332 1333 void tcg_gen_smin_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b) 1334 { 1335 tcg_gen_movcond_i32(TCG_COND_LT, ret, a, b, a, b); 1336 } 1337 1338 void tcg_gen_umin_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b) 1339 { 1340 tcg_gen_movcond_i32(TCG_COND_LTU, ret, a, b, a, b); 1341 } 1342 1343 void tcg_gen_smax_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b) 1344 { 1345 tcg_gen_movcond_i32(TCG_COND_LT, ret, a, b, b, a); 1346 } 1347 1348 void tcg_gen_umax_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b) 1349 { 1350 tcg_gen_movcond_i32(TCG_COND_LTU, ret, a, b, b, a); 1351 } 1352 1353 void tcg_gen_abs_i32(TCGv_i32 ret, TCGv_i32 a) 1354 { 1355 TCGv_i32 t = tcg_temp_ebb_new_i32(); 1356 1357 tcg_gen_sari_i32(t, a, 31); 1358 tcg_gen_xor_i32(ret, a, t); 1359 tcg_gen_sub_i32(ret, ret, t); 1360 tcg_temp_free_i32(t); 1361 } 1362 1363 void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) 1364 { 1365 tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset); 1366 } 1367 1368 void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) 1369 { 1370 tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset); 1371 } 1372 1373 void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) 1374 { 1375 tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset); 1376 } 1377 1378 void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) 1379 { 1380 tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset); 1381 } 1382 1383 void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) 1384 { 1385 tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset); 1386 } 1387 1388 void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) 1389 { 1390 tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset); 1391 } 1392 1393 void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) 1394 { 1395 tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset); 1396 } 1397 1398 void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) 1399 { 1400 tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset); 1401 } 1402 1403 1404 /* 64-bit ops */ 1405 1406 void tcg_gen_discard_i64(TCGv_i64 arg) 1407 { 1408 if (TCG_TARGET_REG_BITS == 64) { 1409 tcg_gen_op1_i64(INDEX_op_discard, TCG_TYPE_I64, arg); 1410 } else { 1411 tcg_gen_discard_i32(TCGV_LOW(arg)); 1412 tcg_gen_discard_i32(TCGV_HIGH(arg)); 1413 } 1414 } 1415 1416 void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) 1417 { 1418 if (ret == arg) { 1419 return; 1420 } 1421 if (TCG_TARGET_REG_BITS == 64) { 1422 tcg_gen_op2_i64(INDEX_op_mov, ret, arg); 1423 } else { 1424 TCGTemp *ts = tcgv_i64_temp(arg); 1425 1426 /* Canonicalize TCGv_i64 TEMP_CONST into TCGv_i32 TEMP_CONST. */ 1427 if (ts->kind == TEMP_CONST) { 1428 tcg_gen_movi_i64(ret, ts->val); 1429 } else { 1430 tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); 1431 tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); 1432 } 1433 } 1434 } 1435 1436 void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) 1437 { 1438 if (TCG_TARGET_REG_BITS == 64) { 1439 tcg_gen_mov_i64(ret, tcg_constant_i64(arg)); 1440 } else { 1441 tcg_gen_movi_i32(TCGV_LOW(ret), arg); 1442 tcg_gen_movi_i32(TCGV_HIGH(ret), arg >> 32); 1443 } 1444 } 1445 1446 void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) 1447 { 1448 if (TCG_TARGET_REG_BITS == 64) { 1449 tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset); 1450 } else { 1451 tcg_gen_ld8u_i32(TCGV_LOW(ret), arg2, offset); 1452 tcg_gen_movi_i32(TCGV_HIGH(ret), 0); 1453 } 1454 } 1455 1456 void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) 1457 { 1458 if (TCG_TARGET_REG_BITS == 64) { 1459 tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset); 1460 } else { 1461 tcg_gen_ld8s_i32(TCGV_LOW(ret), arg2, offset); 1462 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); 1463 } 1464 } 1465 1466 void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) 1467 { 1468 if (TCG_TARGET_REG_BITS == 64) { 1469 tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset); 1470 } else { 1471 tcg_gen_ld16u_i32(TCGV_LOW(ret), arg2, offset); 1472 tcg_gen_movi_i32(TCGV_HIGH(ret), 0); 1473 } 1474 } 1475 1476 void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) 1477 { 1478 if (TCG_TARGET_REG_BITS == 64) { 1479 tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset); 1480 } else { 1481 tcg_gen_ld16s_i32(TCGV_LOW(ret), arg2, offset); 1482 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); 1483 } 1484 } 1485 1486 void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) 1487 { 1488 if (TCG_TARGET_REG_BITS == 64) { 1489 tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset); 1490 } else { 1491 tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); 1492 tcg_gen_movi_i32(TCGV_HIGH(ret), 0); 1493 } 1494 } 1495 1496 void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) 1497 { 1498 if (TCG_TARGET_REG_BITS == 64) { 1499 tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset); 1500 } else { 1501 tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); 1502 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); 1503 } 1504 } 1505 1506 void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) 1507 { 1508 /* 1509 * For 32-bit host, since arg2 and ret have different types, 1510 * they cannot be the same temporary -- no chance of overlap. 1511 */ 1512 if (TCG_TARGET_REG_BITS == 64) { 1513 tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset); 1514 } else if (HOST_BIG_ENDIAN) { 1515 tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset); 1516 tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset + 4); 1517 } else { 1518 tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); 1519 tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset + 4); 1520 } 1521 } 1522 1523 void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset) 1524 { 1525 if (TCG_TARGET_REG_BITS == 64) { 1526 tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset); 1527 } else { 1528 tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset); 1529 } 1530 } 1531 1532 void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset) 1533 { 1534 if (TCG_TARGET_REG_BITS == 64) { 1535 tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset); 1536 } else { 1537 tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset); 1538 } 1539 } 1540 1541 void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset) 1542 { 1543 if (TCG_TARGET_REG_BITS == 64) { 1544 tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset); 1545 } else { 1546 tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset); 1547 } 1548 } 1549 1550 void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset) 1551 { 1552 if (TCG_TARGET_REG_BITS == 64) { 1553 tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset); 1554 } else if (HOST_BIG_ENDIAN) { 1555 tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset); 1556 tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset + 4); 1557 } else { 1558 tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset); 1559 tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset + 4); 1560 } 1561 } 1562 1563 void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) 1564 { 1565 if (TCG_TARGET_REG_BITS == 64) { 1566 tcg_gen_op3_i64(INDEX_op_add, ret, arg1, arg2); 1567 } else { 1568 tcg_gen_add2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1), 1569 TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2)); 1570 } 1571 } 1572 1573 void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) 1574 { 1575 if (TCG_TARGET_REG_BITS == 64) { 1576 tcg_gen_op3_i64(INDEX_op_sub, ret, arg1, arg2); 1577 } else { 1578 tcg_gen_sub2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1), 1579 TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2)); 1580 } 1581 } 1582 1583 void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) 1584 { 1585 if (TCG_TARGET_REG_BITS == 64) { 1586 tcg_gen_op3_i64(INDEX_op_and, ret, arg1, arg2); 1587 } else { 1588 tcg_gen_and_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); 1589 tcg_gen_and_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); 1590 } 1591 } 1592 1593 void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) 1594 { 1595 if (TCG_TARGET_REG_BITS == 64) { 1596 tcg_gen_op3_i64(INDEX_op_or, ret, arg1, arg2); 1597 } else { 1598 tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); 1599 tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); 1600 } 1601 } 1602 1603 void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) 1604 { 1605 if (TCG_TARGET_REG_BITS == 64) { 1606 tcg_gen_op3_i64(INDEX_op_xor, ret, arg1, arg2); 1607 } else { 1608 tcg_gen_xor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); 1609 tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); 1610 } 1611 } 1612 1613 void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) 1614 { 1615 if (TCG_TARGET_REG_BITS == 64) { 1616 tcg_gen_op3_i64(INDEX_op_shl, ret, arg1, arg2); 1617 } else { 1618 gen_helper_shl_i64(ret, arg1, arg2); 1619 } 1620 } 1621 1622 void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) 1623 { 1624 if (TCG_TARGET_REG_BITS == 64) { 1625 tcg_gen_op3_i64(INDEX_op_shr, ret, arg1, arg2); 1626 } else { 1627 gen_helper_shr_i64(ret, arg1, arg2); 1628 } 1629 } 1630 1631 void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) 1632 { 1633 if (TCG_TARGET_REG_BITS == 64) { 1634 tcg_gen_op3_i64(INDEX_op_sar, ret, arg1, arg2); 1635 } else { 1636 gen_helper_sar_i64(ret, arg1, arg2); 1637 } 1638 } 1639 1640 void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) 1641 { 1642 TCGv_i64 t0; 1643 TCGv_i32 t1; 1644 1645 if (TCG_TARGET_REG_BITS == 64) { 1646 tcg_gen_op3_i64(INDEX_op_mul, ret, arg1, arg2); 1647 return; 1648 } 1649 1650 1651 t0 = tcg_temp_ebb_new_i64(); 1652 t1 = tcg_temp_ebb_new_i32(); 1653 1654 tcg_gen_mulu2_i32(TCGV_LOW(t0), TCGV_HIGH(t0), 1655 TCGV_LOW(arg1), TCGV_LOW(arg2)); 1656 1657 tcg_gen_mul_i32(t1, TCGV_LOW(arg1), TCGV_HIGH(arg2)); 1658 tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1); 1659 tcg_gen_mul_i32(t1, TCGV_HIGH(arg1), TCGV_LOW(arg2)); 1660 tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1); 1661 1662 tcg_gen_mov_i64(ret, t0); 1663 tcg_temp_free_i64(t0); 1664 tcg_temp_free_i32(t1); 1665 } 1666 1667 void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) 1668 { 1669 /* some cases can be optimized here */ 1670 if (arg2 == 0) { 1671 tcg_gen_mov_i64(ret, arg1); 1672 } else if (TCG_TARGET_REG_BITS == 64) { 1673 tcg_gen_add_i64(ret, arg1, tcg_constant_i64(arg2)); 1674 } else { 1675 tcg_gen_add2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), 1676 TCGV_LOW(arg1), TCGV_HIGH(arg1), 1677 tcg_constant_i32(arg2), tcg_constant_i32(arg2 >> 32)); 1678 } 1679 } 1680 1681 void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2) 1682 { 1683 if (arg1 == 0) { 1684 tcg_gen_neg_i64(ret, arg2); 1685 } else if (TCG_TARGET_REG_BITS == 64) { 1686 tcg_gen_sub_i64(ret, tcg_constant_i64(arg1), arg2); 1687 } else { 1688 tcg_gen_sub2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), 1689 tcg_constant_i32(arg1), tcg_constant_i32(arg1 >> 32), 1690 TCGV_LOW(arg2), TCGV_HIGH(arg2)); 1691 } 1692 } 1693 1694 void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) 1695 { 1696 tcg_gen_addi_i64(ret, arg1, -arg2); 1697 } 1698 1699 void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg) 1700 { 1701 if (TCG_TARGET_REG_BITS == 64) { 1702 tcg_gen_op2_i64(INDEX_op_neg, ret, arg); 1703 } else { 1704 TCGv_i32 zero = tcg_constant_i32(0); 1705 tcg_gen_sub2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), 1706 zero, zero, TCGV_LOW(arg), TCGV_HIGH(arg)); 1707 } 1708 } 1709 1710 void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) 1711 { 1712 if (TCG_TARGET_REG_BITS == 32) { 1713 tcg_gen_andi_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); 1714 tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32); 1715 return; 1716 } 1717 1718 /* Some cases can be optimized here. */ 1719 switch (arg2) { 1720 case 0: 1721 tcg_gen_movi_i64(ret, 0); 1722 return; 1723 case -1: 1724 tcg_gen_mov_i64(ret, arg1); 1725 return; 1726 default: 1727 /* 1728 * Canonicalize on extract, if valid. This aids x86 with its 1729 * 2 operand MOVZBL and 2 operand AND, selecting the TCGOpcode 1730 * which does not require matching operands. Other backends can 1731 * trivially expand the extract to AND during code generation. 1732 */ 1733 if (!(arg2 & (arg2 + 1))) { 1734 unsigned len = ctz64(~arg2); 1735 if (TCG_TARGET_extract_valid(TCG_TYPE_I64, 0, len)) { 1736 tcg_gen_extract_i64(ret, arg1, 0, len); 1737 return; 1738 } 1739 } 1740 break; 1741 } 1742 1743 tcg_gen_and_i64(ret, arg1, tcg_constant_i64(arg2)); 1744 } 1745 1746 void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) 1747 { 1748 if (TCG_TARGET_REG_BITS == 32) { 1749 tcg_gen_ori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); 1750 tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32); 1751 return; 1752 } 1753 /* Some cases can be optimized here. */ 1754 if (arg2 == -1) { 1755 tcg_gen_movi_i64(ret, -1); 1756 } else if (arg2 == 0) { 1757 tcg_gen_mov_i64(ret, arg1); 1758 } else { 1759 tcg_gen_or_i64(ret, arg1, tcg_constant_i64(arg2)); 1760 } 1761 } 1762 1763 void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) 1764 { 1765 if (TCG_TARGET_REG_BITS == 32) { 1766 tcg_gen_xori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); 1767 tcg_gen_xori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32); 1768 return; 1769 } 1770 /* Some cases can be optimized here. */ 1771 if (arg2 == 0) { 1772 tcg_gen_mov_i64(ret, arg1); 1773 } else if (arg2 == -1 && 1774 tcg_op_supported(INDEX_op_not, TCG_TYPE_I64, 0)) { 1775 /* Don't recurse with tcg_gen_not_i64. */ 1776 tcg_gen_op2_i64(INDEX_op_not, ret, arg1); 1777 } else { 1778 tcg_gen_xor_i64(ret, arg1, tcg_constant_i64(arg2)); 1779 } 1780 } 1781 1782 static inline void tcg_gen_shifti_i64(TCGv_i64 ret, TCGv_i64 arg1, 1783 unsigned c, bool right, bool arith) 1784 { 1785 tcg_debug_assert(c < 64); 1786 if (c == 0) { 1787 tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg1)); 1788 tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1)); 1789 } else if (c >= 32) { 1790 c -= 32; 1791 if (right) { 1792 if (arith) { 1793 tcg_gen_sari_i32(TCGV_LOW(ret), TCGV_HIGH(arg1), c); 1794 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), 31); 1795 } else { 1796 tcg_gen_shri_i32(TCGV_LOW(ret), TCGV_HIGH(arg1), c); 1797 tcg_gen_movi_i32(TCGV_HIGH(ret), 0); 1798 } 1799 } else { 1800 tcg_gen_shli_i32(TCGV_HIGH(ret), TCGV_LOW(arg1), c); 1801 tcg_gen_movi_i32(TCGV_LOW(ret), 0); 1802 } 1803 } else if (right) { 1804 if (tcg_op_supported(INDEX_op_extract2, TCG_TYPE_I32, 0)) { 1805 tcg_gen_extract2_i32(TCGV_LOW(ret), 1806 TCGV_LOW(arg1), TCGV_HIGH(arg1), c); 1807 } else { 1808 tcg_gen_shri_i32(TCGV_LOW(ret), TCGV_LOW(arg1), c); 1809 tcg_gen_deposit_i32(TCGV_LOW(ret), TCGV_LOW(ret), 1810 TCGV_HIGH(arg1), 32 - c, c); 1811 } 1812 if (arith) { 1813 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), c); 1814 } else { 1815 tcg_gen_shri_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), c); 1816 } 1817 } else { 1818 if (tcg_op_supported(INDEX_op_extract2, TCG_TYPE_I32, 0)) { 1819 tcg_gen_extract2_i32(TCGV_HIGH(ret), 1820 TCGV_LOW(arg1), TCGV_HIGH(arg1), 32 - c); 1821 } else { 1822 TCGv_i32 t0 = tcg_temp_ebb_new_i32(); 1823 tcg_gen_shri_i32(t0, TCGV_LOW(arg1), 32 - c); 1824 tcg_gen_deposit_i32(TCGV_HIGH(ret), t0, 1825 TCGV_HIGH(arg1), c, 32 - c); 1826 tcg_temp_free_i32(t0); 1827 } 1828 tcg_gen_shli_i32(TCGV_LOW(ret), TCGV_LOW(arg1), c); 1829 } 1830 } 1831 1832 void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) 1833 { 1834 tcg_debug_assert(arg2 >= 0 && arg2 < 64); 1835 if (TCG_TARGET_REG_BITS == 32) { 1836 tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0); 1837 } else if (arg2 == 0) { 1838 tcg_gen_mov_i64(ret, arg1); 1839 } else { 1840 tcg_gen_shl_i64(ret, arg1, tcg_constant_i64(arg2)); 1841 } 1842 } 1843 1844 void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) 1845 { 1846 tcg_debug_assert(arg2 >= 0 && arg2 < 64); 1847 if (TCG_TARGET_REG_BITS == 32) { 1848 tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0); 1849 } else if (arg2 == 0) { 1850 tcg_gen_mov_i64(ret, arg1); 1851 } else { 1852 tcg_gen_shr_i64(ret, arg1, tcg_constant_i64(arg2)); 1853 } 1854 } 1855 1856 void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) 1857 { 1858 tcg_debug_assert(arg2 >= 0 && arg2 < 64); 1859 if (TCG_TARGET_REG_BITS == 32) { 1860 tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1); 1861 } else if (arg2 == 0) { 1862 tcg_gen_mov_i64(ret, arg1); 1863 } else { 1864 tcg_gen_sar_i64(ret, arg1, tcg_constant_i64(arg2)); 1865 } 1866 } 1867 1868 void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLabel *l) 1869 { 1870 if (cond == TCG_COND_ALWAYS) { 1871 tcg_gen_br(l); 1872 } else if (cond != TCG_COND_NEVER) { 1873 TCGOp *op; 1874 if (TCG_TARGET_REG_BITS == 32) { 1875 op = tcg_gen_op6ii_i32(INDEX_op_brcond2_i32, TCGV_LOW(arg1), 1876 TCGV_HIGH(arg1), TCGV_LOW(arg2), 1877 TCGV_HIGH(arg2), cond, label_arg(l)); 1878 } else { 1879 op = tcg_gen_op4ii_i64(INDEX_op_brcond, arg1, arg2, cond, 1880 label_arg(l)); 1881 } 1882 add_as_label_use(l, op); 1883 } 1884 } 1885 1886 void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLabel *l) 1887 { 1888 if (TCG_TARGET_REG_BITS == 64) { 1889 tcg_gen_brcond_i64(cond, arg1, tcg_constant_i64(arg2), l); 1890 } else if (cond == TCG_COND_ALWAYS) { 1891 tcg_gen_br(l); 1892 } else if (cond != TCG_COND_NEVER) { 1893 TCGOp *op = tcg_gen_op6ii_i32(INDEX_op_brcond2_i32, 1894 TCGV_LOW(arg1), TCGV_HIGH(arg1), 1895 tcg_constant_i32(arg2), 1896 tcg_constant_i32(arg2 >> 32), 1897 cond, label_arg(l)); 1898 add_as_label_use(l, op); 1899 } 1900 } 1901 1902 void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret, 1903 TCGv_i64 arg1, TCGv_i64 arg2) 1904 { 1905 if (cond == TCG_COND_ALWAYS) { 1906 tcg_gen_movi_i64(ret, 1); 1907 } else if (cond == TCG_COND_NEVER) { 1908 tcg_gen_movi_i64(ret, 0); 1909 } else { 1910 if (TCG_TARGET_REG_BITS == 32) { 1911 tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret), 1912 TCGV_LOW(arg1), TCGV_HIGH(arg1), 1913 TCGV_LOW(arg2), TCGV_HIGH(arg2), cond); 1914 tcg_gen_movi_i32(TCGV_HIGH(ret), 0); 1915 } else { 1916 tcg_gen_op4i_i64(INDEX_op_setcond, ret, arg1, arg2, cond); 1917 } 1918 } 1919 } 1920 1921 void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret, 1922 TCGv_i64 arg1, int64_t arg2) 1923 { 1924 if (TCG_TARGET_REG_BITS == 64) { 1925 tcg_gen_setcond_i64(cond, ret, arg1, tcg_constant_i64(arg2)); 1926 } else if (cond == TCG_COND_ALWAYS) { 1927 tcg_gen_movi_i64(ret, 1); 1928 } else if (cond == TCG_COND_NEVER) { 1929 tcg_gen_movi_i64(ret, 0); 1930 } else { 1931 tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret), 1932 TCGV_LOW(arg1), TCGV_HIGH(arg1), 1933 tcg_constant_i32(arg2), 1934 tcg_constant_i32(arg2 >> 32), cond); 1935 tcg_gen_movi_i32(TCGV_HIGH(ret), 0); 1936 } 1937 } 1938 1939 void tcg_gen_negsetcondi_i64(TCGCond cond, TCGv_i64 ret, 1940 TCGv_i64 arg1, int64_t arg2) 1941 { 1942 tcg_gen_negsetcond_i64(cond, ret, arg1, tcg_constant_i64(arg2)); 1943 } 1944 1945 void tcg_gen_negsetcond_i64(TCGCond cond, TCGv_i64 ret, 1946 TCGv_i64 arg1, TCGv_i64 arg2) 1947 { 1948 if (cond == TCG_COND_ALWAYS) { 1949 tcg_gen_movi_i64(ret, -1); 1950 } else if (cond == TCG_COND_NEVER) { 1951 tcg_gen_movi_i64(ret, 0); 1952 } else if (TCG_TARGET_REG_BITS == 64) { 1953 tcg_gen_op4i_i64(INDEX_op_negsetcond, ret, arg1, arg2, cond); 1954 } else { 1955 tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret), 1956 TCGV_LOW(arg1), TCGV_HIGH(arg1), 1957 TCGV_LOW(arg2), TCGV_HIGH(arg2), cond); 1958 tcg_gen_neg_i32(TCGV_LOW(ret), TCGV_LOW(ret)); 1959 tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_LOW(ret)); 1960 } 1961 } 1962 1963 void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) 1964 { 1965 if (arg2 == 0) { 1966 tcg_gen_movi_i64(ret, 0); 1967 } else if (is_power_of_2(arg2)) { 1968 tcg_gen_shli_i64(ret, arg1, ctz64(arg2)); 1969 } else { 1970 tcg_gen_mul_i64(ret, arg1, tcg_constant_i64(arg2)); 1971 } 1972 } 1973 1974 void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) 1975 { 1976 if (tcg_op_supported(INDEX_op_divs, TCG_TYPE_I64, 0)) { 1977 tcg_gen_op3_i64(INDEX_op_divs, ret, arg1, arg2); 1978 } else if (tcg_op_supported(INDEX_op_divs2, TCG_TYPE_I64, 0)) { 1979 TCGv_i64 t0 = tcg_temp_ebb_new_i64(); 1980 tcg_gen_sari_i64(t0, arg1, 63); 1981 tcg_gen_op5_i64(INDEX_op_divs2, ret, t0, arg1, t0, arg2); 1982 tcg_temp_free_i64(t0); 1983 } else { 1984 gen_helper_div_i64(ret, arg1, arg2); 1985 } 1986 } 1987 1988 void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) 1989 { 1990 if (tcg_op_supported(INDEX_op_rems, TCG_TYPE_I64, 0)) { 1991 tcg_gen_op3_i64(INDEX_op_rems, ret, arg1, arg2); 1992 } else if (tcg_op_supported(INDEX_op_divs, TCG_TYPE_I64, 0)) { 1993 TCGv_i64 t0 = tcg_temp_ebb_new_i64(); 1994 tcg_gen_op3_i64(INDEX_op_divs, t0, arg1, arg2); 1995 tcg_gen_mul_i64(t0, t0, arg2); 1996 tcg_gen_sub_i64(ret, arg1, t0); 1997 tcg_temp_free_i64(t0); 1998 } else if (tcg_op_supported(INDEX_op_divs2, TCG_TYPE_I64, 0)) { 1999 TCGv_i64 t0 = tcg_temp_ebb_new_i64(); 2000 tcg_gen_sari_i64(t0, arg1, 63); 2001 tcg_gen_op5_i64(INDEX_op_divs2, t0, ret, arg1, t0, arg2); 2002 tcg_temp_free_i64(t0); 2003 } else { 2004 gen_helper_rem_i64(ret, arg1, arg2); 2005 } 2006 } 2007 2008 void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) 2009 { 2010 if (tcg_op_supported(INDEX_op_divu, TCG_TYPE_I64, 0)) { 2011 tcg_gen_op3_i64(INDEX_op_divu, ret, arg1, arg2); 2012 } else if (tcg_op_supported(INDEX_op_divu2, TCG_TYPE_I64, 0)) { 2013 TCGv_i64 t0 = tcg_temp_ebb_new_i64(); 2014 TCGv_i64 zero = tcg_constant_i64(0); 2015 tcg_gen_op5_i64(INDEX_op_divu2, ret, t0, arg1, zero, arg2); 2016 tcg_temp_free_i64(t0); 2017 } else { 2018 gen_helper_divu_i64(ret, arg1, arg2); 2019 } 2020 } 2021 2022 void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) 2023 { 2024 if (tcg_op_supported(INDEX_op_remu, TCG_TYPE_I64, 0)) { 2025 tcg_gen_op3_i64(INDEX_op_remu, ret, arg1, arg2); 2026 } else if (tcg_op_supported(INDEX_op_divu, TCG_TYPE_I64, 0)) { 2027 TCGv_i64 t0 = tcg_temp_ebb_new_i64(); 2028 tcg_gen_op3_i64(INDEX_op_divu, t0, arg1, arg2); 2029 tcg_gen_mul_i64(t0, t0, arg2); 2030 tcg_gen_sub_i64(ret, arg1, t0); 2031 tcg_temp_free_i64(t0); 2032 } else if (tcg_op_supported(INDEX_op_divu2, TCG_TYPE_I64, 0)) { 2033 TCGv_i64 t0 = tcg_temp_ebb_new_i64(); 2034 TCGv_i64 zero = tcg_constant_i64(0); 2035 tcg_gen_op5_i64(INDEX_op_divu2, t0, ret, arg1, zero, arg2); 2036 tcg_temp_free_i64(t0); 2037 } else { 2038 gen_helper_remu_i64(ret, arg1, arg2); 2039 } 2040 } 2041 2042 void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg) 2043 { 2044 tcg_gen_sextract_i64(ret, arg, 0, 8); 2045 } 2046 2047 void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg) 2048 { 2049 tcg_gen_sextract_i64(ret, arg, 0, 16); 2050 } 2051 2052 void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg) 2053 { 2054 tcg_gen_sextract_i64(ret, arg, 0, 32); 2055 } 2056 2057 void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg) 2058 { 2059 tcg_gen_extract_i64(ret, arg, 0, 8); 2060 } 2061 2062 void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg) 2063 { 2064 tcg_gen_extract_i64(ret, arg, 0, 16); 2065 } 2066 2067 void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg) 2068 { 2069 tcg_gen_extract_i64(ret, arg, 0, 32); 2070 } 2071 2072 /* 2073 * bswap16_i64: 16-bit byte swap on the low bits of a 64-bit value. 2074 * 2075 * Byte pattern: xxxxxxxxab -> yyyyyyyyba 2076 * 2077 * With TCG_BSWAP_IZ, x == zero, else undefined. 2078 * With TCG_BSWAP_OZ, y == zero, with TCG_BSWAP_OS y == sign, else undefined. 2079 */ 2080 void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg, int flags) 2081 { 2082 /* Only one extension flag may be present. */ 2083 tcg_debug_assert(!(flags & TCG_BSWAP_OS) || !(flags & TCG_BSWAP_OZ)); 2084 2085 if (TCG_TARGET_REG_BITS == 32) { 2086 tcg_gen_bswap16_i32(TCGV_LOW(ret), TCGV_LOW(arg), flags); 2087 if (flags & TCG_BSWAP_OS) { 2088 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); 2089 } else { 2090 tcg_gen_movi_i32(TCGV_HIGH(ret), 0); 2091 } 2092 } else if (tcg_op_supported(INDEX_op_bswap16, TCG_TYPE_I64, 0)) { 2093 tcg_gen_op3i_i64(INDEX_op_bswap16, ret, arg, flags); 2094 } else { 2095 TCGv_i64 t0 = tcg_temp_ebb_new_i64(); 2096 TCGv_i64 t1 = tcg_temp_ebb_new_i64(); 2097 2098 /* arg = ......ab or xxxxxxab */ 2099 tcg_gen_shri_i64(t0, arg, 8); /* t0 = .......a or .xxxxxxa */ 2100 if (!(flags & TCG_BSWAP_IZ)) { 2101 tcg_gen_ext8u_i64(t0, t0); /* t0 = .......a */ 2102 } 2103 2104 if (flags & TCG_BSWAP_OS) { 2105 tcg_gen_shli_i64(t1, arg, 56); /* t1 = b....... */ 2106 tcg_gen_sari_i64(t1, t1, 48); /* t1 = ssssssb. */ 2107 } else if (flags & TCG_BSWAP_OZ) { 2108 tcg_gen_ext8u_i64(t1, arg); /* t1 = .......b */ 2109 tcg_gen_shli_i64(t1, t1, 8); /* t1 = ......b. */ 2110 } else { 2111 tcg_gen_shli_i64(t1, arg, 8); /* t1 = xxxxxab. */ 2112 } 2113 2114 tcg_gen_or_i64(ret, t0, t1); /* ret = ......ba (OZ) */ 2115 /* ssssssba (OS) */ 2116 /* xxxxxaba (no flag) */ 2117 tcg_temp_free_i64(t0); 2118 tcg_temp_free_i64(t1); 2119 } 2120 } 2121 2122 /* 2123 * bswap32_i64: 32-bit byte swap on the low bits of a 64-bit value. 2124 * 2125 * Byte pattern: xxxxabcd -> yyyydcba 2126 * 2127 * With TCG_BSWAP_IZ, x == zero, else undefined. 2128 * With TCG_BSWAP_OZ, y == zero, with TCG_BSWAP_OS y == sign, else undefined. 2129 */ 2130 void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg, int flags) 2131 { 2132 /* Only one extension flag may be present. */ 2133 tcg_debug_assert(!(flags & TCG_BSWAP_OS) || !(flags & TCG_BSWAP_OZ)); 2134 2135 if (TCG_TARGET_REG_BITS == 32) { 2136 tcg_gen_bswap32_i32(TCGV_LOW(ret), TCGV_LOW(arg)); 2137 if (flags & TCG_BSWAP_OS) { 2138 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); 2139 } else { 2140 tcg_gen_movi_i32(TCGV_HIGH(ret), 0); 2141 } 2142 } else if (tcg_op_supported(INDEX_op_bswap32, TCG_TYPE_I64, 0)) { 2143 tcg_gen_op3i_i64(INDEX_op_bswap32, ret, arg, flags); 2144 } else { 2145 TCGv_i64 t0 = tcg_temp_ebb_new_i64(); 2146 TCGv_i64 t1 = tcg_temp_ebb_new_i64(); 2147 TCGv_i64 t2 = tcg_constant_i64(0x00ff00ff); 2148 2149 /* arg = xxxxabcd */ 2150 tcg_gen_shri_i64(t0, arg, 8); /* t0 = .xxxxabc */ 2151 tcg_gen_and_i64(t1, arg, t2); /* t1 = .....b.d */ 2152 tcg_gen_and_i64(t0, t0, t2); /* t0 = .....a.c */ 2153 tcg_gen_shli_i64(t1, t1, 8); /* t1 = ....b.d. */ 2154 tcg_gen_or_i64(ret, t0, t1); /* ret = ....badc */ 2155 2156 tcg_gen_shli_i64(t1, ret, 48); /* t1 = dc...... */ 2157 tcg_gen_shri_i64(t0, ret, 16); /* t0 = ......ba */ 2158 if (flags & TCG_BSWAP_OS) { 2159 tcg_gen_sari_i64(t1, t1, 32); /* t1 = ssssdc.. */ 2160 } else { 2161 tcg_gen_shri_i64(t1, t1, 32); /* t1 = ....dc.. */ 2162 } 2163 tcg_gen_or_i64(ret, t0, t1); /* ret = ssssdcba (OS) */ 2164 /* ....dcba (else) */ 2165 2166 tcg_temp_free_i64(t0); 2167 tcg_temp_free_i64(t1); 2168 } 2169 } 2170 2171 /* 2172 * bswap64_i64: 64-bit byte swap on a 64-bit value. 2173 * 2174 * Byte pattern: abcdefgh -> hgfedcba 2175 */ 2176 void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg) 2177 { 2178 if (TCG_TARGET_REG_BITS == 32) { 2179 TCGv_i32 t0, t1; 2180 t0 = tcg_temp_ebb_new_i32(); 2181 t1 = tcg_temp_ebb_new_i32(); 2182 2183 tcg_gen_bswap32_i32(t0, TCGV_LOW(arg)); 2184 tcg_gen_bswap32_i32(t1, TCGV_HIGH(arg)); 2185 tcg_gen_mov_i32(TCGV_LOW(ret), t1); 2186 tcg_gen_mov_i32(TCGV_HIGH(ret), t0); 2187 tcg_temp_free_i32(t0); 2188 tcg_temp_free_i32(t1); 2189 } else if (tcg_op_supported(INDEX_op_bswap64, TCG_TYPE_I64, 0)) { 2190 tcg_gen_op3i_i64(INDEX_op_bswap64, ret, arg, 0); 2191 } else { 2192 TCGv_i64 t0 = tcg_temp_ebb_new_i64(); 2193 TCGv_i64 t1 = tcg_temp_ebb_new_i64(); 2194 TCGv_i64 t2 = tcg_temp_ebb_new_i64(); 2195 2196 /* arg = abcdefgh */ 2197 tcg_gen_movi_i64(t2, 0x00ff00ff00ff00ffull); 2198 tcg_gen_shri_i64(t0, arg, 8); /* t0 = .abcdefg */ 2199 tcg_gen_and_i64(t1, arg, t2); /* t1 = .b.d.f.h */ 2200 tcg_gen_and_i64(t0, t0, t2); /* t0 = .a.c.e.g */ 2201 tcg_gen_shli_i64(t1, t1, 8); /* t1 = b.d.f.h. */ 2202 tcg_gen_or_i64(ret, t0, t1); /* ret = badcfehg */ 2203 2204 tcg_gen_movi_i64(t2, 0x0000ffff0000ffffull); 2205 tcg_gen_shri_i64(t0, ret, 16); /* t0 = ..badcfe */ 2206 tcg_gen_and_i64(t1, ret, t2); /* t1 = ..dc..hg */ 2207 tcg_gen_and_i64(t0, t0, t2); /* t0 = ..ba..fe */ 2208 tcg_gen_shli_i64(t1, t1, 16); /* t1 = dc..hg.. */ 2209 tcg_gen_or_i64(ret, t0, t1); /* ret = dcbahgfe */ 2210 2211 tcg_gen_shri_i64(t0, ret, 32); /* t0 = ....dcba */ 2212 tcg_gen_shli_i64(t1, ret, 32); /* t1 = hgfe.... */ 2213 tcg_gen_or_i64(ret, t0, t1); /* ret = hgfedcba */ 2214 2215 tcg_temp_free_i64(t0); 2216 tcg_temp_free_i64(t1); 2217 tcg_temp_free_i64(t2); 2218 } 2219 } 2220 2221 /* 2222 * hswap_i64: Swap 16-bit halfwords within a 64-bit value. 2223 * See also include/qemu/bitops.h, hswap64. 2224 * 2225 * Byte pattern: abcdefgh -> ghefcdab 2226 */ 2227 void tcg_gen_hswap_i64(TCGv_i64 ret, TCGv_i64 arg) 2228 { 2229 uint64_t m = 0x0000ffff0000ffffull; 2230 TCGv_i64 t0 = tcg_temp_ebb_new_i64(); 2231 TCGv_i64 t1 = tcg_temp_ebb_new_i64(); 2232 2233 /* arg = abcdefgh */ 2234 tcg_gen_rotli_i64(t1, arg, 32); /* t1 = efghabcd */ 2235 tcg_gen_andi_i64(t0, t1, m); /* t0 = ..gh..cd */ 2236 tcg_gen_shli_i64(t0, t0, 16); /* t0 = gh..cd.. */ 2237 tcg_gen_shri_i64(t1, t1, 16); /* t1 = ..efghab */ 2238 tcg_gen_andi_i64(t1, t1, m); /* t1 = ..ef..ab */ 2239 tcg_gen_or_i64(ret, t0, t1); /* ret = ghefcdab */ 2240 2241 tcg_temp_free_i64(t0); 2242 tcg_temp_free_i64(t1); 2243 } 2244 2245 /* 2246 * wswap_i64: Swap 32-bit words within a 64-bit value. 2247 * 2248 * Byte pattern: abcdefgh -> efghabcd 2249 */ 2250 void tcg_gen_wswap_i64(TCGv_i64 ret, TCGv_i64 arg) 2251 { 2252 /* Swapping 2 32-bit elements is a rotate. */ 2253 tcg_gen_rotli_i64(ret, arg, 32); 2254 } 2255 2256 void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg) 2257 { 2258 if (TCG_TARGET_REG_BITS == 32) { 2259 tcg_gen_not_i32(TCGV_LOW(ret), TCGV_LOW(arg)); 2260 tcg_gen_not_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); 2261 } else if (tcg_op_supported(INDEX_op_not, TCG_TYPE_I64, 0)) { 2262 tcg_gen_op2_i64(INDEX_op_not, ret, arg); 2263 } else { 2264 tcg_gen_xori_i64(ret, arg, -1); 2265 } 2266 } 2267 2268 void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) 2269 { 2270 if (TCG_TARGET_REG_BITS == 32) { 2271 tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); 2272 tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); 2273 } else if (tcg_op_supported(INDEX_op_andc, TCG_TYPE_I64, 0)) { 2274 tcg_gen_op3_i64(INDEX_op_andc, ret, arg1, arg2); 2275 } else { 2276 TCGv_i64 t0 = tcg_temp_ebb_new_i64(); 2277 tcg_gen_not_i64(t0, arg2); 2278 tcg_gen_and_i64(ret, arg1, t0); 2279 tcg_temp_free_i64(t0); 2280 } 2281 } 2282 2283 void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) 2284 { 2285 if (TCG_TARGET_REG_BITS == 32) { 2286 tcg_gen_eqv_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); 2287 tcg_gen_eqv_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); 2288 } else if (tcg_op_supported(INDEX_op_eqv, TCG_TYPE_I64, 0)) { 2289 tcg_gen_op3_i64(INDEX_op_eqv, ret, arg1, arg2); 2290 } else { 2291 tcg_gen_xor_i64(ret, arg1, arg2); 2292 tcg_gen_not_i64(ret, ret); 2293 } 2294 } 2295 2296 void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) 2297 { 2298 if (TCG_TARGET_REG_BITS == 32) { 2299 tcg_gen_nand_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); 2300 tcg_gen_nand_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); 2301 } else if (tcg_op_supported(INDEX_op_nand, TCG_TYPE_I64, 0)) { 2302 tcg_gen_op3_i64(INDEX_op_nand, ret, arg1, arg2); 2303 } else { 2304 tcg_gen_and_i64(ret, arg1, arg2); 2305 tcg_gen_not_i64(ret, ret); 2306 } 2307 } 2308 2309 void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) 2310 { 2311 if (TCG_TARGET_REG_BITS == 32) { 2312 tcg_gen_nor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); 2313 tcg_gen_nor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); 2314 } else if (tcg_op_supported(INDEX_op_nor, TCG_TYPE_I64, 0)) { 2315 tcg_gen_op3_i64(INDEX_op_nor, ret, arg1, arg2); 2316 } else { 2317 tcg_gen_or_i64(ret, arg1, arg2); 2318 tcg_gen_not_i64(ret, ret); 2319 } 2320 } 2321 2322 void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) 2323 { 2324 if (TCG_TARGET_REG_BITS == 32) { 2325 tcg_gen_orc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); 2326 tcg_gen_orc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); 2327 } else if (tcg_op_supported(INDEX_op_orc, TCG_TYPE_I64, 0)) { 2328 tcg_gen_op3_i64(INDEX_op_orc, ret, arg1, arg2); 2329 } else { 2330 TCGv_i64 t0 = tcg_temp_ebb_new_i64(); 2331 tcg_gen_not_i64(t0, arg2); 2332 tcg_gen_or_i64(ret, arg1, t0); 2333 tcg_temp_free_i64(t0); 2334 } 2335 } 2336 2337 void tcg_gen_clz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) 2338 { 2339 if (tcg_op_supported(INDEX_op_clz, TCG_TYPE_I64, 0)) { 2340 tcg_gen_op3_i64(INDEX_op_clz, ret, arg1, arg2); 2341 } else { 2342 gen_helper_clz_i64(ret, arg1, arg2); 2343 } 2344 } 2345 2346 void tcg_gen_clzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2) 2347 { 2348 if (TCG_TARGET_REG_BITS == 32 2349 && arg2 <= 0xffffffffu 2350 && tcg_op_supported(INDEX_op_clz, TCG_TYPE_I32, 0)) { 2351 TCGv_i32 t = tcg_temp_ebb_new_i32(); 2352 tcg_gen_clzi_i32(t, TCGV_LOW(arg1), arg2 - 32); 2353 tcg_gen_addi_i32(t, t, 32); 2354 tcg_gen_clz_i32(TCGV_LOW(ret), TCGV_HIGH(arg1), t); 2355 tcg_gen_movi_i32(TCGV_HIGH(ret), 0); 2356 tcg_temp_free_i32(t); 2357 } else { 2358 tcg_gen_clz_i64(ret, arg1, tcg_constant_i64(arg2)); 2359 } 2360 } 2361 2362 void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) 2363 { 2364 TCGv_i64 z, t; 2365 2366 if (tcg_op_supported(INDEX_op_ctz, TCG_TYPE_I64, 0)) { 2367 tcg_gen_op3_i64(INDEX_op_ctz, ret, arg1, arg2); 2368 return; 2369 } 2370 if (tcg_op_supported(INDEX_op_ctpop, TCG_TYPE_I64, 0)) { 2371 t = tcg_temp_ebb_new_i64(); 2372 tcg_gen_subi_i64(t, arg1, 1); 2373 tcg_gen_andc_i64(t, t, arg1); 2374 tcg_gen_ctpop_i64(t, t); 2375 } else if (tcg_op_supported(INDEX_op_clz, TCG_TYPE_I64, 0)) { 2376 t = tcg_temp_ebb_new_i64(); 2377 tcg_gen_neg_i64(t, arg1); 2378 tcg_gen_and_i64(t, t, arg1); 2379 tcg_gen_clzi_i64(t, t, 64); 2380 tcg_gen_xori_i64(t, t, 63); 2381 } else { 2382 gen_helper_ctz_i64(ret, arg1, arg2); 2383 return; 2384 } 2385 2386 z = tcg_constant_i64(0); 2387 tcg_gen_movcond_i64(TCG_COND_EQ, ret, arg1, z, arg2, t); 2388 tcg_temp_free_i64(t); 2389 } 2390 2391 void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2) 2392 { 2393 if (TCG_TARGET_REG_BITS == 32 2394 && arg2 <= 0xffffffffu 2395 && tcg_op_supported(INDEX_op_ctz, TCG_TYPE_I32, 0)) { 2396 TCGv_i32 t32 = tcg_temp_ebb_new_i32(); 2397 tcg_gen_ctzi_i32(t32, TCGV_HIGH(arg1), arg2 - 32); 2398 tcg_gen_addi_i32(t32, t32, 32); 2399 tcg_gen_ctz_i32(TCGV_LOW(ret), TCGV_LOW(arg1), t32); 2400 tcg_gen_movi_i32(TCGV_HIGH(ret), 0); 2401 tcg_temp_free_i32(t32); 2402 } else if (arg2 == 64 2403 && !tcg_op_supported(INDEX_op_ctz, TCG_TYPE_I64, 0) 2404 && tcg_op_supported(INDEX_op_ctpop, TCG_TYPE_I64, 0)) { 2405 /* This equivalence has the advantage of not requiring a fixup. */ 2406 TCGv_i64 t = tcg_temp_ebb_new_i64(); 2407 tcg_gen_subi_i64(t, arg1, 1); 2408 tcg_gen_andc_i64(t, t, arg1); 2409 tcg_gen_ctpop_i64(ret, t); 2410 tcg_temp_free_i64(t); 2411 } else { 2412 tcg_gen_ctz_i64(ret, arg1, tcg_constant_i64(arg2)); 2413 } 2414 } 2415 2416 void tcg_gen_clrsb_i64(TCGv_i64 ret, TCGv_i64 arg) 2417 { 2418 if (tcg_op_supported(INDEX_op_clz, TCG_TYPE_I64, 0)) { 2419 TCGv_i64 t = tcg_temp_ebb_new_i64(); 2420 tcg_gen_sari_i64(t, arg, 63); 2421 tcg_gen_xor_i64(t, t, arg); 2422 tcg_gen_clzi_i64(t, t, 64); 2423 tcg_gen_subi_i64(ret, t, 1); 2424 tcg_temp_free_i64(t); 2425 } else { 2426 gen_helper_clrsb_i64(ret, arg); 2427 } 2428 } 2429 2430 void tcg_gen_ctpop_i64(TCGv_i64 ret, TCGv_i64 arg1) 2431 { 2432 if (TCG_TARGET_REG_BITS == 64) { 2433 if (tcg_op_supported(INDEX_op_ctpop, TCG_TYPE_I64, 0)) { 2434 tcg_gen_op2_i64(INDEX_op_ctpop, ret, arg1); 2435 return; 2436 } 2437 } else { 2438 if (tcg_op_supported(INDEX_op_ctpop, TCG_TYPE_I32, 0)) { 2439 tcg_gen_ctpop_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1)); 2440 tcg_gen_ctpop_i32(TCGV_LOW(ret), TCGV_LOW(arg1)); 2441 tcg_gen_add_i32(TCGV_LOW(ret), TCGV_LOW(ret), TCGV_HIGH(ret)); 2442 tcg_gen_movi_i32(TCGV_HIGH(ret), 0); 2443 return; 2444 } 2445 } 2446 gen_helper_ctpop_i64(ret, arg1); 2447 } 2448 2449 void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) 2450 { 2451 if (tcg_op_supported(INDEX_op_rotl, TCG_TYPE_I64, 0)) { 2452 tcg_gen_op3_i64(INDEX_op_rotl, ret, arg1, arg2); 2453 } else if (tcg_op_supported(INDEX_op_rotl, TCG_TYPE_I64, 0)) { 2454 TCGv_i64 t0 = tcg_temp_ebb_new_i64(); 2455 tcg_gen_neg_i64(t0, arg2); 2456 tcg_gen_op3_i64(INDEX_op_rotr, ret, arg1, t0); 2457 tcg_temp_free_i64(t0); 2458 } else { 2459 TCGv_i64 t0 = tcg_temp_ebb_new_i64(); 2460 TCGv_i64 t1 = tcg_temp_ebb_new_i64(); 2461 tcg_gen_shl_i64(t0, arg1, arg2); 2462 tcg_gen_neg_i64(t1, arg2); 2463 tcg_gen_shr_i64(t1, arg1, t1); 2464 tcg_gen_or_i64(ret, t0, t1); 2465 tcg_temp_free_i64(t0); 2466 tcg_temp_free_i64(t1); 2467 } 2468 } 2469 2470 void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) 2471 { 2472 tcg_debug_assert(arg2 >= 0 && arg2 < 64); 2473 /* some cases can be optimized here */ 2474 if (arg2 == 0) { 2475 tcg_gen_mov_i64(ret, arg1); 2476 } else if (tcg_op_supported(INDEX_op_rotl, TCG_TYPE_I64, 0)) { 2477 TCGv_i64 t0 = tcg_constant_i64(arg2); 2478 tcg_gen_op3_i64(INDEX_op_rotl, ret, arg1, t0); 2479 } else if (tcg_op_supported(INDEX_op_rotr, TCG_TYPE_I64, 0)) { 2480 TCGv_i64 t0 = tcg_constant_i64(64 - arg2); 2481 tcg_gen_op3_i64(INDEX_op_rotr, ret, arg1, t0); 2482 } else { 2483 TCGv_i64 t0 = tcg_temp_ebb_new_i64(); 2484 TCGv_i64 t1 = tcg_temp_ebb_new_i64(); 2485 tcg_gen_shli_i64(t0, arg1, arg2); 2486 tcg_gen_shri_i64(t1, arg1, 64 - arg2); 2487 tcg_gen_or_i64(ret, t0, t1); 2488 tcg_temp_free_i64(t0); 2489 tcg_temp_free_i64(t1); 2490 } 2491 } 2492 2493 void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) 2494 { 2495 if (tcg_op_supported(INDEX_op_rotr, TCG_TYPE_I64, 0)) { 2496 tcg_gen_op3_i64(INDEX_op_rotr, ret, arg1, arg2); 2497 } else if (tcg_op_supported(INDEX_op_rotl, TCG_TYPE_I64, 0)) { 2498 TCGv_i64 t0 = tcg_temp_ebb_new_i64(); 2499 tcg_gen_neg_i64(t0, arg2); 2500 tcg_gen_op3_i64(INDEX_op_rotl, ret, arg1, t0); 2501 tcg_temp_free_i64(t0); 2502 } else { 2503 TCGv_i64 t0 = tcg_temp_ebb_new_i64(); 2504 TCGv_i64 t1 = tcg_temp_ebb_new_i64(); 2505 tcg_gen_shr_i64(t0, arg1, arg2); 2506 tcg_gen_neg_i64(t1, arg2); 2507 tcg_gen_shl_i64(t1, arg1, t1); 2508 tcg_gen_or_i64(ret, t0, t1); 2509 tcg_temp_free_i64(t0); 2510 tcg_temp_free_i64(t1); 2511 } 2512 } 2513 2514 void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) 2515 { 2516 tcg_debug_assert(arg2 >= 0 && arg2 < 64); 2517 tcg_gen_rotli_i64(ret, arg1, -arg2 & 63); 2518 } 2519 2520 void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2, 2521 unsigned int ofs, unsigned int len) 2522 { 2523 uint64_t mask; 2524 TCGv_i64 t1; 2525 2526 tcg_debug_assert(ofs < 64); 2527 tcg_debug_assert(len > 0); 2528 tcg_debug_assert(len <= 64); 2529 tcg_debug_assert(ofs + len <= 64); 2530 2531 if (len == 64) { 2532 tcg_gen_mov_i64(ret, arg2); 2533 return; 2534 } 2535 2536 if (TCG_TARGET_REG_BITS == 64) { 2537 if (TCG_TARGET_deposit_valid(TCG_TYPE_I64, ofs, len)) { 2538 tcg_gen_op5ii_i64(INDEX_op_deposit, ret, arg1, arg2, ofs, len); 2539 return; 2540 } 2541 } else { 2542 if (ofs >= 32) { 2543 tcg_gen_deposit_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), 2544 TCGV_LOW(arg2), ofs - 32, len); 2545 tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg1)); 2546 return; 2547 } 2548 if (ofs + len <= 32) { 2549 tcg_gen_deposit_i32(TCGV_LOW(ret), TCGV_LOW(arg1), 2550 TCGV_LOW(arg2), ofs, len); 2551 tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1)); 2552 return; 2553 } 2554 } 2555 2556 t1 = tcg_temp_ebb_new_i64(); 2557 2558 if (tcg_op_supported(INDEX_op_extract2, TCG_TYPE_I64, 0)) { 2559 if (ofs + len == 64) { 2560 tcg_gen_shli_i64(t1, arg1, len); 2561 tcg_gen_extract2_i64(ret, t1, arg2, len); 2562 goto done; 2563 } 2564 if (ofs == 0) { 2565 tcg_gen_extract2_i64(ret, arg1, arg2, len); 2566 tcg_gen_rotli_i64(ret, ret, len); 2567 goto done; 2568 } 2569 } 2570 2571 mask = (1ull << len) - 1; 2572 if (ofs + len < 64) { 2573 tcg_gen_andi_i64(t1, arg2, mask); 2574 tcg_gen_shli_i64(t1, t1, ofs); 2575 } else { 2576 tcg_gen_shli_i64(t1, arg2, ofs); 2577 } 2578 tcg_gen_andi_i64(ret, arg1, ~(mask << ofs)); 2579 tcg_gen_or_i64(ret, ret, t1); 2580 done: 2581 tcg_temp_free_i64(t1); 2582 } 2583 2584 void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg, 2585 unsigned int ofs, unsigned int len) 2586 { 2587 tcg_debug_assert(ofs < 64); 2588 tcg_debug_assert(len > 0); 2589 tcg_debug_assert(len <= 64); 2590 tcg_debug_assert(ofs + len <= 64); 2591 2592 if (ofs + len == 64) { 2593 tcg_gen_shli_i64(ret, arg, ofs); 2594 } else if (ofs == 0) { 2595 tcg_gen_andi_i64(ret, arg, (1ull << len) - 1); 2596 } else if (TCG_TARGET_REG_BITS == 64 && 2597 TCG_TARGET_deposit_valid(TCG_TYPE_I64, ofs, len)) { 2598 TCGv_i64 zero = tcg_constant_i64(0); 2599 tcg_gen_op5ii_i64(INDEX_op_deposit, ret, zero, arg, ofs, len); 2600 } else { 2601 if (TCG_TARGET_REG_BITS == 32) { 2602 if (ofs >= 32) { 2603 tcg_gen_deposit_z_i32(TCGV_HIGH(ret), TCGV_LOW(arg), 2604 ofs - 32, len); 2605 tcg_gen_movi_i32(TCGV_LOW(ret), 0); 2606 return; 2607 } 2608 if (ofs + len <= 32) { 2609 tcg_gen_deposit_z_i32(TCGV_LOW(ret), TCGV_LOW(arg), ofs, len); 2610 tcg_gen_movi_i32(TCGV_HIGH(ret), 0); 2611 return; 2612 } 2613 } 2614 /* 2615 * To help two-operand hosts we prefer to zero-extend first, 2616 * which allows ARG to stay live. 2617 */ 2618 if (TCG_TARGET_extract_valid(TCG_TYPE_I64, 0, len)) { 2619 tcg_gen_extract_i64(ret, arg, 0, len); 2620 tcg_gen_shli_i64(ret, ret, ofs); 2621 return; 2622 } 2623 /* Otherwise prefer zero-extension over AND for code size. */ 2624 if (TCG_TARGET_extract_valid(TCG_TYPE_I64, 0, ofs + len)) { 2625 tcg_gen_shli_i64(ret, arg, ofs); 2626 tcg_gen_extract_i64(ret, ret, 0, ofs + len); 2627 return; 2628 } 2629 tcg_gen_andi_i64(ret, arg, (1ull << len) - 1); 2630 tcg_gen_shli_i64(ret, ret, ofs); 2631 } 2632 } 2633 2634 void tcg_gen_extract_i64(TCGv_i64 ret, TCGv_i64 arg, 2635 unsigned int ofs, unsigned int len) 2636 { 2637 tcg_debug_assert(ofs < 64); 2638 tcg_debug_assert(len > 0); 2639 tcg_debug_assert(len <= 64); 2640 tcg_debug_assert(ofs + len <= 64); 2641 2642 /* Canonicalize certain special cases, even if extract is supported. */ 2643 if (ofs + len == 64) { 2644 tcg_gen_shri_i64(ret, arg, 64 - len); 2645 return; 2646 } 2647 2648 if (TCG_TARGET_REG_BITS == 32) { 2649 /* Look for a 32-bit extract within one of the two words. */ 2650 if (ofs >= 32) { 2651 tcg_gen_extract_i32(TCGV_LOW(ret), TCGV_HIGH(arg), ofs - 32, len); 2652 tcg_gen_movi_i32(TCGV_HIGH(ret), 0); 2653 return; 2654 } 2655 if (ofs + len <= 32) { 2656 tcg_gen_extract_i32(TCGV_LOW(ret), TCGV_LOW(arg), ofs, len); 2657 tcg_gen_movi_i32(TCGV_HIGH(ret), 0); 2658 return; 2659 } 2660 2661 /* The field is split across two words. */ 2662 tcg_gen_extract2_i32(TCGV_LOW(ret), TCGV_LOW(arg), 2663 TCGV_HIGH(arg), ofs); 2664 if (len <= 32) { 2665 tcg_gen_extract_i32(TCGV_LOW(ret), TCGV_LOW(ret), 0, len); 2666 tcg_gen_movi_i32(TCGV_HIGH(ret), 0); 2667 } else { 2668 tcg_gen_extract_i32(TCGV_HIGH(ret), TCGV_HIGH(arg), 2669 ofs, len - 32); 2670 } 2671 return; 2672 } 2673 2674 if (TCG_TARGET_extract_valid(TCG_TYPE_I64, ofs, len)) { 2675 tcg_gen_op4ii_i64(INDEX_op_extract, ret, arg, ofs, len); 2676 return; 2677 } 2678 if (ofs == 0) { 2679 tcg_gen_andi_i64(ret, arg, (1ull << len) - 1); 2680 return; 2681 } 2682 2683 /* Assume that zero-extension, if available, is cheaper than a shift. */ 2684 if (TCG_TARGET_extract_valid(TCG_TYPE_I64, 0, ofs + len)) { 2685 tcg_gen_op4ii_i64(INDEX_op_extract, ret, arg, 0, ofs + len); 2686 tcg_gen_shri_i64(ret, ret, ofs); 2687 return; 2688 } 2689 2690 /* ??? Ideally we'd know what values are available for immediate AND. 2691 Assume that 8 bits are available, plus the special cases of 16 and 32, 2692 so that we get ext8u, ext16u, and ext32u. */ 2693 switch (len) { 2694 case 1 ... 8: case 16: case 32: 2695 tcg_gen_shri_i64(ret, arg, ofs); 2696 tcg_gen_andi_i64(ret, ret, (1ull << len) - 1); 2697 break; 2698 default: 2699 tcg_gen_shli_i64(ret, arg, 64 - len - ofs); 2700 tcg_gen_shri_i64(ret, ret, 64 - len); 2701 break; 2702 } 2703 } 2704 2705 void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg, 2706 unsigned int ofs, unsigned int len) 2707 { 2708 tcg_debug_assert(ofs < 64); 2709 tcg_debug_assert(len > 0); 2710 tcg_debug_assert(len <= 64); 2711 tcg_debug_assert(ofs + len <= 64); 2712 2713 /* Canonicalize certain special cases, even if sextract is supported. */ 2714 if (ofs + len == 64) { 2715 tcg_gen_sari_i64(ret, arg, 64 - len); 2716 return; 2717 } 2718 2719 if (TCG_TARGET_REG_BITS == 32) { 2720 /* Look for a 32-bit extract within one of the two words. */ 2721 if (ofs >= 32) { 2722 tcg_gen_sextract_i32(TCGV_LOW(ret), TCGV_HIGH(arg), ofs - 32, len); 2723 } else if (ofs + len <= 32) { 2724 tcg_gen_sextract_i32(TCGV_LOW(ret), TCGV_LOW(arg), ofs, len); 2725 } else if (ofs == 0) { 2726 tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); 2727 tcg_gen_sextract_i32(TCGV_HIGH(ret), TCGV_HIGH(arg), 0, len - 32); 2728 return; 2729 } else if (len > 32) { 2730 TCGv_i32 t = tcg_temp_ebb_new_i32(); 2731 /* Extract the bits for the high word normally. */ 2732 tcg_gen_sextract_i32(t, TCGV_HIGH(arg), ofs + 32, len - 32); 2733 /* Shift the field down for the low part. */ 2734 tcg_gen_shri_i64(ret, arg, ofs); 2735 /* Overwrite the shift into the high part. */ 2736 tcg_gen_mov_i32(TCGV_HIGH(ret), t); 2737 tcg_temp_free_i32(t); 2738 return; 2739 } else { 2740 /* Shift the field down for the low part, such that the 2741 field sits at the MSB. */ 2742 tcg_gen_shri_i64(ret, arg, ofs + len - 32); 2743 /* Shift the field down from the MSB, sign extending. */ 2744 tcg_gen_sari_i32(TCGV_LOW(ret), TCGV_LOW(ret), 32 - len); 2745 } 2746 /* Sign-extend the field from 32 bits. */ 2747 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); 2748 return; 2749 } 2750 2751 if (TCG_TARGET_sextract_valid(TCG_TYPE_I64, ofs, len)) { 2752 tcg_gen_op4ii_i64(INDEX_op_sextract, ret, arg, ofs, len); 2753 return; 2754 } 2755 2756 /* Assume that sign-extension, if available, is cheaper than a shift. */ 2757 if (TCG_TARGET_sextract_valid(TCG_TYPE_I64, 0, ofs + len)) { 2758 tcg_gen_op4ii_i64(INDEX_op_sextract, ret, arg, 0, ofs + len); 2759 tcg_gen_sari_i64(ret, ret, ofs); 2760 return; 2761 } 2762 if (TCG_TARGET_sextract_valid(TCG_TYPE_I64, 0, len)) { 2763 tcg_gen_shri_i64(ret, arg, ofs); 2764 tcg_gen_op4ii_i64(INDEX_op_sextract, ret, ret, 0, len); 2765 return; 2766 } 2767 2768 tcg_gen_shli_i64(ret, arg, 64 - len - ofs); 2769 tcg_gen_sari_i64(ret, ret, 64 - len); 2770 } 2771 2772 /* 2773 * Extract 64 bits from a 128-bit input, ah:al, starting from ofs. 2774 * Unlike tcg_gen_extract_i64 above, len is fixed at 64. 2775 */ 2776 void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah, 2777 unsigned int ofs) 2778 { 2779 tcg_debug_assert(ofs <= 64); 2780 if (ofs == 0) { 2781 tcg_gen_mov_i64(ret, al); 2782 } else if (ofs == 64) { 2783 tcg_gen_mov_i64(ret, ah); 2784 } else if (al == ah) { 2785 tcg_gen_rotri_i64(ret, al, ofs); 2786 } else if (tcg_op_supported(INDEX_op_extract2, TCG_TYPE_I64, 0)) { 2787 tcg_gen_op4i_i64(INDEX_op_extract2, ret, al, ah, ofs); 2788 } else { 2789 TCGv_i64 t0 = tcg_temp_ebb_new_i64(); 2790 tcg_gen_shri_i64(t0, al, ofs); 2791 tcg_gen_deposit_i64(ret, t0, ah, 64 - ofs, ofs); 2792 tcg_temp_free_i64(t0); 2793 } 2794 } 2795 2796 void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1, 2797 TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2) 2798 { 2799 if (cond == TCG_COND_ALWAYS) { 2800 tcg_gen_mov_i64(ret, v1); 2801 } else if (cond == TCG_COND_NEVER) { 2802 tcg_gen_mov_i64(ret, v2); 2803 } else if (TCG_TARGET_REG_BITS == 64) { 2804 tcg_gen_op6i_i64(INDEX_op_movcond, ret, c1, c2, v1, v2, cond); 2805 } else { 2806 TCGv_i32 t0 = tcg_temp_ebb_new_i32(); 2807 TCGv_i32 zero = tcg_constant_i32(0); 2808 2809 tcg_gen_op6i_i32(INDEX_op_setcond2_i32, t0, 2810 TCGV_LOW(c1), TCGV_HIGH(c1), 2811 TCGV_LOW(c2), TCGV_HIGH(c2), cond); 2812 2813 tcg_gen_movcond_i32(TCG_COND_NE, TCGV_LOW(ret), t0, zero, 2814 TCGV_LOW(v1), TCGV_LOW(v2)); 2815 tcg_gen_movcond_i32(TCG_COND_NE, TCGV_HIGH(ret), t0, zero, 2816 TCGV_HIGH(v1), TCGV_HIGH(v2)); 2817 2818 tcg_temp_free_i32(t0); 2819 } 2820 } 2821 2822 void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, 2823 TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh) 2824 { 2825 if (TCG_TARGET_HAS_add2_i64) { 2826 tcg_gen_op6_i64(INDEX_op_add2_i64, rl, rh, al, ah, bl, bh); 2827 } else { 2828 TCGv_i64 t0 = tcg_temp_ebb_new_i64(); 2829 TCGv_i64 t1 = tcg_temp_ebb_new_i64(); 2830 tcg_gen_add_i64(t0, al, bl); 2831 tcg_gen_setcond_i64(TCG_COND_LTU, t1, t0, al); 2832 tcg_gen_add_i64(rh, ah, bh); 2833 tcg_gen_add_i64(rh, rh, t1); 2834 tcg_gen_mov_i64(rl, t0); 2835 tcg_temp_free_i64(t0); 2836 tcg_temp_free_i64(t1); 2837 } 2838 } 2839 2840 void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, 2841 TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh) 2842 { 2843 if (TCG_TARGET_HAS_sub2_i64) { 2844 tcg_gen_op6_i64(INDEX_op_sub2_i64, rl, rh, al, ah, bl, bh); 2845 } else { 2846 TCGv_i64 t0 = tcg_temp_ebb_new_i64(); 2847 TCGv_i64 t1 = tcg_temp_ebb_new_i64(); 2848 tcg_gen_sub_i64(t0, al, bl); 2849 tcg_gen_setcond_i64(TCG_COND_LTU, t1, al, bl); 2850 tcg_gen_sub_i64(rh, ah, bh); 2851 tcg_gen_sub_i64(rh, rh, t1); 2852 tcg_gen_mov_i64(rl, t0); 2853 tcg_temp_free_i64(t0); 2854 tcg_temp_free_i64(t1); 2855 } 2856 } 2857 2858 void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2) 2859 { 2860 if (tcg_op_supported(INDEX_op_mulu2, TCG_TYPE_I64, 0)) { 2861 tcg_gen_op4_i64(INDEX_op_mulu2, rl, rh, arg1, arg2); 2862 } else if (tcg_op_supported(INDEX_op_muluh, TCG_TYPE_I64, 0)) { 2863 TCGv_i64 t = tcg_temp_ebb_new_i64(); 2864 tcg_gen_op3_i64(INDEX_op_mul, t, arg1, arg2); 2865 tcg_gen_op3_i64(INDEX_op_muluh, rh, arg1, arg2); 2866 tcg_gen_mov_i64(rl, t); 2867 tcg_temp_free_i64(t); 2868 } else { 2869 TCGv_i64 t0 = tcg_temp_ebb_new_i64(); 2870 tcg_gen_mul_i64(t0, arg1, arg2); 2871 gen_helper_muluh_i64(rh, arg1, arg2); 2872 tcg_gen_mov_i64(rl, t0); 2873 tcg_temp_free_i64(t0); 2874 } 2875 } 2876 2877 void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2) 2878 { 2879 if (tcg_op_supported(INDEX_op_muls2, TCG_TYPE_I64, 0)) { 2880 tcg_gen_op4_i64(INDEX_op_muls2, rl, rh, arg1, arg2); 2881 } else if (tcg_op_supported(INDEX_op_mulsh, TCG_TYPE_I64, 0)) { 2882 TCGv_i64 t = tcg_temp_ebb_new_i64(); 2883 tcg_gen_op3_i64(INDEX_op_mul, t, arg1, arg2); 2884 tcg_gen_op3_i64(INDEX_op_mulsh, rh, arg1, arg2); 2885 tcg_gen_mov_i64(rl, t); 2886 tcg_temp_free_i64(t); 2887 } else if (tcg_op_supported(INDEX_op_mulu2, TCG_TYPE_I64, 0) || 2888 tcg_op_supported(INDEX_op_muluh, TCG_TYPE_I64, 0)) { 2889 TCGv_i64 t0 = tcg_temp_ebb_new_i64(); 2890 TCGv_i64 t1 = tcg_temp_ebb_new_i64(); 2891 TCGv_i64 t2 = tcg_temp_ebb_new_i64(); 2892 TCGv_i64 t3 = tcg_temp_ebb_new_i64(); 2893 tcg_gen_mulu2_i64(t0, t1, arg1, arg2); 2894 /* Adjust for negative inputs. */ 2895 tcg_gen_sari_i64(t2, arg1, 63); 2896 tcg_gen_sari_i64(t3, arg2, 63); 2897 tcg_gen_and_i64(t2, t2, arg2); 2898 tcg_gen_and_i64(t3, t3, arg1); 2899 tcg_gen_sub_i64(rh, t1, t2); 2900 tcg_gen_sub_i64(rh, rh, t3); 2901 tcg_gen_mov_i64(rl, t0); 2902 tcg_temp_free_i64(t0); 2903 tcg_temp_free_i64(t1); 2904 tcg_temp_free_i64(t2); 2905 tcg_temp_free_i64(t3); 2906 } else { 2907 TCGv_i64 t0 = tcg_temp_ebb_new_i64(); 2908 tcg_gen_mul_i64(t0, arg1, arg2); 2909 gen_helper_mulsh_i64(rh, arg1, arg2); 2910 tcg_gen_mov_i64(rl, t0); 2911 tcg_temp_free_i64(t0); 2912 } 2913 } 2914 2915 void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2) 2916 { 2917 TCGv_i64 t0 = tcg_temp_ebb_new_i64(); 2918 TCGv_i64 t1 = tcg_temp_ebb_new_i64(); 2919 TCGv_i64 t2 = tcg_temp_ebb_new_i64(); 2920 tcg_gen_mulu2_i64(t0, t1, arg1, arg2); 2921 /* Adjust for negative input for the signed arg1. */ 2922 tcg_gen_sari_i64(t2, arg1, 63); 2923 tcg_gen_and_i64(t2, t2, arg2); 2924 tcg_gen_sub_i64(rh, t1, t2); 2925 tcg_gen_mov_i64(rl, t0); 2926 tcg_temp_free_i64(t0); 2927 tcg_temp_free_i64(t1); 2928 tcg_temp_free_i64(t2); 2929 } 2930 2931 void tcg_gen_smin_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b) 2932 { 2933 tcg_gen_movcond_i64(TCG_COND_LT, ret, a, b, a, b); 2934 } 2935 2936 void tcg_gen_umin_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b) 2937 { 2938 tcg_gen_movcond_i64(TCG_COND_LTU, ret, a, b, a, b); 2939 } 2940 2941 void tcg_gen_smax_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b) 2942 { 2943 tcg_gen_movcond_i64(TCG_COND_LT, ret, a, b, b, a); 2944 } 2945 2946 void tcg_gen_umax_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b) 2947 { 2948 tcg_gen_movcond_i64(TCG_COND_LTU, ret, a, b, b, a); 2949 } 2950 2951 void tcg_gen_abs_i64(TCGv_i64 ret, TCGv_i64 a) 2952 { 2953 TCGv_i64 t = tcg_temp_ebb_new_i64(); 2954 2955 tcg_gen_sari_i64(t, a, 63); 2956 tcg_gen_xor_i64(ret, a, t); 2957 tcg_gen_sub_i64(ret, ret, t); 2958 tcg_temp_free_i64(t); 2959 } 2960 2961 /* Size changing operations. */ 2962 2963 void tcg_gen_extrl_i64_i32(TCGv_i32 ret, TCGv_i64 arg) 2964 { 2965 if (TCG_TARGET_REG_BITS == 32) { 2966 tcg_gen_mov_i32(ret, TCGV_LOW(arg)); 2967 } else { 2968 tcg_gen_op2(INDEX_op_extrl_i64_i32, TCG_TYPE_I32, 2969 tcgv_i32_arg(ret), tcgv_i64_arg(arg)); 2970 } 2971 } 2972 2973 void tcg_gen_extrh_i64_i32(TCGv_i32 ret, TCGv_i64 arg) 2974 { 2975 if (TCG_TARGET_REG_BITS == 32) { 2976 tcg_gen_mov_i32(ret, TCGV_HIGH(arg)); 2977 } else { 2978 tcg_gen_op2(INDEX_op_extrh_i64_i32, TCG_TYPE_I32, 2979 tcgv_i32_arg(ret), tcgv_i64_arg(arg)); 2980 } 2981 } 2982 2983 void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg) 2984 { 2985 if (TCG_TARGET_REG_BITS == 32) { 2986 tcg_gen_mov_i32(TCGV_LOW(ret), arg); 2987 tcg_gen_movi_i32(TCGV_HIGH(ret), 0); 2988 } else { 2989 tcg_gen_op2(INDEX_op_extu_i32_i64, TCG_TYPE_I64, 2990 tcgv_i64_arg(ret), tcgv_i32_arg(arg)); 2991 } 2992 } 2993 2994 void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg) 2995 { 2996 if (TCG_TARGET_REG_BITS == 32) { 2997 tcg_gen_mov_i32(TCGV_LOW(ret), arg); 2998 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); 2999 } else { 3000 tcg_gen_op2(INDEX_op_ext_i32_i64, TCG_TYPE_I64, 3001 tcgv_i64_arg(ret), tcgv_i32_arg(arg)); 3002 } 3003 } 3004 3005 void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high) 3006 { 3007 TCGv_i64 tmp; 3008 3009 if (TCG_TARGET_REG_BITS == 32) { 3010 tcg_gen_mov_i32(TCGV_LOW(dest), low); 3011 tcg_gen_mov_i32(TCGV_HIGH(dest), high); 3012 return; 3013 } 3014 3015 tmp = tcg_temp_ebb_new_i64(); 3016 /* These extensions are only needed for type correctness. 3017 We may be able to do better given target specific information. */ 3018 tcg_gen_extu_i32_i64(tmp, high); 3019 tcg_gen_extu_i32_i64(dest, low); 3020 /* If deposit is available, use it. Otherwise use the extra 3021 knowledge that we have of the zero-extensions above. */ 3022 if (TCG_TARGET_deposit_valid(TCG_TYPE_I64, 32, 32)) { 3023 tcg_gen_deposit_i64(dest, dest, tmp, 32, 32); 3024 } else { 3025 tcg_gen_shli_i64(tmp, tmp, 32); 3026 tcg_gen_or_i64(dest, dest, tmp); 3027 } 3028 tcg_temp_free_i64(tmp); 3029 } 3030 3031 void tcg_gen_extr_i64_i32(TCGv_i32 lo, TCGv_i32 hi, TCGv_i64 arg) 3032 { 3033 if (TCG_TARGET_REG_BITS == 32) { 3034 tcg_gen_mov_i32(lo, TCGV_LOW(arg)); 3035 tcg_gen_mov_i32(hi, TCGV_HIGH(arg)); 3036 } else { 3037 tcg_gen_extrl_i64_i32(lo, arg); 3038 tcg_gen_extrh_i64_i32(hi, arg); 3039 } 3040 } 3041 3042 void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg) 3043 { 3044 tcg_gen_ext32u_i64(lo, arg); 3045 tcg_gen_shri_i64(hi, arg, 32); 3046 } 3047 3048 void tcg_gen_concat32_i64(TCGv_i64 ret, TCGv_i64 lo, TCGv_i64 hi) 3049 { 3050 tcg_gen_deposit_i64(ret, lo, hi, 32, 32); 3051 } 3052 3053 void tcg_gen_extr_i128_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i128 arg) 3054 { 3055 tcg_gen_mov_i64(lo, TCGV128_LOW(arg)); 3056 tcg_gen_mov_i64(hi, TCGV128_HIGH(arg)); 3057 } 3058 3059 void tcg_gen_concat_i64_i128(TCGv_i128 ret, TCGv_i64 lo, TCGv_i64 hi) 3060 { 3061 tcg_gen_mov_i64(TCGV128_LOW(ret), lo); 3062 tcg_gen_mov_i64(TCGV128_HIGH(ret), hi); 3063 } 3064 3065 void tcg_gen_mov_i128(TCGv_i128 dst, TCGv_i128 src) 3066 { 3067 if (dst != src) { 3068 tcg_gen_mov_i64(TCGV128_LOW(dst), TCGV128_LOW(src)); 3069 tcg_gen_mov_i64(TCGV128_HIGH(dst), TCGV128_HIGH(src)); 3070 } 3071 } 3072 3073 void tcg_gen_ld_i128(TCGv_i128 ret, TCGv_ptr base, tcg_target_long offset) 3074 { 3075 if (HOST_BIG_ENDIAN) { 3076 tcg_gen_ld_i64(TCGV128_HIGH(ret), base, offset); 3077 tcg_gen_ld_i64(TCGV128_LOW(ret), base, offset + 8); 3078 } else { 3079 tcg_gen_ld_i64(TCGV128_LOW(ret), base, offset); 3080 tcg_gen_ld_i64(TCGV128_HIGH(ret), base, offset + 8); 3081 } 3082 } 3083 3084 void tcg_gen_st_i128(TCGv_i128 val, TCGv_ptr base, tcg_target_long offset) 3085 { 3086 if (HOST_BIG_ENDIAN) { 3087 tcg_gen_st_i64(TCGV128_HIGH(val), base, offset); 3088 tcg_gen_st_i64(TCGV128_LOW(val), base, offset + 8); 3089 } else { 3090 tcg_gen_st_i64(TCGV128_LOW(val), base, offset); 3091 tcg_gen_st_i64(TCGV128_HIGH(val), base, offset + 8); 3092 } 3093 } 3094 3095 /* QEMU specific operations. */ 3096 3097 void tcg_gen_exit_tb(const TranslationBlock *tb, unsigned idx) 3098 { 3099 /* 3100 * Let the jit code return the read-only version of the 3101 * TranslationBlock, so that we minimize the pc-relative 3102 * distance of the address of the exit_tb code to TB. 3103 * This will improve utilization of pc-relative address loads. 3104 * 3105 * TODO: Move this to translator_loop, so that all const 3106 * TranslationBlock pointers refer to read-only memory. 3107 * This requires coordination with targets that do not use 3108 * the translator_loop. 3109 */ 3110 uintptr_t val = (uintptr_t)tcg_splitwx_to_rx((void *)tb) + idx; 3111 3112 if (tb == NULL) { 3113 tcg_debug_assert(idx == 0); 3114 } else if (idx <= TB_EXIT_IDXMAX) { 3115 #ifdef CONFIG_DEBUG_TCG 3116 /* This is an exit following a goto_tb. Verify that we have 3117 seen this numbered exit before, via tcg_gen_goto_tb. */ 3118 tcg_debug_assert(tcg_ctx->goto_tb_issue_mask & (1 << idx)); 3119 #endif 3120 } else { 3121 /* This is an exit via the exitreq label. */ 3122 tcg_debug_assert(idx == TB_EXIT_REQUESTED); 3123 } 3124 3125 tcg_gen_op1i(INDEX_op_exit_tb, 0, val); 3126 } 3127 3128 void tcg_gen_goto_tb(unsigned idx) 3129 { 3130 /* We tested CF_NO_GOTO_TB in translator_use_goto_tb. */ 3131 tcg_debug_assert(!(tcg_ctx->gen_tb->cflags & CF_NO_GOTO_TB)); 3132 /* We only support two chained exits. */ 3133 tcg_debug_assert(idx <= TB_EXIT_IDXMAX); 3134 #ifdef CONFIG_DEBUG_TCG 3135 /* Verify that we haven't seen this numbered exit before. */ 3136 tcg_debug_assert((tcg_ctx->goto_tb_issue_mask & (1 << idx)) == 0); 3137 tcg_ctx->goto_tb_issue_mask |= 1 << idx; 3138 #endif 3139 plugin_gen_disable_mem_helpers(); 3140 tcg_gen_op1i(INDEX_op_goto_tb, 0, idx); 3141 } 3142 3143 void tcg_gen_lookup_and_goto_ptr(void) 3144 { 3145 TCGv_ptr ptr; 3146 3147 if (tcg_ctx->gen_tb->cflags & CF_NO_GOTO_PTR) { 3148 tcg_gen_exit_tb(NULL, 0); 3149 return; 3150 } 3151 3152 plugin_gen_disable_mem_helpers(); 3153 ptr = tcg_temp_ebb_new_ptr(); 3154 gen_helper_lookup_tb_ptr(ptr, tcg_env); 3155 tcg_gen_op1i(INDEX_op_goto_ptr, TCG_TYPE_PTR, tcgv_ptr_arg(ptr)); 3156 tcg_temp_free_ptr(ptr); 3157 } 3158