1 /* 2 * Generic vector operation expansion 3 * 4 * Copyright (c) 2018 Linaro 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "tcg/tcg.h" 22 #include "tcg/tcg-temp-internal.h" 23 #include "tcg/tcg-op.h" 24 #include "tcg/tcg-op-gvec.h" 25 #include "tcg/tcg-gvec-desc.h" 26 27 #define MAX_UNROLL 4 28 29 #ifdef CONFIG_DEBUG_TCG 30 static const TCGOpcode vecop_list_empty[1] = { 0 }; 31 #else 32 #define vecop_list_empty NULL 33 #endif 34 35 36 /* Verify vector size and alignment rules. OFS should be the OR of all 37 of the operand offsets so that we can check them all at once. */ 38 static void check_size_align(uint32_t oprsz, uint32_t maxsz, uint32_t ofs) 39 { 40 uint32_t max_align; 41 42 switch (oprsz) { 43 case 8: 44 case 16: 45 case 32: 46 tcg_debug_assert(oprsz <= maxsz); 47 break; 48 default: 49 tcg_debug_assert(oprsz == maxsz); 50 break; 51 } 52 tcg_debug_assert(maxsz <= (8 << SIMD_MAXSZ_BITS)); 53 54 max_align = maxsz >= 16 ? 15 : 7; 55 tcg_debug_assert((maxsz & max_align) == 0); 56 tcg_debug_assert((ofs & max_align) == 0); 57 } 58 59 /* Verify vector overlap rules for two operands. */ 60 static void check_overlap_2(uint32_t d, uint32_t a, uint32_t s) 61 { 62 tcg_debug_assert(d == a || d + s <= a || a + s <= d); 63 } 64 65 /* Verify vector overlap rules for three operands. */ 66 static void check_overlap_3(uint32_t d, uint32_t a, uint32_t b, uint32_t s) 67 { 68 check_overlap_2(d, a, s); 69 check_overlap_2(d, b, s); 70 check_overlap_2(a, b, s); 71 } 72 73 /* Verify vector overlap rules for four operands. */ 74 static void check_overlap_4(uint32_t d, uint32_t a, uint32_t b, 75 uint32_t c, uint32_t s) 76 { 77 check_overlap_2(d, a, s); 78 check_overlap_2(d, b, s); 79 check_overlap_2(d, c, s); 80 check_overlap_2(a, b, s); 81 check_overlap_2(a, c, s); 82 check_overlap_2(b, c, s); 83 } 84 85 /* Create a descriptor from components. */ 86 uint32_t simd_desc(uint32_t oprsz, uint32_t maxsz, int32_t data) 87 { 88 uint32_t desc = 0; 89 90 check_size_align(oprsz, maxsz, 0); 91 tcg_debug_assert(data == sextract32(data, 0, SIMD_DATA_BITS)); 92 93 oprsz = (oprsz / 8) - 1; 94 maxsz = (maxsz / 8) - 1; 95 96 /* 97 * We have just asserted in check_size_align that either 98 * oprsz is {8,16,32} or matches maxsz. Encode the final 99 * case with '2', as that would otherwise map to 24. 100 */ 101 if (oprsz == maxsz) { 102 oprsz = 2; 103 } 104 105 desc = deposit32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS, oprsz); 106 desc = deposit32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS, maxsz); 107 desc = deposit32(desc, SIMD_DATA_SHIFT, SIMD_DATA_BITS, data); 108 109 return desc; 110 } 111 112 /* Generate a call to a gvec-style helper with two vector operands. */ 113 void tcg_gen_gvec_2_ool(uint32_t dofs, uint32_t aofs, 114 uint32_t oprsz, uint32_t maxsz, int32_t data, 115 gen_helper_gvec_2 *fn) 116 { 117 TCGv_ptr a0, a1; 118 TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data)); 119 120 a0 = tcg_temp_ebb_new_ptr(); 121 a1 = tcg_temp_ebb_new_ptr(); 122 123 tcg_gen_addi_ptr(a0, cpu_env, dofs); 124 tcg_gen_addi_ptr(a1, cpu_env, aofs); 125 126 fn(a0, a1, desc); 127 128 tcg_temp_free_ptr(a0); 129 tcg_temp_free_ptr(a1); 130 } 131 132 /* Generate a call to a gvec-style helper with two vector operands 133 and one scalar operand. */ 134 void tcg_gen_gvec_2i_ool(uint32_t dofs, uint32_t aofs, TCGv_i64 c, 135 uint32_t oprsz, uint32_t maxsz, int32_t data, 136 gen_helper_gvec_2i *fn) 137 { 138 TCGv_ptr a0, a1; 139 TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data)); 140 141 a0 = tcg_temp_ebb_new_ptr(); 142 a1 = tcg_temp_ebb_new_ptr(); 143 144 tcg_gen_addi_ptr(a0, cpu_env, dofs); 145 tcg_gen_addi_ptr(a1, cpu_env, aofs); 146 147 fn(a0, a1, c, desc); 148 149 tcg_temp_free_ptr(a0); 150 tcg_temp_free_ptr(a1); 151 } 152 153 /* Generate a call to a gvec-style helper with three vector operands. */ 154 void tcg_gen_gvec_3_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs, 155 uint32_t oprsz, uint32_t maxsz, int32_t data, 156 gen_helper_gvec_3 *fn) 157 { 158 TCGv_ptr a0, a1, a2; 159 TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data)); 160 161 a0 = tcg_temp_ebb_new_ptr(); 162 a1 = tcg_temp_ebb_new_ptr(); 163 a2 = tcg_temp_ebb_new_ptr(); 164 165 tcg_gen_addi_ptr(a0, cpu_env, dofs); 166 tcg_gen_addi_ptr(a1, cpu_env, aofs); 167 tcg_gen_addi_ptr(a2, cpu_env, bofs); 168 169 fn(a0, a1, a2, desc); 170 171 tcg_temp_free_ptr(a0); 172 tcg_temp_free_ptr(a1); 173 tcg_temp_free_ptr(a2); 174 } 175 176 /* Generate a call to a gvec-style helper with four vector operands. */ 177 void tcg_gen_gvec_4_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs, 178 uint32_t cofs, uint32_t oprsz, uint32_t maxsz, 179 int32_t data, gen_helper_gvec_4 *fn) 180 { 181 TCGv_ptr a0, a1, a2, a3; 182 TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data)); 183 184 a0 = tcg_temp_ebb_new_ptr(); 185 a1 = tcg_temp_ebb_new_ptr(); 186 a2 = tcg_temp_ebb_new_ptr(); 187 a3 = tcg_temp_ebb_new_ptr(); 188 189 tcg_gen_addi_ptr(a0, cpu_env, dofs); 190 tcg_gen_addi_ptr(a1, cpu_env, aofs); 191 tcg_gen_addi_ptr(a2, cpu_env, bofs); 192 tcg_gen_addi_ptr(a3, cpu_env, cofs); 193 194 fn(a0, a1, a2, a3, desc); 195 196 tcg_temp_free_ptr(a0); 197 tcg_temp_free_ptr(a1); 198 tcg_temp_free_ptr(a2); 199 tcg_temp_free_ptr(a3); 200 } 201 202 /* Generate a call to a gvec-style helper with five vector operands. */ 203 void tcg_gen_gvec_5_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs, 204 uint32_t cofs, uint32_t xofs, uint32_t oprsz, 205 uint32_t maxsz, int32_t data, gen_helper_gvec_5 *fn) 206 { 207 TCGv_ptr a0, a1, a2, a3, a4; 208 TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data)); 209 210 a0 = tcg_temp_ebb_new_ptr(); 211 a1 = tcg_temp_ebb_new_ptr(); 212 a2 = tcg_temp_ebb_new_ptr(); 213 a3 = tcg_temp_ebb_new_ptr(); 214 a4 = tcg_temp_ebb_new_ptr(); 215 216 tcg_gen_addi_ptr(a0, cpu_env, dofs); 217 tcg_gen_addi_ptr(a1, cpu_env, aofs); 218 tcg_gen_addi_ptr(a2, cpu_env, bofs); 219 tcg_gen_addi_ptr(a3, cpu_env, cofs); 220 tcg_gen_addi_ptr(a4, cpu_env, xofs); 221 222 fn(a0, a1, a2, a3, a4, desc); 223 224 tcg_temp_free_ptr(a0); 225 tcg_temp_free_ptr(a1); 226 tcg_temp_free_ptr(a2); 227 tcg_temp_free_ptr(a3); 228 tcg_temp_free_ptr(a4); 229 } 230 231 /* Generate a call to a gvec-style helper with three vector operands 232 and an extra pointer operand. */ 233 void tcg_gen_gvec_2_ptr(uint32_t dofs, uint32_t aofs, 234 TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz, 235 int32_t data, gen_helper_gvec_2_ptr *fn) 236 { 237 TCGv_ptr a0, a1; 238 TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data)); 239 240 a0 = tcg_temp_ebb_new_ptr(); 241 a1 = tcg_temp_ebb_new_ptr(); 242 243 tcg_gen_addi_ptr(a0, cpu_env, dofs); 244 tcg_gen_addi_ptr(a1, cpu_env, aofs); 245 246 fn(a0, a1, ptr, desc); 247 248 tcg_temp_free_ptr(a0); 249 tcg_temp_free_ptr(a1); 250 } 251 252 /* Generate a call to a gvec-style helper with three vector operands 253 and an extra pointer operand. */ 254 void tcg_gen_gvec_3_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs, 255 TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz, 256 int32_t data, gen_helper_gvec_3_ptr *fn) 257 { 258 TCGv_ptr a0, a1, a2; 259 TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data)); 260 261 a0 = tcg_temp_ebb_new_ptr(); 262 a1 = tcg_temp_ebb_new_ptr(); 263 a2 = tcg_temp_ebb_new_ptr(); 264 265 tcg_gen_addi_ptr(a0, cpu_env, dofs); 266 tcg_gen_addi_ptr(a1, cpu_env, aofs); 267 tcg_gen_addi_ptr(a2, cpu_env, bofs); 268 269 fn(a0, a1, a2, ptr, desc); 270 271 tcg_temp_free_ptr(a0); 272 tcg_temp_free_ptr(a1); 273 tcg_temp_free_ptr(a2); 274 } 275 276 /* Generate a call to a gvec-style helper with four vector operands 277 and an extra pointer operand. */ 278 void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs, 279 uint32_t cofs, TCGv_ptr ptr, uint32_t oprsz, 280 uint32_t maxsz, int32_t data, 281 gen_helper_gvec_4_ptr *fn) 282 { 283 TCGv_ptr a0, a1, a2, a3; 284 TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data)); 285 286 a0 = tcg_temp_ebb_new_ptr(); 287 a1 = tcg_temp_ebb_new_ptr(); 288 a2 = tcg_temp_ebb_new_ptr(); 289 a3 = tcg_temp_ebb_new_ptr(); 290 291 tcg_gen_addi_ptr(a0, cpu_env, dofs); 292 tcg_gen_addi_ptr(a1, cpu_env, aofs); 293 tcg_gen_addi_ptr(a2, cpu_env, bofs); 294 tcg_gen_addi_ptr(a3, cpu_env, cofs); 295 296 fn(a0, a1, a2, a3, ptr, desc); 297 298 tcg_temp_free_ptr(a0); 299 tcg_temp_free_ptr(a1); 300 tcg_temp_free_ptr(a2); 301 tcg_temp_free_ptr(a3); 302 } 303 304 /* Generate a call to a gvec-style helper with five vector operands 305 and an extra pointer operand. */ 306 void tcg_gen_gvec_5_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs, 307 uint32_t cofs, uint32_t eofs, TCGv_ptr ptr, 308 uint32_t oprsz, uint32_t maxsz, int32_t data, 309 gen_helper_gvec_5_ptr *fn) 310 { 311 TCGv_ptr a0, a1, a2, a3, a4; 312 TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data)); 313 314 a0 = tcg_temp_ebb_new_ptr(); 315 a1 = tcg_temp_ebb_new_ptr(); 316 a2 = tcg_temp_ebb_new_ptr(); 317 a3 = tcg_temp_ebb_new_ptr(); 318 a4 = tcg_temp_ebb_new_ptr(); 319 320 tcg_gen_addi_ptr(a0, cpu_env, dofs); 321 tcg_gen_addi_ptr(a1, cpu_env, aofs); 322 tcg_gen_addi_ptr(a2, cpu_env, bofs); 323 tcg_gen_addi_ptr(a3, cpu_env, cofs); 324 tcg_gen_addi_ptr(a4, cpu_env, eofs); 325 326 fn(a0, a1, a2, a3, a4, ptr, desc); 327 328 tcg_temp_free_ptr(a0); 329 tcg_temp_free_ptr(a1); 330 tcg_temp_free_ptr(a2); 331 tcg_temp_free_ptr(a3); 332 tcg_temp_free_ptr(a4); 333 } 334 335 /* Return true if we want to implement something of OPRSZ bytes 336 in units of LNSZ. This limits the expansion of inline code. */ 337 static inline bool check_size_impl(uint32_t oprsz, uint32_t lnsz) 338 { 339 uint32_t q, r; 340 341 if (oprsz < lnsz) { 342 return false; 343 } 344 345 q = oprsz / lnsz; 346 r = oprsz % lnsz; 347 tcg_debug_assert((r & 7) == 0); 348 349 if (lnsz < 16) { 350 /* For sizes below 16, accept no remainder. */ 351 if (r != 0) { 352 return false; 353 } 354 } else { 355 /* 356 * Recall that ARM SVE allows vector sizes that are not a 357 * power of 2, but always a multiple of 16. The intent is 358 * that e.g. size == 80 would be expanded with 2x32 + 1x16. 359 * In addition, expand_clr needs to handle a multiple of 8. 360 * Thus we can handle the tail with one more operation per 361 * diminishing power of 2. 362 */ 363 q += ctpop32(r); 364 } 365 366 return q <= MAX_UNROLL; 367 } 368 369 static void expand_clr(uint32_t dofs, uint32_t maxsz); 370 371 /* Duplicate C as per VECE. */ 372 uint64_t (dup_const)(unsigned vece, uint64_t c) 373 { 374 switch (vece) { 375 case MO_8: 376 return 0x0101010101010101ull * (uint8_t)c; 377 case MO_16: 378 return 0x0001000100010001ull * (uint16_t)c; 379 case MO_32: 380 return 0x0000000100000001ull * (uint32_t)c; 381 case MO_64: 382 return c; 383 default: 384 g_assert_not_reached(); 385 } 386 } 387 388 /* Duplicate IN into OUT as per VECE. */ 389 void tcg_gen_dup_i32(unsigned vece, TCGv_i32 out, TCGv_i32 in) 390 { 391 switch (vece) { 392 case MO_8: 393 tcg_gen_ext8u_i32(out, in); 394 tcg_gen_muli_i32(out, out, 0x01010101); 395 break; 396 case MO_16: 397 tcg_gen_deposit_i32(out, in, in, 16, 16); 398 break; 399 case MO_32: 400 tcg_gen_mov_i32(out, in); 401 break; 402 default: 403 g_assert_not_reached(); 404 } 405 } 406 407 void tcg_gen_dup_i64(unsigned vece, TCGv_i64 out, TCGv_i64 in) 408 { 409 switch (vece) { 410 case MO_8: 411 tcg_gen_ext8u_i64(out, in); 412 tcg_gen_muli_i64(out, out, 0x0101010101010101ull); 413 break; 414 case MO_16: 415 tcg_gen_ext16u_i64(out, in); 416 tcg_gen_muli_i64(out, out, 0x0001000100010001ull); 417 break; 418 case MO_32: 419 tcg_gen_deposit_i64(out, in, in, 32, 32); 420 break; 421 case MO_64: 422 tcg_gen_mov_i64(out, in); 423 break; 424 default: 425 g_assert_not_reached(); 426 } 427 } 428 429 /* Select a supported vector type for implementing an operation on SIZE 430 * bytes. If OP is 0, assume that the real operation to be performed is 431 * required by all backends. Otherwise, make sure than OP can be performed 432 * on elements of size VECE in the selected type. Do not select V64 if 433 * PREFER_I64 is true. Return 0 if no vector type is selected. 434 */ 435 static TCGType choose_vector_type(const TCGOpcode *list, unsigned vece, 436 uint32_t size, bool prefer_i64) 437 { 438 /* 439 * Recall that ARM SVE allows vector sizes that are not a 440 * power of 2, but always a multiple of 16. The intent is 441 * that e.g. size == 80 would be expanded with 2x32 + 1x16. 442 * It is hard to imagine a case in which v256 is supported 443 * but v128 is not, but check anyway. 444 * In addition, expand_clr needs to handle a multiple of 8. 445 */ 446 if (TCG_TARGET_HAS_v256 && 447 check_size_impl(size, 32) && 448 tcg_can_emit_vecop_list(list, TCG_TYPE_V256, vece) && 449 (!(size & 16) || 450 (TCG_TARGET_HAS_v128 && 451 tcg_can_emit_vecop_list(list, TCG_TYPE_V128, vece))) && 452 (!(size & 8) || 453 (TCG_TARGET_HAS_v64 && 454 tcg_can_emit_vecop_list(list, TCG_TYPE_V64, vece)))) { 455 return TCG_TYPE_V256; 456 } 457 if (TCG_TARGET_HAS_v128 && 458 check_size_impl(size, 16) && 459 tcg_can_emit_vecop_list(list, TCG_TYPE_V128, vece) && 460 (!(size & 8) || 461 (TCG_TARGET_HAS_v64 && 462 tcg_can_emit_vecop_list(list, TCG_TYPE_V64, vece)))) { 463 return TCG_TYPE_V128; 464 } 465 if (TCG_TARGET_HAS_v64 && !prefer_i64 && check_size_impl(size, 8) 466 && tcg_can_emit_vecop_list(list, TCG_TYPE_V64, vece)) { 467 return TCG_TYPE_V64; 468 } 469 return 0; 470 } 471 472 static void do_dup_store(TCGType type, uint32_t dofs, uint32_t oprsz, 473 uint32_t maxsz, TCGv_vec t_vec) 474 { 475 uint32_t i = 0; 476 477 tcg_debug_assert(oprsz >= 8); 478 479 /* 480 * This may be expand_clr for the tail of an operation, e.g. 481 * oprsz == 8 && maxsz == 64. The first 8 bytes of this store 482 * are misaligned wrt the maximum vector size, so do that first. 483 */ 484 if (dofs & 8) { 485 tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V64); 486 i += 8; 487 } 488 489 switch (type) { 490 case TCG_TYPE_V256: 491 /* 492 * Recall that ARM SVE allows vector sizes that are not a 493 * power of 2, but always a multiple of 16. The intent is 494 * that e.g. size == 80 would be expanded with 2x32 + 1x16. 495 */ 496 for (; i + 32 <= oprsz; i += 32) { 497 tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V256); 498 } 499 /* fallthru */ 500 case TCG_TYPE_V128: 501 for (; i + 16 <= oprsz; i += 16) { 502 tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V128); 503 } 504 break; 505 case TCG_TYPE_V64: 506 for (; i < oprsz; i += 8) { 507 tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V64); 508 } 509 break; 510 default: 511 g_assert_not_reached(); 512 } 513 514 if (oprsz < maxsz) { 515 expand_clr(dofs + oprsz, maxsz - oprsz); 516 } 517 } 518 519 /* Set OPRSZ bytes at DOFS to replications of IN_32, IN_64 or IN_C. 520 * Only one of IN_32 or IN_64 may be set; 521 * IN_C is used if IN_32 and IN_64 are unset. 522 */ 523 static void do_dup(unsigned vece, uint32_t dofs, uint32_t oprsz, 524 uint32_t maxsz, TCGv_i32 in_32, TCGv_i64 in_64, 525 uint64_t in_c) 526 { 527 TCGType type; 528 TCGv_i64 t_64; 529 TCGv_i32 t_32, t_desc; 530 TCGv_ptr t_ptr; 531 uint32_t i; 532 533 assert(vece <= (in_32 ? MO_32 : MO_64)); 534 assert(in_32 == NULL || in_64 == NULL); 535 536 /* If we're storing 0, expand oprsz to maxsz. */ 537 if (in_32 == NULL && in_64 == NULL) { 538 in_c = dup_const(vece, in_c); 539 if (in_c == 0) { 540 oprsz = maxsz; 541 vece = MO_8; 542 } else if (in_c == dup_const(MO_8, in_c)) { 543 vece = MO_8; 544 } 545 } 546 547 /* Implement inline with a vector type, if possible. 548 * Prefer integer when 64-bit host and no variable dup. 549 */ 550 type = choose_vector_type(NULL, vece, oprsz, 551 (TCG_TARGET_REG_BITS == 64 && in_32 == NULL 552 && (in_64 == NULL || vece == MO_64))); 553 if (type != 0) { 554 TCGv_vec t_vec = tcg_temp_new_vec(type); 555 556 if (in_32) { 557 tcg_gen_dup_i32_vec(vece, t_vec, in_32); 558 } else if (in_64) { 559 tcg_gen_dup_i64_vec(vece, t_vec, in_64); 560 } else { 561 tcg_gen_dupi_vec(vece, t_vec, in_c); 562 } 563 do_dup_store(type, dofs, oprsz, maxsz, t_vec); 564 tcg_temp_free_vec(t_vec); 565 return; 566 } 567 568 /* Otherwise, inline with an integer type, unless "large". */ 569 if (check_size_impl(oprsz, TCG_TARGET_REG_BITS / 8)) { 570 t_64 = NULL; 571 t_32 = NULL; 572 573 if (in_32) { 574 /* We are given a 32-bit variable input. For a 64-bit host, 575 use a 64-bit operation unless the 32-bit operation would 576 be simple enough. */ 577 if (TCG_TARGET_REG_BITS == 64 578 && (vece != MO_32 || !check_size_impl(oprsz, 4))) { 579 t_64 = tcg_temp_ebb_new_i64(); 580 tcg_gen_extu_i32_i64(t_64, in_32); 581 tcg_gen_dup_i64(vece, t_64, t_64); 582 } else { 583 t_32 = tcg_temp_ebb_new_i32(); 584 tcg_gen_dup_i32(vece, t_32, in_32); 585 } 586 } else if (in_64) { 587 /* We are given a 64-bit variable input. */ 588 t_64 = tcg_temp_ebb_new_i64(); 589 tcg_gen_dup_i64(vece, t_64, in_64); 590 } else { 591 /* We are given a constant input. */ 592 /* For 64-bit hosts, use 64-bit constants for "simple" constants 593 or when we'd need too many 32-bit stores, or when a 64-bit 594 constant is really required. */ 595 if (vece == MO_64 596 || (TCG_TARGET_REG_BITS == 64 597 && (in_c == 0 || in_c == -1 598 || !check_size_impl(oprsz, 4)))) { 599 t_64 = tcg_constant_i64(in_c); 600 } else { 601 t_32 = tcg_constant_i32(in_c); 602 } 603 } 604 605 /* Implement inline if we picked an implementation size above. */ 606 if (t_32) { 607 for (i = 0; i < oprsz; i += 4) { 608 tcg_gen_st_i32(t_32, cpu_env, dofs + i); 609 } 610 tcg_temp_free_i32(t_32); 611 goto done; 612 } 613 if (t_64) { 614 for (i = 0; i < oprsz; i += 8) { 615 tcg_gen_st_i64(t_64, cpu_env, dofs + i); 616 } 617 tcg_temp_free_i64(t_64); 618 goto done; 619 } 620 } 621 622 /* Otherwise implement out of line. */ 623 t_ptr = tcg_temp_ebb_new_ptr(); 624 tcg_gen_addi_ptr(t_ptr, cpu_env, dofs); 625 626 /* 627 * This may be expand_clr for the tail of an operation, e.g. 628 * oprsz == 8 && maxsz == 64. The size of the clear is misaligned 629 * wrt simd_desc and will assert. Simply pass all replicated byte 630 * stores through to memset. 631 */ 632 if (oprsz == maxsz && vece == MO_8) { 633 TCGv_ptr t_size = tcg_constant_ptr(oprsz); 634 TCGv_i32 t_val; 635 636 if (in_32) { 637 t_val = in_32; 638 } else if (in_64) { 639 t_val = tcg_temp_ebb_new_i32(); 640 tcg_gen_extrl_i64_i32(t_val, in_64); 641 } else { 642 t_val = tcg_constant_i32(in_c); 643 } 644 gen_helper_memset(t_ptr, t_ptr, t_val, t_size); 645 646 if (in_64) { 647 tcg_temp_free_i32(t_val); 648 } 649 tcg_temp_free_ptr(t_ptr); 650 return; 651 } 652 653 t_desc = tcg_constant_i32(simd_desc(oprsz, maxsz, 0)); 654 655 if (vece == MO_64) { 656 if (in_64) { 657 gen_helper_gvec_dup64(t_ptr, t_desc, in_64); 658 } else { 659 t_64 = tcg_constant_i64(in_c); 660 gen_helper_gvec_dup64(t_ptr, t_desc, t_64); 661 } 662 } else { 663 typedef void dup_fn(TCGv_ptr, TCGv_i32, TCGv_i32); 664 static dup_fn * const fns[3] = { 665 gen_helper_gvec_dup8, 666 gen_helper_gvec_dup16, 667 gen_helper_gvec_dup32 668 }; 669 670 if (in_32) { 671 fns[vece](t_ptr, t_desc, in_32); 672 } else if (in_64) { 673 t_32 = tcg_temp_ebb_new_i32(); 674 tcg_gen_extrl_i64_i32(t_32, in_64); 675 fns[vece](t_ptr, t_desc, t_32); 676 tcg_temp_free_i32(t_32); 677 } else { 678 if (vece == MO_8) { 679 in_c &= 0xff; 680 } else if (vece == MO_16) { 681 in_c &= 0xffff; 682 } 683 t_32 = tcg_constant_i32(in_c); 684 fns[vece](t_ptr, t_desc, t_32); 685 } 686 } 687 688 tcg_temp_free_ptr(t_ptr); 689 return; 690 691 done: 692 if (oprsz < maxsz) { 693 expand_clr(dofs + oprsz, maxsz - oprsz); 694 } 695 } 696 697 /* Likewise, but with zero. */ 698 static void expand_clr(uint32_t dofs, uint32_t maxsz) 699 { 700 do_dup(MO_8, dofs, maxsz, maxsz, NULL, NULL, 0); 701 } 702 703 /* Expand OPSZ bytes worth of two-operand operations using i32 elements. */ 704 static void expand_2_i32(uint32_t dofs, uint32_t aofs, uint32_t oprsz, 705 bool load_dest, void (*fni)(TCGv_i32, TCGv_i32)) 706 { 707 TCGv_i32 t0 = tcg_temp_new_i32(); 708 TCGv_i32 t1 = tcg_temp_new_i32(); 709 uint32_t i; 710 711 for (i = 0; i < oprsz; i += 4) { 712 tcg_gen_ld_i32(t0, cpu_env, aofs + i); 713 if (load_dest) { 714 tcg_gen_ld_i32(t1, cpu_env, dofs + i); 715 } 716 fni(t1, t0); 717 tcg_gen_st_i32(t1, cpu_env, dofs + i); 718 } 719 tcg_temp_free_i32(t0); 720 tcg_temp_free_i32(t1); 721 } 722 723 static void expand_2i_i32(uint32_t dofs, uint32_t aofs, uint32_t oprsz, 724 int32_t c, bool load_dest, 725 void (*fni)(TCGv_i32, TCGv_i32, int32_t)) 726 { 727 TCGv_i32 t0 = tcg_temp_new_i32(); 728 TCGv_i32 t1 = tcg_temp_new_i32(); 729 uint32_t i; 730 731 for (i = 0; i < oprsz; i += 4) { 732 tcg_gen_ld_i32(t0, cpu_env, aofs + i); 733 if (load_dest) { 734 tcg_gen_ld_i32(t1, cpu_env, dofs + i); 735 } 736 fni(t1, t0, c); 737 tcg_gen_st_i32(t1, cpu_env, dofs + i); 738 } 739 tcg_temp_free_i32(t0); 740 tcg_temp_free_i32(t1); 741 } 742 743 static void expand_2s_i32(uint32_t dofs, uint32_t aofs, uint32_t oprsz, 744 TCGv_i32 c, bool scalar_first, 745 void (*fni)(TCGv_i32, TCGv_i32, TCGv_i32)) 746 { 747 TCGv_i32 t0 = tcg_temp_new_i32(); 748 TCGv_i32 t1 = tcg_temp_new_i32(); 749 uint32_t i; 750 751 for (i = 0; i < oprsz; i += 4) { 752 tcg_gen_ld_i32(t0, cpu_env, aofs + i); 753 if (scalar_first) { 754 fni(t1, c, t0); 755 } else { 756 fni(t1, t0, c); 757 } 758 tcg_gen_st_i32(t1, cpu_env, dofs + i); 759 } 760 tcg_temp_free_i32(t0); 761 tcg_temp_free_i32(t1); 762 } 763 764 /* Expand OPSZ bytes worth of three-operand operations using i32 elements. */ 765 static void expand_3_i32(uint32_t dofs, uint32_t aofs, 766 uint32_t bofs, uint32_t oprsz, bool load_dest, 767 void (*fni)(TCGv_i32, TCGv_i32, TCGv_i32)) 768 { 769 TCGv_i32 t0 = tcg_temp_new_i32(); 770 TCGv_i32 t1 = tcg_temp_new_i32(); 771 TCGv_i32 t2 = tcg_temp_new_i32(); 772 uint32_t i; 773 774 for (i = 0; i < oprsz; i += 4) { 775 tcg_gen_ld_i32(t0, cpu_env, aofs + i); 776 tcg_gen_ld_i32(t1, cpu_env, bofs + i); 777 if (load_dest) { 778 tcg_gen_ld_i32(t2, cpu_env, dofs + i); 779 } 780 fni(t2, t0, t1); 781 tcg_gen_st_i32(t2, cpu_env, dofs + i); 782 } 783 tcg_temp_free_i32(t2); 784 tcg_temp_free_i32(t1); 785 tcg_temp_free_i32(t0); 786 } 787 788 static void expand_3i_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs, 789 uint32_t oprsz, int32_t c, bool load_dest, 790 void (*fni)(TCGv_i32, TCGv_i32, TCGv_i32, int32_t)) 791 { 792 TCGv_i32 t0 = tcg_temp_new_i32(); 793 TCGv_i32 t1 = tcg_temp_new_i32(); 794 TCGv_i32 t2 = tcg_temp_new_i32(); 795 uint32_t i; 796 797 for (i = 0; i < oprsz; i += 4) { 798 tcg_gen_ld_i32(t0, cpu_env, aofs + i); 799 tcg_gen_ld_i32(t1, cpu_env, bofs + i); 800 if (load_dest) { 801 tcg_gen_ld_i32(t2, cpu_env, dofs + i); 802 } 803 fni(t2, t0, t1, c); 804 tcg_gen_st_i32(t2, cpu_env, dofs + i); 805 } 806 tcg_temp_free_i32(t0); 807 tcg_temp_free_i32(t1); 808 tcg_temp_free_i32(t2); 809 } 810 811 /* Expand OPSZ bytes worth of three-operand operations using i32 elements. */ 812 static void expand_4_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs, 813 uint32_t cofs, uint32_t oprsz, bool write_aofs, 814 void (*fni)(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32)) 815 { 816 TCGv_i32 t0 = tcg_temp_new_i32(); 817 TCGv_i32 t1 = tcg_temp_new_i32(); 818 TCGv_i32 t2 = tcg_temp_new_i32(); 819 TCGv_i32 t3 = tcg_temp_new_i32(); 820 uint32_t i; 821 822 for (i = 0; i < oprsz; i += 4) { 823 tcg_gen_ld_i32(t1, cpu_env, aofs + i); 824 tcg_gen_ld_i32(t2, cpu_env, bofs + i); 825 tcg_gen_ld_i32(t3, cpu_env, cofs + i); 826 fni(t0, t1, t2, t3); 827 tcg_gen_st_i32(t0, cpu_env, dofs + i); 828 if (write_aofs) { 829 tcg_gen_st_i32(t1, cpu_env, aofs + i); 830 } 831 } 832 tcg_temp_free_i32(t3); 833 tcg_temp_free_i32(t2); 834 tcg_temp_free_i32(t1); 835 tcg_temp_free_i32(t0); 836 } 837 838 static void expand_4i_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs, 839 uint32_t cofs, uint32_t oprsz, int32_t c, 840 void (*fni)(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32, 841 int32_t)) 842 { 843 TCGv_i32 t0 = tcg_temp_new_i32(); 844 TCGv_i32 t1 = tcg_temp_new_i32(); 845 TCGv_i32 t2 = tcg_temp_new_i32(); 846 TCGv_i32 t3 = tcg_temp_new_i32(); 847 uint32_t i; 848 849 for (i = 0; i < oprsz; i += 4) { 850 tcg_gen_ld_i32(t1, cpu_env, aofs + i); 851 tcg_gen_ld_i32(t2, cpu_env, bofs + i); 852 tcg_gen_ld_i32(t3, cpu_env, cofs + i); 853 fni(t0, t1, t2, t3, c); 854 tcg_gen_st_i32(t0, cpu_env, dofs + i); 855 } 856 tcg_temp_free_i32(t3); 857 tcg_temp_free_i32(t2); 858 tcg_temp_free_i32(t1); 859 tcg_temp_free_i32(t0); 860 } 861 862 /* Expand OPSZ bytes worth of two-operand operations using i64 elements. */ 863 static void expand_2_i64(uint32_t dofs, uint32_t aofs, uint32_t oprsz, 864 bool load_dest, void (*fni)(TCGv_i64, TCGv_i64)) 865 { 866 TCGv_i64 t0 = tcg_temp_new_i64(); 867 TCGv_i64 t1 = tcg_temp_new_i64(); 868 uint32_t i; 869 870 for (i = 0; i < oprsz; i += 8) { 871 tcg_gen_ld_i64(t0, cpu_env, aofs + i); 872 if (load_dest) { 873 tcg_gen_ld_i64(t1, cpu_env, dofs + i); 874 } 875 fni(t1, t0); 876 tcg_gen_st_i64(t1, cpu_env, dofs + i); 877 } 878 tcg_temp_free_i64(t0); 879 tcg_temp_free_i64(t1); 880 } 881 882 static void expand_2i_i64(uint32_t dofs, uint32_t aofs, uint32_t oprsz, 883 int64_t c, bool load_dest, 884 void (*fni)(TCGv_i64, TCGv_i64, int64_t)) 885 { 886 TCGv_i64 t0 = tcg_temp_new_i64(); 887 TCGv_i64 t1 = tcg_temp_new_i64(); 888 uint32_t i; 889 890 for (i = 0; i < oprsz; i += 8) { 891 tcg_gen_ld_i64(t0, cpu_env, aofs + i); 892 if (load_dest) { 893 tcg_gen_ld_i64(t1, cpu_env, dofs + i); 894 } 895 fni(t1, t0, c); 896 tcg_gen_st_i64(t1, cpu_env, dofs + i); 897 } 898 tcg_temp_free_i64(t0); 899 tcg_temp_free_i64(t1); 900 } 901 902 static void expand_2s_i64(uint32_t dofs, uint32_t aofs, uint32_t oprsz, 903 TCGv_i64 c, bool scalar_first, 904 void (*fni)(TCGv_i64, TCGv_i64, TCGv_i64)) 905 { 906 TCGv_i64 t0 = tcg_temp_new_i64(); 907 TCGv_i64 t1 = tcg_temp_new_i64(); 908 uint32_t i; 909 910 for (i = 0; i < oprsz; i += 8) { 911 tcg_gen_ld_i64(t0, cpu_env, aofs + i); 912 if (scalar_first) { 913 fni(t1, c, t0); 914 } else { 915 fni(t1, t0, c); 916 } 917 tcg_gen_st_i64(t1, cpu_env, dofs + i); 918 } 919 tcg_temp_free_i64(t0); 920 tcg_temp_free_i64(t1); 921 } 922 923 /* Expand OPSZ bytes worth of three-operand operations using i64 elements. */ 924 static void expand_3_i64(uint32_t dofs, uint32_t aofs, 925 uint32_t bofs, uint32_t oprsz, bool load_dest, 926 void (*fni)(TCGv_i64, TCGv_i64, TCGv_i64)) 927 { 928 TCGv_i64 t0 = tcg_temp_new_i64(); 929 TCGv_i64 t1 = tcg_temp_new_i64(); 930 TCGv_i64 t2 = tcg_temp_new_i64(); 931 uint32_t i; 932 933 for (i = 0; i < oprsz; i += 8) { 934 tcg_gen_ld_i64(t0, cpu_env, aofs + i); 935 tcg_gen_ld_i64(t1, cpu_env, bofs + i); 936 if (load_dest) { 937 tcg_gen_ld_i64(t2, cpu_env, dofs + i); 938 } 939 fni(t2, t0, t1); 940 tcg_gen_st_i64(t2, cpu_env, dofs + i); 941 } 942 tcg_temp_free_i64(t2); 943 tcg_temp_free_i64(t1); 944 tcg_temp_free_i64(t0); 945 } 946 947 static void expand_3i_i64(uint32_t dofs, uint32_t aofs, uint32_t bofs, 948 uint32_t oprsz, int64_t c, bool load_dest, 949 void (*fni)(TCGv_i64, TCGv_i64, TCGv_i64, int64_t)) 950 { 951 TCGv_i64 t0 = tcg_temp_new_i64(); 952 TCGv_i64 t1 = tcg_temp_new_i64(); 953 TCGv_i64 t2 = tcg_temp_new_i64(); 954 uint32_t i; 955 956 for (i = 0; i < oprsz; i += 8) { 957 tcg_gen_ld_i64(t0, cpu_env, aofs + i); 958 tcg_gen_ld_i64(t1, cpu_env, bofs + i); 959 if (load_dest) { 960 tcg_gen_ld_i64(t2, cpu_env, dofs + i); 961 } 962 fni(t2, t0, t1, c); 963 tcg_gen_st_i64(t2, cpu_env, dofs + i); 964 } 965 tcg_temp_free_i64(t0); 966 tcg_temp_free_i64(t1); 967 tcg_temp_free_i64(t2); 968 } 969 970 /* Expand OPSZ bytes worth of three-operand operations using i64 elements. */ 971 static void expand_4_i64(uint32_t dofs, uint32_t aofs, uint32_t bofs, 972 uint32_t cofs, uint32_t oprsz, bool write_aofs, 973 void (*fni)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64)) 974 { 975 TCGv_i64 t0 = tcg_temp_new_i64(); 976 TCGv_i64 t1 = tcg_temp_new_i64(); 977 TCGv_i64 t2 = tcg_temp_new_i64(); 978 TCGv_i64 t3 = tcg_temp_new_i64(); 979 uint32_t i; 980 981 for (i = 0; i < oprsz; i += 8) { 982 tcg_gen_ld_i64(t1, cpu_env, aofs + i); 983 tcg_gen_ld_i64(t2, cpu_env, bofs + i); 984 tcg_gen_ld_i64(t3, cpu_env, cofs + i); 985 fni(t0, t1, t2, t3); 986 tcg_gen_st_i64(t0, cpu_env, dofs + i); 987 if (write_aofs) { 988 tcg_gen_st_i64(t1, cpu_env, aofs + i); 989 } 990 } 991 tcg_temp_free_i64(t3); 992 tcg_temp_free_i64(t2); 993 tcg_temp_free_i64(t1); 994 tcg_temp_free_i64(t0); 995 } 996 997 static void expand_4i_i64(uint32_t dofs, uint32_t aofs, uint32_t bofs, 998 uint32_t cofs, uint32_t oprsz, int64_t c, 999 void (*fni)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64, 1000 int64_t)) 1001 { 1002 TCGv_i64 t0 = tcg_temp_new_i64(); 1003 TCGv_i64 t1 = tcg_temp_new_i64(); 1004 TCGv_i64 t2 = tcg_temp_new_i64(); 1005 TCGv_i64 t3 = tcg_temp_new_i64(); 1006 uint32_t i; 1007 1008 for (i = 0; i < oprsz; i += 8) { 1009 tcg_gen_ld_i64(t1, cpu_env, aofs + i); 1010 tcg_gen_ld_i64(t2, cpu_env, bofs + i); 1011 tcg_gen_ld_i64(t3, cpu_env, cofs + i); 1012 fni(t0, t1, t2, t3, c); 1013 tcg_gen_st_i64(t0, cpu_env, dofs + i); 1014 } 1015 tcg_temp_free_i64(t3); 1016 tcg_temp_free_i64(t2); 1017 tcg_temp_free_i64(t1); 1018 tcg_temp_free_i64(t0); 1019 } 1020 1021 /* Expand OPSZ bytes worth of two-operand operations using host vectors. */ 1022 static void expand_2_vec(unsigned vece, uint32_t dofs, uint32_t aofs, 1023 uint32_t oprsz, uint32_t tysz, TCGType type, 1024 bool load_dest, 1025 void (*fni)(unsigned, TCGv_vec, TCGv_vec)) 1026 { 1027 TCGv_vec t0 = tcg_temp_new_vec(type); 1028 TCGv_vec t1 = tcg_temp_new_vec(type); 1029 uint32_t i; 1030 1031 for (i = 0; i < oprsz; i += tysz) { 1032 tcg_gen_ld_vec(t0, cpu_env, aofs + i); 1033 if (load_dest) { 1034 tcg_gen_ld_vec(t1, cpu_env, dofs + i); 1035 } 1036 fni(vece, t1, t0); 1037 tcg_gen_st_vec(t1, cpu_env, dofs + i); 1038 } 1039 tcg_temp_free_vec(t0); 1040 tcg_temp_free_vec(t1); 1041 } 1042 1043 /* Expand OPSZ bytes worth of two-vector operands and an immediate operand 1044 using host vectors. */ 1045 static void expand_2i_vec(unsigned vece, uint32_t dofs, uint32_t aofs, 1046 uint32_t oprsz, uint32_t tysz, TCGType type, 1047 int64_t c, bool load_dest, 1048 void (*fni)(unsigned, TCGv_vec, TCGv_vec, int64_t)) 1049 { 1050 TCGv_vec t0 = tcg_temp_new_vec(type); 1051 TCGv_vec t1 = tcg_temp_new_vec(type); 1052 uint32_t i; 1053 1054 for (i = 0; i < oprsz; i += tysz) { 1055 tcg_gen_ld_vec(t0, cpu_env, aofs + i); 1056 if (load_dest) { 1057 tcg_gen_ld_vec(t1, cpu_env, dofs + i); 1058 } 1059 fni(vece, t1, t0, c); 1060 tcg_gen_st_vec(t1, cpu_env, dofs + i); 1061 } 1062 tcg_temp_free_vec(t0); 1063 tcg_temp_free_vec(t1); 1064 } 1065 1066 static void expand_2s_vec(unsigned vece, uint32_t dofs, uint32_t aofs, 1067 uint32_t oprsz, uint32_t tysz, TCGType type, 1068 TCGv_vec c, bool scalar_first, 1069 void (*fni)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec)) 1070 { 1071 TCGv_vec t0 = tcg_temp_new_vec(type); 1072 TCGv_vec t1 = tcg_temp_new_vec(type); 1073 uint32_t i; 1074 1075 for (i = 0; i < oprsz; i += tysz) { 1076 tcg_gen_ld_vec(t0, cpu_env, aofs + i); 1077 if (scalar_first) { 1078 fni(vece, t1, c, t0); 1079 } else { 1080 fni(vece, t1, t0, c); 1081 } 1082 tcg_gen_st_vec(t1, cpu_env, dofs + i); 1083 } 1084 tcg_temp_free_vec(t0); 1085 tcg_temp_free_vec(t1); 1086 } 1087 1088 /* Expand OPSZ bytes worth of three-operand operations using host vectors. */ 1089 static void expand_3_vec(unsigned vece, uint32_t dofs, uint32_t aofs, 1090 uint32_t bofs, uint32_t oprsz, 1091 uint32_t tysz, TCGType type, bool load_dest, 1092 void (*fni)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec)) 1093 { 1094 TCGv_vec t0 = tcg_temp_new_vec(type); 1095 TCGv_vec t1 = tcg_temp_new_vec(type); 1096 TCGv_vec t2 = tcg_temp_new_vec(type); 1097 uint32_t i; 1098 1099 for (i = 0; i < oprsz; i += tysz) { 1100 tcg_gen_ld_vec(t0, cpu_env, aofs + i); 1101 tcg_gen_ld_vec(t1, cpu_env, bofs + i); 1102 if (load_dest) { 1103 tcg_gen_ld_vec(t2, cpu_env, dofs + i); 1104 } 1105 fni(vece, t2, t0, t1); 1106 tcg_gen_st_vec(t2, cpu_env, dofs + i); 1107 } 1108 tcg_temp_free_vec(t2); 1109 tcg_temp_free_vec(t1); 1110 tcg_temp_free_vec(t0); 1111 } 1112 1113 /* 1114 * Expand OPSZ bytes worth of three-vector operands and an immediate operand 1115 * using host vectors. 1116 */ 1117 static void expand_3i_vec(unsigned vece, uint32_t dofs, uint32_t aofs, 1118 uint32_t bofs, uint32_t oprsz, uint32_t tysz, 1119 TCGType type, int64_t c, bool load_dest, 1120 void (*fni)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec, 1121 int64_t)) 1122 { 1123 TCGv_vec t0 = tcg_temp_new_vec(type); 1124 TCGv_vec t1 = tcg_temp_new_vec(type); 1125 TCGv_vec t2 = tcg_temp_new_vec(type); 1126 uint32_t i; 1127 1128 for (i = 0; i < oprsz; i += tysz) { 1129 tcg_gen_ld_vec(t0, cpu_env, aofs + i); 1130 tcg_gen_ld_vec(t1, cpu_env, bofs + i); 1131 if (load_dest) { 1132 tcg_gen_ld_vec(t2, cpu_env, dofs + i); 1133 } 1134 fni(vece, t2, t0, t1, c); 1135 tcg_gen_st_vec(t2, cpu_env, dofs + i); 1136 } 1137 tcg_temp_free_vec(t0); 1138 tcg_temp_free_vec(t1); 1139 tcg_temp_free_vec(t2); 1140 } 1141 1142 /* Expand OPSZ bytes worth of four-operand operations using host vectors. */ 1143 static void expand_4_vec(unsigned vece, uint32_t dofs, uint32_t aofs, 1144 uint32_t bofs, uint32_t cofs, uint32_t oprsz, 1145 uint32_t tysz, TCGType type, bool write_aofs, 1146 void (*fni)(unsigned, TCGv_vec, TCGv_vec, 1147 TCGv_vec, TCGv_vec)) 1148 { 1149 TCGv_vec t0 = tcg_temp_new_vec(type); 1150 TCGv_vec t1 = tcg_temp_new_vec(type); 1151 TCGv_vec t2 = tcg_temp_new_vec(type); 1152 TCGv_vec t3 = tcg_temp_new_vec(type); 1153 uint32_t i; 1154 1155 for (i = 0; i < oprsz; i += tysz) { 1156 tcg_gen_ld_vec(t1, cpu_env, aofs + i); 1157 tcg_gen_ld_vec(t2, cpu_env, bofs + i); 1158 tcg_gen_ld_vec(t3, cpu_env, cofs + i); 1159 fni(vece, t0, t1, t2, t3); 1160 tcg_gen_st_vec(t0, cpu_env, dofs + i); 1161 if (write_aofs) { 1162 tcg_gen_st_vec(t1, cpu_env, aofs + i); 1163 } 1164 } 1165 tcg_temp_free_vec(t3); 1166 tcg_temp_free_vec(t2); 1167 tcg_temp_free_vec(t1); 1168 tcg_temp_free_vec(t0); 1169 } 1170 1171 /* 1172 * Expand OPSZ bytes worth of four-vector operands and an immediate operand 1173 * using host vectors. 1174 */ 1175 static void expand_4i_vec(unsigned vece, uint32_t dofs, uint32_t aofs, 1176 uint32_t bofs, uint32_t cofs, uint32_t oprsz, 1177 uint32_t tysz, TCGType type, int64_t c, 1178 void (*fni)(unsigned, TCGv_vec, TCGv_vec, 1179 TCGv_vec, TCGv_vec, int64_t)) 1180 { 1181 TCGv_vec t0 = tcg_temp_new_vec(type); 1182 TCGv_vec t1 = tcg_temp_new_vec(type); 1183 TCGv_vec t2 = tcg_temp_new_vec(type); 1184 TCGv_vec t3 = tcg_temp_new_vec(type); 1185 uint32_t i; 1186 1187 for (i = 0; i < oprsz; i += tysz) { 1188 tcg_gen_ld_vec(t1, cpu_env, aofs + i); 1189 tcg_gen_ld_vec(t2, cpu_env, bofs + i); 1190 tcg_gen_ld_vec(t3, cpu_env, cofs + i); 1191 fni(vece, t0, t1, t2, t3, c); 1192 tcg_gen_st_vec(t0, cpu_env, dofs + i); 1193 } 1194 tcg_temp_free_vec(t3); 1195 tcg_temp_free_vec(t2); 1196 tcg_temp_free_vec(t1); 1197 tcg_temp_free_vec(t0); 1198 } 1199 1200 /* Expand a vector two-operand operation. */ 1201 void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs, 1202 uint32_t oprsz, uint32_t maxsz, const GVecGen2 *g) 1203 { 1204 const TCGOpcode *this_list = g->opt_opc ? : vecop_list_empty; 1205 const TCGOpcode *hold_list = tcg_swap_vecop_list(this_list); 1206 TCGType type; 1207 uint32_t some; 1208 1209 check_size_align(oprsz, maxsz, dofs | aofs); 1210 check_overlap_2(dofs, aofs, maxsz); 1211 1212 type = 0; 1213 if (g->fniv) { 1214 type = choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_i64); 1215 } 1216 switch (type) { 1217 case TCG_TYPE_V256: 1218 /* Recall that ARM SVE allows vector sizes that are not a 1219 * power of 2, but always a multiple of 16. The intent is 1220 * that e.g. size == 80 would be expanded with 2x32 + 1x16. 1221 */ 1222 some = QEMU_ALIGN_DOWN(oprsz, 32); 1223 expand_2_vec(g->vece, dofs, aofs, some, 32, TCG_TYPE_V256, 1224 g->load_dest, g->fniv); 1225 if (some == oprsz) { 1226 break; 1227 } 1228 dofs += some; 1229 aofs += some; 1230 oprsz -= some; 1231 maxsz -= some; 1232 /* fallthru */ 1233 case TCG_TYPE_V128: 1234 expand_2_vec(g->vece, dofs, aofs, oprsz, 16, TCG_TYPE_V128, 1235 g->load_dest, g->fniv); 1236 break; 1237 case TCG_TYPE_V64: 1238 expand_2_vec(g->vece, dofs, aofs, oprsz, 8, TCG_TYPE_V64, 1239 g->load_dest, g->fniv); 1240 break; 1241 1242 case 0: 1243 if (g->fni8 && check_size_impl(oprsz, 8)) { 1244 expand_2_i64(dofs, aofs, oprsz, g->load_dest, g->fni8); 1245 } else if (g->fni4 && check_size_impl(oprsz, 4)) { 1246 expand_2_i32(dofs, aofs, oprsz, g->load_dest, g->fni4); 1247 } else { 1248 assert(g->fno != NULL); 1249 tcg_gen_gvec_2_ool(dofs, aofs, oprsz, maxsz, g->data, g->fno); 1250 oprsz = maxsz; 1251 } 1252 break; 1253 1254 default: 1255 g_assert_not_reached(); 1256 } 1257 tcg_swap_vecop_list(hold_list); 1258 1259 if (oprsz < maxsz) { 1260 expand_clr(dofs + oprsz, maxsz - oprsz); 1261 } 1262 } 1263 1264 /* Expand a vector operation with two vectors and an immediate. */ 1265 void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, uint32_t oprsz, 1266 uint32_t maxsz, int64_t c, const GVecGen2i *g) 1267 { 1268 const TCGOpcode *this_list = g->opt_opc ? : vecop_list_empty; 1269 const TCGOpcode *hold_list = tcg_swap_vecop_list(this_list); 1270 TCGType type; 1271 uint32_t some; 1272 1273 check_size_align(oprsz, maxsz, dofs | aofs); 1274 check_overlap_2(dofs, aofs, maxsz); 1275 1276 type = 0; 1277 if (g->fniv) { 1278 type = choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_i64); 1279 } 1280 switch (type) { 1281 case TCG_TYPE_V256: 1282 /* Recall that ARM SVE allows vector sizes that are not a 1283 * power of 2, but always a multiple of 16. The intent is 1284 * that e.g. size == 80 would be expanded with 2x32 + 1x16. 1285 */ 1286 some = QEMU_ALIGN_DOWN(oprsz, 32); 1287 expand_2i_vec(g->vece, dofs, aofs, some, 32, TCG_TYPE_V256, 1288 c, g->load_dest, g->fniv); 1289 if (some == oprsz) { 1290 break; 1291 } 1292 dofs += some; 1293 aofs += some; 1294 oprsz -= some; 1295 maxsz -= some; 1296 /* fallthru */ 1297 case TCG_TYPE_V128: 1298 expand_2i_vec(g->vece, dofs, aofs, oprsz, 16, TCG_TYPE_V128, 1299 c, g->load_dest, g->fniv); 1300 break; 1301 case TCG_TYPE_V64: 1302 expand_2i_vec(g->vece, dofs, aofs, oprsz, 8, TCG_TYPE_V64, 1303 c, g->load_dest, g->fniv); 1304 break; 1305 1306 case 0: 1307 if (g->fni8 && check_size_impl(oprsz, 8)) { 1308 expand_2i_i64(dofs, aofs, oprsz, c, g->load_dest, g->fni8); 1309 } else if (g->fni4 && check_size_impl(oprsz, 4)) { 1310 expand_2i_i32(dofs, aofs, oprsz, c, g->load_dest, g->fni4); 1311 } else { 1312 if (g->fno) { 1313 tcg_gen_gvec_2_ool(dofs, aofs, oprsz, maxsz, c, g->fno); 1314 } else { 1315 TCGv_i64 tcg_c = tcg_constant_i64(c); 1316 tcg_gen_gvec_2i_ool(dofs, aofs, tcg_c, oprsz, 1317 maxsz, c, g->fnoi); 1318 } 1319 oprsz = maxsz; 1320 } 1321 break; 1322 1323 default: 1324 g_assert_not_reached(); 1325 } 1326 tcg_swap_vecop_list(hold_list); 1327 1328 if (oprsz < maxsz) { 1329 expand_clr(dofs + oprsz, maxsz - oprsz); 1330 } 1331 } 1332 1333 /* Expand a vector operation with two vectors and a scalar. */ 1334 void tcg_gen_gvec_2s(uint32_t dofs, uint32_t aofs, uint32_t oprsz, 1335 uint32_t maxsz, TCGv_i64 c, const GVecGen2s *g) 1336 { 1337 TCGType type; 1338 1339 check_size_align(oprsz, maxsz, dofs | aofs); 1340 check_overlap_2(dofs, aofs, maxsz); 1341 1342 type = 0; 1343 if (g->fniv) { 1344 type = choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_i64); 1345 } 1346 if (type != 0) { 1347 const TCGOpcode *this_list = g->opt_opc ? : vecop_list_empty; 1348 const TCGOpcode *hold_list = tcg_swap_vecop_list(this_list); 1349 TCGv_vec t_vec = tcg_temp_new_vec(type); 1350 uint32_t some; 1351 1352 tcg_gen_dup_i64_vec(g->vece, t_vec, c); 1353 1354 switch (type) { 1355 case TCG_TYPE_V256: 1356 /* Recall that ARM SVE allows vector sizes that are not a 1357 * power of 2, but always a multiple of 16. The intent is 1358 * that e.g. size == 80 would be expanded with 2x32 + 1x16. 1359 */ 1360 some = QEMU_ALIGN_DOWN(oprsz, 32); 1361 expand_2s_vec(g->vece, dofs, aofs, some, 32, TCG_TYPE_V256, 1362 t_vec, g->scalar_first, g->fniv); 1363 if (some == oprsz) { 1364 break; 1365 } 1366 dofs += some; 1367 aofs += some; 1368 oprsz -= some; 1369 maxsz -= some; 1370 /* fallthru */ 1371 1372 case TCG_TYPE_V128: 1373 expand_2s_vec(g->vece, dofs, aofs, oprsz, 16, TCG_TYPE_V128, 1374 t_vec, g->scalar_first, g->fniv); 1375 break; 1376 1377 case TCG_TYPE_V64: 1378 expand_2s_vec(g->vece, dofs, aofs, oprsz, 8, TCG_TYPE_V64, 1379 t_vec, g->scalar_first, g->fniv); 1380 break; 1381 1382 default: 1383 g_assert_not_reached(); 1384 } 1385 tcg_temp_free_vec(t_vec); 1386 tcg_swap_vecop_list(hold_list); 1387 } else if (g->fni8 && check_size_impl(oprsz, 8)) { 1388 TCGv_i64 t64 = tcg_temp_new_i64(); 1389 1390 tcg_gen_dup_i64(g->vece, t64, c); 1391 expand_2s_i64(dofs, aofs, oprsz, t64, g->scalar_first, g->fni8); 1392 tcg_temp_free_i64(t64); 1393 } else if (g->fni4 && check_size_impl(oprsz, 4)) { 1394 TCGv_i32 t32 = tcg_temp_new_i32(); 1395 1396 tcg_gen_extrl_i64_i32(t32, c); 1397 tcg_gen_dup_i32(g->vece, t32, t32); 1398 expand_2s_i32(dofs, aofs, oprsz, t32, g->scalar_first, g->fni4); 1399 tcg_temp_free_i32(t32); 1400 } else { 1401 tcg_gen_gvec_2i_ool(dofs, aofs, c, oprsz, maxsz, 0, g->fno); 1402 return; 1403 } 1404 1405 if (oprsz < maxsz) { 1406 expand_clr(dofs + oprsz, maxsz - oprsz); 1407 } 1408 } 1409 1410 /* Expand a vector three-operand operation. */ 1411 void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs, 1412 uint32_t oprsz, uint32_t maxsz, const GVecGen3 *g) 1413 { 1414 const TCGOpcode *this_list = g->opt_opc ? : vecop_list_empty; 1415 const TCGOpcode *hold_list = tcg_swap_vecop_list(this_list); 1416 TCGType type; 1417 uint32_t some; 1418 1419 check_size_align(oprsz, maxsz, dofs | aofs | bofs); 1420 check_overlap_3(dofs, aofs, bofs, maxsz); 1421 1422 type = 0; 1423 if (g->fniv) { 1424 type = choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_i64); 1425 } 1426 switch (type) { 1427 case TCG_TYPE_V256: 1428 /* Recall that ARM SVE allows vector sizes that are not a 1429 * power of 2, but always a multiple of 16. The intent is 1430 * that e.g. size == 80 would be expanded with 2x32 + 1x16. 1431 */ 1432 some = QEMU_ALIGN_DOWN(oprsz, 32); 1433 expand_3_vec(g->vece, dofs, aofs, bofs, some, 32, TCG_TYPE_V256, 1434 g->load_dest, g->fniv); 1435 if (some == oprsz) { 1436 break; 1437 } 1438 dofs += some; 1439 aofs += some; 1440 bofs += some; 1441 oprsz -= some; 1442 maxsz -= some; 1443 /* fallthru */ 1444 case TCG_TYPE_V128: 1445 expand_3_vec(g->vece, dofs, aofs, bofs, oprsz, 16, TCG_TYPE_V128, 1446 g->load_dest, g->fniv); 1447 break; 1448 case TCG_TYPE_V64: 1449 expand_3_vec(g->vece, dofs, aofs, bofs, oprsz, 8, TCG_TYPE_V64, 1450 g->load_dest, g->fniv); 1451 break; 1452 1453 case 0: 1454 if (g->fni8 && check_size_impl(oprsz, 8)) { 1455 expand_3_i64(dofs, aofs, bofs, oprsz, g->load_dest, g->fni8); 1456 } else if (g->fni4 && check_size_impl(oprsz, 4)) { 1457 expand_3_i32(dofs, aofs, bofs, oprsz, g->load_dest, g->fni4); 1458 } else { 1459 assert(g->fno != NULL); 1460 tcg_gen_gvec_3_ool(dofs, aofs, bofs, oprsz, 1461 maxsz, g->data, g->fno); 1462 oprsz = maxsz; 1463 } 1464 break; 1465 1466 default: 1467 g_assert_not_reached(); 1468 } 1469 tcg_swap_vecop_list(hold_list); 1470 1471 if (oprsz < maxsz) { 1472 expand_clr(dofs + oprsz, maxsz - oprsz); 1473 } 1474 } 1475 1476 /* Expand a vector operation with three vectors and an immediate. */ 1477 void tcg_gen_gvec_3i(uint32_t dofs, uint32_t aofs, uint32_t bofs, 1478 uint32_t oprsz, uint32_t maxsz, int64_t c, 1479 const GVecGen3i *g) 1480 { 1481 const TCGOpcode *this_list = g->opt_opc ? : vecop_list_empty; 1482 const TCGOpcode *hold_list = tcg_swap_vecop_list(this_list); 1483 TCGType type; 1484 uint32_t some; 1485 1486 check_size_align(oprsz, maxsz, dofs | aofs | bofs); 1487 check_overlap_3(dofs, aofs, bofs, maxsz); 1488 1489 type = 0; 1490 if (g->fniv) { 1491 type = choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_i64); 1492 } 1493 switch (type) { 1494 case TCG_TYPE_V256: 1495 /* 1496 * Recall that ARM SVE allows vector sizes that are not a 1497 * power of 2, but always a multiple of 16. The intent is 1498 * that e.g. size == 80 would be expanded with 2x32 + 1x16. 1499 */ 1500 some = QEMU_ALIGN_DOWN(oprsz, 32); 1501 expand_3i_vec(g->vece, dofs, aofs, bofs, some, 32, TCG_TYPE_V256, 1502 c, g->load_dest, g->fniv); 1503 if (some == oprsz) { 1504 break; 1505 } 1506 dofs += some; 1507 aofs += some; 1508 bofs += some; 1509 oprsz -= some; 1510 maxsz -= some; 1511 /* fallthru */ 1512 case TCG_TYPE_V128: 1513 expand_3i_vec(g->vece, dofs, aofs, bofs, oprsz, 16, TCG_TYPE_V128, 1514 c, g->load_dest, g->fniv); 1515 break; 1516 case TCG_TYPE_V64: 1517 expand_3i_vec(g->vece, dofs, aofs, bofs, oprsz, 8, TCG_TYPE_V64, 1518 c, g->load_dest, g->fniv); 1519 break; 1520 1521 case 0: 1522 if (g->fni8 && check_size_impl(oprsz, 8)) { 1523 expand_3i_i64(dofs, aofs, bofs, oprsz, c, g->load_dest, g->fni8); 1524 } else if (g->fni4 && check_size_impl(oprsz, 4)) { 1525 expand_3i_i32(dofs, aofs, bofs, oprsz, c, g->load_dest, g->fni4); 1526 } else { 1527 assert(g->fno != NULL); 1528 tcg_gen_gvec_3_ool(dofs, aofs, bofs, oprsz, maxsz, c, g->fno); 1529 oprsz = maxsz; 1530 } 1531 break; 1532 1533 default: 1534 g_assert_not_reached(); 1535 } 1536 tcg_swap_vecop_list(hold_list); 1537 1538 if (oprsz < maxsz) { 1539 expand_clr(dofs + oprsz, maxsz - oprsz); 1540 } 1541 } 1542 1543 /* Expand a vector four-operand operation. */ 1544 void tcg_gen_gvec_4(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs, 1545 uint32_t oprsz, uint32_t maxsz, const GVecGen4 *g) 1546 { 1547 const TCGOpcode *this_list = g->opt_opc ? : vecop_list_empty; 1548 const TCGOpcode *hold_list = tcg_swap_vecop_list(this_list); 1549 TCGType type; 1550 uint32_t some; 1551 1552 check_size_align(oprsz, maxsz, dofs | aofs | bofs | cofs); 1553 check_overlap_4(dofs, aofs, bofs, cofs, maxsz); 1554 1555 type = 0; 1556 if (g->fniv) { 1557 type = choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_i64); 1558 } 1559 switch (type) { 1560 case TCG_TYPE_V256: 1561 /* Recall that ARM SVE allows vector sizes that are not a 1562 * power of 2, but always a multiple of 16. The intent is 1563 * that e.g. size == 80 would be expanded with 2x32 + 1x16. 1564 */ 1565 some = QEMU_ALIGN_DOWN(oprsz, 32); 1566 expand_4_vec(g->vece, dofs, aofs, bofs, cofs, some, 1567 32, TCG_TYPE_V256, g->write_aofs, g->fniv); 1568 if (some == oprsz) { 1569 break; 1570 } 1571 dofs += some; 1572 aofs += some; 1573 bofs += some; 1574 cofs += some; 1575 oprsz -= some; 1576 maxsz -= some; 1577 /* fallthru */ 1578 case TCG_TYPE_V128: 1579 expand_4_vec(g->vece, dofs, aofs, bofs, cofs, oprsz, 1580 16, TCG_TYPE_V128, g->write_aofs, g->fniv); 1581 break; 1582 case TCG_TYPE_V64: 1583 expand_4_vec(g->vece, dofs, aofs, bofs, cofs, oprsz, 1584 8, TCG_TYPE_V64, g->write_aofs, g->fniv); 1585 break; 1586 1587 case 0: 1588 if (g->fni8 && check_size_impl(oprsz, 8)) { 1589 expand_4_i64(dofs, aofs, bofs, cofs, oprsz, 1590 g->write_aofs, g->fni8); 1591 } else if (g->fni4 && check_size_impl(oprsz, 4)) { 1592 expand_4_i32(dofs, aofs, bofs, cofs, oprsz, 1593 g->write_aofs, g->fni4); 1594 } else { 1595 assert(g->fno != NULL); 1596 tcg_gen_gvec_4_ool(dofs, aofs, bofs, cofs, 1597 oprsz, maxsz, g->data, g->fno); 1598 oprsz = maxsz; 1599 } 1600 break; 1601 1602 default: 1603 g_assert_not_reached(); 1604 } 1605 tcg_swap_vecop_list(hold_list); 1606 1607 if (oprsz < maxsz) { 1608 expand_clr(dofs + oprsz, maxsz - oprsz); 1609 } 1610 } 1611 1612 /* Expand a vector four-operand operation. */ 1613 void tcg_gen_gvec_4i(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs, 1614 uint32_t oprsz, uint32_t maxsz, int64_t c, 1615 const GVecGen4i *g) 1616 { 1617 const TCGOpcode *this_list = g->opt_opc ? : vecop_list_empty; 1618 const TCGOpcode *hold_list = tcg_swap_vecop_list(this_list); 1619 TCGType type; 1620 uint32_t some; 1621 1622 check_size_align(oprsz, maxsz, dofs | aofs | bofs | cofs); 1623 check_overlap_4(dofs, aofs, bofs, cofs, maxsz); 1624 1625 type = 0; 1626 if (g->fniv) { 1627 type = choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_i64); 1628 } 1629 switch (type) { 1630 case TCG_TYPE_V256: 1631 /* 1632 * Recall that ARM SVE allows vector sizes that are not a 1633 * power of 2, but always a multiple of 16. The intent is 1634 * that e.g. size == 80 would be expanded with 2x32 + 1x16. 1635 */ 1636 some = QEMU_ALIGN_DOWN(oprsz, 32); 1637 expand_4i_vec(g->vece, dofs, aofs, bofs, cofs, some, 1638 32, TCG_TYPE_V256, c, g->fniv); 1639 if (some == oprsz) { 1640 break; 1641 } 1642 dofs += some; 1643 aofs += some; 1644 bofs += some; 1645 cofs += some; 1646 oprsz -= some; 1647 maxsz -= some; 1648 /* fallthru */ 1649 case TCG_TYPE_V128: 1650 expand_4i_vec(g->vece, dofs, aofs, bofs, cofs, oprsz, 1651 16, TCG_TYPE_V128, c, g->fniv); 1652 break; 1653 case TCG_TYPE_V64: 1654 expand_4i_vec(g->vece, dofs, aofs, bofs, cofs, oprsz, 1655 8, TCG_TYPE_V64, c, g->fniv); 1656 break; 1657 1658 case 0: 1659 if (g->fni8 && check_size_impl(oprsz, 8)) { 1660 expand_4i_i64(dofs, aofs, bofs, cofs, oprsz, c, g->fni8); 1661 } else if (g->fni4 && check_size_impl(oprsz, 4)) { 1662 expand_4i_i32(dofs, aofs, bofs, cofs, oprsz, c, g->fni4); 1663 } else { 1664 assert(g->fno != NULL); 1665 tcg_gen_gvec_4_ool(dofs, aofs, bofs, cofs, 1666 oprsz, maxsz, c, g->fno); 1667 oprsz = maxsz; 1668 } 1669 break; 1670 1671 default: 1672 g_assert_not_reached(); 1673 } 1674 tcg_swap_vecop_list(hold_list); 1675 1676 if (oprsz < maxsz) { 1677 expand_clr(dofs + oprsz, maxsz - oprsz); 1678 } 1679 } 1680 1681 /* 1682 * Expand specific vector operations. 1683 */ 1684 1685 static void vec_mov2(unsigned vece, TCGv_vec a, TCGv_vec b) 1686 { 1687 tcg_gen_mov_vec(a, b); 1688 } 1689 1690 void tcg_gen_gvec_mov(unsigned vece, uint32_t dofs, uint32_t aofs, 1691 uint32_t oprsz, uint32_t maxsz) 1692 { 1693 static const GVecGen2 g = { 1694 .fni8 = tcg_gen_mov_i64, 1695 .fniv = vec_mov2, 1696 .fno = gen_helper_gvec_mov, 1697 .prefer_i64 = TCG_TARGET_REG_BITS == 64, 1698 }; 1699 if (dofs != aofs) { 1700 tcg_gen_gvec_2(dofs, aofs, oprsz, maxsz, &g); 1701 } else { 1702 check_size_align(oprsz, maxsz, dofs); 1703 if (oprsz < maxsz) { 1704 expand_clr(dofs + oprsz, maxsz - oprsz); 1705 } 1706 } 1707 } 1708 1709 void tcg_gen_gvec_dup_i32(unsigned vece, uint32_t dofs, uint32_t oprsz, 1710 uint32_t maxsz, TCGv_i32 in) 1711 { 1712 check_size_align(oprsz, maxsz, dofs); 1713 tcg_debug_assert(vece <= MO_32); 1714 do_dup(vece, dofs, oprsz, maxsz, in, NULL, 0); 1715 } 1716 1717 void tcg_gen_gvec_dup_i64(unsigned vece, uint32_t dofs, uint32_t oprsz, 1718 uint32_t maxsz, TCGv_i64 in) 1719 { 1720 check_size_align(oprsz, maxsz, dofs); 1721 tcg_debug_assert(vece <= MO_64); 1722 do_dup(vece, dofs, oprsz, maxsz, NULL, in, 0); 1723 } 1724 1725 void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs, uint32_t aofs, 1726 uint32_t oprsz, uint32_t maxsz) 1727 { 1728 check_size_align(oprsz, maxsz, dofs); 1729 if (vece <= MO_64) { 1730 TCGType type = choose_vector_type(NULL, vece, oprsz, 0); 1731 if (type != 0) { 1732 TCGv_vec t_vec = tcg_temp_new_vec(type); 1733 tcg_gen_dup_mem_vec(vece, t_vec, cpu_env, aofs); 1734 do_dup_store(type, dofs, oprsz, maxsz, t_vec); 1735 tcg_temp_free_vec(t_vec); 1736 } else if (vece <= MO_32) { 1737 TCGv_i32 in = tcg_temp_ebb_new_i32(); 1738 switch (vece) { 1739 case MO_8: 1740 tcg_gen_ld8u_i32(in, cpu_env, aofs); 1741 break; 1742 case MO_16: 1743 tcg_gen_ld16u_i32(in, cpu_env, aofs); 1744 break; 1745 default: 1746 tcg_gen_ld_i32(in, cpu_env, aofs); 1747 break; 1748 } 1749 do_dup(vece, dofs, oprsz, maxsz, in, NULL, 0); 1750 tcg_temp_free_i32(in); 1751 } else { 1752 TCGv_i64 in = tcg_temp_ebb_new_i64(); 1753 tcg_gen_ld_i64(in, cpu_env, aofs); 1754 do_dup(vece, dofs, oprsz, maxsz, NULL, in, 0); 1755 tcg_temp_free_i64(in); 1756 } 1757 } else if (vece == 4) { 1758 /* 128-bit duplicate. */ 1759 int i; 1760 1761 tcg_debug_assert(oprsz >= 16); 1762 if (TCG_TARGET_HAS_v128) { 1763 TCGv_vec in = tcg_temp_new_vec(TCG_TYPE_V128); 1764 1765 tcg_gen_ld_vec(in, cpu_env, aofs); 1766 for (i = (aofs == dofs) * 16; i < oprsz; i += 16) { 1767 tcg_gen_st_vec(in, cpu_env, dofs + i); 1768 } 1769 tcg_temp_free_vec(in); 1770 } else { 1771 TCGv_i64 in0 = tcg_temp_ebb_new_i64(); 1772 TCGv_i64 in1 = tcg_temp_ebb_new_i64(); 1773 1774 tcg_gen_ld_i64(in0, cpu_env, aofs); 1775 tcg_gen_ld_i64(in1, cpu_env, aofs + 8); 1776 for (i = (aofs == dofs) * 16; i < oprsz; i += 16) { 1777 tcg_gen_st_i64(in0, cpu_env, dofs + i); 1778 tcg_gen_st_i64(in1, cpu_env, dofs + i + 8); 1779 } 1780 tcg_temp_free_i64(in0); 1781 tcg_temp_free_i64(in1); 1782 } 1783 if (oprsz < maxsz) { 1784 expand_clr(dofs + oprsz, maxsz - oprsz); 1785 } 1786 } else if (vece == 5) { 1787 /* 256-bit duplicate. */ 1788 int i; 1789 1790 tcg_debug_assert(oprsz >= 32); 1791 tcg_debug_assert(oprsz % 32 == 0); 1792 if (TCG_TARGET_HAS_v256) { 1793 TCGv_vec in = tcg_temp_new_vec(TCG_TYPE_V256); 1794 1795 tcg_gen_ld_vec(in, cpu_env, aofs); 1796 for (i = (aofs == dofs) * 32; i < oprsz; i += 32) { 1797 tcg_gen_st_vec(in, cpu_env, dofs + i); 1798 } 1799 tcg_temp_free_vec(in); 1800 } else if (TCG_TARGET_HAS_v128) { 1801 TCGv_vec in0 = tcg_temp_new_vec(TCG_TYPE_V128); 1802 TCGv_vec in1 = tcg_temp_new_vec(TCG_TYPE_V128); 1803 1804 tcg_gen_ld_vec(in0, cpu_env, aofs); 1805 tcg_gen_ld_vec(in1, cpu_env, aofs + 16); 1806 for (i = (aofs == dofs) * 32; i < oprsz; i += 32) { 1807 tcg_gen_st_vec(in0, cpu_env, dofs + i); 1808 tcg_gen_st_vec(in1, cpu_env, dofs + i + 16); 1809 } 1810 tcg_temp_free_vec(in0); 1811 tcg_temp_free_vec(in1); 1812 } else { 1813 TCGv_i64 in[4]; 1814 int j; 1815 1816 for (j = 0; j < 4; ++j) { 1817 in[j] = tcg_temp_ebb_new_i64(); 1818 tcg_gen_ld_i64(in[j], cpu_env, aofs + j * 8); 1819 } 1820 for (i = (aofs == dofs) * 32; i < oprsz; i += 32) { 1821 for (j = 0; j < 4; ++j) { 1822 tcg_gen_st_i64(in[j], cpu_env, dofs + i + j * 8); 1823 } 1824 } 1825 for (j = 0; j < 4; ++j) { 1826 tcg_temp_free_i64(in[j]); 1827 } 1828 } 1829 if (oprsz < maxsz) { 1830 expand_clr(dofs + oprsz, maxsz - oprsz); 1831 } 1832 } else { 1833 g_assert_not_reached(); 1834 } 1835 } 1836 1837 void tcg_gen_gvec_dup_imm(unsigned vece, uint32_t dofs, uint32_t oprsz, 1838 uint32_t maxsz, uint64_t x) 1839 { 1840 check_size_align(oprsz, maxsz, dofs); 1841 do_dup(vece, dofs, oprsz, maxsz, NULL, NULL, x); 1842 } 1843 1844 void tcg_gen_gvec_not(unsigned vece, uint32_t dofs, uint32_t aofs, 1845 uint32_t oprsz, uint32_t maxsz) 1846 { 1847 static const GVecGen2 g = { 1848 .fni8 = tcg_gen_not_i64, 1849 .fniv = tcg_gen_not_vec, 1850 .fno = gen_helper_gvec_not, 1851 .prefer_i64 = TCG_TARGET_REG_BITS == 64, 1852 }; 1853 tcg_gen_gvec_2(dofs, aofs, oprsz, maxsz, &g); 1854 } 1855 1856 /* Perform a vector addition using normal addition and a mask. The mask 1857 should be the sign bit of each lane. This 6-operation form is more 1858 efficient than separate additions when there are 4 or more lanes in 1859 the 64-bit operation. */ 1860 static void gen_addv_mask(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, TCGv_i64 m) 1861 { 1862 TCGv_i64 t1 = tcg_temp_ebb_new_i64(); 1863 TCGv_i64 t2 = tcg_temp_ebb_new_i64(); 1864 TCGv_i64 t3 = tcg_temp_ebb_new_i64(); 1865 1866 tcg_gen_andc_i64(t1, a, m); 1867 tcg_gen_andc_i64(t2, b, m); 1868 tcg_gen_xor_i64(t3, a, b); 1869 tcg_gen_add_i64(d, t1, t2); 1870 tcg_gen_and_i64(t3, t3, m); 1871 tcg_gen_xor_i64(d, d, t3); 1872 1873 tcg_temp_free_i64(t1); 1874 tcg_temp_free_i64(t2); 1875 tcg_temp_free_i64(t3); 1876 } 1877 1878 void tcg_gen_vec_add8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) 1879 { 1880 TCGv_i64 m = tcg_constant_i64(dup_const(MO_8, 0x80)); 1881 gen_addv_mask(d, a, b, m); 1882 } 1883 1884 void tcg_gen_vec_add8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) 1885 { 1886 TCGv_i32 m = tcg_constant_i32((int32_t)dup_const(MO_8, 0x80)); 1887 TCGv_i32 t1 = tcg_temp_ebb_new_i32(); 1888 TCGv_i32 t2 = tcg_temp_ebb_new_i32(); 1889 TCGv_i32 t3 = tcg_temp_ebb_new_i32(); 1890 1891 tcg_gen_andc_i32(t1, a, m); 1892 tcg_gen_andc_i32(t2, b, m); 1893 tcg_gen_xor_i32(t3, a, b); 1894 tcg_gen_add_i32(d, t1, t2); 1895 tcg_gen_and_i32(t3, t3, m); 1896 tcg_gen_xor_i32(d, d, t3); 1897 1898 tcg_temp_free_i32(t1); 1899 tcg_temp_free_i32(t2); 1900 tcg_temp_free_i32(t3); 1901 } 1902 1903 void tcg_gen_vec_add16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) 1904 { 1905 TCGv_i64 m = tcg_constant_i64(dup_const(MO_16, 0x8000)); 1906 gen_addv_mask(d, a, b, m); 1907 } 1908 1909 void tcg_gen_vec_add16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) 1910 { 1911 TCGv_i32 t1 = tcg_temp_ebb_new_i32(); 1912 TCGv_i32 t2 = tcg_temp_ebb_new_i32(); 1913 1914 tcg_gen_andi_i32(t1, a, ~0xffff); 1915 tcg_gen_add_i32(t2, a, b); 1916 tcg_gen_add_i32(t1, t1, b); 1917 tcg_gen_deposit_i32(d, t1, t2, 0, 16); 1918 1919 tcg_temp_free_i32(t1); 1920 tcg_temp_free_i32(t2); 1921 } 1922 1923 void tcg_gen_vec_add32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) 1924 { 1925 TCGv_i64 t1 = tcg_temp_ebb_new_i64(); 1926 TCGv_i64 t2 = tcg_temp_ebb_new_i64(); 1927 1928 tcg_gen_andi_i64(t1, a, ~0xffffffffull); 1929 tcg_gen_add_i64(t2, a, b); 1930 tcg_gen_add_i64(t1, t1, b); 1931 tcg_gen_deposit_i64(d, t1, t2, 0, 32); 1932 1933 tcg_temp_free_i64(t1); 1934 tcg_temp_free_i64(t2); 1935 } 1936 1937 static const TCGOpcode vecop_list_add[] = { INDEX_op_add_vec, 0 }; 1938 1939 void tcg_gen_gvec_add(unsigned vece, uint32_t dofs, uint32_t aofs, 1940 uint32_t bofs, uint32_t oprsz, uint32_t maxsz) 1941 { 1942 static const GVecGen3 g[4] = { 1943 { .fni8 = tcg_gen_vec_add8_i64, 1944 .fniv = tcg_gen_add_vec, 1945 .fno = gen_helper_gvec_add8, 1946 .opt_opc = vecop_list_add, 1947 .vece = MO_8 }, 1948 { .fni8 = tcg_gen_vec_add16_i64, 1949 .fniv = tcg_gen_add_vec, 1950 .fno = gen_helper_gvec_add16, 1951 .opt_opc = vecop_list_add, 1952 .vece = MO_16 }, 1953 { .fni4 = tcg_gen_add_i32, 1954 .fniv = tcg_gen_add_vec, 1955 .fno = gen_helper_gvec_add32, 1956 .opt_opc = vecop_list_add, 1957 .vece = MO_32 }, 1958 { .fni8 = tcg_gen_add_i64, 1959 .fniv = tcg_gen_add_vec, 1960 .fno = gen_helper_gvec_add64, 1961 .opt_opc = vecop_list_add, 1962 .prefer_i64 = TCG_TARGET_REG_BITS == 64, 1963 .vece = MO_64 }, 1964 }; 1965 1966 tcg_debug_assert(vece <= MO_64); 1967 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); 1968 } 1969 1970 void tcg_gen_gvec_adds(unsigned vece, uint32_t dofs, uint32_t aofs, 1971 TCGv_i64 c, uint32_t oprsz, uint32_t maxsz) 1972 { 1973 static const GVecGen2s g[4] = { 1974 { .fni8 = tcg_gen_vec_add8_i64, 1975 .fniv = tcg_gen_add_vec, 1976 .fno = gen_helper_gvec_adds8, 1977 .opt_opc = vecop_list_add, 1978 .vece = MO_8 }, 1979 { .fni8 = tcg_gen_vec_add16_i64, 1980 .fniv = tcg_gen_add_vec, 1981 .fno = gen_helper_gvec_adds16, 1982 .opt_opc = vecop_list_add, 1983 .vece = MO_16 }, 1984 { .fni4 = tcg_gen_add_i32, 1985 .fniv = tcg_gen_add_vec, 1986 .fno = gen_helper_gvec_adds32, 1987 .opt_opc = vecop_list_add, 1988 .vece = MO_32 }, 1989 { .fni8 = tcg_gen_add_i64, 1990 .fniv = tcg_gen_add_vec, 1991 .fno = gen_helper_gvec_adds64, 1992 .opt_opc = vecop_list_add, 1993 .prefer_i64 = TCG_TARGET_REG_BITS == 64, 1994 .vece = MO_64 }, 1995 }; 1996 1997 tcg_debug_assert(vece <= MO_64); 1998 tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, c, &g[vece]); 1999 } 2000 2001 void tcg_gen_gvec_addi(unsigned vece, uint32_t dofs, uint32_t aofs, 2002 int64_t c, uint32_t oprsz, uint32_t maxsz) 2003 { 2004 TCGv_i64 tmp = tcg_constant_i64(c); 2005 tcg_gen_gvec_adds(vece, dofs, aofs, tmp, oprsz, maxsz); 2006 } 2007 2008 static const TCGOpcode vecop_list_sub[] = { INDEX_op_sub_vec, 0 }; 2009 2010 void tcg_gen_gvec_subs(unsigned vece, uint32_t dofs, uint32_t aofs, 2011 TCGv_i64 c, uint32_t oprsz, uint32_t maxsz) 2012 { 2013 static const GVecGen2s g[4] = { 2014 { .fni8 = tcg_gen_vec_sub8_i64, 2015 .fniv = tcg_gen_sub_vec, 2016 .fno = gen_helper_gvec_subs8, 2017 .opt_opc = vecop_list_sub, 2018 .vece = MO_8 }, 2019 { .fni8 = tcg_gen_vec_sub16_i64, 2020 .fniv = tcg_gen_sub_vec, 2021 .fno = gen_helper_gvec_subs16, 2022 .opt_opc = vecop_list_sub, 2023 .vece = MO_16 }, 2024 { .fni4 = tcg_gen_sub_i32, 2025 .fniv = tcg_gen_sub_vec, 2026 .fno = gen_helper_gvec_subs32, 2027 .opt_opc = vecop_list_sub, 2028 .vece = MO_32 }, 2029 { .fni8 = tcg_gen_sub_i64, 2030 .fniv = tcg_gen_sub_vec, 2031 .fno = gen_helper_gvec_subs64, 2032 .opt_opc = vecop_list_sub, 2033 .prefer_i64 = TCG_TARGET_REG_BITS == 64, 2034 .vece = MO_64 }, 2035 }; 2036 2037 tcg_debug_assert(vece <= MO_64); 2038 tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, c, &g[vece]); 2039 } 2040 2041 /* Perform a vector subtraction using normal subtraction and a mask. 2042 Compare gen_addv_mask above. */ 2043 static void gen_subv_mask(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, TCGv_i64 m) 2044 { 2045 TCGv_i64 t1 = tcg_temp_ebb_new_i64(); 2046 TCGv_i64 t2 = tcg_temp_ebb_new_i64(); 2047 TCGv_i64 t3 = tcg_temp_ebb_new_i64(); 2048 2049 tcg_gen_or_i64(t1, a, m); 2050 tcg_gen_andc_i64(t2, b, m); 2051 tcg_gen_eqv_i64(t3, a, b); 2052 tcg_gen_sub_i64(d, t1, t2); 2053 tcg_gen_and_i64(t3, t3, m); 2054 tcg_gen_xor_i64(d, d, t3); 2055 2056 tcg_temp_free_i64(t1); 2057 tcg_temp_free_i64(t2); 2058 tcg_temp_free_i64(t3); 2059 } 2060 2061 void tcg_gen_vec_sub8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) 2062 { 2063 TCGv_i64 m = tcg_constant_i64(dup_const(MO_8, 0x80)); 2064 gen_subv_mask(d, a, b, m); 2065 } 2066 2067 void tcg_gen_vec_sub8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) 2068 { 2069 TCGv_i32 m = tcg_constant_i32((int32_t)dup_const(MO_8, 0x80)); 2070 TCGv_i32 t1 = tcg_temp_ebb_new_i32(); 2071 TCGv_i32 t2 = tcg_temp_ebb_new_i32(); 2072 TCGv_i32 t3 = tcg_temp_ebb_new_i32(); 2073 2074 tcg_gen_or_i32(t1, a, m); 2075 tcg_gen_andc_i32(t2, b, m); 2076 tcg_gen_eqv_i32(t3, a, b); 2077 tcg_gen_sub_i32(d, t1, t2); 2078 tcg_gen_and_i32(t3, t3, m); 2079 tcg_gen_xor_i32(d, d, t3); 2080 2081 tcg_temp_free_i32(t1); 2082 tcg_temp_free_i32(t2); 2083 tcg_temp_free_i32(t3); 2084 } 2085 2086 void tcg_gen_vec_sub16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) 2087 { 2088 TCGv_i64 m = tcg_constant_i64(dup_const(MO_16, 0x8000)); 2089 gen_subv_mask(d, a, b, m); 2090 } 2091 2092 void tcg_gen_vec_sub16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) 2093 { 2094 TCGv_i32 t1 = tcg_temp_ebb_new_i32(); 2095 TCGv_i32 t2 = tcg_temp_ebb_new_i32(); 2096 2097 tcg_gen_andi_i32(t1, b, ~0xffff); 2098 tcg_gen_sub_i32(t2, a, b); 2099 tcg_gen_sub_i32(t1, a, t1); 2100 tcg_gen_deposit_i32(d, t1, t2, 0, 16); 2101 2102 tcg_temp_free_i32(t1); 2103 tcg_temp_free_i32(t2); 2104 } 2105 2106 void tcg_gen_vec_sub32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) 2107 { 2108 TCGv_i64 t1 = tcg_temp_ebb_new_i64(); 2109 TCGv_i64 t2 = tcg_temp_ebb_new_i64(); 2110 2111 tcg_gen_andi_i64(t1, b, ~0xffffffffull); 2112 tcg_gen_sub_i64(t2, a, b); 2113 tcg_gen_sub_i64(t1, a, t1); 2114 tcg_gen_deposit_i64(d, t1, t2, 0, 32); 2115 2116 tcg_temp_free_i64(t1); 2117 tcg_temp_free_i64(t2); 2118 } 2119 2120 void tcg_gen_gvec_sub(unsigned vece, uint32_t dofs, uint32_t aofs, 2121 uint32_t bofs, uint32_t oprsz, uint32_t maxsz) 2122 { 2123 static const GVecGen3 g[4] = { 2124 { .fni8 = tcg_gen_vec_sub8_i64, 2125 .fniv = tcg_gen_sub_vec, 2126 .fno = gen_helper_gvec_sub8, 2127 .opt_opc = vecop_list_sub, 2128 .vece = MO_8 }, 2129 { .fni8 = tcg_gen_vec_sub16_i64, 2130 .fniv = tcg_gen_sub_vec, 2131 .fno = gen_helper_gvec_sub16, 2132 .opt_opc = vecop_list_sub, 2133 .vece = MO_16 }, 2134 { .fni4 = tcg_gen_sub_i32, 2135 .fniv = tcg_gen_sub_vec, 2136 .fno = gen_helper_gvec_sub32, 2137 .opt_opc = vecop_list_sub, 2138 .vece = MO_32 }, 2139 { .fni8 = tcg_gen_sub_i64, 2140 .fniv = tcg_gen_sub_vec, 2141 .fno = gen_helper_gvec_sub64, 2142 .opt_opc = vecop_list_sub, 2143 .prefer_i64 = TCG_TARGET_REG_BITS == 64, 2144 .vece = MO_64 }, 2145 }; 2146 2147 tcg_debug_assert(vece <= MO_64); 2148 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); 2149 } 2150 2151 static const TCGOpcode vecop_list_mul[] = { INDEX_op_mul_vec, 0 }; 2152 2153 void tcg_gen_gvec_mul(unsigned vece, uint32_t dofs, uint32_t aofs, 2154 uint32_t bofs, uint32_t oprsz, uint32_t maxsz) 2155 { 2156 static const GVecGen3 g[4] = { 2157 { .fniv = tcg_gen_mul_vec, 2158 .fno = gen_helper_gvec_mul8, 2159 .opt_opc = vecop_list_mul, 2160 .vece = MO_8 }, 2161 { .fniv = tcg_gen_mul_vec, 2162 .fno = gen_helper_gvec_mul16, 2163 .opt_opc = vecop_list_mul, 2164 .vece = MO_16 }, 2165 { .fni4 = tcg_gen_mul_i32, 2166 .fniv = tcg_gen_mul_vec, 2167 .fno = gen_helper_gvec_mul32, 2168 .opt_opc = vecop_list_mul, 2169 .vece = MO_32 }, 2170 { .fni8 = tcg_gen_mul_i64, 2171 .fniv = tcg_gen_mul_vec, 2172 .fno = gen_helper_gvec_mul64, 2173 .opt_opc = vecop_list_mul, 2174 .prefer_i64 = TCG_TARGET_REG_BITS == 64, 2175 .vece = MO_64 }, 2176 }; 2177 2178 tcg_debug_assert(vece <= MO_64); 2179 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); 2180 } 2181 2182 void tcg_gen_gvec_muls(unsigned vece, uint32_t dofs, uint32_t aofs, 2183 TCGv_i64 c, uint32_t oprsz, uint32_t maxsz) 2184 { 2185 static const GVecGen2s g[4] = { 2186 { .fniv = tcg_gen_mul_vec, 2187 .fno = gen_helper_gvec_muls8, 2188 .opt_opc = vecop_list_mul, 2189 .vece = MO_8 }, 2190 { .fniv = tcg_gen_mul_vec, 2191 .fno = gen_helper_gvec_muls16, 2192 .opt_opc = vecop_list_mul, 2193 .vece = MO_16 }, 2194 { .fni4 = tcg_gen_mul_i32, 2195 .fniv = tcg_gen_mul_vec, 2196 .fno = gen_helper_gvec_muls32, 2197 .opt_opc = vecop_list_mul, 2198 .vece = MO_32 }, 2199 { .fni8 = tcg_gen_mul_i64, 2200 .fniv = tcg_gen_mul_vec, 2201 .fno = gen_helper_gvec_muls64, 2202 .opt_opc = vecop_list_mul, 2203 .prefer_i64 = TCG_TARGET_REG_BITS == 64, 2204 .vece = MO_64 }, 2205 }; 2206 2207 tcg_debug_assert(vece <= MO_64); 2208 tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, c, &g[vece]); 2209 } 2210 2211 void tcg_gen_gvec_muli(unsigned vece, uint32_t dofs, uint32_t aofs, 2212 int64_t c, uint32_t oprsz, uint32_t maxsz) 2213 { 2214 TCGv_i64 tmp = tcg_constant_i64(c); 2215 tcg_gen_gvec_muls(vece, dofs, aofs, tmp, oprsz, maxsz); 2216 } 2217 2218 void tcg_gen_gvec_ssadd(unsigned vece, uint32_t dofs, uint32_t aofs, 2219 uint32_t bofs, uint32_t oprsz, uint32_t maxsz) 2220 { 2221 static const TCGOpcode vecop_list[] = { INDEX_op_ssadd_vec, 0 }; 2222 static const GVecGen3 g[4] = { 2223 { .fniv = tcg_gen_ssadd_vec, 2224 .fno = gen_helper_gvec_ssadd8, 2225 .opt_opc = vecop_list, 2226 .vece = MO_8 }, 2227 { .fniv = tcg_gen_ssadd_vec, 2228 .fno = gen_helper_gvec_ssadd16, 2229 .opt_opc = vecop_list, 2230 .vece = MO_16 }, 2231 { .fniv = tcg_gen_ssadd_vec, 2232 .fno = gen_helper_gvec_ssadd32, 2233 .opt_opc = vecop_list, 2234 .vece = MO_32 }, 2235 { .fniv = tcg_gen_ssadd_vec, 2236 .fno = gen_helper_gvec_ssadd64, 2237 .opt_opc = vecop_list, 2238 .vece = MO_64 }, 2239 }; 2240 tcg_debug_assert(vece <= MO_64); 2241 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); 2242 } 2243 2244 void tcg_gen_gvec_sssub(unsigned vece, uint32_t dofs, uint32_t aofs, 2245 uint32_t bofs, uint32_t oprsz, uint32_t maxsz) 2246 { 2247 static const TCGOpcode vecop_list[] = { INDEX_op_sssub_vec, 0 }; 2248 static const GVecGen3 g[4] = { 2249 { .fniv = tcg_gen_sssub_vec, 2250 .fno = gen_helper_gvec_sssub8, 2251 .opt_opc = vecop_list, 2252 .vece = MO_8 }, 2253 { .fniv = tcg_gen_sssub_vec, 2254 .fno = gen_helper_gvec_sssub16, 2255 .opt_opc = vecop_list, 2256 .vece = MO_16 }, 2257 { .fniv = tcg_gen_sssub_vec, 2258 .fno = gen_helper_gvec_sssub32, 2259 .opt_opc = vecop_list, 2260 .vece = MO_32 }, 2261 { .fniv = tcg_gen_sssub_vec, 2262 .fno = gen_helper_gvec_sssub64, 2263 .opt_opc = vecop_list, 2264 .vece = MO_64 }, 2265 }; 2266 tcg_debug_assert(vece <= MO_64); 2267 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); 2268 } 2269 2270 static void tcg_gen_usadd_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) 2271 { 2272 TCGv_i32 max = tcg_constant_i32(-1); 2273 tcg_gen_add_i32(d, a, b); 2274 tcg_gen_movcond_i32(TCG_COND_LTU, d, d, a, max, d); 2275 } 2276 2277 static void tcg_gen_usadd_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) 2278 { 2279 TCGv_i64 max = tcg_constant_i64(-1); 2280 tcg_gen_add_i64(d, a, b); 2281 tcg_gen_movcond_i64(TCG_COND_LTU, d, d, a, max, d); 2282 } 2283 2284 void tcg_gen_gvec_usadd(unsigned vece, uint32_t dofs, uint32_t aofs, 2285 uint32_t bofs, uint32_t oprsz, uint32_t maxsz) 2286 { 2287 static const TCGOpcode vecop_list[] = { INDEX_op_usadd_vec, 0 }; 2288 static const GVecGen3 g[4] = { 2289 { .fniv = tcg_gen_usadd_vec, 2290 .fno = gen_helper_gvec_usadd8, 2291 .opt_opc = vecop_list, 2292 .vece = MO_8 }, 2293 { .fniv = tcg_gen_usadd_vec, 2294 .fno = gen_helper_gvec_usadd16, 2295 .opt_opc = vecop_list, 2296 .vece = MO_16 }, 2297 { .fni4 = tcg_gen_usadd_i32, 2298 .fniv = tcg_gen_usadd_vec, 2299 .fno = gen_helper_gvec_usadd32, 2300 .opt_opc = vecop_list, 2301 .vece = MO_32 }, 2302 { .fni8 = tcg_gen_usadd_i64, 2303 .fniv = tcg_gen_usadd_vec, 2304 .fno = gen_helper_gvec_usadd64, 2305 .opt_opc = vecop_list, 2306 .vece = MO_64 } 2307 }; 2308 tcg_debug_assert(vece <= MO_64); 2309 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); 2310 } 2311 2312 static void tcg_gen_ussub_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) 2313 { 2314 TCGv_i32 min = tcg_constant_i32(0); 2315 tcg_gen_sub_i32(d, a, b); 2316 tcg_gen_movcond_i32(TCG_COND_LTU, d, a, b, min, d); 2317 } 2318 2319 static void tcg_gen_ussub_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) 2320 { 2321 TCGv_i64 min = tcg_constant_i64(0); 2322 tcg_gen_sub_i64(d, a, b); 2323 tcg_gen_movcond_i64(TCG_COND_LTU, d, a, b, min, d); 2324 } 2325 2326 void tcg_gen_gvec_ussub(unsigned vece, uint32_t dofs, uint32_t aofs, 2327 uint32_t bofs, uint32_t oprsz, uint32_t maxsz) 2328 { 2329 static const TCGOpcode vecop_list[] = { INDEX_op_ussub_vec, 0 }; 2330 static const GVecGen3 g[4] = { 2331 { .fniv = tcg_gen_ussub_vec, 2332 .fno = gen_helper_gvec_ussub8, 2333 .opt_opc = vecop_list, 2334 .vece = MO_8 }, 2335 { .fniv = tcg_gen_ussub_vec, 2336 .fno = gen_helper_gvec_ussub16, 2337 .opt_opc = vecop_list, 2338 .vece = MO_16 }, 2339 { .fni4 = tcg_gen_ussub_i32, 2340 .fniv = tcg_gen_ussub_vec, 2341 .fno = gen_helper_gvec_ussub32, 2342 .opt_opc = vecop_list, 2343 .vece = MO_32 }, 2344 { .fni8 = tcg_gen_ussub_i64, 2345 .fniv = tcg_gen_ussub_vec, 2346 .fno = gen_helper_gvec_ussub64, 2347 .opt_opc = vecop_list, 2348 .vece = MO_64 } 2349 }; 2350 tcg_debug_assert(vece <= MO_64); 2351 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); 2352 } 2353 2354 void tcg_gen_gvec_smin(unsigned vece, uint32_t dofs, uint32_t aofs, 2355 uint32_t bofs, uint32_t oprsz, uint32_t maxsz) 2356 { 2357 static const TCGOpcode vecop_list[] = { INDEX_op_smin_vec, 0 }; 2358 static const GVecGen3 g[4] = { 2359 { .fniv = tcg_gen_smin_vec, 2360 .fno = gen_helper_gvec_smin8, 2361 .opt_opc = vecop_list, 2362 .vece = MO_8 }, 2363 { .fniv = tcg_gen_smin_vec, 2364 .fno = gen_helper_gvec_smin16, 2365 .opt_opc = vecop_list, 2366 .vece = MO_16 }, 2367 { .fni4 = tcg_gen_smin_i32, 2368 .fniv = tcg_gen_smin_vec, 2369 .fno = gen_helper_gvec_smin32, 2370 .opt_opc = vecop_list, 2371 .vece = MO_32 }, 2372 { .fni8 = tcg_gen_smin_i64, 2373 .fniv = tcg_gen_smin_vec, 2374 .fno = gen_helper_gvec_smin64, 2375 .opt_opc = vecop_list, 2376 .vece = MO_64 } 2377 }; 2378 tcg_debug_assert(vece <= MO_64); 2379 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); 2380 } 2381 2382 void tcg_gen_gvec_umin(unsigned vece, uint32_t dofs, uint32_t aofs, 2383 uint32_t bofs, uint32_t oprsz, uint32_t maxsz) 2384 { 2385 static const TCGOpcode vecop_list[] = { INDEX_op_umin_vec, 0 }; 2386 static const GVecGen3 g[4] = { 2387 { .fniv = tcg_gen_umin_vec, 2388 .fno = gen_helper_gvec_umin8, 2389 .opt_opc = vecop_list, 2390 .vece = MO_8 }, 2391 { .fniv = tcg_gen_umin_vec, 2392 .fno = gen_helper_gvec_umin16, 2393 .opt_opc = vecop_list, 2394 .vece = MO_16 }, 2395 { .fni4 = tcg_gen_umin_i32, 2396 .fniv = tcg_gen_umin_vec, 2397 .fno = gen_helper_gvec_umin32, 2398 .opt_opc = vecop_list, 2399 .vece = MO_32 }, 2400 { .fni8 = tcg_gen_umin_i64, 2401 .fniv = tcg_gen_umin_vec, 2402 .fno = gen_helper_gvec_umin64, 2403 .opt_opc = vecop_list, 2404 .vece = MO_64 } 2405 }; 2406 tcg_debug_assert(vece <= MO_64); 2407 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); 2408 } 2409 2410 void tcg_gen_gvec_smax(unsigned vece, uint32_t dofs, uint32_t aofs, 2411 uint32_t bofs, uint32_t oprsz, uint32_t maxsz) 2412 { 2413 static const TCGOpcode vecop_list[] = { INDEX_op_smax_vec, 0 }; 2414 static const GVecGen3 g[4] = { 2415 { .fniv = tcg_gen_smax_vec, 2416 .fno = gen_helper_gvec_smax8, 2417 .opt_opc = vecop_list, 2418 .vece = MO_8 }, 2419 { .fniv = tcg_gen_smax_vec, 2420 .fno = gen_helper_gvec_smax16, 2421 .opt_opc = vecop_list, 2422 .vece = MO_16 }, 2423 { .fni4 = tcg_gen_smax_i32, 2424 .fniv = tcg_gen_smax_vec, 2425 .fno = gen_helper_gvec_smax32, 2426 .opt_opc = vecop_list, 2427 .vece = MO_32 }, 2428 { .fni8 = tcg_gen_smax_i64, 2429 .fniv = tcg_gen_smax_vec, 2430 .fno = gen_helper_gvec_smax64, 2431 .opt_opc = vecop_list, 2432 .vece = MO_64 } 2433 }; 2434 tcg_debug_assert(vece <= MO_64); 2435 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); 2436 } 2437 2438 void tcg_gen_gvec_umax(unsigned vece, uint32_t dofs, uint32_t aofs, 2439 uint32_t bofs, uint32_t oprsz, uint32_t maxsz) 2440 { 2441 static const TCGOpcode vecop_list[] = { INDEX_op_umax_vec, 0 }; 2442 static const GVecGen3 g[4] = { 2443 { .fniv = tcg_gen_umax_vec, 2444 .fno = gen_helper_gvec_umax8, 2445 .opt_opc = vecop_list, 2446 .vece = MO_8 }, 2447 { .fniv = tcg_gen_umax_vec, 2448 .fno = gen_helper_gvec_umax16, 2449 .opt_opc = vecop_list, 2450 .vece = MO_16 }, 2451 { .fni4 = tcg_gen_umax_i32, 2452 .fniv = tcg_gen_umax_vec, 2453 .fno = gen_helper_gvec_umax32, 2454 .opt_opc = vecop_list, 2455 .vece = MO_32 }, 2456 { .fni8 = tcg_gen_umax_i64, 2457 .fniv = tcg_gen_umax_vec, 2458 .fno = gen_helper_gvec_umax64, 2459 .opt_opc = vecop_list, 2460 .vece = MO_64 } 2461 }; 2462 tcg_debug_assert(vece <= MO_64); 2463 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); 2464 } 2465 2466 /* Perform a vector negation using normal negation and a mask. 2467 Compare gen_subv_mask above. */ 2468 static void gen_negv_mask(TCGv_i64 d, TCGv_i64 b, TCGv_i64 m) 2469 { 2470 TCGv_i64 t2 = tcg_temp_ebb_new_i64(); 2471 TCGv_i64 t3 = tcg_temp_ebb_new_i64(); 2472 2473 tcg_gen_andc_i64(t3, m, b); 2474 tcg_gen_andc_i64(t2, b, m); 2475 tcg_gen_sub_i64(d, m, t2); 2476 tcg_gen_xor_i64(d, d, t3); 2477 2478 tcg_temp_free_i64(t2); 2479 tcg_temp_free_i64(t3); 2480 } 2481 2482 void tcg_gen_vec_neg8_i64(TCGv_i64 d, TCGv_i64 b) 2483 { 2484 TCGv_i64 m = tcg_constant_i64(dup_const(MO_8, 0x80)); 2485 gen_negv_mask(d, b, m); 2486 } 2487 2488 void tcg_gen_vec_neg16_i64(TCGv_i64 d, TCGv_i64 b) 2489 { 2490 TCGv_i64 m = tcg_constant_i64(dup_const(MO_16, 0x8000)); 2491 gen_negv_mask(d, b, m); 2492 } 2493 2494 void tcg_gen_vec_neg32_i64(TCGv_i64 d, TCGv_i64 b) 2495 { 2496 TCGv_i64 t1 = tcg_temp_ebb_new_i64(); 2497 TCGv_i64 t2 = tcg_temp_ebb_new_i64(); 2498 2499 tcg_gen_andi_i64(t1, b, ~0xffffffffull); 2500 tcg_gen_neg_i64(t2, b); 2501 tcg_gen_neg_i64(t1, t1); 2502 tcg_gen_deposit_i64(d, t1, t2, 0, 32); 2503 2504 tcg_temp_free_i64(t1); 2505 tcg_temp_free_i64(t2); 2506 } 2507 2508 void tcg_gen_gvec_neg(unsigned vece, uint32_t dofs, uint32_t aofs, 2509 uint32_t oprsz, uint32_t maxsz) 2510 { 2511 static const TCGOpcode vecop_list[] = { INDEX_op_neg_vec, 0 }; 2512 static const GVecGen2 g[4] = { 2513 { .fni8 = tcg_gen_vec_neg8_i64, 2514 .fniv = tcg_gen_neg_vec, 2515 .fno = gen_helper_gvec_neg8, 2516 .opt_opc = vecop_list, 2517 .vece = MO_8 }, 2518 { .fni8 = tcg_gen_vec_neg16_i64, 2519 .fniv = tcg_gen_neg_vec, 2520 .fno = gen_helper_gvec_neg16, 2521 .opt_opc = vecop_list, 2522 .vece = MO_16 }, 2523 { .fni4 = tcg_gen_neg_i32, 2524 .fniv = tcg_gen_neg_vec, 2525 .fno = gen_helper_gvec_neg32, 2526 .opt_opc = vecop_list, 2527 .vece = MO_32 }, 2528 { .fni8 = tcg_gen_neg_i64, 2529 .fniv = tcg_gen_neg_vec, 2530 .fno = gen_helper_gvec_neg64, 2531 .opt_opc = vecop_list, 2532 .prefer_i64 = TCG_TARGET_REG_BITS == 64, 2533 .vece = MO_64 }, 2534 }; 2535 2536 tcg_debug_assert(vece <= MO_64); 2537 tcg_gen_gvec_2(dofs, aofs, oprsz, maxsz, &g[vece]); 2538 } 2539 2540 static void gen_absv_mask(TCGv_i64 d, TCGv_i64 b, unsigned vece) 2541 { 2542 TCGv_i64 t = tcg_temp_ebb_new_i64(); 2543 int nbit = 8 << vece; 2544 2545 /* Create -1 for each negative element. */ 2546 tcg_gen_shri_i64(t, b, nbit - 1); 2547 tcg_gen_andi_i64(t, t, dup_const(vece, 1)); 2548 tcg_gen_muli_i64(t, t, (1 << nbit) - 1); 2549 2550 /* 2551 * Invert (via xor -1) and add one. 2552 * Because of the ordering the msb is cleared, 2553 * so we never have carry into the next element. 2554 */ 2555 tcg_gen_xor_i64(d, b, t); 2556 tcg_gen_andi_i64(t, t, dup_const(vece, 1)); 2557 tcg_gen_add_i64(d, d, t); 2558 2559 tcg_temp_free_i64(t); 2560 } 2561 2562 static void tcg_gen_vec_abs8_i64(TCGv_i64 d, TCGv_i64 b) 2563 { 2564 gen_absv_mask(d, b, MO_8); 2565 } 2566 2567 static void tcg_gen_vec_abs16_i64(TCGv_i64 d, TCGv_i64 b) 2568 { 2569 gen_absv_mask(d, b, MO_16); 2570 } 2571 2572 void tcg_gen_gvec_abs(unsigned vece, uint32_t dofs, uint32_t aofs, 2573 uint32_t oprsz, uint32_t maxsz) 2574 { 2575 static const TCGOpcode vecop_list[] = { INDEX_op_abs_vec, 0 }; 2576 static const GVecGen2 g[4] = { 2577 { .fni8 = tcg_gen_vec_abs8_i64, 2578 .fniv = tcg_gen_abs_vec, 2579 .fno = gen_helper_gvec_abs8, 2580 .opt_opc = vecop_list, 2581 .vece = MO_8 }, 2582 { .fni8 = tcg_gen_vec_abs16_i64, 2583 .fniv = tcg_gen_abs_vec, 2584 .fno = gen_helper_gvec_abs16, 2585 .opt_opc = vecop_list, 2586 .vece = MO_16 }, 2587 { .fni4 = tcg_gen_abs_i32, 2588 .fniv = tcg_gen_abs_vec, 2589 .fno = gen_helper_gvec_abs32, 2590 .opt_opc = vecop_list, 2591 .vece = MO_32 }, 2592 { .fni8 = tcg_gen_abs_i64, 2593 .fniv = tcg_gen_abs_vec, 2594 .fno = gen_helper_gvec_abs64, 2595 .opt_opc = vecop_list, 2596 .prefer_i64 = TCG_TARGET_REG_BITS == 64, 2597 .vece = MO_64 }, 2598 }; 2599 2600 tcg_debug_assert(vece <= MO_64); 2601 tcg_gen_gvec_2(dofs, aofs, oprsz, maxsz, &g[vece]); 2602 } 2603 2604 void tcg_gen_gvec_and(unsigned vece, uint32_t dofs, uint32_t aofs, 2605 uint32_t bofs, uint32_t oprsz, uint32_t maxsz) 2606 { 2607 static const GVecGen3 g = { 2608 .fni8 = tcg_gen_and_i64, 2609 .fniv = tcg_gen_and_vec, 2610 .fno = gen_helper_gvec_and, 2611 .prefer_i64 = TCG_TARGET_REG_BITS == 64, 2612 }; 2613 2614 if (aofs == bofs) { 2615 tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz); 2616 } else { 2617 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); 2618 } 2619 } 2620 2621 void tcg_gen_gvec_or(unsigned vece, uint32_t dofs, uint32_t aofs, 2622 uint32_t bofs, uint32_t oprsz, uint32_t maxsz) 2623 { 2624 static const GVecGen3 g = { 2625 .fni8 = tcg_gen_or_i64, 2626 .fniv = tcg_gen_or_vec, 2627 .fno = gen_helper_gvec_or, 2628 .prefer_i64 = TCG_TARGET_REG_BITS == 64, 2629 }; 2630 2631 if (aofs == bofs) { 2632 tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz); 2633 } else { 2634 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); 2635 } 2636 } 2637 2638 void tcg_gen_gvec_xor(unsigned vece, uint32_t dofs, uint32_t aofs, 2639 uint32_t bofs, uint32_t oprsz, uint32_t maxsz) 2640 { 2641 static const GVecGen3 g = { 2642 .fni8 = tcg_gen_xor_i64, 2643 .fniv = tcg_gen_xor_vec, 2644 .fno = gen_helper_gvec_xor, 2645 .prefer_i64 = TCG_TARGET_REG_BITS == 64, 2646 }; 2647 2648 if (aofs == bofs) { 2649 tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, 0); 2650 } else { 2651 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); 2652 } 2653 } 2654 2655 void tcg_gen_gvec_andc(unsigned vece, uint32_t dofs, uint32_t aofs, 2656 uint32_t bofs, uint32_t oprsz, uint32_t maxsz) 2657 { 2658 static const GVecGen3 g = { 2659 .fni8 = tcg_gen_andc_i64, 2660 .fniv = tcg_gen_andc_vec, 2661 .fno = gen_helper_gvec_andc, 2662 .prefer_i64 = TCG_TARGET_REG_BITS == 64, 2663 }; 2664 2665 if (aofs == bofs) { 2666 tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, 0); 2667 } else { 2668 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); 2669 } 2670 } 2671 2672 void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs, uint32_t aofs, 2673 uint32_t bofs, uint32_t oprsz, uint32_t maxsz) 2674 { 2675 static const GVecGen3 g = { 2676 .fni8 = tcg_gen_orc_i64, 2677 .fniv = tcg_gen_orc_vec, 2678 .fno = gen_helper_gvec_orc, 2679 .prefer_i64 = TCG_TARGET_REG_BITS == 64, 2680 }; 2681 2682 if (aofs == bofs) { 2683 tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, -1); 2684 } else { 2685 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); 2686 } 2687 } 2688 2689 void tcg_gen_gvec_nand(unsigned vece, uint32_t dofs, uint32_t aofs, 2690 uint32_t bofs, uint32_t oprsz, uint32_t maxsz) 2691 { 2692 static const GVecGen3 g = { 2693 .fni8 = tcg_gen_nand_i64, 2694 .fniv = tcg_gen_nand_vec, 2695 .fno = gen_helper_gvec_nand, 2696 .prefer_i64 = TCG_TARGET_REG_BITS == 64, 2697 }; 2698 2699 if (aofs == bofs) { 2700 tcg_gen_gvec_not(vece, dofs, aofs, oprsz, maxsz); 2701 } else { 2702 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); 2703 } 2704 } 2705 2706 void tcg_gen_gvec_nor(unsigned vece, uint32_t dofs, uint32_t aofs, 2707 uint32_t bofs, uint32_t oprsz, uint32_t maxsz) 2708 { 2709 static const GVecGen3 g = { 2710 .fni8 = tcg_gen_nor_i64, 2711 .fniv = tcg_gen_nor_vec, 2712 .fno = gen_helper_gvec_nor, 2713 .prefer_i64 = TCG_TARGET_REG_BITS == 64, 2714 }; 2715 2716 if (aofs == bofs) { 2717 tcg_gen_gvec_not(vece, dofs, aofs, oprsz, maxsz); 2718 } else { 2719 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); 2720 } 2721 } 2722 2723 void tcg_gen_gvec_eqv(unsigned vece, uint32_t dofs, uint32_t aofs, 2724 uint32_t bofs, uint32_t oprsz, uint32_t maxsz) 2725 { 2726 static const GVecGen3 g = { 2727 .fni8 = tcg_gen_eqv_i64, 2728 .fniv = tcg_gen_eqv_vec, 2729 .fno = gen_helper_gvec_eqv, 2730 .prefer_i64 = TCG_TARGET_REG_BITS == 64, 2731 }; 2732 2733 if (aofs == bofs) { 2734 tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, -1); 2735 } else { 2736 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); 2737 } 2738 } 2739 2740 static const GVecGen2s gop_ands = { 2741 .fni8 = tcg_gen_and_i64, 2742 .fniv = tcg_gen_and_vec, 2743 .fno = gen_helper_gvec_ands, 2744 .prefer_i64 = TCG_TARGET_REG_BITS == 64, 2745 .vece = MO_64 2746 }; 2747 2748 void tcg_gen_gvec_ands(unsigned vece, uint32_t dofs, uint32_t aofs, 2749 TCGv_i64 c, uint32_t oprsz, uint32_t maxsz) 2750 { 2751 TCGv_i64 tmp = tcg_temp_ebb_new_i64(); 2752 tcg_gen_dup_i64(vece, tmp, c); 2753 tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &gop_ands); 2754 tcg_temp_free_i64(tmp); 2755 } 2756 2757 void tcg_gen_gvec_andi(unsigned vece, uint32_t dofs, uint32_t aofs, 2758 int64_t c, uint32_t oprsz, uint32_t maxsz) 2759 { 2760 TCGv_i64 tmp = tcg_constant_i64(dup_const(vece, c)); 2761 tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &gop_ands); 2762 } 2763 2764 static const GVecGen2s gop_xors = { 2765 .fni8 = tcg_gen_xor_i64, 2766 .fniv = tcg_gen_xor_vec, 2767 .fno = gen_helper_gvec_xors, 2768 .prefer_i64 = TCG_TARGET_REG_BITS == 64, 2769 .vece = MO_64 2770 }; 2771 2772 void tcg_gen_gvec_xors(unsigned vece, uint32_t dofs, uint32_t aofs, 2773 TCGv_i64 c, uint32_t oprsz, uint32_t maxsz) 2774 { 2775 TCGv_i64 tmp = tcg_temp_ebb_new_i64(); 2776 tcg_gen_dup_i64(vece, tmp, c); 2777 tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &gop_xors); 2778 tcg_temp_free_i64(tmp); 2779 } 2780 2781 void tcg_gen_gvec_xori(unsigned vece, uint32_t dofs, uint32_t aofs, 2782 int64_t c, uint32_t oprsz, uint32_t maxsz) 2783 { 2784 TCGv_i64 tmp = tcg_constant_i64(dup_const(vece, c)); 2785 tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &gop_xors); 2786 } 2787 2788 static const GVecGen2s gop_ors = { 2789 .fni8 = tcg_gen_or_i64, 2790 .fniv = tcg_gen_or_vec, 2791 .fno = gen_helper_gvec_ors, 2792 .prefer_i64 = TCG_TARGET_REG_BITS == 64, 2793 .vece = MO_64 2794 }; 2795 2796 void tcg_gen_gvec_ors(unsigned vece, uint32_t dofs, uint32_t aofs, 2797 TCGv_i64 c, uint32_t oprsz, uint32_t maxsz) 2798 { 2799 TCGv_i64 tmp = tcg_temp_ebb_new_i64(); 2800 tcg_gen_dup_i64(vece, tmp, c); 2801 tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &gop_ors); 2802 tcg_temp_free_i64(tmp); 2803 } 2804 2805 void tcg_gen_gvec_ori(unsigned vece, uint32_t dofs, uint32_t aofs, 2806 int64_t c, uint32_t oprsz, uint32_t maxsz) 2807 { 2808 TCGv_i64 tmp = tcg_constant_i64(dup_const(vece, c)); 2809 tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &gop_ors); 2810 } 2811 2812 void tcg_gen_vec_shl8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c) 2813 { 2814 uint64_t mask = dup_const(MO_8, 0xff << c); 2815 tcg_gen_shli_i64(d, a, c); 2816 tcg_gen_andi_i64(d, d, mask); 2817 } 2818 2819 void tcg_gen_vec_shl16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c) 2820 { 2821 uint64_t mask = dup_const(MO_16, 0xffff << c); 2822 tcg_gen_shli_i64(d, a, c); 2823 tcg_gen_andi_i64(d, d, mask); 2824 } 2825 2826 void tcg_gen_vec_shl8i_i32(TCGv_i32 d, TCGv_i32 a, int32_t c) 2827 { 2828 uint32_t mask = dup_const(MO_8, 0xff << c); 2829 tcg_gen_shli_i32(d, a, c); 2830 tcg_gen_andi_i32(d, d, mask); 2831 } 2832 2833 void tcg_gen_vec_shl16i_i32(TCGv_i32 d, TCGv_i32 a, int32_t c) 2834 { 2835 uint32_t mask = dup_const(MO_16, 0xffff << c); 2836 tcg_gen_shli_i32(d, a, c); 2837 tcg_gen_andi_i32(d, d, mask); 2838 } 2839 2840 void tcg_gen_gvec_shli(unsigned vece, uint32_t dofs, uint32_t aofs, 2841 int64_t shift, uint32_t oprsz, uint32_t maxsz) 2842 { 2843 static const TCGOpcode vecop_list[] = { INDEX_op_shli_vec, 0 }; 2844 static const GVecGen2i g[4] = { 2845 { .fni8 = tcg_gen_vec_shl8i_i64, 2846 .fniv = tcg_gen_shli_vec, 2847 .fno = gen_helper_gvec_shl8i, 2848 .opt_opc = vecop_list, 2849 .vece = MO_8 }, 2850 { .fni8 = tcg_gen_vec_shl16i_i64, 2851 .fniv = tcg_gen_shli_vec, 2852 .fno = gen_helper_gvec_shl16i, 2853 .opt_opc = vecop_list, 2854 .vece = MO_16 }, 2855 { .fni4 = tcg_gen_shli_i32, 2856 .fniv = tcg_gen_shli_vec, 2857 .fno = gen_helper_gvec_shl32i, 2858 .opt_opc = vecop_list, 2859 .vece = MO_32 }, 2860 { .fni8 = tcg_gen_shli_i64, 2861 .fniv = tcg_gen_shli_vec, 2862 .fno = gen_helper_gvec_shl64i, 2863 .opt_opc = vecop_list, 2864 .prefer_i64 = TCG_TARGET_REG_BITS == 64, 2865 .vece = MO_64 }, 2866 }; 2867 2868 tcg_debug_assert(vece <= MO_64); 2869 tcg_debug_assert(shift >= 0 && shift < (8 << vece)); 2870 if (shift == 0) { 2871 tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz); 2872 } else { 2873 tcg_gen_gvec_2i(dofs, aofs, oprsz, maxsz, shift, &g[vece]); 2874 } 2875 } 2876 2877 void tcg_gen_vec_shr8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c) 2878 { 2879 uint64_t mask = dup_const(MO_8, 0xff >> c); 2880 tcg_gen_shri_i64(d, a, c); 2881 tcg_gen_andi_i64(d, d, mask); 2882 } 2883 2884 void tcg_gen_vec_shr16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c) 2885 { 2886 uint64_t mask = dup_const(MO_16, 0xffff >> c); 2887 tcg_gen_shri_i64(d, a, c); 2888 tcg_gen_andi_i64(d, d, mask); 2889 } 2890 2891 void tcg_gen_vec_shr8i_i32(TCGv_i32 d, TCGv_i32 a, int32_t c) 2892 { 2893 uint32_t mask = dup_const(MO_8, 0xff >> c); 2894 tcg_gen_shri_i32(d, a, c); 2895 tcg_gen_andi_i32(d, d, mask); 2896 } 2897 2898 void tcg_gen_vec_shr16i_i32(TCGv_i32 d, TCGv_i32 a, int32_t c) 2899 { 2900 uint32_t mask = dup_const(MO_16, 0xffff >> c); 2901 tcg_gen_shri_i32(d, a, c); 2902 tcg_gen_andi_i32(d, d, mask); 2903 } 2904 2905 void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs, 2906 int64_t shift, uint32_t oprsz, uint32_t maxsz) 2907 { 2908 static const TCGOpcode vecop_list[] = { INDEX_op_shri_vec, 0 }; 2909 static const GVecGen2i g[4] = { 2910 { .fni8 = tcg_gen_vec_shr8i_i64, 2911 .fniv = tcg_gen_shri_vec, 2912 .fno = gen_helper_gvec_shr8i, 2913 .opt_opc = vecop_list, 2914 .vece = MO_8 }, 2915 { .fni8 = tcg_gen_vec_shr16i_i64, 2916 .fniv = tcg_gen_shri_vec, 2917 .fno = gen_helper_gvec_shr16i, 2918 .opt_opc = vecop_list, 2919 .vece = MO_16 }, 2920 { .fni4 = tcg_gen_shri_i32, 2921 .fniv = tcg_gen_shri_vec, 2922 .fno = gen_helper_gvec_shr32i, 2923 .opt_opc = vecop_list, 2924 .vece = MO_32 }, 2925 { .fni8 = tcg_gen_shri_i64, 2926 .fniv = tcg_gen_shri_vec, 2927 .fno = gen_helper_gvec_shr64i, 2928 .opt_opc = vecop_list, 2929 .prefer_i64 = TCG_TARGET_REG_BITS == 64, 2930 .vece = MO_64 }, 2931 }; 2932 2933 tcg_debug_assert(vece <= MO_64); 2934 tcg_debug_assert(shift >= 0 && shift < (8 << vece)); 2935 if (shift == 0) { 2936 tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz); 2937 } else { 2938 tcg_gen_gvec_2i(dofs, aofs, oprsz, maxsz, shift, &g[vece]); 2939 } 2940 } 2941 2942 void tcg_gen_vec_sar8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c) 2943 { 2944 uint64_t s_mask = dup_const(MO_8, 0x80 >> c); 2945 uint64_t c_mask = dup_const(MO_8, 0xff >> c); 2946 TCGv_i64 s = tcg_temp_ebb_new_i64(); 2947 2948 tcg_gen_shri_i64(d, a, c); 2949 tcg_gen_andi_i64(s, d, s_mask); /* isolate (shifted) sign bit */ 2950 tcg_gen_muli_i64(s, s, (2 << c) - 2); /* replicate isolated signs */ 2951 tcg_gen_andi_i64(d, d, c_mask); /* clear out bits above sign */ 2952 tcg_gen_or_i64(d, d, s); /* include sign extension */ 2953 tcg_temp_free_i64(s); 2954 } 2955 2956 void tcg_gen_vec_sar16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c) 2957 { 2958 uint64_t s_mask = dup_const(MO_16, 0x8000 >> c); 2959 uint64_t c_mask = dup_const(MO_16, 0xffff >> c); 2960 TCGv_i64 s = tcg_temp_ebb_new_i64(); 2961 2962 tcg_gen_shri_i64(d, a, c); 2963 tcg_gen_andi_i64(s, d, s_mask); /* isolate (shifted) sign bit */ 2964 tcg_gen_andi_i64(d, d, c_mask); /* clear out bits above sign */ 2965 tcg_gen_muli_i64(s, s, (2 << c) - 2); /* replicate isolated signs */ 2966 tcg_gen_or_i64(d, d, s); /* include sign extension */ 2967 tcg_temp_free_i64(s); 2968 } 2969 2970 void tcg_gen_vec_sar8i_i32(TCGv_i32 d, TCGv_i32 a, int32_t c) 2971 { 2972 uint32_t s_mask = dup_const(MO_8, 0x80 >> c); 2973 uint32_t c_mask = dup_const(MO_8, 0xff >> c); 2974 TCGv_i32 s = tcg_temp_ebb_new_i32(); 2975 2976 tcg_gen_shri_i32(d, a, c); 2977 tcg_gen_andi_i32(s, d, s_mask); /* isolate (shifted) sign bit */ 2978 tcg_gen_muli_i32(s, s, (2 << c) - 2); /* replicate isolated signs */ 2979 tcg_gen_andi_i32(d, d, c_mask); /* clear out bits above sign */ 2980 tcg_gen_or_i32(d, d, s); /* include sign extension */ 2981 tcg_temp_free_i32(s); 2982 } 2983 2984 void tcg_gen_vec_sar16i_i32(TCGv_i32 d, TCGv_i32 a, int32_t c) 2985 { 2986 uint32_t s_mask = dup_const(MO_16, 0x8000 >> c); 2987 uint32_t c_mask = dup_const(MO_16, 0xffff >> c); 2988 TCGv_i32 s = tcg_temp_ebb_new_i32(); 2989 2990 tcg_gen_shri_i32(d, a, c); 2991 tcg_gen_andi_i32(s, d, s_mask); /* isolate (shifted) sign bit */ 2992 tcg_gen_andi_i32(d, d, c_mask); /* clear out bits above sign */ 2993 tcg_gen_muli_i32(s, s, (2 << c) - 2); /* replicate isolated signs */ 2994 tcg_gen_or_i32(d, d, s); /* include sign extension */ 2995 tcg_temp_free_i32(s); 2996 } 2997 2998 void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs, 2999 int64_t shift, uint32_t oprsz, uint32_t maxsz) 3000 { 3001 static const TCGOpcode vecop_list[] = { INDEX_op_sari_vec, 0 }; 3002 static const GVecGen2i g[4] = { 3003 { .fni8 = tcg_gen_vec_sar8i_i64, 3004 .fniv = tcg_gen_sari_vec, 3005 .fno = gen_helper_gvec_sar8i, 3006 .opt_opc = vecop_list, 3007 .vece = MO_8 }, 3008 { .fni8 = tcg_gen_vec_sar16i_i64, 3009 .fniv = tcg_gen_sari_vec, 3010 .fno = gen_helper_gvec_sar16i, 3011 .opt_opc = vecop_list, 3012 .vece = MO_16 }, 3013 { .fni4 = tcg_gen_sari_i32, 3014 .fniv = tcg_gen_sari_vec, 3015 .fno = gen_helper_gvec_sar32i, 3016 .opt_opc = vecop_list, 3017 .vece = MO_32 }, 3018 { .fni8 = tcg_gen_sari_i64, 3019 .fniv = tcg_gen_sari_vec, 3020 .fno = gen_helper_gvec_sar64i, 3021 .opt_opc = vecop_list, 3022 .prefer_i64 = TCG_TARGET_REG_BITS == 64, 3023 .vece = MO_64 }, 3024 }; 3025 3026 tcg_debug_assert(vece <= MO_64); 3027 tcg_debug_assert(shift >= 0 && shift < (8 << vece)); 3028 if (shift == 0) { 3029 tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz); 3030 } else { 3031 tcg_gen_gvec_2i(dofs, aofs, oprsz, maxsz, shift, &g[vece]); 3032 } 3033 } 3034 3035 void tcg_gen_vec_rotl8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c) 3036 { 3037 uint64_t mask = dup_const(MO_8, 0xff << c); 3038 3039 tcg_gen_shli_i64(d, a, c); 3040 tcg_gen_shri_i64(a, a, 8 - c); 3041 tcg_gen_andi_i64(d, d, mask); 3042 tcg_gen_andi_i64(a, a, ~mask); 3043 tcg_gen_or_i64(d, d, a); 3044 } 3045 3046 void tcg_gen_vec_rotl16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c) 3047 { 3048 uint64_t mask = dup_const(MO_16, 0xffff << c); 3049 3050 tcg_gen_shli_i64(d, a, c); 3051 tcg_gen_shri_i64(a, a, 16 - c); 3052 tcg_gen_andi_i64(d, d, mask); 3053 tcg_gen_andi_i64(a, a, ~mask); 3054 tcg_gen_or_i64(d, d, a); 3055 } 3056 3057 void tcg_gen_gvec_rotli(unsigned vece, uint32_t dofs, uint32_t aofs, 3058 int64_t shift, uint32_t oprsz, uint32_t maxsz) 3059 { 3060 static const TCGOpcode vecop_list[] = { INDEX_op_rotli_vec, 0 }; 3061 static const GVecGen2i g[4] = { 3062 { .fni8 = tcg_gen_vec_rotl8i_i64, 3063 .fniv = tcg_gen_rotli_vec, 3064 .fno = gen_helper_gvec_rotl8i, 3065 .opt_opc = vecop_list, 3066 .vece = MO_8 }, 3067 { .fni8 = tcg_gen_vec_rotl16i_i64, 3068 .fniv = tcg_gen_rotli_vec, 3069 .fno = gen_helper_gvec_rotl16i, 3070 .opt_opc = vecop_list, 3071 .vece = MO_16 }, 3072 { .fni4 = tcg_gen_rotli_i32, 3073 .fniv = tcg_gen_rotli_vec, 3074 .fno = gen_helper_gvec_rotl32i, 3075 .opt_opc = vecop_list, 3076 .vece = MO_32 }, 3077 { .fni8 = tcg_gen_rotli_i64, 3078 .fniv = tcg_gen_rotli_vec, 3079 .fno = gen_helper_gvec_rotl64i, 3080 .opt_opc = vecop_list, 3081 .prefer_i64 = TCG_TARGET_REG_BITS == 64, 3082 .vece = MO_64 }, 3083 }; 3084 3085 tcg_debug_assert(vece <= MO_64); 3086 tcg_debug_assert(shift >= 0 && shift < (8 << vece)); 3087 if (shift == 0) { 3088 tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz); 3089 } else { 3090 tcg_gen_gvec_2i(dofs, aofs, oprsz, maxsz, shift, &g[vece]); 3091 } 3092 } 3093 3094 void tcg_gen_gvec_rotri(unsigned vece, uint32_t dofs, uint32_t aofs, 3095 int64_t shift, uint32_t oprsz, uint32_t maxsz) 3096 { 3097 tcg_debug_assert(vece <= MO_64); 3098 tcg_debug_assert(shift >= 0 && shift < (8 << vece)); 3099 tcg_gen_gvec_rotli(vece, dofs, aofs, -shift & ((8 << vece) - 1), 3100 oprsz, maxsz); 3101 } 3102 3103 /* 3104 * Specialized generation vector shifts by a non-constant scalar. 3105 */ 3106 3107 typedef struct { 3108 void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32); 3109 void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64); 3110 void (*fniv_s)(unsigned, TCGv_vec, TCGv_vec, TCGv_i32); 3111 void (*fniv_v)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec); 3112 gen_helper_gvec_2 *fno[4]; 3113 TCGOpcode s_list[2]; 3114 TCGOpcode v_list[2]; 3115 } GVecGen2sh; 3116 3117 static void expand_2sh_vec(unsigned vece, uint32_t dofs, uint32_t aofs, 3118 uint32_t oprsz, uint32_t tysz, TCGType type, 3119 TCGv_i32 shift, 3120 void (*fni)(unsigned, TCGv_vec, TCGv_vec, TCGv_i32)) 3121 { 3122 TCGv_vec t0 = tcg_temp_new_vec(type); 3123 uint32_t i; 3124 3125 for (i = 0; i < oprsz; i += tysz) { 3126 tcg_gen_ld_vec(t0, cpu_env, aofs + i); 3127 fni(vece, t0, t0, shift); 3128 tcg_gen_st_vec(t0, cpu_env, dofs + i); 3129 } 3130 tcg_temp_free_vec(t0); 3131 } 3132 3133 static void 3134 do_gvec_shifts(unsigned vece, uint32_t dofs, uint32_t aofs, TCGv_i32 shift, 3135 uint32_t oprsz, uint32_t maxsz, const GVecGen2sh *g) 3136 { 3137 TCGType type; 3138 uint32_t some; 3139 3140 check_size_align(oprsz, maxsz, dofs | aofs); 3141 check_overlap_2(dofs, aofs, maxsz); 3142 3143 /* If the backend has a scalar expansion, great. */ 3144 type = choose_vector_type(g->s_list, vece, oprsz, vece == MO_64); 3145 if (type) { 3146 const TCGOpcode *hold_list = tcg_swap_vecop_list(NULL); 3147 switch (type) { 3148 case TCG_TYPE_V256: 3149 some = QEMU_ALIGN_DOWN(oprsz, 32); 3150 expand_2sh_vec(vece, dofs, aofs, some, 32, 3151 TCG_TYPE_V256, shift, g->fniv_s); 3152 if (some == oprsz) { 3153 break; 3154 } 3155 dofs += some; 3156 aofs += some; 3157 oprsz -= some; 3158 maxsz -= some; 3159 /* fallthru */ 3160 case TCG_TYPE_V128: 3161 expand_2sh_vec(vece, dofs, aofs, oprsz, 16, 3162 TCG_TYPE_V128, shift, g->fniv_s); 3163 break; 3164 case TCG_TYPE_V64: 3165 expand_2sh_vec(vece, dofs, aofs, oprsz, 8, 3166 TCG_TYPE_V64, shift, g->fniv_s); 3167 break; 3168 default: 3169 g_assert_not_reached(); 3170 } 3171 tcg_swap_vecop_list(hold_list); 3172 goto clear_tail; 3173 } 3174 3175 /* If the backend supports variable vector shifts, also cool. */ 3176 type = choose_vector_type(g->v_list, vece, oprsz, vece == MO_64); 3177 if (type) { 3178 const TCGOpcode *hold_list = tcg_swap_vecop_list(NULL); 3179 TCGv_vec v_shift = tcg_temp_new_vec(type); 3180 3181 if (vece == MO_64) { 3182 TCGv_i64 sh64 = tcg_temp_ebb_new_i64(); 3183 tcg_gen_extu_i32_i64(sh64, shift); 3184 tcg_gen_dup_i64_vec(MO_64, v_shift, sh64); 3185 tcg_temp_free_i64(sh64); 3186 } else { 3187 tcg_gen_dup_i32_vec(vece, v_shift, shift); 3188 } 3189 3190 switch (type) { 3191 case TCG_TYPE_V256: 3192 some = QEMU_ALIGN_DOWN(oprsz, 32); 3193 expand_2s_vec(vece, dofs, aofs, some, 32, TCG_TYPE_V256, 3194 v_shift, false, g->fniv_v); 3195 if (some == oprsz) { 3196 break; 3197 } 3198 dofs += some; 3199 aofs += some; 3200 oprsz -= some; 3201 maxsz -= some; 3202 /* fallthru */ 3203 case TCG_TYPE_V128: 3204 expand_2s_vec(vece, dofs, aofs, oprsz, 16, TCG_TYPE_V128, 3205 v_shift, false, g->fniv_v); 3206 break; 3207 case TCG_TYPE_V64: 3208 expand_2s_vec(vece, dofs, aofs, oprsz, 8, TCG_TYPE_V64, 3209 v_shift, false, g->fniv_v); 3210 break; 3211 default: 3212 g_assert_not_reached(); 3213 } 3214 tcg_temp_free_vec(v_shift); 3215 tcg_swap_vecop_list(hold_list); 3216 goto clear_tail; 3217 } 3218 3219 /* Otherwise fall back to integral... */ 3220 if (vece == MO_32 && check_size_impl(oprsz, 4)) { 3221 expand_2s_i32(dofs, aofs, oprsz, shift, false, g->fni4); 3222 } else if (vece == MO_64 && check_size_impl(oprsz, 8)) { 3223 TCGv_i64 sh64 = tcg_temp_ebb_new_i64(); 3224 tcg_gen_extu_i32_i64(sh64, shift); 3225 expand_2s_i64(dofs, aofs, oprsz, sh64, false, g->fni8); 3226 tcg_temp_free_i64(sh64); 3227 } else { 3228 TCGv_ptr a0 = tcg_temp_ebb_new_ptr(); 3229 TCGv_ptr a1 = tcg_temp_ebb_new_ptr(); 3230 TCGv_i32 desc = tcg_temp_ebb_new_i32(); 3231 3232 tcg_gen_shli_i32(desc, shift, SIMD_DATA_SHIFT); 3233 tcg_gen_ori_i32(desc, desc, simd_desc(oprsz, maxsz, 0)); 3234 tcg_gen_addi_ptr(a0, cpu_env, dofs); 3235 tcg_gen_addi_ptr(a1, cpu_env, aofs); 3236 3237 g->fno[vece](a0, a1, desc); 3238 3239 tcg_temp_free_ptr(a0); 3240 tcg_temp_free_ptr(a1); 3241 tcg_temp_free_i32(desc); 3242 return; 3243 } 3244 3245 clear_tail: 3246 if (oprsz < maxsz) { 3247 expand_clr(dofs + oprsz, maxsz - oprsz); 3248 } 3249 } 3250 3251 void tcg_gen_gvec_shls(unsigned vece, uint32_t dofs, uint32_t aofs, 3252 TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz) 3253 { 3254 static const GVecGen2sh g = { 3255 .fni4 = tcg_gen_shl_i32, 3256 .fni8 = tcg_gen_shl_i64, 3257 .fniv_s = tcg_gen_shls_vec, 3258 .fniv_v = tcg_gen_shlv_vec, 3259 .fno = { 3260 gen_helper_gvec_shl8i, 3261 gen_helper_gvec_shl16i, 3262 gen_helper_gvec_shl32i, 3263 gen_helper_gvec_shl64i, 3264 }, 3265 .s_list = { INDEX_op_shls_vec, 0 }, 3266 .v_list = { INDEX_op_shlv_vec, 0 }, 3267 }; 3268 3269 tcg_debug_assert(vece <= MO_64); 3270 do_gvec_shifts(vece, dofs, aofs, shift, oprsz, maxsz, &g); 3271 } 3272 3273 void tcg_gen_gvec_shrs(unsigned vece, uint32_t dofs, uint32_t aofs, 3274 TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz) 3275 { 3276 static const GVecGen2sh g = { 3277 .fni4 = tcg_gen_shr_i32, 3278 .fni8 = tcg_gen_shr_i64, 3279 .fniv_s = tcg_gen_shrs_vec, 3280 .fniv_v = tcg_gen_shrv_vec, 3281 .fno = { 3282 gen_helper_gvec_shr8i, 3283 gen_helper_gvec_shr16i, 3284 gen_helper_gvec_shr32i, 3285 gen_helper_gvec_shr64i, 3286 }, 3287 .s_list = { INDEX_op_shrs_vec, 0 }, 3288 .v_list = { INDEX_op_shrv_vec, 0 }, 3289 }; 3290 3291 tcg_debug_assert(vece <= MO_64); 3292 do_gvec_shifts(vece, dofs, aofs, shift, oprsz, maxsz, &g); 3293 } 3294 3295 void tcg_gen_gvec_sars(unsigned vece, uint32_t dofs, uint32_t aofs, 3296 TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz) 3297 { 3298 static const GVecGen2sh g = { 3299 .fni4 = tcg_gen_sar_i32, 3300 .fni8 = tcg_gen_sar_i64, 3301 .fniv_s = tcg_gen_sars_vec, 3302 .fniv_v = tcg_gen_sarv_vec, 3303 .fno = { 3304 gen_helper_gvec_sar8i, 3305 gen_helper_gvec_sar16i, 3306 gen_helper_gvec_sar32i, 3307 gen_helper_gvec_sar64i, 3308 }, 3309 .s_list = { INDEX_op_sars_vec, 0 }, 3310 .v_list = { INDEX_op_sarv_vec, 0 }, 3311 }; 3312 3313 tcg_debug_assert(vece <= MO_64); 3314 do_gvec_shifts(vece, dofs, aofs, shift, oprsz, maxsz, &g); 3315 } 3316 3317 void tcg_gen_gvec_rotls(unsigned vece, uint32_t dofs, uint32_t aofs, 3318 TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz) 3319 { 3320 static const GVecGen2sh g = { 3321 .fni4 = tcg_gen_rotl_i32, 3322 .fni8 = tcg_gen_rotl_i64, 3323 .fniv_s = tcg_gen_rotls_vec, 3324 .fniv_v = tcg_gen_rotlv_vec, 3325 .fno = { 3326 gen_helper_gvec_rotl8i, 3327 gen_helper_gvec_rotl16i, 3328 gen_helper_gvec_rotl32i, 3329 gen_helper_gvec_rotl64i, 3330 }, 3331 .s_list = { INDEX_op_rotls_vec, 0 }, 3332 .v_list = { INDEX_op_rotlv_vec, 0 }, 3333 }; 3334 3335 tcg_debug_assert(vece <= MO_64); 3336 do_gvec_shifts(vece, dofs, aofs, shift, oprsz, maxsz, &g); 3337 } 3338 3339 /* 3340 * Expand D = A << (B % element bits) 3341 * 3342 * Unlike scalar shifts, where it is easy for the target front end 3343 * to include the modulo as part of the expansion. If the target 3344 * naturally includes the modulo as part of the operation, great! 3345 * If the target has some other behaviour from out-of-range shifts, 3346 * then it could not use this function anyway, and would need to 3347 * do it's own expansion with custom functions. 3348 */ 3349 static void tcg_gen_shlv_mod_vec(unsigned vece, TCGv_vec d, 3350 TCGv_vec a, TCGv_vec b) 3351 { 3352 TCGv_vec t = tcg_temp_new_vec_matching(d); 3353 TCGv_vec m = tcg_constant_vec_matching(d, vece, (8 << vece) - 1); 3354 3355 tcg_gen_and_vec(vece, t, b, m); 3356 tcg_gen_shlv_vec(vece, d, a, t); 3357 tcg_temp_free_vec(t); 3358 } 3359 3360 static void tcg_gen_shl_mod_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) 3361 { 3362 TCGv_i32 t = tcg_temp_ebb_new_i32(); 3363 3364 tcg_gen_andi_i32(t, b, 31); 3365 tcg_gen_shl_i32(d, a, t); 3366 tcg_temp_free_i32(t); 3367 } 3368 3369 static void tcg_gen_shl_mod_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) 3370 { 3371 TCGv_i64 t = tcg_temp_ebb_new_i64(); 3372 3373 tcg_gen_andi_i64(t, b, 63); 3374 tcg_gen_shl_i64(d, a, t); 3375 tcg_temp_free_i64(t); 3376 } 3377 3378 void tcg_gen_gvec_shlv(unsigned vece, uint32_t dofs, uint32_t aofs, 3379 uint32_t bofs, uint32_t oprsz, uint32_t maxsz) 3380 { 3381 static const TCGOpcode vecop_list[] = { INDEX_op_shlv_vec, 0 }; 3382 static const GVecGen3 g[4] = { 3383 { .fniv = tcg_gen_shlv_mod_vec, 3384 .fno = gen_helper_gvec_shl8v, 3385 .opt_opc = vecop_list, 3386 .vece = MO_8 }, 3387 { .fniv = tcg_gen_shlv_mod_vec, 3388 .fno = gen_helper_gvec_shl16v, 3389 .opt_opc = vecop_list, 3390 .vece = MO_16 }, 3391 { .fni4 = tcg_gen_shl_mod_i32, 3392 .fniv = tcg_gen_shlv_mod_vec, 3393 .fno = gen_helper_gvec_shl32v, 3394 .opt_opc = vecop_list, 3395 .vece = MO_32 }, 3396 { .fni8 = tcg_gen_shl_mod_i64, 3397 .fniv = tcg_gen_shlv_mod_vec, 3398 .fno = gen_helper_gvec_shl64v, 3399 .opt_opc = vecop_list, 3400 .prefer_i64 = TCG_TARGET_REG_BITS == 64, 3401 .vece = MO_64 }, 3402 }; 3403 3404 tcg_debug_assert(vece <= MO_64); 3405 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); 3406 } 3407 3408 /* 3409 * Similarly for logical right shifts. 3410 */ 3411 3412 static void tcg_gen_shrv_mod_vec(unsigned vece, TCGv_vec d, 3413 TCGv_vec a, TCGv_vec b) 3414 { 3415 TCGv_vec t = tcg_temp_new_vec_matching(d); 3416 TCGv_vec m = tcg_constant_vec_matching(d, vece, (8 << vece) - 1); 3417 3418 tcg_gen_and_vec(vece, t, b, m); 3419 tcg_gen_shrv_vec(vece, d, a, t); 3420 tcg_temp_free_vec(t); 3421 } 3422 3423 static void tcg_gen_shr_mod_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) 3424 { 3425 TCGv_i32 t = tcg_temp_ebb_new_i32(); 3426 3427 tcg_gen_andi_i32(t, b, 31); 3428 tcg_gen_shr_i32(d, a, t); 3429 tcg_temp_free_i32(t); 3430 } 3431 3432 static void tcg_gen_shr_mod_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) 3433 { 3434 TCGv_i64 t = tcg_temp_ebb_new_i64(); 3435 3436 tcg_gen_andi_i64(t, b, 63); 3437 tcg_gen_shr_i64(d, a, t); 3438 tcg_temp_free_i64(t); 3439 } 3440 3441 void tcg_gen_gvec_shrv(unsigned vece, uint32_t dofs, uint32_t aofs, 3442 uint32_t bofs, uint32_t oprsz, uint32_t maxsz) 3443 { 3444 static const TCGOpcode vecop_list[] = { INDEX_op_shrv_vec, 0 }; 3445 static const GVecGen3 g[4] = { 3446 { .fniv = tcg_gen_shrv_mod_vec, 3447 .fno = gen_helper_gvec_shr8v, 3448 .opt_opc = vecop_list, 3449 .vece = MO_8 }, 3450 { .fniv = tcg_gen_shrv_mod_vec, 3451 .fno = gen_helper_gvec_shr16v, 3452 .opt_opc = vecop_list, 3453 .vece = MO_16 }, 3454 { .fni4 = tcg_gen_shr_mod_i32, 3455 .fniv = tcg_gen_shrv_mod_vec, 3456 .fno = gen_helper_gvec_shr32v, 3457 .opt_opc = vecop_list, 3458 .vece = MO_32 }, 3459 { .fni8 = tcg_gen_shr_mod_i64, 3460 .fniv = tcg_gen_shrv_mod_vec, 3461 .fno = gen_helper_gvec_shr64v, 3462 .opt_opc = vecop_list, 3463 .prefer_i64 = TCG_TARGET_REG_BITS == 64, 3464 .vece = MO_64 }, 3465 }; 3466 3467 tcg_debug_assert(vece <= MO_64); 3468 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); 3469 } 3470 3471 /* 3472 * Similarly for arithmetic right shifts. 3473 */ 3474 3475 static void tcg_gen_sarv_mod_vec(unsigned vece, TCGv_vec d, 3476 TCGv_vec a, TCGv_vec b) 3477 { 3478 TCGv_vec t = tcg_temp_new_vec_matching(d); 3479 TCGv_vec m = tcg_constant_vec_matching(d, vece, (8 << vece) - 1); 3480 3481 tcg_gen_and_vec(vece, t, b, m); 3482 tcg_gen_sarv_vec(vece, d, a, t); 3483 tcg_temp_free_vec(t); 3484 } 3485 3486 static void tcg_gen_sar_mod_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) 3487 { 3488 TCGv_i32 t = tcg_temp_ebb_new_i32(); 3489 3490 tcg_gen_andi_i32(t, b, 31); 3491 tcg_gen_sar_i32(d, a, t); 3492 tcg_temp_free_i32(t); 3493 } 3494 3495 static void tcg_gen_sar_mod_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) 3496 { 3497 TCGv_i64 t = tcg_temp_ebb_new_i64(); 3498 3499 tcg_gen_andi_i64(t, b, 63); 3500 tcg_gen_sar_i64(d, a, t); 3501 tcg_temp_free_i64(t); 3502 } 3503 3504 void tcg_gen_gvec_sarv(unsigned vece, uint32_t dofs, uint32_t aofs, 3505 uint32_t bofs, uint32_t oprsz, uint32_t maxsz) 3506 { 3507 static const TCGOpcode vecop_list[] = { INDEX_op_sarv_vec, 0 }; 3508 static const GVecGen3 g[4] = { 3509 { .fniv = tcg_gen_sarv_mod_vec, 3510 .fno = gen_helper_gvec_sar8v, 3511 .opt_opc = vecop_list, 3512 .vece = MO_8 }, 3513 { .fniv = tcg_gen_sarv_mod_vec, 3514 .fno = gen_helper_gvec_sar16v, 3515 .opt_opc = vecop_list, 3516 .vece = MO_16 }, 3517 { .fni4 = tcg_gen_sar_mod_i32, 3518 .fniv = tcg_gen_sarv_mod_vec, 3519 .fno = gen_helper_gvec_sar32v, 3520 .opt_opc = vecop_list, 3521 .vece = MO_32 }, 3522 { .fni8 = tcg_gen_sar_mod_i64, 3523 .fniv = tcg_gen_sarv_mod_vec, 3524 .fno = gen_helper_gvec_sar64v, 3525 .opt_opc = vecop_list, 3526 .prefer_i64 = TCG_TARGET_REG_BITS == 64, 3527 .vece = MO_64 }, 3528 }; 3529 3530 tcg_debug_assert(vece <= MO_64); 3531 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); 3532 } 3533 3534 /* 3535 * Similarly for rotates. 3536 */ 3537 3538 static void tcg_gen_rotlv_mod_vec(unsigned vece, TCGv_vec d, 3539 TCGv_vec a, TCGv_vec b) 3540 { 3541 TCGv_vec t = tcg_temp_new_vec_matching(d); 3542 TCGv_vec m = tcg_constant_vec_matching(d, vece, (8 << vece) - 1); 3543 3544 tcg_gen_and_vec(vece, t, b, m); 3545 tcg_gen_rotlv_vec(vece, d, a, t); 3546 tcg_temp_free_vec(t); 3547 } 3548 3549 static void tcg_gen_rotl_mod_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) 3550 { 3551 TCGv_i32 t = tcg_temp_ebb_new_i32(); 3552 3553 tcg_gen_andi_i32(t, b, 31); 3554 tcg_gen_rotl_i32(d, a, t); 3555 tcg_temp_free_i32(t); 3556 } 3557 3558 static void tcg_gen_rotl_mod_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) 3559 { 3560 TCGv_i64 t = tcg_temp_ebb_new_i64(); 3561 3562 tcg_gen_andi_i64(t, b, 63); 3563 tcg_gen_rotl_i64(d, a, t); 3564 tcg_temp_free_i64(t); 3565 } 3566 3567 void tcg_gen_gvec_rotlv(unsigned vece, uint32_t dofs, uint32_t aofs, 3568 uint32_t bofs, uint32_t oprsz, uint32_t maxsz) 3569 { 3570 static const TCGOpcode vecop_list[] = { INDEX_op_rotlv_vec, 0 }; 3571 static const GVecGen3 g[4] = { 3572 { .fniv = tcg_gen_rotlv_mod_vec, 3573 .fno = gen_helper_gvec_rotl8v, 3574 .opt_opc = vecop_list, 3575 .vece = MO_8 }, 3576 { .fniv = tcg_gen_rotlv_mod_vec, 3577 .fno = gen_helper_gvec_rotl16v, 3578 .opt_opc = vecop_list, 3579 .vece = MO_16 }, 3580 { .fni4 = tcg_gen_rotl_mod_i32, 3581 .fniv = tcg_gen_rotlv_mod_vec, 3582 .fno = gen_helper_gvec_rotl32v, 3583 .opt_opc = vecop_list, 3584 .vece = MO_32 }, 3585 { .fni8 = tcg_gen_rotl_mod_i64, 3586 .fniv = tcg_gen_rotlv_mod_vec, 3587 .fno = gen_helper_gvec_rotl64v, 3588 .opt_opc = vecop_list, 3589 .prefer_i64 = TCG_TARGET_REG_BITS == 64, 3590 .vece = MO_64 }, 3591 }; 3592 3593 tcg_debug_assert(vece <= MO_64); 3594 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); 3595 } 3596 3597 static void tcg_gen_rotrv_mod_vec(unsigned vece, TCGv_vec d, 3598 TCGv_vec a, TCGv_vec b) 3599 { 3600 TCGv_vec t = tcg_temp_new_vec_matching(d); 3601 TCGv_vec m = tcg_constant_vec_matching(d, vece, (8 << vece) - 1); 3602 3603 tcg_gen_and_vec(vece, t, b, m); 3604 tcg_gen_rotrv_vec(vece, d, a, t); 3605 tcg_temp_free_vec(t); 3606 } 3607 3608 static void tcg_gen_rotr_mod_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) 3609 { 3610 TCGv_i32 t = tcg_temp_ebb_new_i32(); 3611 3612 tcg_gen_andi_i32(t, b, 31); 3613 tcg_gen_rotr_i32(d, a, t); 3614 tcg_temp_free_i32(t); 3615 } 3616 3617 static void tcg_gen_rotr_mod_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) 3618 { 3619 TCGv_i64 t = tcg_temp_ebb_new_i64(); 3620 3621 tcg_gen_andi_i64(t, b, 63); 3622 tcg_gen_rotr_i64(d, a, t); 3623 tcg_temp_free_i64(t); 3624 } 3625 3626 void tcg_gen_gvec_rotrv(unsigned vece, uint32_t dofs, uint32_t aofs, 3627 uint32_t bofs, uint32_t oprsz, uint32_t maxsz) 3628 { 3629 static const TCGOpcode vecop_list[] = { INDEX_op_rotrv_vec, 0 }; 3630 static const GVecGen3 g[4] = { 3631 { .fniv = tcg_gen_rotrv_mod_vec, 3632 .fno = gen_helper_gvec_rotr8v, 3633 .opt_opc = vecop_list, 3634 .vece = MO_8 }, 3635 { .fniv = tcg_gen_rotrv_mod_vec, 3636 .fno = gen_helper_gvec_rotr16v, 3637 .opt_opc = vecop_list, 3638 .vece = MO_16 }, 3639 { .fni4 = tcg_gen_rotr_mod_i32, 3640 .fniv = tcg_gen_rotrv_mod_vec, 3641 .fno = gen_helper_gvec_rotr32v, 3642 .opt_opc = vecop_list, 3643 .vece = MO_32 }, 3644 { .fni8 = tcg_gen_rotr_mod_i64, 3645 .fniv = tcg_gen_rotrv_mod_vec, 3646 .fno = gen_helper_gvec_rotr64v, 3647 .opt_opc = vecop_list, 3648 .prefer_i64 = TCG_TARGET_REG_BITS == 64, 3649 .vece = MO_64 }, 3650 }; 3651 3652 tcg_debug_assert(vece <= MO_64); 3653 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); 3654 } 3655 3656 /* Expand OPSZ bytes worth of three-operand operations using i32 elements. */ 3657 static void expand_cmp_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs, 3658 uint32_t oprsz, TCGCond cond) 3659 { 3660 TCGv_i32 t0 = tcg_temp_ebb_new_i32(); 3661 TCGv_i32 t1 = tcg_temp_ebb_new_i32(); 3662 uint32_t i; 3663 3664 for (i = 0; i < oprsz; i += 4) { 3665 tcg_gen_ld_i32(t0, cpu_env, aofs + i); 3666 tcg_gen_ld_i32(t1, cpu_env, bofs + i); 3667 tcg_gen_setcond_i32(cond, t0, t0, t1); 3668 tcg_gen_neg_i32(t0, t0); 3669 tcg_gen_st_i32(t0, cpu_env, dofs + i); 3670 } 3671 tcg_temp_free_i32(t1); 3672 tcg_temp_free_i32(t0); 3673 } 3674 3675 static void expand_cmp_i64(uint32_t dofs, uint32_t aofs, uint32_t bofs, 3676 uint32_t oprsz, TCGCond cond) 3677 { 3678 TCGv_i64 t0 = tcg_temp_ebb_new_i64(); 3679 TCGv_i64 t1 = tcg_temp_ebb_new_i64(); 3680 uint32_t i; 3681 3682 for (i = 0; i < oprsz; i += 8) { 3683 tcg_gen_ld_i64(t0, cpu_env, aofs + i); 3684 tcg_gen_ld_i64(t1, cpu_env, bofs + i); 3685 tcg_gen_setcond_i64(cond, t0, t0, t1); 3686 tcg_gen_neg_i64(t0, t0); 3687 tcg_gen_st_i64(t0, cpu_env, dofs + i); 3688 } 3689 tcg_temp_free_i64(t1); 3690 tcg_temp_free_i64(t0); 3691 } 3692 3693 static void expand_cmp_vec(unsigned vece, uint32_t dofs, uint32_t aofs, 3694 uint32_t bofs, uint32_t oprsz, uint32_t tysz, 3695 TCGType type, TCGCond cond) 3696 { 3697 TCGv_vec t0 = tcg_temp_new_vec(type); 3698 TCGv_vec t1 = tcg_temp_new_vec(type); 3699 uint32_t i; 3700 3701 for (i = 0; i < oprsz; i += tysz) { 3702 tcg_gen_ld_vec(t0, cpu_env, aofs + i); 3703 tcg_gen_ld_vec(t1, cpu_env, bofs + i); 3704 tcg_gen_cmp_vec(cond, vece, t0, t0, t1); 3705 tcg_gen_st_vec(t0, cpu_env, dofs + i); 3706 } 3707 tcg_temp_free_vec(t1); 3708 tcg_temp_free_vec(t0); 3709 } 3710 3711 void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs, 3712 uint32_t aofs, uint32_t bofs, 3713 uint32_t oprsz, uint32_t maxsz) 3714 { 3715 static const TCGOpcode cmp_list[] = { INDEX_op_cmp_vec, 0 }; 3716 static gen_helper_gvec_3 * const eq_fn[4] = { 3717 gen_helper_gvec_eq8, gen_helper_gvec_eq16, 3718 gen_helper_gvec_eq32, gen_helper_gvec_eq64 3719 }; 3720 static gen_helper_gvec_3 * const ne_fn[4] = { 3721 gen_helper_gvec_ne8, gen_helper_gvec_ne16, 3722 gen_helper_gvec_ne32, gen_helper_gvec_ne64 3723 }; 3724 static gen_helper_gvec_3 * const lt_fn[4] = { 3725 gen_helper_gvec_lt8, gen_helper_gvec_lt16, 3726 gen_helper_gvec_lt32, gen_helper_gvec_lt64 3727 }; 3728 static gen_helper_gvec_3 * const le_fn[4] = { 3729 gen_helper_gvec_le8, gen_helper_gvec_le16, 3730 gen_helper_gvec_le32, gen_helper_gvec_le64 3731 }; 3732 static gen_helper_gvec_3 * const ltu_fn[4] = { 3733 gen_helper_gvec_ltu8, gen_helper_gvec_ltu16, 3734 gen_helper_gvec_ltu32, gen_helper_gvec_ltu64 3735 }; 3736 static gen_helper_gvec_3 * const leu_fn[4] = { 3737 gen_helper_gvec_leu8, gen_helper_gvec_leu16, 3738 gen_helper_gvec_leu32, gen_helper_gvec_leu64 3739 }; 3740 static gen_helper_gvec_3 * const * const fns[16] = { 3741 [TCG_COND_EQ] = eq_fn, 3742 [TCG_COND_NE] = ne_fn, 3743 [TCG_COND_LT] = lt_fn, 3744 [TCG_COND_LE] = le_fn, 3745 [TCG_COND_LTU] = ltu_fn, 3746 [TCG_COND_LEU] = leu_fn, 3747 }; 3748 3749 const TCGOpcode *hold_list; 3750 TCGType type; 3751 uint32_t some; 3752 3753 check_size_align(oprsz, maxsz, dofs | aofs | bofs); 3754 check_overlap_3(dofs, aofs, bofs, maxsz); 3755 3756 if (cond == TCG_COND_NEVER || cond == TCG_COND_ALWAYS) { 3757 do_dup(MO_8, dofs, oprsz, maxsz, 3758 NULL, NULL, -(cond == TCG_COND_ALWAYS)); 3759 return; 3760 } 3761 3762 /* 3763 * Implement inline with a vector type, if possible. 3764 * Prefer integer when 64-bit host and 64-bit comparison. 3765 */ 3766 hold_list = tcg_swap_vecop_list(cmp_list); 3767 type = choose_vector_type(cmp_list, vece, oprsz, 3768 TCG_TARGET_REG_BITS == 64 && vece == MO_64); 3769 switch (type) { 3770 case TCG_TYPE_V256: 3771 /* Recall that ARM SVE allows vector sizes that are not a 3772 * power of 2, but always a multiple of 16. The intent is 3773 * that e.g. size == 80 would be expanded with 2x32 + 1x16. 3774 */ 3775 some = QEMU_ALIGN_DOWN(oprsz, 32); 3776 expand_cmp_vec(vece, dofs, aofs, bofs, some, 32, TCG_TYPE_V256, cond); 3777 if (some == oprsz) { 3778 break; 3779 } 3780 dofs += some; 3781 aofs += some; 3782 bofs += some; 3783 oprsz -= some; 3784 maxsz -= some; 3785 /* fallthru */ 3786 case TCG_TYPE_V128: 3787 expand_cmp_vec(vece, dofs, aofs, bofs, oprsz, 16, TCG_TYPE_V128, cond); 3788 break; 3789 case TCG_TYPE_V64: 3790 expand_cmp_vec(vece, dofs, aofs, bofs, oprsz, 8, TCG_TYPE_V64, cond); 3791 break; 3792 3793 case 0: 3794 if (vece == MO_64 && check_size_impl(oprsz, 8)) { 3795 expand_cmp_i64(dofs, aofs, bofs, oprsz, cond); 3796 } else if (vece == MO_32 && check_size_impl(oprsz, 4)) { 3797 expand_cmp_i32(dofs, aofs, bofs, oprsz, cond); 3798 } else { 3799 gen_helper_gvec_3 * const *fn = fns[cond]; 3800 3801 if (fn == NULL) { 3802 uint32_t tmp; 3803 tmp = aofs, aofs = bofs, bofs = tmp; 3804 cond = tcg_swap_cond(cond); 3805 fn = fns[cond]; 3806 assert(fn != NULL); 3807 } 3808 tcg_gen_gvec_3_ool(dofs, aofs, bofs, oprsz, maxsz, 0, fn[vece]); 3809 oprsz = maxsz; 3810 } 3811 break; 3812 3813 default: 3814 g_assert_not_reached(); 3815 } 3816 tcg_swap_vecop_list(hold_list); 3817 3818 if (oprsz < maxsz) { 3819 expand_clr(dofs + oprsz, maxsz - oprsz); 3820 } 3821 } 3822 3823 static void tcg_gen_bitsel_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, TCGv_i64 c) 3824 { 3825 TCGv_i64 t = tcg_temp_ebb_new_i64(); 3826 3827 tcg_gen_and_i64(t, b, a); 3828 tcg_gen_andc_i64(d, c, a); 3829 tcg_gen_or_i64(d, d, t); 3830 tcg_temp_free_i64(t); 3831 } 3832 3833 void tcg_gen_gvec_bitsel(unsigned vece, uint32_t dofs, uint32_t aofs, 3834 uint32_t bofs, uint32_t cofs, 3835 uint32_t oprsz, uint32_t maxsz) 3836 { 3837 static const GVecGen4 g = { 3838 .fni8 = tcg_gen_bitsel_i64, 3839 .fniv = tcg_gen_bitsel_vec, 3840 .fno = gen_helper_gvec_bitsel, 3841 }; 3842 3843 tcg_gen_gvec_4(dofs, aofs, bofs, cofs, oprsz, maxsz, &g); 3844 } 3845