1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25/* We only support generating code for 64-bit mode. */ 26#ifndef __arch64__ 27#error "unsupported code generation mode" 28#endif 29 30/* Used for function call generation. */ 31#define TCG_REG_CALL_STACK TCG_REG_O6 32#define TCG_TARGET_STACK_BIAS 2047 33#define TCG_TARGET_STACK_ALIGN 16 34#define TCG_TARGET_CALL_STACK_OFFSET (128 + 6 * 8 + TCG_TARGET_STACK_BIAS) 35#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EXTEND 36#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL 37#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL 38#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL 39 40#ifdef CONFIG_DEBUG_TCG 41static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 42 "%g0", 43 "%g1", 44 "%g2", 45 "%g3", 46 "%g4", 47 "%g5", 48 "%g6", 49 "%g7", 50 "%o0", 51 "%o1", 52 "%o2", 53 "%o3", 54 "%o4", 55 "%o5", 56 "%o6", 57 "%o7", 58 "%l0", 59 "%l1", 60 "%l2", 61 "%l3", 62 "%l4", 63 "%l5", 64 "%l6", 65 "%l7", 66 "%i0", 67 "%i1", 68 "%i2", 69 "%i3", 70 "%i4", 71 "%i5", 72 "%i6", 73 "%i7", 74}; 75#endif 76 77#define TCG_CT_CONST_S11 0x100 78#define TCG_CT_CONST_S13 0x200 79#define TCG_CT_CONST_ZERO 0x400 80 81#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) 82 83/* Define some temporary registers. T3 is used for constant generation. */ 84#define TCG_REG_T1 TCG_REG_G1 85#define TCG_REG_T2 TCG_REG_G2 86#define TCG_REG_T3 TCG_REG_O7 87 88#ifndef CONFIG_SOFTMMU 89# define TCG_GUEST_BASE_REG TCG_REG_I5 90#endif 91 92#define TCG_REG_TB TCG_REG_I1 93 94static const int tcg_target_reg_alloc_order[] = { 95 TCG_REG_L0, 96 TCG_REG_L1, 97 TCG_REG_L2, 98 TCG_REG_L3, 99 TCG_REG_L4, 100 TCG_REG_L5, 101 TCG_REG_L6, 102 TCG_REG_L7, 103 104 TCG_REG_I0, 105 TCG_REG_I1, 106 TCG_REG_I2, 107 TCG_REG_I3, 108 TCG_REG_I4, 109 TCG_REG_I5, 110 111 TCG_REG_G3, 112 TCG_REG_G4, 113 TCG_REG_G5, 114 115 TCG_REG_O0, 116 TCG_REG_O1, 117 TCG_REG_O2, 118 TCG_REG_O3, 119 TCG_REG_O4, 120 TCG_REG_O5, 121}; 122 123static const int tcg_target_call_iarg_regs[6] = { 124 TCG_REG_O0, 125 TCG_REG_O1, 126 TCG_REG_O2, 127 TCG_REG_O3, 128 TCG_REG_O4, 129 TCG_REG_O5, 130}; 131 132static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 133{ 134 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 135 tcg_debug_assert(slot >= 0 && slot <= 3); 136 return TCG_REG_O0 + slot; 137} 138 139#define INSN_OP(x) ((x) << 30) 140#define INSN_OP2(x) ((x) << 22) 141#define INSN_OP3(x) ((x) << 19) 142#define INSN_OPF(x) ((x) << 5) 143#define INSN_RD(x) ((x) << 25) 144#define INSN_RS1(x) ((x) << 14) 145#define INSN_RS2(x) (x) 146#define INSN_ASI(x) ((x) << 5) 147 148#define INSN_IMM10(x) ((1 << 13) | ((x) & 0x3ff)) 149#define INSN_IMM11(x) ((1 << 13) | ((x) & 0x7ff)) 150#define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff)) 151#define INSN_OFF16(x) ((((x) >> 2) & 0x3fff) | ((((x) >> 16) & 3) << 20)) 152#define INSN_OFF19(x) (((x) >> 2) & 0x07ffff) 153#define INSN_COND(x) ((x) << 25) 154 155#define COND_N 0x0 156#define COND_E 0x1 157#define COND_LE 0x2 158#define COND_L 0x3 159#define COND_LEU 0x4 160#define COND_CS 0x5 161#define COND_NEG 0x6 162#define COND_VS 0x7 163#define COND_A 0x8 164#define COND_NE 0x9 165#define COND_G 0xa 166#define COND_GE 0xb 167#define COND_GU 0xc 168#define COND_CC 0xd 169#define COND_POS 0xe 170#define COND_VC 0xf 171#define BA (INSN_OP(0) | INSN_COND(COND_A) | INSN_OP2(0x2)) 172 173#define RCOND_Z 1 174#define RCOND_LEZ 2 175#define RCOND_LZ 3 176#define RCOND_NZ 5 177#define RCOND_GZ 6 178#define RCOND_GEZ 7 179 180#define MOVCC_ICC (1 << 18) 181#define MOVCC_XCC (1 << 18 | 1 << 12) 182 183#define BPCC_ICC 0 184#define BPCC_XCC (2 << 20) 185#define BPCC_PT (1 << 19) 186#define BPCC_PN 0 187#define BPCC_A (1 << 29) 188 189#define BPR_PT BPCC_PT 190 191#define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00)) 192#define ARITH_ADDCC (INSN_OP(2) | INSN_OP3(0x10)) 193#define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01)) 194#define ARITH_ANDCC (INSN_OP(2) | INSN_OP3(0x11)) 195#define ARITH_ANDN (INSN_OP(2) | INSN_OP3(0x05)) 196#define ARITH_OR (INSN_OP(2) | INSN_OP3(0x02)) 197#define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12)) 198#define ARITH_ORN (INSN_OP(2) | INSN_OP3(0x06)) 199#define ARITH_XOR (INSN_OP(2) | INSN_OP3(0x03)) 200#define ARITH_SUB (INSN_OP(2) | INSN_OP3(0x04)) 201#define ARITH_SUBCC (INSN_OP(2) | INSN_OP3(0x14)) 202#define ARITH_ADDC (INSN_OP(2) | INSN_OP3(0x08)) 203#define ARITH_SUBC (INSN_OP(2) | INSN_OP3(0x0c)) 204#define ARITH_UMUL (INSN_OP(2) | INSN_OP3(0x0a)) 205#define ARITH_SMUL (INSN_OP(2) | INSN_OP3(0x0b)) 206#define ARITH_UDIV (INSN_OP(2) | INSN_OP3(0x0e)) 207#define ARITH_SDIV (INSN_OP(2) | INSN_OP3(0x0f)) 208#define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09)) 209#define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d)) 210#define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d)) 211#define ARITH_MOVCC (INSN_OP(2) | INSN_OP3(0x2c)) 212#define ARITH_MOVR (INSN_OP(2) | INSN_OP3(0x2f)) 213 214#define ARITH_ADDXC (INSN_OP(2) | INSN_OP3(0x36) | INSN_OPF(0x11)) 215#define ARITH_UMULXHI (INSN_OP(2) | INSN_OP3(0x36) | INSN_OPF(0x16)) 216 217#define SHIFT_SLL (INSN_OP(2) | INSN_OP3(0x25)) 218#define SHIFT_SRL (INSN_OP(2) | INSN_OP3(0x26)) 219#define SHIFT_SRA (INSN_OP(2) | INSN_OP3(0x27)) 220 221#define SHIFT_SLLX (INSN_OP(2) | INSN_OP3(0x25) | (1 << 12)) 222#define SHIFT_SRLX (INSN_OP(2) | INSN_OP3(0x26) | (1 << 12)) 223#define SHIFT_SRAX (INSN_OP(2) | INSN_OP3(0x27) | (1 << 12)) 224 225#define RDY (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(0)) 226#define WRY (INSN_OP(2) | INSN_OP3(0x30) | INSN_RD(0)) 227#define JMPL (INSN_OP(2) | INSN_OP3(0x38)) 228#define RETURN (INSN_OP(2) | INSN_OP3(0x39)) 229#define SAVE (INSN_OP(2) | INSN_OP3(0x3c)) 230#define RESTORE (INSN_OP(2) | INSN_OP3(0x3d)) 231#define SETHI (INSN_OP(0) | INSN_OP2(0x4)) 232#define CALL INSN_OP(1) 233#define LDUB (INSN_OP(3) | INSN_OP3(0x01)) 234#define LDSB (INSN_OP(3) | INSN_OP3(0x09)) 235#define LDUH (INSN_OP(3) | INSN_OP3(0x02)) 236#define LDSH (INSN_OP(3) | INSN_OP3(0x0a)) 237#define LDUW (INSN_OP(3) | INSN_OP3(0x00)) 238#define LDSW (INSN_OP(3) | INSN_OP3(0x08)) 239#define LDX (INSN_OP(3) | INSN_OP3(0x0b)) 240#define STB (INSN_OP(3) | INSN_OP3(0x05)) 241#define STH (INSN_OP(3) | INSN_OP3(0x06)) 242#define STW (INSN_OP(3) | INSN_OP3(0x04)) 243#define STX (INSN_OP(3) | INSN_OP3(0x0e)) 244#define LDUBA (INSN_OP(3) | INSN_OP3(0x11)) 245#define LDSBA (INSN_OP(3) | INSN_OP3(0x19)) 246#define LDUHA (INSN_OP(3) | INSN_OP3(0x12)) 247#define LDSHA (INSN_OP(3) | INSN_OP3(0x1a)) 248#define LDUWA (INSN_OP(3) | INSN_OP3(0x10)) 249#define LDSWA (INSN_OP(3) | INSN_OP3(0x18)) 250#define LDXA (INSN_OP(3) | INSN_OP3(0x1b)) 251#define STBA (INSN_OP(3) | INSN_OP3(0x15)) 252#define STHA (INSN_OP(3) | INSN_OP3(0x16)) 253#define STWA (INSN_OP(3) | INSN_OP3(0x14)) 254#define STXA (INSN_OP(3) | INSN_OP3(0x1e)) 255 256#define MEMBAR (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(15) | (1 << 13)) 257 258#define NOP (SETHI | INSN_RD(TCG_REG_G0) | 0) 259 260#ifndef ASI_PRIMARY_LITTLE 261#define ASI_PRIMARY_LITTLE 0x88 262#endif 263 264#define LDUH_LE (LDUHA | INSN_ASI(ASI_PRIMARY_LITTLE)) 265#define LDSH_LE (LDSHA | INSN_ASI(ASI_PRIMARY_LITTLE)) 266#define LDUW_LE (LDUWA | INSN_ASI(ASI_PRIMARY_LITTLE)) 267#define LDSW_LE (LDSWA | INSN_ASI(ASI_PRIMARY_LITTLE)) 268#define LDX_LE (LDXA | INSN_ASI(ASI_PRIMARY_LITTLE)) 269 270#define STH_LE (STHA | INSN_ASI(ASI_PRIMARY_LITTLE)) 271#define STW_LE (STWA | INSN_ASI(ASI_PRIMARY_LITTLE)) 272#define STX_LE (STXA | INSN_ASI(ASI_PRIMARY_LITTLE)) 273 274#ifndef use_vis3_instructions 275bool use_vis3_instructions; 276#endif 277 278static bool check_fit_i64(int64_t val, unsigned int bits) 279{ 280 return val == sextract64(val, 0, bits); 281} 282 283static bool check_fit_i32(int32_t val, unsigned int bits) 284{ 285 return val == sextract32(val, 0, bits); 286} 287 288#define check_fit_tl check_fit_i64 289#define check_fit_ptr check_fit_i64 290 291static bool patch_reloc(tcg_insn_unit *src_rw, int type, 292 intptr_t value, intptr_t addend) 293{ 294 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 295 uint32_t insn = *src_rw; 296 intptr_t pcrel; 297 298 value += addend; 299 pcrel = tcg_ptr_byte_diff((tcg_insn_unit *)value, src_rx); 300 301 switch (type) { 302 case R_SPARC_WDISP16: 303 if (!check_fit_ptr(pcrel >> 2, 16)) { 304 return false; 305 } 306 insn &= ~INSN_OFF16(-1); 307 insn |= INSN_OFF16(pcrel); 308 break; 309 case R_SPARC_WDISP19: 310 if (!check_fit_ptr(pcrel >> 2, 19)) { 311 return false; 312 } 313 insn &= ~INSN_OFF19(-1); 314 insn |= INSN_OFF19(pcrel); 315 break; 316 case R_SPARC_13: 317 if (!check_fit_ptr(value, 13)) { 318 return false; 319 } 320 insn &= ~INSN_IMM13(-1); 321 insn |= INSN_IMM13(value); 322 break; 323 default: 324 g_assert_not_reached(); 325 } 326 327 *src_rw = insn; 328 return true; 329} 330 331/* test if a constant matches the constraint */ 332static bool tcg_target_const_match(int64_t val, int ct, 333 TCGType type, TCGCond cond, int vece) 334{ 335 if (ct & TCG_CT_CONST) { 336 return 1; 337 } 338 339 if (type == TCG_TYPE_I32) { 340 val = (int32_t)val; 341 } 342 343 if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 344 return 1; 345 } else if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11)) { 346 return 1; 347 } else if ((ct & TCG_CT_CONST_S13) && check_fit_tl(val, 13)) { 348 return 1; 349 } else { 350 return 0; 351 } 352} 353 354static void tcg_out_nop(TCGContext *s) 355{ 356 tcg_out32(s, NOP); 357} 358 359static void tcg_out_arith(TCGContext *s, TCGReg rd, TCGReg rs1, 360 TCGReg rs2, int op) 361{ 362 tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | INSN_RS2(rs2)); 363} 364 365static void tcg_out_arithi(TCGContext *s, TCGReg rd, TCGReg rs1, 366 int32_t offset, int op) 367{ 368 tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | INSN_IMM13(offset)); 369} 370 371static void tcg_out_arithc(TCGContext *s, TCGReg rd, TCGReg rs1, 372 int32_t val2, int val2const, int op) 373{ 374 tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) 375 | (val2const ? INSN_IMM13(val2) : INSN_RS2(val2))); 376} 377 378static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 379{ 380 if (ret != arg) { 381 tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR); 382 } 383 return true; 384} 385 386static void tcg_out_mov_delay(TCGContext *s, TCGReg ret, TCGReg arg) 387{ 388 if (ret != arg) { 389 tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR); 390 } else { 391 tcg_out_nop(s); 392 } 393} 394 395static void tcg_out_sethi(TCGContext *s, TCGReg ret, uint32_t arg) 396{ 397 tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10)); 398} 399 400/* A 13-bit constant sign-extended to 64 bits. */ 401static void tcg_out_movi_s13(TCGContext *s, TCGReg ret, int32_t arg) 402{ 403 tcg_out_arithi(s, ret, TCG_REG_G0, arg, ARITH_OR); 404} 405 406/* A 32-bit constant sign-extended to 64 bits. */ 407static void tcg_out_movi_s32(TCGContext *s, TCGReg ret, int32_t arg) 408{ 409 tcg_out_sethi(s, ret, ~arg); 410 tcg_out_arithi(s, ret, ret, (arg & 0x3ff) | -0x400, ARITH_XOR); 411} 412 413/* A 32-bit constant zero-extended to 64 bits. */ 414static void tcg_out_movi_u32(TCGContext *s, TCGReg ret, uint32_t arg) 415{ 416 tcg_out_sethi(s, ret, arg); 417 if (arg & 0x3ff) { 418 tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR); 419 } 420} 421 422static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, 423 tcg_target_long arg, bool in_prologue, 424 TCGReg scratch) 425{ 426 tcg_target_long hi, lo = (int32_t)arg; 427 tcg_target_long test, lsb; 428 429 /* A 13-bit constant sign-extended to 64-bits. */ 430 if (check_fit_tl(arg, 13)) { 431 tcg_out_movi_s13(s, ret, arg); 432 return; 433 } 434 435 /* A 32-bit constant, or 32-bit zero-extended to 64-bits. */ 436 if (type == TCG_TYPE_I32 || arg == (uint32_t)arg) { 437 tcg_out_movi_u32(s, ret, arg); 438 return; 439 } 440 441 /* A 13-bit constant relative to the TB. */ 442 if (!in_prologue) { 443 test = tcg_tbrel_diff(s, (void *)arg); 444 if (check_fit_ptr(test, 13)) { 445 tcg_out_arithi(s, ret, TCG_REG_TB, test, ARITH_ADD); 446 return; 447 } 448 } 449 450 /* A 32-bit constant sign-extended to 64-bits. */ 451 if (arg == lo) { 452 tcg_out_movi_s32(s, ret, arg); 453 return; 454 } 455 456 /* A 32-bit constant, shifted. */ 457 lsb = ctz64(arg); 458 test = (tcg_target_long)arg >> lsb; 459 if (lsb > 10 && test == extract64(test, 0, 21)) { 460 tcg_out_sethi(s, ret, test << 10); 461 tcg_out_arithi(s, ret, ret, lsb - 10, SHIFT_SLLX); 462 return; 463 } else if (test == (uint32_t)test || test == (int32_t)test) { 464 tcg_out_movi_int(s, TCG_TYPE_I64, ret, test, in_prologue, scratch); 465 tcg_out_arithi(s, ret, ret, lsb, SHIFT_SLLX); 466 return; 467 } 468 469 /* Use the constant pool, if possible. */ 470 if (!in_prologue) { 471 new_pool_label(s, arg, R_SPARC_13, s->code_ptr, 472 tcg_tbrel_diff(s, NULL)); 473 tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(TCG_REG_TB)); 474 return; 475 } 476 477 /* A 64-bit constant decomposed into 2 32-bit pieces. */ 478 if (check_fit_i32(lo, 13)) { 479 hi = (arg - lo) >> 32; 480 tcg_out_movi_u32(s, ret, hi); 481 tcg_out_arithi(s, ret, ret, 32, SHIFT_SLLX); 482 tcg_out_arithi(s, ret, ret, lo, ARITH_ADD); 483 } else { 484 hi = arg >> 32; 485 tcg_out_movi_u32(s, ret, hi); 486 tcg_out_movi_u32(s, scratch, lo); 487 tcg_out_arithi(s, ret, ret, 32, SHIFT_SLLX); 488 tcg_out_arith(s, ret, ret, scratch, ARITH_OR); 489 } 490} 491 492static void tcg_out_movi(TCGContext *s, TCGType type, 493 TCGReg ret, tcg_target_long arg) 494{ 495 tcg_debug_assert(ret != TCG_REG_T3); 496 tcg_out_movi_int(s, type, ret, arg, false, TCG_REG_T3); 497} 498 499static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) 500{ 501 g_assert_not_reached(); 502} 503 504static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) 505{ 506 g_assert_not_reached(); 507} 508 509static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rs) 510{ 511 tcg_out_arithi(s, rd, rs, 0xff, ARITH_AND); 512} 513 514static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rs) 515{ 516 tcg_out_arithi(s, rd, rs, 16, SHIFT_SLL); 517 tcg_out_arithi(s, rd, rd, 16, SHIFT_SRL); 518} 519 520static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rs) 521{ 522 tcg_out_arithi(s, rd, rs, 0, SHIFT_SRA); 523} 524 525static void tcg_out_ext32u(TCGContext *s, TCGReg rd, TCGReg rs) 526{ 527 tcg_out_arithi(s, rd, rs, 0, SHIFT_SRL); 528} 529 530static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) 531{ 532 tcg_out_ext32s(s, rd, rs); 533} 534 535static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) 536{ 537 tcg_out_ext32u(s, rd, rs); 538} 539 540static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rs) 541{ 542 tcg_out_ext32u(s, rd, rs); 543} 544 545static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 546{ 547 return false; 548} 549 550static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 551 tcg_target_long imm) 552{ 553 /* This function is only used for passing structs by reference. */ 554 g_assert_not_reached(); 555} 556 557static void tcg_out_ldst_rr(TCGContext *s, TCGReg data, TCGReg a1, 558 TCGReg a2, int op) 559{ 560 tcg_out32(s, op | INSN_RD(data) | INSN_RS1(a1) | INSN_RS2(a2)); 561} 562 563static void tcg_out_ldst(TCGContext *s, TCGReg ret, TCGReg addr, 564 intptr_t offset, int op) 565{ 566 if (check_fit_ptr(offset, 13)) { 567 tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(addr) | 568 INSN_IMM13(offset)); 569 } else { 570 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, offset); 571 tcg_out_ldst_rr(s, ret, addr, TCG_REG_T1, op); 572 } 573} 574 575static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, 576 TCGReg arg1, intptr_t arg2) 577{ 578 tcg_out_ldst(s, ret, arg1, arg2, (type == TCG_TYPE_I32 ? LDUW : LDX)); 579} 580 581static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 582 TCGReg arg1, intptr_t arg2) 583{ 584 tcg_out_ldst(s, arg, arg1, arg2, (type == TCG_TYPE_I32 ? STW : STX)); 585} 586 587static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 588 TCGReg base, intptr_t ofs) 589{ 590 if (val == 0) { 591 tcg_out_st(s, type, TCG_REG_G0, base, ofs); 592 return true; 593 } 594 return false; 595} 596 597static void tcg_out_sety(TCGContext *s, TCGReg rs) 598{ 599 tcg_out32(s, WRY | INSN_RS1(TCG_REG_G0) | INSN_RS2(rs)); 600} 601 602static void tcg_out_div32(TCGContext *s, TCGReg rd, TCGReg rs1, 603 int32_t val2, int val2const, int uns) 604{ 605 /* Load Y with the sign/zero extension of RS1 to 64-bits. */ 606 if (uns) { 607 tcg_out_sety(s, TCG_REG_G0); 608 } else { 609 tcg_out_arithi(s, TCG_REG_T1, rs1, 31, SHIFT_SRA); 610 tcg_out_sety(s, TCG_REG_T1); 611 } 612 613 tcg_out_arithc(s, rd, rs1, val2, val2const, 614 uns ? ARITH_UDIV : ARITH_SDIV); 615} 616 617static const uint8_t tcg_cond_to_bcond[16] = { 618 [TCG_COND_EQ] = COND_E, 619 [TCG_COND_NE] = COND_NE, 620 [TCG_COND_TSTEQ] = COND_E, 621 [TCG_COND_TSTNE] = COND_NE, 622 [TCG_COND_LT] = COND_L, 623 [TCG_COND_GE] = COND_GE, 624 [TCG_COND_LE] = COND_LE, 625 [TCG_COND_GT] = COND_G, 626 [TCG_COND_LTU] = COND_CS, 627 [TCG_COND_GEU] = COND_CC, 628 [TCG_COND_LEU] = COND_LEU, 629 [TCG_COND_GTU] = COND_GU, 630}; 631 632static const uint8_t tcg_cond_to_rcond[16] = { 633 [TCG_COND_EQ] = RCOND_Z, 634 [TCG_COND_NE] = RCOND_NZ, 635 [TCG_COND_LT] = RCOND_LZ, 636 [TCG_COND_GT] = RCOND_GZ, 637 [TCG_COND_LE] = RCOND_LEZ, 638 [TCG_COND_GE] = RCOND_GEZ 639}; 640 641static void tcg_out_bpcc0(TCGContext *s, int scond, int flags, int off19) 642{ 643 tcg_out32(s, INSN_OP(0) | INSN_OP2(1) | INSN_COND(scond) | flags | off19); 644} 645 646static void tcg_out_bpcc(TCGContext *s, int scond, int flags, TCGLabel *l) 647{ 648 int off19 = 0; 649 650 if (l->has_value) { 651 off19 = INSN_OFF19(tcg_pcrel_diff(s, l->u.value_ptr)); 652 } else { 653 tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP19, l, 0); 654 } 655 tcg_out_bpcc0(s, scond, flags, off19); 656} 657 658static void tcg_out_cmp(TCGContext *s, TCGCond cond, 659 TCGReg c1, int32_t c2, int c2const) 660{ 661 tcg_out_arithc(s, TCG_REG_G0, c1, c2, c2const, 662 is_tst_cond(cond) ? ARITH_ANDCC : ARITH_SUBCC); 663} 664 665static void tcg_out_brcond_i32(TCGContext *s, TCGCond cond, TCGReg arg1, 666 int32_t arg2, int const_arg2, TCGLabel *l) 667{ 668 tcg_out_cmp(s, cond, arg1, arg2, const_arg2); 669 tcg_out_bpcc(s, tcg_cond_to_bcond[cond], BPCC_ICC | BPCC_PT, l); 670 tcg_out_nop(s); 671} 672 673static void tcg_out_movcc(TCGContext *s, TCGCond cond, int cc, TCGReg ret, 674 int32_t v1, int v1const) 675{ 676 tcg_out32(s, ARITH_MOVCC | cc | INSN_RD(ret) 677 | INSN_RS1(tcg_cond_to_bcond[cond]) 678 | (v1const ? INSN_IMM11(v1) : INSN_RS2(v1))); 679} 680 681static void tcg_out_movcond_i32(TCGContext *s, TCGCond cond, TCGReg ret, 682 TCGReg c1, int32_t c2, int c2const, 683 int32_t v1, int v1const) 684{ 685 tcg_out_cmp(s, cond, c1, c2, c2const); 686 tcg_out_movcc(s, cond, MOVCC_ICC, ret, v1, v1const); 687} 688 689static void tcg_out_brcond_i64(TCGContext *s, TCGCond cond, TCGReg arg1, 690 int32_t arg2, int const_arg2, TCGLabel *l) 691{ 692 /* For 64-bit signed comparisons vs zero, we can avoid the compare. */ 693 int rcond = tcg_cond_to_rcond[cond]; 694 if (arg2 == 0 && rcond) { 695 int off16 = 0; 696 697 if (l->has_value) { 698 off16 = INSN_OFF16(tcg_pcrel_diff(s, l->u.value_ptr)); 699 } else { 700 tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP16, l, 0); 701 } 702 tcg_out32(s, INSN_OP(0) | INSN_OP2(3) | BPR_PT | INSN_RS1(arg1) 703 | INSN_COND(rcond) | off16); 704 } else { 705 tcg_out_cmp(s, cond, arg1, arg2, const_arg2); 706 tcg_out_bpcc(s, tcg_cond_to_bcond[cond], BPCC_XCC | BPCC_PT, l); 707 } 708 tcg_out_nop(s); 709} 710 711static void tcg_out_movr(TCGContext *s, int rcond, TCGReg ret, TCGReg c1, 712 int32_t v1, int v1const) 713{ 714 tcg_out32(s, ARITH_MOVR | INSN_RD(ret) | INSN_RS1(c1) | (rcond << 10) 715 | (v1const ? INSN_IMM10(v1) : INSN_RS2(v1))); 716} 717 718static void tcg_out_movcond_i64(TCGContext *s, TCGCond cond, TCGReg ret, 719 TCGReg c1, int32_t c2, int c2const, 720 int32_t v1, int v1const) 721{ 722 /* For 64-bit signed comparisons vs zero, we can avoid the compare. 723 Note that the immediate range is one bit smaller, so we must check 724 for that as well. */ 725 int rcond = tcg_cond_to_rcond[cond]; 726 if (c2 == 0 && rcond && (!v1const || check_fit_i32(v1, 10))) { 727 tcg_out_movr(s, rcond, ret, c1, v1, v1const); 728 } else { 729 tcg_out_cmp(s, cond, c1, c2, c2const); 730 tcg_out_movcc(s, cond, MOVCC_XCC, ret, v1, v1const); 731 } 732} 733 734static void tcg_out_setcond_i32(TCGContext *s, TCGCond cond, TCGReg ret, 735 TCGReg c1, int32_t c2, int c2const, bool neg) 736{ 737 /* For 32-bit comparisons, we can play games with ADDC/SUBC. */ 738 switch (cond) { 739 case TCG_COND_LTU: 740 case TCG_COND_GEU: 741 /* The result of the comparison is in the carry bit. */ 742 break; 743 744 case TCG_COND_EQ: 745 case TCG_COND_NE: 746 /* For equality, we can transform to inequality vs zero. */ 747 if (c2 != 0) { 748 tcg_out_arithc(s, TCG_REG_T1, c1, c2, c2const, ARITH_XOR); 749 c2 = TCG_REG_T1; 750 } else { 751 c2 = c1; 752 } 753 c1 = TCG_REG_G0, c2const = 0; 754 cond = (cond == TCG_COND_EQ ? TCG_COND_GEU : TCG_COND_LTU); 755 break; 756 757 case TCG_COND_TSTEQ: 758 case TCG_COND_TSTNE: 759 /* Transform to inequality vs zero. */ 760 tcg_out_arithc(s, TCG_REG_T1, c1, c2, c2const, ARITH_AND); 761 c1 = TCG_REG_G0; 762 c2 = TCG_REG_T1, c2const = 0; 763 cond = (cond == TCG_COND_TSTEQ ? TCG_COND_GEU : TCG_COND_LTU); 764 break; 765 766 case TCG_COND_GTU: 767 case TCG_COND_LEU: 768 /* If we don't need to load a constant into a register, we can 769 swap the operands on GTU/LEU. There's no benefit to loading 770 the constant into a temporary register. */ 771 if (!c2const || c2 == 0) { 772 TCGReg t = c1; 773 c1 = c2; 774 c2 = t; 775 c2const = 0; 776 cond = tcg_swap_cond(cond); 777 break; 778 } 779 /* FALLTHRU */ 780 781 default: 782 tcg_out_cmp(s, cond, c1, c2, c2const); 783 tcg_out_movi_s13(s, ret, 0); 784 tcg_out_movcc(s, cond, MOVCC_ICC, ret, neg ? -1 : 1, 1); 785 return; 786 } 787 788 tcg_out_cmp(s, cond, c1, c2, c2const); 789 if (cond == TCG_COND_LTU) { 790 if (neg) { 791 /* 0 - 0 - C = -C = (C ? -1 : 0) */ 792 tcg_out_arithi(s, ret, TCG_REG_G0, 0, ARITH_SUBC); 793 } else { 794 /* 0 + 0 + C = C = (C ? 1 : 0) */ 795 tcg_out_arithi(s, ret, TCG_REG_G0, 0, ARITH_ADDC); 796 } 797 } else { 798 if (neg) { 799 /* 0 + -1 + C = C - 1 = (C ? 0 : -1) */ 800 tcg_out_arithi(s, ret, TCG_REG_G0, -1, ARITH_ADDC); 801 } else { 802 /* 0 - -1 - C = 1 - C = (C ? 0 : 1) */ 803 tcg_out_arithi(s, ret, TCG_REG_G0, -1, ARITH_SUBC); 804 } 805 } 806} 807 808static void tcg_out_setcond_i64(TCGContext *s, TCGCond cond, TCGReg ret, 809 TCGReg c1, int32_t c2, int c2const, bool neg) 810{ 811 int rcond; 812 813 if (use_vis3_instructions && !neg) { 814 switch (cond) { 815 case TCG_COND_NE: 816 if (c2 != 0) { 817 break; 818 } 819 c2 = c1, c2const = 0, c1 = TCG_REG_G0; 820 /* FALLTHRU */ 821 case TCG_COND_LTU: 822 tcg_out_cmp(s, cond, c1, c2, c2const); 823 tcg_out_arith(s, ret, TCG_REG_G0, TCG_REG_G0, ARITH_ADDXC); 824 return; 825 default: 826 break; 827 } 828 } 829 830 /* For 64-bit signed comparisons vs zero, we can avoid the compare 831 if the input does not overlap the output. */ 832 rcond = tcg_cond_to_rcond[cond]; 833 if (c2 == 0 && rcond && c1 != ret) { 834 tcg_out_movi_s13(s, ret, 0); 835 tcg_out_movr(s, rcond, ret, c1, neg ? -1 : 1, 1); 836 } else { 837 tcg_out_cmp(s, cond, c1, c2, c2const); 838 tcg_out_movi_s13(s, ret, 0); 839 tcg_out_movcc(s, cond, MOVCC_XCC, ret, neg ? -1 : 1, 1); 840 } 841} 842 843static void tcg_out_addsub2_i32(TCGContext *s, TCGReg rl, TCGReg rh, 844 TCGReg al, TCGReg ah, int32_t bl, int blconst, 845 int32_t bh, int bhconst, int opl, int oph) 846{ 847 TCGReg tmp = TCG_REG_T1; 848 849 /* Note that the low parts are fully consumed before tmp is set. */ 850 if (rl != ah && (bhconst || rl != bh)) { 851 tmp = rl; 852 } 853 854 tcg_out_arithc(s, tmp, al, bl, blconst, opl); 855 tcg_out_arithc(s, rh, ah, bh, bhconst, oph); 856 tcg_out_mov(s, TCG_TYPE_I32, rl, tmp); 857} 858 859static void tcg_out_addsub2_i64(TCGContext *s, TCGReg rl, TCGReg rh, 860 TCGReg al, TCGReg ah, int32_t bl, int blconst, 861 int32_t bh, int bhconst, bool is_sub) 862{ 863 TCGReg tmp = TCG_REG_T1; 864 865 /* Note that the low parts are fully consumed before tmp is set. */ 866 if (rl != ah && (bhconst || rl != bh)) { 867 tmp = rl; 868 } 869 870 tcg_out_arithc(s, tmp, al, bl, blconst, is_sub ? ARITH_SUBCC : ARITH_ADDCC); 871 872 if (use_vis3_instructions && !is_sub) { 873 /* Note that ADDXC doesn't accept immediates. */ 874 if (bhconst && bh != 0) { 875 tcg_out_movi_s13(s, TCG_REG_T2, bh); 876 bh = TCG_REG_T2; 877 } 878 tcg_out_arith(s, rh, ah, bh, ARITH_ADDXC); 879 } else if (bh == TCG_REG_G0) { 880 /* If we have a zero, we can perform the operation in two insns, 881 with the arithmetic first, and a conditional move into place. */ 882 if (rh == ah) { 883 tcg_out_arithi(s, TCG_REG_T2, ah, 1, 884 is_sub ? ARITH_SUB : ARITH_ADD); 885 tcg_out_movcc(s, TCG_COND_LTU, MOVCC_XCC, rh, TCG_REG_T2, 0); 886 } else { 887 tcg_out_arithi(s, rh, ah, 1, is_sub ? ARITH_SUB : ARITH_ADD); 888 tcg_out_movcc(s, TCG_COND_GEU, MOVCC_XCC, rh, ah, 0); 889 } 890 } else { 891 /* 892 * Otherwise adjust BH as if there is carry into T2. 893 * Note that constant BH is constrained to 11 bits for the MOVCC, 894 * so the adjustment fits 12 bits. 895 */ 896 if (bhconst) { 897 tcg_out_movi_s13(s, TCG_REG_T2, bh + (is_sub ? -1 : 1)); 898 } else { 899 tcg_out_arithi(s, TCG_REG_T2, bh, 1, 900 is_sub ? ARITH_SUB : ARITH_ADD); 901 } 902 /* ... smoosh T2 back to original BH if carry is clear ... */ 903 tcg_out_movcc(s, TCG_COND_GEU, MOVCC_XCC, TCG_REG_T2, bh, bhconst); 904 /* ... and finally perform the arithmetic with the new operand. */ 905 tcg_out_arith(s, rh, ah, TCG_REG_T2, is_sub ? ARITH_SUB : ARITH_ADD); 906 } 907 908 tcg_out_mov(s, TCG_TYPE_I64, rl, tmp); 909} 910 911static void tcg_out_jmpl_const(TCGContext *s, const tcg_insn_unit *dest, 912 bool in_prologue, bool tail_call) 913{ 914 uintptr_t desti = (uintptr_t)dest; 915 916 tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_REG_T1, 917 desti & ~0xfff, in_prologue, TCG_REG_T2); 918 tcg_out_arithi(s, tail_call ? TCG_REG_G0 : TCG_REG_O7, 919 TCG_REG_T1, desti & 0xfff, JMPL); 920} 921 922static void tcg_out_call_nodelay(TCGContext *s, const tcg_insn_unit *dest, 923 bool in_prologue) 924{ 925 ptrdiff_t disp = tcg_pcrel_diff(s, dest); 926 927 if (disp == (int32_t)disp) { 928 tcg_out32(s, CALL | (uint32_t)disp >> 2); 929 } else { 930 tcg_out_jmpl_const(s, dest, in_prologue, false); 931 } 932} 933 934static void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest, 935 const TCGHelperInfo *info) 936{ 937 tcg_out_call_nodelay(s, dest, false); 938 tcg_out_nop(s); 939} 940 941static void tcg_out_mb(TCGContext *s, TCGArg a0) 942{ 943 /* Note that the TCG memory order constants mirror the Sparc MEMBAR. */ 944 tcg_out32(s, MEMBAR | (a0 & TCG_MO_ALL)); 945} 946 947/* Generate global QEMU prologue and epilogue code */ 948static void tcg_target_qemu_prologue(TCGContext *s) 949{ 950 int tmp_buf_size, frame_size; 951 952 /* 953 * The TCG temp buffer is at the top of the frame, immediately 954 * below the frame pointer. Use the logical (aligned) offset here; 955 * the stack bias is applied in temp_allocate_frame(). 956 */ 957 tmp_buf_size = CPU_TEMP_BUF_NLONGS * (int)sizeof(long); 958 tcg_set_frame(s, TCG_REG_I6, -tmp_buf_size, tmp_buf_size); 959 960 /* 961 * TCG_TARGET_CALL_STACK_OFFSET includes the stack bias, but is 962 * otherwise the minimal frame usable by callees. 963 */ 964 frame_size = TCG_TARGET_CALL_STACK_OFFSET - TCG_TARGET_STACK_BIAS; 965 frame_size += TCG_STATIC_CALL_ARGS_SIZE + tmp_buf_size; 966 frame_size += TCG_TARGET_STACK_ALIGN - 1; 967 frame_size &= -TCG_TARGET_STACK_ALIGN; 968 tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) | 969 INSN_IMM13(-frame_size)); 970 971#ifndef CONFIG_SOFTMMU 972 if (guest_base != 0) { 973 tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, 974 guest_base, true, TCG_REG_T1); 975 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 976 } 977#endif 978 979 /* We choose TCG_REG_TB such that no move is required. */ 980 QEMU_BUILD_BUG_ON(TCG_REG_TB != TCG_REG_I1); 981 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); 982 983 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I1, 0, JMPL); 984 /* delay slot */ 985 tcg_out_nop(s); 986 987 /* Epilogue for goto_ptr. */ 988 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 989 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); 990 /* delay slot */ 991 tcg_out_movi_s13(s, TCG_REG_O0, 0); 992} 993 994static void tcg_out_tb_start(TCGContext *s) 995{ 996 /* nothing to do */ 997} 998 999static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 1000{ 1001 int i; 1002 for (i = 0; i < count; ++i) { 1003 p[i] = NOP; 1004 } 1005} 1006 1007static const TCGLdstHelperParam ldst_helper_param = { 1008 .ntmp = 1, .tmp = { TCG_REG_T1 } 1009}; 1010 1011static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1012{ 1013 MemOp opc = get_memop(lb->oi); 1014 MemOp sgn; 1015 1016 if (!patch_reloc(lb->label_ptr[0], R_SPARC_WDISP19, 1017 (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 0)) { 1018 return false; 1019 } 1020 1021 /* Use inline tcg_out_ext32s; otherwise let the helper sign-extend. */ 1022 sgn = (opc & MO_SIZE) < MO_32 ? MO_SIGN : 0; 1023 1024 tcg_out_ld_helper_args(s, lb, &ldst_helper_param); 1025 tcg_out_call(s, qemu_ld_helpers[opc & (MO_SIZE | sgn)], NULL); 1026 tcg_out_ld_helper_ret(s, lb, sgn, &ldst_helper_param); 1027 1028 tcg_out_bpcc0(s, COND_A, BPCC_A | BPCC_PT, 0); 1029 return patch_reloc(s->code_ptr - 1, R_SPARC_WDISP19, 1030 (intptr_t)lb->raddr, 0); 1031} 1032 1033static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1034{ 1035 MemOp opc = get_memop(lb->oi); 1036 1037 if (!patch_reloc(lb->label_ptr[0], R_SPARC_WDISP19, 1038 (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 0)) { 1039 return false; 1040 } 1041 1042 tcg_out_st_helper_args(s, lb, &ldst_helper_param); 1043 tcg_out_call(s, qemu_st_helpers[opc & MO_SIZE], NULL); 1044 1045 tcg_out_bpcc0(s, COND_A, BPCC_A | BPCC_PT, 0); 1046 return patch_reloc(s->code_ptr - 1, R_SPARC_WDISP19, 1047 (intptr_t)lb->raddr, 0); 1048} 1049 1050typedef struct { 1051 TCGReg base; 1052 TCGReg index; 1053 TCGAtomAlign aa; 1054} HostAddress; 1055 1056bool tcg_target_has_memory_bswap(MemOp memop) 1057{ 1058 return true; 1059} 1060 1061/* We expect to use a 13-bit negative offset from ENV. */ 1062#define MIN_TLB_MASK_TABLE_OFS -(1 << 12) 1063 1064/* 1065 * For system-mode, perform the TLB load and compare. 1066 * For user-mode, perform any required alignment tests. 1067 * In both cases, return a TCGLabelQemuLdst structure if the slow path 1068 * is required and fill in @h with the host address for the fast path. 1069 */ 1070static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 1071 TCGReg addr_reg, MemOpIdx oi, 1072 bool is_ld) 1073{ 1074 TCGType addr_type = s->addr_type; 1075 TCGLabelQemuLdst *ldst = NULL; 1076 MemOp opc = get_memop(oi); 1077 MemOp s_bits = opc & MO_SIZE; 1078 unsigned a_mask; 1079 1080 /* We don't support unaligned accesses. */ 1081 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); 1082 h->aa.align = MAX(h->aa.align, s_bits); 1083 a_mask = (1u << h->aa.align) - 1; 1084 1085#ifdef CONFIG_SOFTMMU 1086 int mem_index = get_mmuidx(oi); 1087 int fast_off = tlb_mask_table_ofs(s, mem_index); 1088 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); 1089 int table_off = fast_off + offsetof(CPUTLBDescFast, table); 1090 int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read) 1091 : offsetof(CPUTLBEntry, addr_write); 1092 int add_off = offsetof(CPUTLBEntry, addend); 1093 int compare_mask; 1094 int cc; 1095 1096 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ 1097 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_T2, TCG_AREG0, mask_off); 1098 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_T3, TCG_AREG0, table_off); 1099 1100 /* Extract the page index, shifted into place for tlb index. */ 1101 tcg_out_arithi(s, TCG_REG_T1, addr_reg, 1102 s->page_bits - CPU_TLB_ENTRY_BITS, SHIFT_SRL); 1103 tcg_out_arith(s, TCG_REG_T1, TCG_REG_T1, TCG_REG_T2, ARITH_AND); 1104 1105 /* Add the tlb_table pointer, creating the CPUTLBEntry address into R2. */ 1106 tcg_out_arith(s, TCG_REG_T1, TCG_REG_T1, TCG_REG_T3, ARITH_ADD); 1107 1108 /* 1109 * Load the tlb comparator and the addend. 1110 * Always load the entire 64-bit comparator for simplicity. 1111 * We will ignore the high bits via BPCC_ICC below. 1112 */ 1113 tcg_out_ld(s, TCG_TYPE_I64, TCG_REG_T2, TCG_REG_T1, cmp_off); 1114 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_T1, TCG_REG_T1, add_off); 1115 h->base = TCG_REG_T1; 1116 1117 /* Mask out the page offset, except for the required alignment. */ 1118 compare_mask = s->page_mask | a_mask; 1119 if (check_fit_tl(compare_mask, 13)) { 1120 tcg_out_arithi(s, TCG_REG_T3, addr_reg, compare_mask, ARITH_AND); 1121 } else { 1122 tcg_out_movi_s32(s, TCG_REG_T3, compare_mask); 1123 tcg_out_arith(s, TCG_REG_T3, addr_reg, TCG_REG_T3, ARITH_AND); 1124 } 1125 tcg_out_cmp(s, TCG_COND_NE, TCG_REG_T2, TCG_REG_T3, 0); 1126 1127 ldst = new_ldst_label(s); 1128 ldst->is_ld = is_ld; 1129 ldst->oi = oi; 1130 ldst->addrlo_reg = addr_reg; 1131 ldst->label_ptr[0] = s->code_ptr; 1132 1133 /* bne,pn %[xi]cc, label0 */ 1134 cc = addr_type == TCG_TYPE_I32 ? BPCC_ICC : BPCC_XCC; 1135 tcg_out_bpcc0(s, COND_NE, BPCC_PN | cc, 0); 1136#else 1137 /* 1138 * If the size equals the required alignment, we can skip the test 1139 * and allow host SIGBUS to deliver SIGBUS to the guest. 1140 * Otherwise, test for at least natural alignment and defer 1141 * everything else to the helper functions. 1142 */ 1143 if (s_bits != memop_alignment_bits(opc)) { 1144 tcg_debug_assert(check_fit_tl(a_mask, 13)); 1145 tcg_out_arithi(s, TCG_REG_G0, addr_reg, a_mask, ARITH_ANDCC); 1146 1147 ldst = new_ldst_label(s); 1148 ldst->is_ld = is_ld; 1149 ldst->oi = oi; 1150 ldst->addrlo_reg = addr_reg; 1151 ldst->label_ptr[0] = s->code_ptr; 1152 1153 /* bne,pn %icc, label0 */ 1154 tcg_out_bpcc0(s, COND_NE, BPCC_PN | BPCC_ICC, 0); 1155 } 1156 h->base = guest_base ? TCG_GUEST_BASE_REG : TCG_REG_G0; 1157#endif 1158 1159 /* If the guest address must be zero-extended, do in the delay slot. */ 1160 if (addr_type == TCG_TYPE_I32) { 1161 tcg_out_ext32u(s, TCG_REG_T2, addr_reg); 1162 h->index = TCG_REG_T2; 1163 } else { 1164 if (ldst) { 1165 tcg_out_nop(s); 1166 } 1167 h->index = addr_reg; 1168 } 1169 return ldst; 1170} 1171 1172static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr, 1173 MemOpIdx oi, TCGType data_type) 1174{ 1175 static const int ld_opc[(MO_SSIZE | MO_BSWAP) + 1] = { 1176 [MO_UB] = LDUB, 1177 [MO_SB] = LDSB, 1178 [MO_UB | MO_LE] = LDUB, 1179 [MO_SB | MO_LE] = LDSB, 1180 1181 [MO_BEUW] = LDUH, 1182 [MO_BESW] = LDSH, 1183 [MO_BEUL] = LDUW, 1184 [MO_BESL] = LDSW, 1185 [MO_BEUQ] = LDX, 1186 [MO_BESQ] = LDX, 1187 1188 [MO_LEUW] = LDUH_LE, 1189 [MO_LESW] = LDSH_LE, 1190 [MO_LEUL] = LDUW_LE, 1191 [MO_LESL] = LDSW_LE, 1192 [MO_LEUQ] = LDX_LE, 1193 [MO_LESQ] = LDX_LE, 1194 }; 1195 1196 TCGLabelQemuLdst *ldst; 1197 HostAddress h; 1198 1199 ldst = prepare_host_addr(s, &h, addr, oi, true); 1200 1201 tcg_out_ldst_rr(s, data, h.base, h.index, 1202 ld_opc[get_memop(oi) & (MO_BSWAP | MO_SSIZE)]); 1203 1204 if (ldst) { 1205 ldst->type = data_type; 1206 ldst->datalo_reg = data; 1207 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1208 } 1209} 1210 1211static void tcg_out_qemu_st(TCGContext *s, TCGReg data, TCGReg addr, 1212 MemOpIdx oi, TCGType data_type) 1213{ 1214 static const int st_opc[(MO_SIZE | MO_BSWAP) + 1] = { 1215 [MO_UB] = STB, 1216 1217 [MO_BEUW] = STH, 1218 [MO_BEUL] = STW, 1219 [MO_BEUQ] = STX, 1220 1221 [MO_LEUW] = STH_LE, 1222 [MO_LEUL] = STW_LE, 1223 [MO_LEUQ] = STX_LE, 1224 }; 1225 1226 TCGLabelQemuLdst *ldst; 1227 HostAddress h; 1228 1229 ldst = prepare_host_addr(s, &h, addr, oi, false); 1230 1231 tcg_out_ldst_rr(s, data, h.base, h.index, 1232 st_opc[get_memop(oi) & (MO_BSWAP | MO_SIZE)]); 1233 1234 if (ldst) { 1235 ldst->type = data_type; 1236 ldst->datalo_reg = data; 1237 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1238 } 1239} 1240 1241static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) 1242{ 1243 if (check_fit_ptr(a0, 13)) { 1244 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); 1245 tcg_out_movi_s13(s, TCG_REG_O0, a0); 1246 return; 1247 } else { 1248 intptr_t tb_diff = tcg_tbrel_diff(s, (void *)a0); 1249 if (check_fit_ptr(tb_diff, 13)) { 1250 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); 1251 /* Note that TCG_REG_TB has been unwound to O1. */ 1252 tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O1, tb_diff, ARITH_ADD); 1253 return; 1254 } 1255 } 1256 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, a0 & ~0x3ff); 1257 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); 1258 tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O0, a0 & 0x3ff, ARITH_OR); 1259} 1260 1261static void tcg_out_goto_tb(TCGContext *s, int which) 1262{ 1263 ptrdiff_t off = tcg_tbrel_diff(s, (void *)get_jmp_target_addr(s, which)); 1264 1265 /* Load link and indirect branch. */ 1266 set_jmp_insn_offset(s, which); 1267 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TB, TCG_REG_TB, off); 1268 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_TB, 0, JMPL); 1269 /* delay slot */ 1270 tcg_out_nop(s); 1271 set_jmp_reset_offset(s, which); 1272 1273 /* 1274 * For the unlinked path of goto_tb, we need to reset TCG_REG_TB 1275 * to the beginning of this TB. 1276 */ 1277 off = -tcg_current_code_size(s); 1278 if (check_fit_i32(off, 13)) { 1279 tcg_out_arithi(s, TCG_REG_TB, TCG_REG_TB, off, ARITH_ADD); 1280 } else { 1281 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, off); 1282 tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB, TCG_REG_T1, ARITH_ADD); 1283 } 1284} 1285 1286void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1287 uintptr_t jmp_rx, uintptr_t jmp_rw) 1288{ 1289} 1290 1291static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, 1292 const TCGArg args[TCG_MAX_OP_ARGS], 1293 const int const_args[TCG_MAX_OP_ARGS]) 1294{ 1295 TCGArg a0, a1, a2; 1296 int c, c2; 1297 1298 /* Hoist the loads of the most common arguments. */ 1299 a0 = args[0]; 1300 a1 = args[1]; 1301 a2 = args[2]; 1302 c2 = const_args[2]; 1303 1304 switch (opc) { 1305 case INDEX_op_goto_ptr: 1306 tcg_out_arithi(s, TCG_REG_G0, a0, 0, JMPL); 1307 tcg_out_mov_delay(s, TCG_REG_TB, a0); 1308 break; 1309 case INDEX_op_br: 1310 tcg_out_bpcc(s, COND_A, BPCC_PT, arg_label(a0)); 1311 tcg_out_nop(s); 1312 break; 1313 1314#define OP_32_64(x) \ 1315 glue(glue(case INDEX_op_, x), _i32): \ 1316 glue(glue(case INDEX_op_, x), _i64) 1317 1318 OP_32_64(ld8u): 1319 tcg_out_ldst(s, a0, a1, a2, LDUB); 1320 break; 1321 OP_32_64(ld8s): 1322 tcg_out_ldst(s, a0, a1, a2, LDSB); 1323 break; 1324 OP_32_64(ld16u): 1325 tcg_out_ldst(s, a0, a1, a2, LDUH); 1326 break; 1327 OP_32_64(ld16s): 1328 tcg_out_ldst(s, a0, a1, a2, LDSH); 1329 break; 1330 case INDEX_op_ld_i32: 1331 case INDEX_op_ld32u_i64: 1332 tcg_out_ldst(s, a0, a1, a2, LDUW); 1333 break; 1334 OP_32_64(st8): 1335 tcg_out_ldst(s, a0, a1, a2, STB); 1336 break; 1337 OP_32_64(st16): 1338 tcg_out_ldst(s, a0, a1, a2, STH); 1339 break; 1340 case INDEX_op_st_i32: 1341 case INDEX_op_st32_i64: 1342 tcg_out_ldst(s, a0, a1, a2, STW); 1343 break; 1344 OP_32_64(add): 1345 c = ARITH_ADD; 1346 goto gen_arith; 1347 OP_32_64(sub): 1348 c = ARITH_SUB; 1349 goto gen_arith; 1350 OP_32_64(and): 1351 c = ARITH_AND; 1352 goto gen_arith; 1353 OP_32_64(andc): 1354 c = ARITH_ANDN; 1355 goto gen_arith; 1356 OP_32_64(or): 1357 c = ARITH_OR; 1358 goto gen_arith; 1359 OP_32_64(orc): 1360 c = ARITH_ORN; 1361 goto gen_arith; 1362 OP_32_64(xor): 1363 c = ARITH_XOR; 1364 goto gen_arith; 1365 case INDEX_op_shl_i32: 1366 c = SHIFT_SLL; 1367 do_shift32: 1368 /* Limit immediate shift count lest we create an illegal insn. */ 1369 tcg_out_arithc(s, a0, a1, a2 & 31, c2, c); 1370 break; 1371 case INDEX_op_shr_i32: 1372 c = SHIFT_SRL; 1373 goto do_shift32; 1374 case INDEX_op_sar_i32: 1375 c = SHIFT_SRA; 1376 goto do_shift32; 1377 case INDEX_op_mul_i32: 1378 c = ARITH_UMUL; 1379 goto gen_arith; 1380 1381 OP_32_64(neg): 1382 c = ARITH_SUB; 1383 goto gen_arith1; 1384 OP_32_64(not): 1385 c = ARITH_ORN; 1386 goto gen_arith1; 1387 1388 case INDEX_op_div_i32: 1389 tcg_out_div32(s, a0, a1, a2, c2, 0); 1390 break; 1391 case INDEX_op_divu_i32: 1392 tcg_out_div32(s, a0, a1, a2, c2, 1); 1393 break; 1394 1395 case INDEX_op_brcond_i32: 1396 tcg_out_brcond_i32(s, a2, a0, a1, const_args[1], arg_label(args[3])); 1397 break; 1398 case INDEX_op_setcond_i32: 1399 tcg_out_setcond_i32(s, args[3], a0, a1, a2, c2, false); 1400 break; 1401 case INDEX_op_negsetcond_i32: 1402 tcg_out_setcond_i32(s, args[3], a0, a1, a2, c2, true); 1403 break; 1404 case INDEX_op_movcond_i32: 1405 tcg_out_movcond_i32(s, args[5], a0, a1, a2, c2, args[3], const_args[3]); 1406 break; 1407 1408 case INDEX_op_add2_i32: 1409 tcg_out_addsub2_i32(s, args[0], args[1], args[2], args[3], 1410 args[4], const_args[4], args[5], const_args[5], 1411 ARITH_ADDCC, ARITH_ADDC); 1412 break; 1413 case INDEX_op_sub2_i32: 1414 tcg_out_addsub2_i32(s, args[0], args[1], args[2], args[3], 1415 args[4], const_args[4], args[5], const_args[5], 1416 ARITH_SUBCC, ARITH_SUBC); 1417 break; 1418 case INDEX_op_mulu2_i32: 1419 c = ARITH_UMUL; 1420 goto do_mul2; 1421 case INDEX_op_muls2_i32: 1422 c = ARITH_SMUL; 1423 do_mul2: 1424 /* The 32-bit multiply insns produce a full 64-bit result. */ 1425 tcg_out_arithc(s, a0, a2, args[3], const_args[3], c); 1426 tcg_out_arithi(s, a1, a0, 32, SHIFT_SRLX); 1427 break; 1428 1429 case INDEX_op_qemu_ld_a32_i32: 1430 case INDEX_op_qemu_ld_a64_i32: 1431 tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32); 1432 break; 1433 case INDEX_op_qemu_ld_a32_i64: 1434 case INDEX_op_qemu_ld_a64_i64: 1435 tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64); 1436 break; 1437 case INDEX_op_qemu_st_a32_i32: 1438 case INDEX_op_qemu_st_a64_i32: 1439 tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32); 1440 break; 1441 case INDEX_op_qemu_st_a32_i64: 1442 case INDEX_op_qemu_st_a64_i64: 1443 tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64); 1444 break; 1445 1446 case INDEX_op_ld32s_i64: 1447 tcg_out_ldst(s, a0, a1, a2, LDSW); 1448 break; 1449 case INDEX_op_ld_i64: 1450 tcg_out_ldst(s, a0, a1, a2, LDX); 1451 break; 1452 case INDEX_op_st_i64: 1453 tcg_out_ldst(s, a0, a1, a2, STX); 1454 break; 1455 case INDEX_op_shl_i64: 1456 c = SHIFT_SLLX; 1457 do_shift64: 1458 /* Limit immediate shift count lest we create an illegal insn. */ 1459 tcg_out_arithc(s, a0, a1, a2 & 63, c2, c); 1460 break; 1461 case INDEX_op_shr_i64: 1462 c = SHIFT_SRLX; 1463 goto do_shift64; 1464 case INDEX_op_sar_i64: 1465 c = SHIFT_SRAX; 1466 goto do_shift64; 1467 case INDEX_op_mul_i64: 1468 c = ARITH_MULX; 1469 goto gen_arith; 1470 case INDEX_op_div_i64: 1471 c = ARITH_SDIVX; 1472 goto gen_arith; 1473 case INDEX_op_divu_i64: 1474 c = ARITH_UDIVX; 1475 goto gen_arith; 1476 1477 case INDEX_op_brcond_i64: 1478 tcg_out_brcond_i64(s, a2, a0, a1, const_args[1], arg_label(args[3])); 1479 break; 1480 case INDEX_op_setcond_i64: 1481 tcg_out_setcond_i64(s, args[3], a0, a1, a2, c2, false); 1482 break; 1483 case INDEX_op_negsetcond_i64: 1484 tcg_out_setcond_i64(s, args[3], a0, a1, a2, c2, true); 1485 break; 1486 case INDEX_op_movcond_i64: 1487 tcg_out_movcond_i64(s, args[5], a0, a1, a2, c2, args[3], const_args[3]); 1488 break; 1489 case INDEX_op_add2_i64: 1490 tcg_out_addsub2_i64(s, args[0], args[1], args[2], args[3], args[4], 1491 const_args[4], args[5], const_args[5], false); 1492 break; 1493 case INDEX_op_sub2_i64: 1494 tcg_out_addsub2_i64(s, args[0], args[1], args[2], args[3], args[4], 1495 const_args[4], args[5], const_args[5], true); 1496 break; 1497 case INDEX_op_muluh_i64: 1498 tcg_out_arith(s, args[0], args[1], args[2], ARITH_UMULXHI); 1499 break; 1500 1501 gen_arith: 1502 tcg_out_arithc(s, a0, a1, a2, c2, c); 1503 break; 1504 1505 gen_arith1: 1506 tcg_out_arithc(s, a0, TCG_REG_G0, a1, const_args[1], c); 1507 break; 1508 1509 case INDEX_op_mb: 1510 tcg_out_mb(s, a0); 1511 break; 1512 1513 case INDEX_op_extract_i64: 1514 tcg_debug_assert(a2 + args[3] == 32); 1515 tcg_out_arithi(s, a0, a1, a2, SHIFT_SRL); 1516 break; 1517 case INDEX_op_sextract_i64: 1518 tcg_debug_assert(a2 + args[3] == 32); 1519 tcg_out_arithi(s, a0, a1, a2, SHIFT_SRA); 1520 break; 1521 1522 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ 1523 case INDEX_op_mov_i64: 1524 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 1525 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 1526 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 1527 case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ 1528 case INDEX_op_ext8s_i64: 1529 case INDEX_op_ext8u_i32: 1530 case INDEX_op_ext8u_i64: 1531 case INDEX_op_ext16s_i32: 1532 case INDEX_op_ext16s_i64: 1533 case INDEX_op_ext16u_i32: 1534 case INDEX_op_ext16u_i64: 1535 case INDEX_op_ext32s_i64: 1536 case INDEX_op_ext32u_i64: 1537 case INDEX_op_ext_i32_i64: 1538 case INDEX_op_extu_i32_i64: 1539 default: 1540 g_assert_not_reached(); 1541 } 1542} 1543 1544static TCGConstraintSetIndex 1545tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) 1546{ 1547 switch (op) { 1548 case INDEX_op_goto_ptr: 1549 return C_O0_I1(r); 1550 1551 case INDEX_op_ld8u_i32: 1552 case INDEX_op_ld8u_i64: 1553 case INDEX_op_ld8s_i32: 1554 case INDEX_op_ld8s_i64: 1555 case INDEX_op_ld16u_i32: 1556 case INDEX_op_ld16u_i64: 1557 case INDEX_op_ld16s_i32: 1558 case INDEX_op_ld16s_i64: 1559 case INDEX_op_ld_i32: 1560 case INDEX_op_ld32u_i64: 1561 case INDEX_op_ld32s_i64: 1562 case INDEX_op_ld_i64: 1563 case INDEX_op_neg_i32: 1564 case INDEX_op_neg_i64: 1565 case INDEX_op_not_i32: 1566 case INDEX_op_not_i64: 1567 case INDEX_op_ext32s_i64: 1568 case INDEX_op_ext32u_i64: 1569 case INDEX_op_ext_i32_i64: 1570 case INDEX_op_extu_i32_i64: 1571 case INDEX_op_extract_i64: 1572 case INDEX_op_sextract_i64: 1573 case INDEX_op_qemu_ld_a32_i32: 1574 case INDEX_op_qemu_ld_a64_i32: 1575 case INDEX_op_qemu_ld_a32_i64: 1576 case INDEX_op_qemu_ld_a64_i64: 1577 return C_O1_I1(r, r); 1578 1579 case INDEX_op_st8_i32: 1580 case INDEX_op_st8_i64: 1581 case INDEX_op_st16_i32: 1582 case INDEX_op_st16_i64: 1583 case INDEX_op_st_i32: 1584 case INDEX_op_st32_i64: 1585 case INDEX_op_st_i64: 1586 case INDEX_op_qemu_st_a32_i32: 1587 case INDEX_op_qemu_st_a64_i32: 1588 case INDEX_op_qemu_st_a32_i64: 1589 case INDEX_op_qemu_st_a64_i64: 1590 return C_O0_I2(rZ, r); 1591 1592 case INDEX_op_add_i32: 1593 case INDEX_op_add_i64: 1594 case INDEX_op_mul_i32: 1595 case INDEX_op_mul_i64: 1596 case INDEX_op_div_i32: 1597 case INDEX_op_div_i64: 1598 case INDEX_op_divu_i32: 1599 case INDEX_op_divu_i64: 1600 case INDEX_op_sub_i32: 1601 case INDEX_op_sub_i64: 1602 case INDEX_op_and_i32: 1603 case INDEX_op_and_i64: 1604 case INDEX_op_andc_i32: 1605 case INDEX_op_andc_i64: 1606 case INDEX_op_or_i32: 1607 case INDEX_op_or_i64: 1608 case INDEX_op_orc_i32: 1609 case INDEX_op_orc_i64: 1610 case INDEX_op_xor_i32: 1611 case INDEX_op_xor_i64: 1612 case INDEX_op_shl_i32: 1613 case INDEX_op_shl_i64: 1614 case INDEX_op_shr_i32: 1615 case INDEX_op_shr_i64: 1616 case INDEX_op_sar_i32: 1617 case INDEX_op_sar_i64: 1618 case INDEX_op_setcond_i32: 1619 case INDEX_op_setcond_i64: 1620 case INDEX_op_negsetcond_i32: 1621 case INDEX_op_negsetcond_i64: 1622 return C_O1_I2(r, rZ, rJ); 1623 1624 case INDEX_op_brcond_i32: 1625 case INDEX_op_brcond_i64: 1626 return C_O0_I2(rZ, rJ); 1627 case INDEX_op_movcond_i32: 1628 case INDEX_op_movcond_i64: 1629 return C_O1_I4(r, rZ, rJ, rI, 0); 1630 case INDEX_op_add2_i32: 1631 case INDEX_op_add2_i64: 1632 case INDEX_op_sub2_i32: 1633 case INDEX_op_sub2_i64: 1634 return C_O2_I4(r, r, rZ, rZ, rJ, rJ); 1635 case INDEX_op_mulu2_i32: 1636 case INDEX_op_muls2_i32: 1637 return C_O2_I2(r, r, rZ, rJ); 1638 case INDEX_op_muluh_i64: 1639 return C_O1_I2(r, r, r); 1640 1641 default: 1642 return C_NotImplemented; 1643 } 1644} 1645 1646static void tcg_target_init(TCGContext *s) 1647{ 1648 /* 1649 * Only probe for the platform and capabilities if we haven't already 1650 * determined maximum values at compile time. 1651 */ 1652#ifndef use_vis3_instructions 1653 { 1654 unsigned long hwcap = qemu_getauxval(AT_HWCAP); 1655 use_vis3_instructions = (hwcap & HWCAP_SPARC_VIS3) != 0; 1656 } 1657#endif 1658 1659 tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS; 1660 tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS; 1661 1662 tcg_target_call_clobber_regs = 0; 1663 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G1); 1664 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G2); 1665 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G3); 1666 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G4); 1667 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G5); 1668 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G6); 1669 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G7); 1670 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O0); 1671 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O1); 1672 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O2); 1673 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O3); 1674 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O4); 1675 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O5); 1676 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O6); 1677 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O7); 1678 1679 s->reserved_regs = 0; 1680 tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0); /* zero */ 1681 tcg_regset_set_reg(s->reserved_regs, TCG_REG_G6); /* reserved for os */ 1682 tcg_regset_set_reg(s->reserved_regs, TCG_REG_G7); /* thread pointer */ 1683 tcg_regset_set_reg(s->reserved_regs, TCG_REG_I6); /* frame pointer */ 1684 tcg_regset_set_reg(s->reserved_regs, TCG_REG_I7); /* return address */ 1685 tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6); /* stack pointer */ 1686 tcg_regset_set_reg(s->reserved_regs, TCG_REG_T1); /* for internal use */ 1687 tcg_regset_set_reg(s->reserved_regs, TCG_REG_T2); /* for internal use */ 1688 tcg_regset_set_reg(s->reserved_regs, TCG_REG_T3); /* for internal use */ 1689} 1690 1691#define ELF_HOST_MACHINE EM_SPARCV9 1692 1693typedef struct { 1694 DebugFrameHeader h; 1695 uint8_t fde_def_cfa[4]; 1696 uint8_t fde_win_save; 1697 uint8_t fde_ret_save[3]; 1698} DebugFrame; 1699 1700static const DebugFrame debug_frame = { 1701 .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ 1702 .h.cie.id = -1, 1703 .h.cie.version = 1, 1704 .h.cie.code_align = 1, 1705 .h.cie.data_align = -sizeof(void *) & 0x7f, 1706 .h.cie.return_column = 15, /* o7 */ 1707 1708 /* Total FDE size does not include the "len" member. */ 1709 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 1710 1711 .fde_def_cfa = { 1712 12, 30, /* DW_CFA_def_cfa i6, 2047 */ 1713 (2047 & 0x7f) | 0x80, (2047 >> 7) 1714 }, 1715 .fde_win_save = 0x2d, /* DW_CFA_GNU_window_save */ 1716 .fde_ret_save = { 9, 15, 31 }, /* DW_CFA_register o7, i7 */ 1717}; 1718 1719void tcg_register_jit(const void *buf, size_t buf_size) 1720{ 1721 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 1722} 1723