1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25/* We only support generating code for 64-bit mode. */ 26#ifndef __arch64__ 27#error "unsupported code generation mode" 28#endif 29 30/* Used for function call generation. */ 31#define TCG_REG_CALL_STACK TCG_REG_O6 32#define TCG_TARGET_STACK_BIAS 2047 33#define TCG_TARGET_STACK_ALIGN 16 34#define TCG_TARGET_CALL_STACK_OFFSET (128 + 6 * 8 + TCG_TARGET_STACK_BIAS) 35#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EXTEND 36#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL 37#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL 38#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL 39 40#ifdef CONFIG_DEBUG_TCG 41static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 42 "%g0", 43 "%g1", 44 "%g2", 45 "%g3", 46 "%g4", 47 "%g5", 48 "%g6", 49 "%g7", 50 "%o0", 51 "%o1", 52 "%o2", 53 "%o3", 54 "%o4", 55 "%o5", 56 "%o6", 57 "%o7", 58 "%l0", 59 "%l1", 60 "%l2", 61 "%l3", 62 "%l4", 63 "%l5", 64 "%l6", 65 "%l7", 66 "%i0", 67 "%i1", 68 "%i2", 69 "%i3", 70 "%i4", 71 "%i5", 72 "%i6", 73 "%i7", 74}; 75#endif 76 77#define TCG_CT_CONST_S11 0x100 78#define TCG_CT_CONST_S13 0x200 79 80#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) 81 82/* Define some temporary registers. T3 is used for constant generation. */ 83#define TCG_REG_T1 TCG_REG_G1 84#define TCG_REG_T2 TCG_REG_G2 85#define TCG_REG_T3 TCG_REG_O7 86 87#ifndef CONFIG_SOFTMMU 88# define TCG_GUEST_BASE_REG TCG_REG_I5 89#endif 90 91#define TCG_REG_TB TCG_REG_I1 92 93static const int tcg_target_reg_alloc_order[] = { 94 TCG_REG_L0, 95 TCG_REG_L1, 96 TCG_REG_L2, 97 TCG_REG_L3, 98 TCG_REG_L4, 99 TCG_REG_L5, 100 TCG_REG_L6, 101 TCG_REG_L7, 102 103 TCG_REG_I0, 104 TCG_REG_I1, 105 TCG_REG_I2, 106 TCG_REG_I3, 107 TCG_REG_I4, 108 TCG_REG_I5, 109 110 TCG_REG_G3, 111 TCG_REG_G4, 112 TCG_REG_G5, 113 114 TCG_REG_O0, 115 TCG_REG_O1, 116 TCG_REG_O2, 117 TCG_REG_O3, 118 TCG_REG_O4, 119 TCG_REG_O5, 120}; 121 122static const int tcg_target_call_iarg_regs[6] = { 123 TCG_REG_O0, 124 TCG_REG_O1, 125 TCG_REG_O2, 126 TCG_REG_O3, 127 TCG_REG_O4, 128 TCG_REG_O5, 129}; 130 131static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 132{ 133 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 134 tcg_debug_assert(slot >= 0 && slot <= 3); 135 return TCG_REG_O0 + slot; 136} 137 138#define INSN_OP(x) ((x) << 30) 139#define INSN_OP2(x) ((x) << 22) 140#define INSN_OP3(x) ((x) << 19) 141#define INSN_OPF(x) ((x) << 5) 142#define INSN_RD(x) ((x) << 25) 143#define INSN_RS1(x) ((x) << 14) 144#define INSN_RS2(x) (x) 145#define INSN_ASI(x) ((x) << 5) 146 147#define INSN_IMM10(x) ((1 << 13) | ((x) & 0x3ff)) 148#define INSN_IMM11(x) ((1 << 13) | ((x) & 0x7ff)) 149#define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff)) 150#define INSN_OFF16(x) ((((x) >> 2) & 0x3fff) | ((((x) >> 16) & 3) << 20)) 151#define INSN_OFF19(x) (((x) >> 2) & 0x07ffff) 152#define INSN_COND(x) ((x) << 25) 153 154#define COND_N 0x0 155#define COND_E 0x1 156#define COND_LE 0x2 157#define COND_L 0x3 158#define COND_LEU 0x4 159#define COND_CS 0x5 160#define COND_NEG 0x6 161#define COND_VS 0x7 162#define COND_A 0x8 163#define COND_NE 0x9 164#define COND_G 0xa 165#define COND_GE 0xb 166#define COND_GU 0xc 167#define COND_CC 0xd 168#define COND_POS 0xe 169#define COND_VC 0xf 170#define BA (INSN_OP(0) | INSN_COND(COND_A) | INSN_OP2(0x2)) 171 172#define RCOND_Z 1 173#define RCOND_LEZ 2 174#define RCOND_LZ 3 175#define RCOND_NZ 5 176#define RCOND_GZ 6 177#define RCOND_GEZ 7 178 179#define MOVCC_ICC (1 << 18) 180#define MOVCC_XCC (1 << 18 | 1 << 12) 181 182#define BPCC_ICC 0 183#define BPCC_XCC (2 << 20) 184#define BPCC_PT (1 << 19) 185#define BPCC_PN 0 186#define BPCC_A (1 << 29) 187 188#define BPR_PT BPCC_PT 189 190#define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00)) 191#define ARITH_ADDCC (INSN_OP(2) | INSN_OP3(0x10)) 192#define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01)) 193#define ARITH_ANDCC (INSN_OP(2) | INSN_OP3(0x11)) 194#define ARITH_ANDN (INSN_OP(2) | INSN_OP3(0x05)) 195#define ARITH_OR (INSN_OP(2) | INSN_OP3(0x02)) 196#define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12)) 197#define ARITH_ORN (INSN_OP(2) | INSN_OP3(0x06)) 198#define ARITH_XOR (INSN_OP(2) | INSN_OP3(0x03)) 199#define ARITH_SUB (INSN_OP(2) | INSN_OP3(0x04)) 200#define ARITH_SUBCC (INSN_OP(2) | INSN_OP3(0x14)) 201#define ARITH_ADDC (INSN_OP(2) | INSN_OP3(0x08)) 202#define ARITH_ADDCCC (INSN_OP(2) | INSN_OP3(0x18)) 203#define ARITH_SUBC (INSN_OP(2) | INSN_OP3(0x0c)) 204#define ARITH_SUBCCC (INSN_OP(2) | INSN_OP3(0x1c)) 205#define ARITH_UMUL (INSN_OP(2) | INSN_OP3(0x0a)) 206#define ARITH_SMUL (INSN_OP(2) | INSN_OP3(0x0b)) 207#define ARITH_UDIV (INSN_OP(2) | INSN_OP3(0x0e)) 208#define ARITH_SDIV (INSN_OP(2) | INSN_OP3(0x0f)) 209#define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09)) 210#define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d)) 211#define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d)) 212#define ARITH_MOVCC (INSN_OP(2) | INSN_OP3(0x2c)) 213#define ARITH_MOVR (INSN_OP(2) | INSN_OP3(0x2f)) 214 215#define ARITH_ADDXC (INSN_OP(2) | INSN_OP3(0x36) | INSN_OPF(0x11)) 216#define ARITH_ADDXCCC (INSN_OP(2) | INSN_OP3(0x36) | INSN_OPF(0x13)) 217#define ARITH_UMULXHI (INSN_OP(2) | INSN_OP3(0x36) | INSN_OPF(0x16)) 218 219#define SHIFT_SLL (INSN_OP(2) | INSN_OP3(0x25)) 220#define SHIFT_SRL (INSN_OP(2) | INSN_OP3(0x26)) 221#define SHIFT_SRA (INSN_OP(2) | INSN_OP3(0x27)) 222 223#define SHIFT_SLLX (INSN_OP(2) | INSN_OP3(0x25) | (1 << 12)) 224#define SHIFT_SRLX (INSN_OP(2) | INSN_OP3(0x26) | (1 << 12)) 225#define SHIFT_SRAX (INSN_OP(2) | INSN_OP3(0x27) | (1 << 12)) 226 227#define RDY (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(0)) 228#define WRY (INSN_OP(2) | INSN_OP3(0x30) | INSN_RD(0)) 229#define WRCCR (INSN_OP(2) | INSN_OP3(0x30) | INSN_RD(2)) 230#define JMPL (INSN_OP(2) | INSN_OP3(0x38)) 231#define RETURN (INSN_OP(2) | INSN_OP3(0x39)) 232#define SAVE (INSN_OP(2) | INSN_OP3(0x3c)) 233#define RESTORE (INSN_OP(2) | INSN_OP3(0x3d)) 234#define SETHI (INSN_OP(0) | INSN_OP2(0x4)) 235#define CALL INSN_OP(1) 236#define LDUB (INSN_OP(3) | INSN_OP3(0x01)) 237#define LDSB (INSN_OP(3) | INSN_OP3(0x09)) 238#define LDUH (INSN_OP(3) | INSN_OP3(0x02)) 239#define LDSH (INSN_OP(3) | INSN_OP3(0x0a)) 240#define LDUW (INSN_OP(3) | INSN_OP3(0x00)) 241#define LDSW (INSN_OP(3) | INSN_OP3(0x08)) 242#define LDX (INSN_OP(3) | INSN_OP3(0x0b)) 243#define STB (INSN_OP(3) | INSN_OP3(0x05)) 244#define STH (INSN_OP(3) | INSN_OP3(0x06)) 245#define STW (INSN_OP(3) | INSN_OP3(0x04)) 246#define STX (INSN_OP(3) | INSN_OP3(0x0e)) 247#define LDUBA (INSN_OP(3) | INSN_OP3(0x11)) 248#define LDSBA (INSN_OP(3) | INSN_OP3(0x19)) 249#define LDUHA (INSN_OP(3) | INSN_OP3(0x12)) 250#define LDSHA (INSN_OP(3) | INSN_OP3(0x1a)) 251#define LDUWA (INSN_OP(3) | INSN_OP3(0x10)) 252#define LDSWA (INSN_OP(3) | INSN_OP3(0x18)) 253#define LDXA (INSN_OP(3) | INSN_OP3(0x1b)) 254#define STBA (INSN_OP(3) | INSN_OP3(0x15)) 255#define STHA (INSN_OP(3) | INSN_OP3(0x16)) 256#define STWA (INSN_OP(3) | INSN_OP3(0x14)) 257#define STXA (INSN_OP(3) | INSN_OP3(0x1e)) 258 259#define MEMBAR (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(15) | (1 << 13)) 260 261#define NOP (SETHI | INSN_RD(TCG_REG_G0) | 0) 262 263#ifndef ASI_PRIMARY_LITTLE 264#define ASI_PRIMARY_LITTLE 0x88 265#endif 266 267#define LDUH_LE (LDUHA | INSN_ASI(ASI_PRIMARY_LITTLE)) 268#define LDSH_LE (LDSHA | INSN_ASI(ASI_PRIMARY_LITTLE)) 269#define LDUW_LE (LDUWA | INSN_ASI(ASI_PRIMARY_LITTLE)) 270#define LDSW_LE (LDSWA | INSN_ASI(ASI_PRIMARY_LITTLE)) 271#define LDX_LE (LDXA | INSN_ASI(ASI_PRIMARY_LITTLE)) 272 273#define STH_LE (STHA | INSN_ASI(ASI_PRIMARY_LITTLE)) 274#define STW_LE (STWA | INSN_ASI(ASI_PRIMARY_LITTLE)) 275#define STX_LE (STXA | INSN_ASI(ASI_PRIMARY_LITTLE)) 276 277#ifndef use_vis3_instructions 278bool use_vis3_instructions; 279#endif 280 281static bool check_fit_i64(int64_t val, unsigned int bits) 282{ 283 return val == sextract64(val, 0, bits); 284} 285 286static bool check_fit_i32(int32_t val, unsigned int bits) 287{ 288 return val == sextract32(val, 0, bits); 289} 290 291#define check_fit_tl check_fit_i64 292#define check_fit_ptr check_fit_i64 293 294static bool patch_reloc(tcg_insn_unit *src_rw, int type, 295 intptr_t value, intptr_t addend) 296{ 297 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 298 uint32_t insn = *src_rw; 299 intptr_t pcrel; 300 301 value += addend; 302 pcrel = tcg_ptr_byte_diff((tcg_insn_unit *)value, src_rx); 303 304 switch (type) { 305 case R_SPARC_WDISP16: 306 if (!check_fit_ptr(pcrel >> 2, 16)) { 307 return false; 308 } 309 insn &= ~INSN_OFF16(-1); 310 insn |= INSN_OFF16(pcrel); 311 break; 312 case R_SPARC_WDISP19: 313 if (!check_fit_ptr(pcrel >> 2, 19)) { 314 return false; 315 } 316 insn &= ~INSN_OFF19(-1); 317 insn |= INSN_OFF19(pcrel); 318 break; 319 case R_SPARC_13: 320 if (!check_fit_ptr(value, 13)) { 321 return false; 322 } 323 insn &= ~INSN_IMM13(-1); 324 insn |= INSN_IMM13(value); 325 break; 326 default: 327 g_assert_not_reached(); 328 } 329 330 *src_rw = insn; 331 return true; 332} 333 334/* test if a constant matches the constraint */ 335static bool tcg_target_const_match(int64_t val, int ct, 336 TCGType type, TCGCond cond, int vece) 337{ 338 if (ct & TCG_CT_CONST) { 339 return 1; 340 } 341 342 if (type == TCG_TYPE_I32) { 343 val = (int32_t)val; 344 } 345 346 if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11)) { 347 return 1; 348 } else if ((ct & TCG_CT_CONST_S13) && check_fit_tl(val, 13)) { 349 return 1; 350 } else { 351 return 0; 352 } 353} 354 355static void tcg_out_nop(TCGContext *s) 356{ 357 tcg_out32(s, NOP); 358} 359 360static void tcg_out_arith(TCGContext *s, TCGReg rd, TCGReg rs1, 361 TCGReg rs2, int op) 362{ 363 tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | INSN_RS2(rs2)); 364} 365 366static void tcg_out_arithi(TCGContext *s, TCGReg rd, TCGReg rs1, 367 int32_t offset, int op) 368{ 369 tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | INSN_IMM13(offset)); 370} 371 372static void tcg_out_arithc(TCGContext *s, TCGReg rd, TCGReg rs1, 373 int32_t val2, int val2const, int op) 374{ 375 tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) 376 | (val2const ? INSN_IMM13(val2) : INSN_RS2(val2))); 377} 378 379static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 380{ 381 if (ret != arg) { 382 tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR); 383 } 384 return true; 385} 386 387static void tcg_out_mov_delay(TCGContext *s, TCGReg ret, TCGReg arg) 388{ 389 if (ret != arg) { 390 tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR); 391 } else { 392 tcg_out_nop(s); 393 } 394} 395 396static void tcg_out_sethi(TCGContext *s, TCGReg ret, uint32_t arg) 397{ 398 tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10)); 399} 400 401/* A 13-bit constant sign-extended to 64 bits. */ 402static void tcg_out_movi_s13(TCGContext *s, TCGReg ret, int32_t arg) 403{ 404 tcg_out_arithi(s, ret, TCG_REG_G0, arg, ARITH_OR); 405} 406 407/* A 32-bit constant sign-extended to 64 bits. */ 408static void tcg_out_movi_s32(TCGContext *s, TCGReg ret, int32_t arg) 409{ 410 tcg_out_sethi(s, ret, ~arg); 411 tcg_out_arithi(s, ret, ret, (arg & 0x3ff) | -0x400, ARITH_XOR); 412} 413 414/* A 32-bit constant zero-extended to 64 bits. */ 415static void tcg_out_movi_u32(TCGContext *s, TCGReg ret, uint32_t arg) 416{ 417 tcg_out_sethi(s, ret, arg); 418 if (arg & 0x3ff) { 419 tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR); 420 } 421} 422 423static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, 424 tcg_target_long arg, bool in_prologue, 425 TCGReg scratch) 426{ 427 tcg_target_long hi, lo = (int32_t)arg; 428 tcg_target_long test, lsb; 429 430 /* A 13-bit constant sign-extended to 64-bits. */ 431 if (check_fit_tl(arg, 13)) { 432 tcg_out_movi_s13(s, ret, arg); 433 return; 434 } 435 436 /* A 32-bit constant, or 32-bit zero-extended to 64-bits. */ 437 if (type == TCG_TYPE_I32 || arg == (uint32_t)arg) { 438 tcg_out_movi_u32(s, ret, arg); 439 return; 440 } 441 442 /* A 13-bit constant relative to the TB. */ 443 if (!in_prologue) { 444 test = tcg_tbrel_diff(s, (void *)arg); 445 if (check_fit_ptr(test, 13)) { 446 tcg_out_arithi(s, ret, TCG_REG_TB, test, ARITH_ADD); 447 return; 448 } 449 } 450 451 /* A 32-bit constant sign-extended to 64-bits. */ 452 if (arg == lo) { 453 tcg_out_movi_s32(s, ret, arg); 454 return; 455 } 456 457 /* A 32-bit constant, shifted. */ 458 lsb = ctz64(arg); 459 test = (tcg_target_long)arg >> lsb; 460 if (lsb > 10 && test == extract64(test, 0, 21)) { 461 tcg_out_sethi(s, ret, test << 10); 462 tcg_out_arithi(s, ret, ret, lsb - 10, SHIFT_SLLX); 463 return; 464 } else if (test == (uint32_t)test || test == (int32_t)test) { 465 tcg_out_movi_int(s, TCG_TYPE_I64, ret, test, in_prologue, scratch); 466 tcg_out_arithi(s, ret, ret, lsb, SHIFT_SLLX); 467 return; 468 } 469 470 /* Use the constant pool, if possible. */ 471 if (!in_prologue) { 472 new_pool_label(s, arg, R_SPARC_13, s->code_ptr, 473 tcg_tbrel_diff(s, NULL)); 474 tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(TCG_REG_TB)); 475 return; 476 } 477 478 /* A 64-bit constant decomposed into 2 32-bit pieces. */ 479 if (check_fit_i32(lo, 13)) { 480 hi = (arg - lo) >> 32; 481 tcg_out_movi_u32(s, ret, hi); 482 tcg_out_arithi(s, ret, ret, 32, SHIFT_SLLX); 483 tcg_out_arithi(s, ret, ret, lo, ARITH_ADD); 484 } else { 485 hi = arg >> 32; 486 tcg_out_movi_u32(s, ret, hi); 487 tcg_out_movi_u32(s, scratch, lo); 488 tcg_out_arithi(s, ret, ret, 32, SHIFT_SLLX); 489 tcg_out_arith(s, ret, ret, scratch, ARITH_OR); 490 } 491} 492 493static void tcg_out_movi(TCGContext *s, TCGType type, 494 TCGReg ret, tcg_target_long arg) 495{ 496 tcg_debug_assert(ret != TCG_REG_T3); 497 tcg_out_movi_int(s, type, ret, arg, false, TCG_REG_T3); 498} 499 500static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) 501{ 502 g_assert_not_reached(); 503} 504 505static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) 506{ 507 g_assert_not_reached(); 508} 509 510static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rs) 511{ 512 tcg_out_arithi(s, rd, rs, 0xff, ARITH_AND); 513} 514 515static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rs) 516{ 517 tcg_out_arithi(s, rd, rs, 16, SHIFT_SLL); 518 tcg_out_arithi(s, rd, rd, 16, SHIFT_SRL); 519} 520 521static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rs) 522{ 523 tcg_out_arithi(s, rd, rs, 0, SHIFT_SRA); 524} 525 526static void tcg_out_ext32u(TCGContext *s, TCGReg rd, TCGReg rs) 527{ 528 tcg_out_arithi(s, rd, rs, 0, SHIFT_SRL); 529} 530 531static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) 532{ 533 tcg_out_ext32s(s, rd, rs); 534} 535 536static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) 537{ 538 tcg_out_ext32u(s, rd, rs); 539} 540 541static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rs) 542{ 543 tcg_out_ext32u(s, rd, rs); 544} 545 546static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 547{ 548 return false; 549} 550 551static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 552 tcg_target_long imm) 553{ 554 /* This function is only used for passing structs by reference. */ 555 g_assert_not_reached(); 556} 557 558static void tcg_out_ldst_rr(TCGContext *s, TCGReg data, TCGReg a1, 559 TCGReg a2, int op) 560{ 561 tcg_out32(s, op | INSN_RD(data) | INSN_RS1(a1) | INSN_RS2(a2)); 562} 563 564static void tcg_out_ldst(TCGContext *s, TCGReg ret, TCGReg addr, 565 intptr_t offset, int op) 566{ 567 if (check_fit_ptr(offset, 13)) { 568 tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(addr) | 569 INSN_IMM13(offset)); 570 } else { 571 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, offset); 572 tcg_out_ldst_rr(s, ret, addr, TCG_REG_T1, op); 573 } 574} 575 576static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, 577 TCGReg arg1, intptr_t arg2) 578{ 579 tcg_out_ldst(s, ret, arg1, arg2, (type == TCG_TYPE_I32 ? LDUW : LDX)); 580} 581 582static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 583 TCGReg arg1, intptr_t arg2) 584{ 585 tcg_out_ldst(s, arg, arg1, arg2, (type == TCG_TYPE_I32 ? STW : STX)); 586} 587 588static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 589 TCGReg base, intptr_t ofs) 590{ 591 if (val == 0) { 592 tcg_out_st(s, type, TCG_REG_G0, base, ofs); 593 return true; 594 } 595 return false; 596} 597 598static void tcg_out_sety(TCGContext *s, TCGReg rs) 599{ 600 tcg_out32(s, WRY | INSN_RS1(TCG_REG_G0) | INSN_RS2(rs)); 601} 602 603static const uint8_t tcg_cond_to_bcond[16] = { 604 [TCG_COND_EQ] = COND_E, 605 [TCG_COND_NE] = COND_NE, 606 [TCG_COND_TSTEQ] = COND_E, 607 [TCG_COND_TSTNE] = COND_NE, 608 [TCG_COND_LT] = COND_L, 609 [TCG_COND_GE] = COND_GE, 610 [TCG_COND_LE] = COND_LE, 611 [TCG_COND_GT] = COND_G, 612 [TCG_COND_LTU] = COND_CS, 613 [TCG_COND_GEU] = COND_CC, 614 [TCG_COND_LEU] = COND_LEU, 615 [TCG_COND_GTU] = COND_GU, 616}; 617 618static const uint8_t tcg_cond_to_rcond[16] = { 619 [TCG_COND_EQ] = RCOND_Z, 620 [TCG_COND_NE] = RCOND_NZ, 621 [TCG_COND_LT] = RCOND_LZ, 622 [TCG_COND_GT] = RCOND_GZ, 623 [TCG_COND_LE] = RCOND_LEZ, 624 [TCG_COND_GE] = RCOND_GEZ 625}; 626 627static void tcg_out_bpcc0(TCGContext *s, int scond, int flags, int off19) 628{ 629 tcg_out32(s, INSN_OP(0) | INSN_OP2(1) | INSN_COND(scond) | flags | off19); 630} 631 632static void tcg_out_bpcc(TCGContext *s, int scond, int flags, TCGLabel *l) 633{ 634 int off19 = 0; 635 636 if (l->has_value) { 637 off19 = INSN_OFF19(tcg_pcrel_diff(s, l->u.value_ptr)); 638 } else { 639 tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP19, l, 0); 640 } 641 tcg_out_bpcc0(s, scond, flags, off19); 642} 643 644static void tcg_out_br(TCGContext *s, TCGLabel *l) 645{ 646 tcg_out_bpcc(s, COND_A, BPCC_PT, l); 647 tcg_out_nop(s); 648} 649 650static void tcg_out_cmp(TCGContext *s, TCGCond cond, 651 TCGReg c1, int32_t c2, int c2const) 652{ 653 tcg_out_arithc(s, TCG_REG_G0, c1, c2, c2const, 654 is_tst_cond(cond) ? ARITH_ANDCC : ARITH_SUBCC); 655} 656 657static void tcg_out_brcond_i32(TCGContext *s, TCGCond cond, TCGReg arg1, 658 int32_t arg2, int const_arg2, TCGLabel *l) 659{ 660 tcg_out_cmp(s, cond, arg1, arg2, const_arg2); 661 tcg_out_bpcc(s, tcg_cond_to_bcond[cond], BPCC_ICC | BPCC_PT, l); 662 tcg_out_nop(s); 663} 664 665static void tcg_out_movcc(TCGContext *s, int scond, int cc, TCGReg ret, 666 int32_t v1, int v1const) 667{ 668 tcg_out32(s, ARITH_MOVCC | cc | INSN_RD(ret) | INSN_RS1(scond) 669 | (v1const ? INSN_IMM11(v1) : INSN_RS2(v1))); 670} 671 672static void tcg_out_movcond_i32(TCGContext *s, TCGCond cond, TCGReg ret, 673 TCGReg c1, int32_t c2, int c2const, 674 int32_t v1, int v1const) 675{ 676 tcg_out_cmp(s, cond, c1, c2, c2const); 677 tcg_out_movcc(s, tcg_cond_to_bcond[cond], MOVCC_ICC, ret, v1, v1const); 678} 679 680static void tcg_out_brcond_i64(TCGContext *s, TCGCond cond, TCGReg arg1, 681 int32_t arg2, int const_arg2, TCGLabel *l) 682{ 683 /* For 64-bit signed comparisons vs zero, we can avoid the compare. */ 684 int rcond = tcg_cond_to_rcond[cond]; 685 if (arg2 == 0 && rcond) { 686 int off16 = 0; 687 688 if (l->has_value) { 689 off16 = INSN_OFF16(tcg_pcrel_diff(s, l->u.value_ptr)); 690 } else { 691 tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP16, l, 0); 692 } 693 tcg_out32(s, INSN_OP(0) | INSN_OP2(3) | BPR_PT | INSN_RS1(arg1) 694 | INSN_COND(rcond) | off16); 695 } else { 696 tcg_out_cmp(s, cond, arg1, arg2, const_arg2); 697 tcg_out_bpcc(s, tcg_cond_to_bcond[cond], BPCC_XCC | BPCC_PT, l); 698 } 699 tcg_out_nop(s); 700} 701 702static void tcg_out_movr(TCGContext *s, int rcond, TCGReg ret, TCGReg c1, 703 int32_t v1, int v1const) 704{ 705 tcg_out32(s, ARITH_MOVR | INSN_RD(ret) | INSN_RS1(c1) | (rcond << 10) 706 | (v1const ? INSN_IMM10(v1) : INSN_RS2(v1))); 707} 708 709static void tcg_out_movcond_i64(TCGContext *s, TCGCond cond, TCGReg ret, 710 TCGReg c1, int32_t c2, int c2const, 711 int32_t v1, int v1const) 712{ 713 /* For 64-bit signed comparisons vs zero, we can avoid the compare. 714 Note that the immediate range is one bit smaller, so we must check 715 for that as well. */ 716 int rcond = tcg_cond_to_rcond[cond]; 717 if (c2 == 0 && rcond && (!v1const || check_fit_i32(v1, 10))) { 718 tcg_out_movr(s, rcond, ret, c1, v1, v1const); 719 } else { 720 tcg_out_cmp(s, cond, c1, c2, c2const); 721 tcg_out_movcc(s, tcg_cond_to_bcond[cond], MOVCC_XCC, ret, v1, v1const); 722 } 723} 724 725static void tcg_out_setcond_i32(TCGContext *s, TCGCond cond, TCGReg ret, 726 TCGReg c1, int32_t c2, bool c2const, bool neg) 727{ 728 /* For 32-bit comparisons, we can play games with ADDC/SUBC. */ 729 switch (cond) { 730 case TCG_COND_LTU: 731 case TCG_COND_GEU: 732 /* The result of the comparison is in the carry bit. */ 733 break; 734 735 case TCG_COND_EQ: 736 case TCG_COND_NE: 737 /* For equality, we can transform to inequality vs zero. */ 738 if (c2 != 0) { 739 tcg_out_arithc(s, TCG_REG_T1, c1, c2, c2const, ARITH_XOR); 740 c2 = TCG_REG_T1; 741 } else { 742 c2 = c1; 743 } 744 c1 = TCG_REG_G0, c2const = 0; 745 cond = (cond == TCG_COND_EQ ? TCG_COND_GEU : TCG_COND_LTU); 746 break; 747 748 case TCG_COND_TSTEQ: 749 case TCG_COND_TSTNE: 750 /* Transform to inequality vs zero. */ 751 tcg_out_arithc(s, TCG_REG_T1, c1, c2, c2const, ARITH_AND); 752 c1 = TCG_REG_G0; 753 c2 = TCG_REG_T1, c2const = 0; 754 cond = (cond == TCG_COND_TSTEQ ? TCG_COND_GEU : TCG_COND_LTU); 755 break; 756 757 case TCG_COND_GTU: 758 case TCG_COND_LEU: 759 /* If we don't need to load a constant into a register, we can 760 swap the operands on GTU/LEU. There's no benefit to loading 761 the constant into a temporary register. */ 762 if (!c2const || c2 == 0) { 763 TCGReg t = c1; 764 c1 = c2; 765 c2 = t; 766 c2const = 0; 767 cond = tcg_swap_cond(cond); 768 break; 769 } 770 /* FALLTHRU */ 771 772 default: 773 tcg_out_cmp(s, cond, c1, c2, c2const); 774 tcg_out_movi_s13(s, ret, 0); 775 tcg_out_movcc(s, tcg_cond_to_bcond[cond], 776 MOVCC_ICC, ret, neg ? -1 : 1, 1); 777 return; 778 } 779 780 tcg_out_cmp(s, cond, c1, c2, c2const); 781 if (cond == TCG_COND_LTU) { 782 if (neg) { 783 /* 0 - 0 - C = -C = (C ? -1 : 0) */ 784 tcg_out_arithi(s, ret, TCG_REG_G0, 0, ARITH_SUBC); 785 } else { 786 /* 0 + 0 + C = C = (C ? 1 : 0) */ 787 tcg_out_arithi(s, ret, TCG_REG_G0, 0, ARITH_ADDC); 788 } 789 } else { 790 if (neg) { 791 /* 0 + -1 + C = C - 1 = (C ? 0 : -1) */ 792 tcg_out_arithi(s, ret, TCG_REG_G0, -1, ARITH_ADDC); 793 } else { 794 /* 0 - -1 - C = 1 - C = (C ? 0 : 1) */ 795 tcg_out_arithi(s, ret, TCG_REG_G0, -1, ARITH_SUBC); 796 } 797 } 798} 799 800static void tcg_out_setcond_i64(TCGContext *s, TCGCond cond, TCGReg ret, 801 TCGReg c1, int32_t c2, bool c2const, bool neg) 802{ 803 int rcond; 804 805 if (use_vis3_instructions && !neg) { 806 switch (cond) { 807 case TCG_COND_NE: 808 if (c2 != 0) { 809 break; 810 } 811 c2 = c1, c2const = 0, c1 = TCG_REG_G0; 812 /* FALLTHRU */ 813 case TCG_COND_LTU: 814 tcg_out_cmp(s, cond, c1, c2, c2const); 815 tcg_out_arith(s, ret, TCG_REG_G0, TCG_REG_G0, ARITH_ADDXC); 816 return; 817 default: 818 break; 819 } 820 } 821 822 /* For 64-bit signed comparisons vs zero, we can avoid the compare 823 if the input does not overlap the output. */ 824 rcond = tcg_cond_to_rcond[cond]; 825 if (c2 == 0 && rcond && c1 != ret) { 826 tcg_out_movi_s13(s, ret, 0); 827 tcg_out_movr(s, rcond, ret, c1, neg ? -1 : 1, 1); 828 } else { 829 tcg_out_cmp(s, cond, c1, c2, c2const); 830 tcg_out_movi_s13(s, ret, 0); 831 tcg_out_movcc(s, tcg_cond_to_bcond[cond], 832 MOVCC_XCC, ret, neg ? -1 : 1, 1); 833 } 834} 835 836static void tcg_out_brcond(TCGContext *s, TCGType type, TCGCond cond, 837 TCGReg arg1, TCGArg arg2, bool const_arg2, 838 TCGLabel *l) 839{ 840 if (type == TCG_TYPE_I32) { 841 tcg_out_brcond_i32(s, cond, arg1, arg2, const_arg2, l); 842 } else { 843 tcg_out_brcond_i64(s, cond, arg1, arg2, const_arg2, l); 844 } 845} 846 847static void tgen_brcond(TCGContext *s, TCGType type, TCGCond cond, 848 TCGReg arg1, TCGReg arg2, TCGLabel *l) 849{ 850 tcg_out_brcond(s, type, cond, arg1, arg2, false, l); 851} 852 853static void tgen_brcondi(TCGContext *s, TCGType type, TCGCond cond, 854 TCGReg arg1, tcg_target_long arg2, TCGLabel *l) 855{ 856 tcg_out_brcond(s, type, cond, arg1, arg2, true, l); 857} 858 859static const TCGOutOpBrcond outop_brcond = { 860 .base.static_constraint = C_O0_I2(r, rJ), 861 .out_rr = tgen_brcond, 862 .out_ri = tgen_brcondi, 863}; 864 865static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond, 866 TCGReg ret, TCGReg c1, 867 TCGArg c2, bool c2const, bool neg) 868{ 869 if (type == TCG_TYPE_I32) { 870 tcg_out_setcond_i32(s, cond, ret, c1, c2, c2const, neg); 871 } else { 872 tcg_out_setcond_i64(s, cond, ret, c1, c2, c2const, neg); 873 } 874} 875 876static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, 877 TCGReg dest, TCGReg arg1, TCGReg arg2) 878{ 879 tcg_out_setcond(s, type, cond, dest, arg1, arg2, false, false); 880} 881 882static void tgen_setcondi(TCGContext *s, TCGType type, TCGCond cond, 883 TCGReg dest, TCGReg arg1, tcg_target_long arg2) 884{ 885 tcg_out_setcond(s, type, cond, dest, arg1, arg2, true, false); 886} 887 888static const TCGOutOpSetcond outop_setcond = { 889 .base.static_constraint = C_O1_I2(r, r, rJ), 890 .out_rrr = tgen_setcond, 891 .out_rri = tgen_setcondi, 892}; 893 894static void tgen_negsetcond(TCGContext *s, TCGType type, TCGCond cond, 895 TCGReg dest, TCGReg arg1, TCGReg arg2) 896{ 897 tcg_out_setcond(s, type, cond, dest, arg1, arg2, false, true); 898} 899 900static void tgen_negsetcondi(TCGContext *s, TCGType type, TCGCond cond, 901 TCGReg dest, TCGReg arg1, tcg_target_long arg2) 902{ 903 tcg_out_setcond(s, type, cond, dest, arg1, arg2, true, true); 904} 905 906static const TCGOutOpSetcond outop_negsetcond = { 907 .base.static_constraint = C_O1_I2(r, r, rJ), 908 .out_rrr = tgen_negsetcond, 909 .out_rri = tgen_negsetcondi, 910}; 911 912static void tgen_movcond(TCGContext *s, TCGType type, TCGCond cond, 913 TCGReg ret, TCGReg c1, TCGArg c2, bool c2const, 914 TCGArg v1, bool v1const, TCGArg v2, bool v2consf) 915{ 916 if (type == TCG_TYPE_I32) { 917 tcg_out_movcond_i32(s, cond, ret, c1, c2, c2const, v1, v1const); 918 } else { 919 tcg_out_movcond_i64(s, cond, ret, c1, c2, c2const, v1, v1const); 920 } 921} 922 923static const TCGOutOpMovcond outop_movcond = { 924 .base.static_constraint = C_O1_I4(r, r, rJ, rI, 0), 925 .out = tgen_movcond, 926}; 927 928static void tcg_out_jmpl_const(TCGContext *s, const tcg_insn_unit *dest, 929 bool in_prologue, bool tail_call) 930{ 931 uintptr_t desti = (uintptr_t)dest; 932 933 tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_REG_T1, 934 desti & ~0xfff, in_prologue, TCG_REG_T2); 935 tcg_out_arithi(s, tail_call ? TCG_REG_G0 : TCG_REG_O7, 936 TCG_REG_T1, desti & 0xfff, JMPL); 937} 938 939static void tcg_out_call_nodelay(TCGContext *s, const tcg_insn_unit *dest, 940 bool in_prologue) 941{ 942 ptrdiff_t disp = tcg_pcrel_diff(s, dest); 943 944 if (disp == (int32_t)disp) { 945 tcg_out32(s, CALL | (uint32_t)disp >> 2); 946 } else { 947 tcg_out_jmpl_const(s, dest, in_prologue, false); 948 } 949} 950 951static void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest, 952 const TCGHelperInfo *info) 953{ 954 tcg_out_call_nodelay(s, dest, false); 955 tcg_out_nop(s); 956} 957 958static void tcg_out_mb(TCGContext *s, unsigned a0) 959{ 960 /* Note that the TCG memory order constants mirror the Sparc MEMBAR. */ 961 tcg_out32(s, MEMBAR | (a0 & TCG_MO_ALL)); 962} 963 964/* Generate global QEMU prologue and epilogue code */ 965static void tcg_target_qemu_prologue(TCGContext *s) 966{ 967 int tmp_buf_size, frame_size; 968 969 /* 970 * The TCG temp buffer is at the top of the frame, immediately 971 * below the frame pointer. Use the logical (aligned) offset here; 972 * the stack bias is applied in temp_allocate_frame(). 973 */ 974 tmp_buf_size = CPU_TEMP_BUF_NLONGS * (int)sizeof(long); 975 tcg_set_frame(s, TCG_REG_I6, -tmp_buf_size, tmp_buf_size); 976 977 /* 978 * TCG_TARGET_CALL_STACK_OFFSET includes the stack bias, but is 979 * otherwise the minimal frame usable by callees. 980 */ 981 frame_size = TCG_TARGET_CALL_STACK_OFFSET - TCG_TARGET_STACK_BIAS; 982 frame_size += TCG_STATIC_CALL_ARGS_SIZE + tmp_buf_size; 983 frame_size += TCG_TARGET_STACK_ALIGN - 1; 984 frame_size &= -TCG_TARGET_STACK_ALIGN; 985 tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) | 986 INSN_IMM13(-frame_size)); 987 988#ifndef CONFIG_SOFTMMU 989 if (guest_base != 0) { 990 tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, 991 guest_base, true, TCG_REG_T1); 992 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 993 } 994#endif 995 996 /* We choose TCG_REG_TB such that no move is required. */ 997 QEMU_BUILD_BUG_ON(TCG_REG_TB != TCG_REG_I1); 998 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); 999 1000 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I1, 0, JMPL); 1001 /* delay slot */ 1002 tcg_out_nop(s); 1003 1004 /* Epilogue for goto_ptr. */ 1005 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 1006 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); 1007 /* delay slot */ 1008 tcg_out_movi_s13(s, TCG_REG_O0, 0); 1009} 1010 1011static void tcg_out_tb_start(TCGContext *s) 1012{ 1013 /* nothing to do */ 1014} 1015 1016static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 1017{ 1018 int i; 1019 for (i = 0; i < count; ++i) { 1020 p[i] = NOP; 1021 } 1022} 1023 1024static const TCGLdstHelperParam ldst_helper_param = { 1025 .ntmp = 1, .tmp = { TCG_REG_T1 } 1026}; 1027 1028static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1029{ 1030 MemOp opc = get_memop(lb->oi); 1031 MemOp sgn; 1032 1033 if (!patch_reloc(lb->label_ptr[0], R_SPARC_WDISP19, 1034 (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 0)) { 1035 return false; 1036 } 1037 1038 /* Use inline tcg_out_ext32s; otherwise let the helper sign-extend. */ 1039 sgn = (opc & MO_SIZE) < MO_32 ? MO_SIGN : 0; 1040 1041 tcg_out_ld_helper_args(s, lb, &ldst_helper_param); 1042 tcg_out_call(s, qemu_ld_helpers[opc & (MO_SIZE | sgn)], NULL); 1043 tcg_out_ld_helper_ret(s, lb, sgn, &ldst_helper_param); 1044 1045 tcg_out_bpcc0(s, COND_A, BPCC_A | BPCC_PT, 0); 1046 return patch_reloc(s->code_ptr - 1, R_SPARC_WDISP19, 1047 (intptr_t)lb->raddr, 0); 1048} 1049 1050static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1051{ 1052 MemOp opc = get_memop(lb->oi); 1053 1054 if (!patch_reloc(lb->label_ptr[0], R_SPARC_WDISP19, 1055 (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 0)) { 1056 return false; 1057 } 1058 1059 tcg_out_st_helper_args(s, lb, &ldst_helper_param); 1060 tcg_out_call(s, qemu_st_helpers[opc & MO_SIZE], NULL); 1061 1062 tcg_out_bpcc0(s, COND_A, BPCC_A | BPCC_PT, 0); 1063 return patch_reloc(s->code_ptr - 1, R_SPARC_WDISP19, 1064 (intptr_t)lb->raddr, 0); 1065} 1066 1067typedef struct { 1068 TCGReg base; 1069 TCGReg index; 1070 TCGAtomAlign aa; 1071} HostAddress; 1072 1073bool tcg_target_has_memory_bswap(MemOp memop) 1074{ 1075 return true; 1076} 1077 1078/* We expect to use a 13-bit negative offset from ENV. */ 1079#define MIN_TLB_MASK_TABLE_OFS -(1 << 12) 1080 1081/* 1082 * For system-mode, perform the TLB load and compare. 1083 * For user-mode, perform any required alignment tests. 1084 * In both cases, return a TCGLabelQemuLdst structure if the slow path 1085 * is required and fill in @h with the host address for the fast path. 1086 */ 1087static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 1088 TCGReg addr_reg, MemOpIdx oi, 1089 bool is_ld) 1090{ 1091 TCGType addr_type = s->addr_type; 1092 TCGLabelQemuLdst *ldst = NULL; 1093 MemOp opc = get_memop(oi); 1094 MemOp s_bits = opc & MO_SIZE; 1095 unsigned a_mask; 1096 1097 /* We don't support unaligned accesses. */ 1098 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); 1099 h->aa.align = MAX(h->aa.align, s_bits); 1100 a_mask = (1u << h->aa.align) - 1; 1101 1102#ifdef CONFIG_SOFTMMU 1103 int mem_index = get_mmuidx(oi); 1104 int fast_off = tlb_mask_table_ofs(s, mem_index); 1105 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); 1106 int table_off = fast_off + offsetof(CPUTLBDescFast, table); 1107 int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read) 1108 : offsetof(CPUTLBEntry, addr_write); 1109 int add_off = offsetof(CPUTLBEntry, addend); 1110 int compare_mask; 1111 int cc; 1112 1113 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ 1114 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_T2, TCG_AREG0, mask_off); 1115 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_T3, TCG_AREG0, table_off); 1116 1117 /* Extract the page index, shifted into place for tlb index. */ 1118 tcg_out_arithi(s, TCG_REG_T1, addr_reg, 1119 s->page_bits - CPU_TLB_ENTRY_BITS, SHIFT_SRL); 1120 tcg_out_arith(s, TCG_REG_T1, TCG_REG_T1, TCG_REG_T2, ARITH_AND); 1121 1122 /* Add the tlb_table pointer, creating the CPUTLBEntry address into R2. */ 1123 tcg_out_arith(s, TCG_REG_T1, TCG_REG_T1, TCG_REG_T3, ARITH_ADD); 1124 1125 /* 1126 * Load the tlb comparator and the addend. 1127 * Always load the entire 64-bit comparator for simplicity. 1128 * We will ignore the high bits via BPCC_ICC below. 1129 */ 1130 tcg_out_ld(s, TCG_TYPE_I64, TCG_REG_T2, TCG_REG_T1, cmp_off); 1131 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_T1, TCG_REG_T1, add_off); 1132 h->base = TCG_REG_T1; 1133 1134 /* Mask out the page offset, except for the required alignment. */ 1135 compare_mask = s->page_mask | a_mask; 1136 if (check_fit_tl(compare_mask, 13)) { 1137 tcg_out_arithi(s, TCG_REG_T3, addr_reg, compare_mask, ARITH_AND); 1138 } else { 1139 tcg_out_movi_s32(s, TCG_REG_T3, compare_mask); 1140 tcg_out_arith(s, TCG_REG_T3, addr_reg, TCG_REG_T3, ARITH_AND); 1141 } 1142 tcg_out_cmp(s, TCG_COND_NE, TCG_REG_T2, TCG_REG_T3, 0); 1143 1144 ldst = new_ldst_label(s); 1145 ldst->is_ld = is_ld; 1146 ldst->oi = oi; 1147 ldst->addr_reg = addr_reg; 1148 ldst->label_ptr[0] = s->code_ptr; 1149 1150 /* bne,pn %[xi]cc, label0 */ 1151 cc = addr_type == TCG_TYPE_I32 ? BPCC_ICC : BPCC_XCC; 1152 tcg_out_bpcc0(s, COND_NE, BPCC_PN | cc, 0); 1153#else 1154 /* 1155 * If the size equals the required alignment, we can skip the test 1156 * and allow host SIGBUS to deliver SIGBUS to the guest. 1157 * Otherwise, test for at least natural alignment and defer 1158 * everything else to the helper functions. 1159 */ 1160 if (s_bits != memop_alignment_bits(opc)) { 1161 tcg_debug_assert(check_fit_tl(a_mask, 13)); 1162 tcg_out_arithi(s, TCG_REG_G0, addr_reg, a_mask, ARITH_ANDCC); 1163 1164 ldst = new_ldst_label(s); 1165 ldst->is_ld = is_ld; 1166 ldst->oi = oi; 1167 ldst->addr_reg = addr_reg; 1168 ldst->label_ptr[0] = s->code_ptr; 1169 1170 /* bne,pn %icc, label0 */ 1171 tcg_out_bpcc0(s, COND_NE, BPCC_PN | BPCC_ICC, 0); 1172 } 1173 h->base = guest_base ? TCG_GUEST_BASE_REG : TCG_REG_G0; 1174#endif 1175 1176 /* If the guest address must be zero-extended, do in the delay slot. */ 1177 if (addr_type == TCG_TYPE_I32) { 1178 tcg_out_ext32u(s, TCG_REG_T2, addr_reg); 1179 h->index = TCG_REG_T2; 1180 } else { 1181 if (ldst) { 1182 tcg_out_nop(s); 1183 } 1184 h->index = addr_reg; 1185 } 1186 return ldst; 1187} 1188 1189static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr, 1190 MemOpIdx oi, TCGType data_type) 1191{ 1192 static const int ld_opc[(MO_SSIZE | MO_BSWAP) + 1] = { 1193 [MO_UB] = LDUB, 1194 [MO_SB] = LDSB, 1195 [MO_UB | MO_LE] = LDUB, 1196 [MO_SB | MO_LE] = LDSB, 1197 1198 [MO_BEUW] = LDUH, 1199 [MO_BESW] = LDSH, 1200 [MO_BEUL] = LDUW, 1201 [MO_BESL] = LDSW, 1202 [MO_BEUQ] = LDX, 1203 [MO_BESQ] = LDX, 1204 1205 [MO_LEUW] = LDUH_LE, 1206 [MO_LESW] = LDSH_LE, 1207 [MO_LEUL] = LDUW_LE, 1208 [MO_LESL] = LDSW_LE, 1209 [MO_LEUQ] = LDX_LE, 1210 [MO_LESQ] = LDX_LE, 1211 }; 1212 1213 TCGLabelQemuLdst *ldst; 1214 HostAddress h; 1215 1216 ldst = prepare_host_addr(s, &h, addr, oi, true); 1217 1218 tcg_out_ldst_rr(s, data, h.base, h.index, 1219 ld_opc[get_memop(oi) & (MO_BSWAP | MO_SSIZE)]); 1220 1221 if (ldst) { 1222 ldst->type = data_type; 1223 ldst->datalo_reg = data; 1224 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1225 } 1226} 1227 1228static void tcg_out_qemu_st(TCGContext *s, TCGReg data, TCGReg addr, 1229 MemOpIdx oi, TCGType data_type) 1230{ 1231 static const int st_opc[(MO_SIZE | MO_BSWAP) + 1] = { 1232 [MO_UB] = STB, 1233 1234 [MO_BEUW] = STH, 1235 [MO_BEUL] = STW, 1236 [MO_BEUQ] = STX, 1237 1238 [MO_LEUW] = STH_LE, 1239 [MO_LEUL] = STW_LE, 1240 [MO_LEUQ] = STX_LE, 1241 }; 1242 1243 TCGLabelQemuLdst *ldst; 1244 HostAddress h; 1245 1246 ldst = prepare_host_addr(s, &h, addr, oi, false); 1247 1248 tcg_out_ldst_rr(s, data, h.base, h.index, 1249 st_opc[get_memop(oi) & (MO_BSWAP | MO_SIZE)]); 1250 1251 if (ldst) { 1252 ldst->type = data_type; 1253 ldst->datalo_reg = data; 1254 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1255 } 1256} 1257 1258static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) 1259{ 1260 if (check_fit_ptr(a0, 13)) { 1261 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); 1262 tcg_out_movi_s13(s, TCG_REG_O0, a0); 1263 return; 1264 } else { 1265 intptr_t tb_diff = tcg_tbrel_diff(s, (void *)a0); 1266 if (check_fit_ptr(tb_diff, 13)) { 1267 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); 1268 /* Note that TCG_REG_TB has been unwound to O1. */ 1269 tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O1, tb_diff, ARITH_ADD); 1270 return; 1271 } 1272 } 1273 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, a0 & ~0x3ff); 1274 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); 1275 tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O0, a0 & 0x3ff, ARITH_OR); 1276} 1277 1278static void tcg_out_goto_tb(TCGContext *s, int which) 1279{ 1280 ptrdiff_t off = tcg_tbrel_diff(s, (void *)get_jmp_target_addr(s, which)); 1281 1282 /* Load link and indirect branch. */ 1283 set_jmp_insn_offset(s, which); 1284 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TB, TCG_REG_TB, off); 1285 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_TB, 0, JMPL); 1286 /* delay slot */ 1287 tcg_out_nop(s); 1288 set_jmp_reset_offset(s, which); 1289 1290 /* 1291 * For the unlinked path of goto_tb, we need to reset TCG_REG_TB 1292 * to the beginning of this TB. 1293 */ 1294 off = -tcg_current_code_size(s); 1295 if (check_fit_i32(off, 13)) { 1296 tcg_out_arithi(s, TCG_REG_TB, TCG_REG_TB, off, ARITH_ADD); 1297 } else { 1298 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, off); 1299 tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB, TCG_REG_T1, ARITH_ADD); 1300 } 1301} 1302 1303static void tcg_out_goto_ptr(TCGContext *s, TCGReg a0) 1304{ 1305 tcg_out_arithi(s, TCG_REG_G0, a0, 0, JMPL); 1306 tcg_out_mov_delay(s, TCG_REG_TB, a0); 1307} 1308 1309void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1310 uintptr_t jmp_rx, uintptr_t jmp_rw) 1311{ 1312} 1313 1314 1315static void tgen_add(TCGContext *s, TCGType type, 1316 TCGReg a0, TCGReg a1, TCGReg a2) 1317{ 1318 tcg_out_arith(s, a0, a1, a2, ARITH_ADD); 1319} 1320 1321static void tgen_addi(TCGContext *s, TCGType type, 1322 TCGReg a0, TCGReg a1, tcg_target_long a2) 1323{ 1324 tcg_out_arithi(s, a0, a1, a2, ARITH_ADD); 1325} 1326 1327static const TCGOutOpBinary outop_add = { 1328 .base.static_constraint = C_O1_I2(r, r, rJ), 1329 .out_rrr = tgen_add, 1330 .out_rri = tgen_addi, 1331}; 1332 1333static void tgen_addco_rrr(TCGContext *s, TCGType type, 1334 TCGReg a0, TCGReg a1, TCGReg a2) 1335{ 1336 tcg_out_arith(s, a0, a1, a2, ARITH_ADDCC); 1337} 1338 1339static void tgen_addco_rri(TCGContext *s, TCGType type, 1340 TCGReg a0, TCGReg a1, tcg_target_long a2) 1341{ 1342 tcg_out_arithi(s, a0, a1, a2, ARITH_ADDCC); 1343} 1344 1345static const TCGOutOpBinary outop_addco = { 1346 .base.static_constraint = C_O1_I2(r, r, rJ), 1347 .out_rrr = tgen_addco_rrr, 1348 .out_rri = tgen_addco_rri, 1349}; 1350 1351static void tgen_addci_rrr(TCGContext *s, TCGType type, 1352 TCGReg a0, TCGReg a1, TCGReg a2) 1353{ 1354 if (type == TCG_TYPE_I32) { 1355 tcg_out_arith(s, a0, a1, a2, ARITH_ADDC); 1356 } else if (use_vis3_instructions) { 1357 tcg_out_arith(s, a0, a1, a2, ARITH_ADDXC); 1358 } else { 1359 tcg_out_arith(s, TCG_REG_T1, a1, a2, ARITH_ADD); /* for CC */ 1360 tcg_out_arithi(s, a0, TCG_REG_T1, 1, ARITH_ADD); /* for CS */ 1361 /* Select the correct result based on actual carry value. */ 1362 tcg_out_movcc(s, COND_CC, MOVCC_XCC, a0, TCG_REG_T1, false); 1363 } 1364} 1365 1366static void tgen_addci_rri(TCGContext *s, TCGType type, 1367 TCGReg a0, TCGReg a1, tcg_target_long a2) 1368{ 1369 if (type == TCG_TYPE_I32) { 1370 tcg_out_arithi(s, a0, a1, a2, ARITH_ADDC); 1371 return; 1372 } 1373 /* !use_vis3_instructions */ 1374 if (a2 != 0) { 1375 tcg_out_arithi(s, TCG_REG_T1, a1, a2, ARITH_ADD); /* for CC */ 1376 tcg_out_arithi(s, a0, TCG_REG_T1, 1, ARITH_ADD); /* for CS */ 1377 tcg_out_movcc(s, COND_CC, MOVCC_XCC, a0, TCG_REG_T1, false); 1378 } else if (a0 == a1) { 1379 tcg_out_arithi(s, TCG_REG_T1, a1, 1, ARITH_ADD); 1380 tcg_out_movcc(s, COND_CS, MOVCC_XCC, a0, TCG_REG_T1, false); 1381 } else { 1382 tcg_out_arithi(s, a0, a1, 1, ARITH_ADD); 1383 tcg_out_movcc(s, COND_CC, MOVCC_XCC, a0, a1, false); 1384 } 1385} 1386 1387static TCGConstraintSetIndex cset_addci(TCGType type, unsigned flags) 1388{ 1389 if (use_vis3_instructions && type == TCG_TYPE_I64) { 1390 /* Note that ADDXC doesn't accept immediates. */ 1391 return C_O1_I2(r, rz, rz); 1392 } 1393 return C_O1_I2(r, rz, rJ); 1394} 1395 1396static const TCGOutOpAddSubCarry outop_addci = { 1397 .base.static_constraint = C_Dynamic, 1398 .base.dynamic_constraint = cset_addci, 1399 .out_rrr = tgen_addci_rrr, 1400 .out_rri = tgen_addci_rri, 1401}; 1402 1403/* Copy %xcc.c to %icc.c */ 1404static void tcg_out_dup_xcc_c(TCGContext *s) 1405{ 1406 if (use_vis3_instructions) { 1407 tcg_out_arith(s, TCG_REG_T1, TCG_REG_G0, TCG_REG_G0, ARITH_ADDXC); 1408 } else { 1409 tcg_out_movi_s13(s, TCG_REG_T1, 0); 1410 tcg_out_movcc(s, COND_CS, MOVCC_XCC, TCG_REG_T1, 1, true); 1411 } 1412 /* Write carry-in into %icc via {0,1} + -1. */ 1413 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_T1, -1, ARITH_ADDCC); 1414} 1415 1416static void tgen_addcio_rrr(TCGContext *s, TCGType type, 1417 TCGReg a0, TCGReg a1, TCGReg a2) 1418{ 1419 if (type != TCG_TYPE_I32) { 1420 if (use_vis3_instructions) { 1421 tcg_out_arith(s, a0, a1, a2, ARITH_ADDXCCC); 1422 return; 1423 } 1424 tcg_out_dup_xcc_c(s); 1425 } 1426 tcg_out_arith(s, a0, a1, a2, ARITH_ADDCCC); 1427} 1428 1429static void tgen_addcio_rri(TCGContext *s, TCGType type, 1430 TCGReg a0, TCGReg a1, tcg_target_long a2) 1431{ 1432 if (type != TCG_TYPE_I32) { 1433 /* !use_vis3_instructions */ 1434 tcg_out_dup_xcc_c(s); 1435 } 1436 tcg_out_arithi(s, a0, a1, a2, ARITH_ADDCCC); 1437} 1438 1439static TCGConstraintSetIndex cset_addcio(TCGType type, unsigned flags) 1440{ 1441 if (use_vis3_instructions && type == TCG_TYPE_I64) { 1442 /* Note that ADDXCCC doesn't accept immediates. */ 1443 return C_O1_I2(r, rz, rz); 1444 } 1445 return C_O1_I2(r, rz, rJ); 1446} 1447 1448static const TCGOutOpBinary outop_addcio = { 1449 .base.static_constraint = C_Dynamic, 1450 .base.dynamic_constraint = cset_addcio, 1451 .out_rrr = tgen_addcio_rrr, 1452 .out_rri = tgen_addcio_rri, 1453}; 1454 1455static void tcg_out_set_carry(TCGContext *s) 1456{ 1457 /* 0x11 -> xcc = nzvC, icc = nzvC */ 1458 tcg_out_arithi(s, 0, TCG_REG_G0, 0x11, WRCCR); 1459} 1460 1461static void tgen_and(TCGContext *s, TCGType type, 1462 TCGReg a0, TCGReg a1, TCGReg a2) 1463{ 1464 tcg_out_arith(s, a0, a1, a2, ARITH_AND); 1465} 1466 1467static void tgen_andi(TCGContext *s, TCGType type, 1468 TCGReg a0, TCGReg a1, tcg_target_long a2) 1469{ 1470 tcg_out_arithi(s, a0, a1, a2, ARITH_AND); 1471} 1472 1473static const TCGOutOpBinary outop_and = { 1474 .base.static_constraint = C_O1_I2(r, r, rJ), 1475 .out_rrr = tgen_and, 1476 .out_rri = tgen_andi, 1477}; 1478 1479static void tgen_andc(TCGContext *s, TCGType type, 1480 TCGReg a0, TCGReg a1, TCGReg a2) 1481{ 1482 tcg_out_arith(s, a0, a1, a2, ARITH_ANDN); 1483} 1484 1485static const TCGOutOpBinary outop_andc = { 1486 .base.static_constraint = C_O1_I2(r, r, r), 1487 .out_rrr = tgen_andc, 1488}; 1489 1490static const TCGOutOpBinary outop_clz = { 1491 .base.static_constraint = C_NotImplemented, 1492}; 1493 1494static const TCGOutOpUnary outop_ctpop = { 1495 .base.static_constraint = C_NotImplemented, 1496}; 1497 1498static const TCGOutOpBinary outop_ctz = { 1499 .base.static_constraint = C_NotImplemented, 1500}; 1501 1502static void tgen_divs_rJ(TCGContext *s, TCGType type, 1503 TCGReg a0, TCGReg a1, TCGArg a2, bool c2) 1504{ 1505 uint32_t insn; 1506 1507 if (type == TCG_TYPE_I32) { 1508 /* Load Y with the sign extension of a1 to 64-bits. */ 1509 tcg_out_arithi(s, TCG_REG_T1, a1, 31, SHIFT_SRA); 1510 tcg_out_sety(s, TCG_REG_T1); 1511 insn = ARITH_SDIV; 1512 } else { 1513 insn = ARITH_SDIVX; 1514 } 1515 tcg_out_arithc(s, a0, a1, a2, c2, insn); 1516} 1517 1518static void tgen_divs(TCGContext *s, TCGType type, 1519 TCGReg a0, TCGReg a1, TCGReg a2) 1520{ 1521 tgen_divs_rJ(s, type, a0, a1, a2, false); 1522} 1523 1524static void tgen_divsi(TCGContext *s, TCGType type, 1525 TCGReg a0, TCGReg a1, tcg_target_long a2) 1526{ 1527 tgen_divs_rJ(s, type, a0, a1, a2, true); 1528} 1529 1530static const TCGOutOpBinary outop_divs = { 1531 .base.static_constraint = C_O1_I2(r, r, rJ), 1532 .out_rrr = tgen_divs, 1533 .out_rri = tgen_divsi, 1534}; 1535 1536static const TCGOutOpDivRem outop_divs2 = { 1537 .base.static_constraint = C_NotImplemented, 1538}; 1539 1540static void tgen_divu_rJ(TCGContext *s, TCGType type, 1541 TCGReg a0, TCGReg a1, TCGArg a2, bool c2) 1542{ 1543 uint32_t insn; 1544 1545 if (type == TCG_TYPE_I32) { 1546 /* Load Y with the zero extension to 64-bits. */ 1547 tcg_out_sety(s, TCG_REG_G0); 1548 insn = ARITH_UDIV; 1549 } else { 1550 insn = ARITH_UDIVX; 1551 } 1552 tcg_out_arithc(s, a0, a1, a2, c2, insn); 1553} 1554 1555static void tgen_divu(TCGContext *s, TCGType type, 1556 TCGReg a0, TCGReg a1, TCGReg a2) 1557{ 1558 tgen_divu_rJ(s, type, a0, a1, a2, false); 1559} 1560 1561static void tgen_divui(TCGContext *s, TCGType type, 1562 TCGReg a0, TCGReg a1, tcg_target_long a2) 1563{ 1564 tgen_divu_rJ(s, type, a0, a1, a2, true); 1565} 1566 1567static const TCGOutOpBinary outop_divu = { 1568 .base.static_constraint = C_O1_I2(r, r, rJ), 1569 .out_rrr = tgen_divu, 1570 .out_rri = tgen_divui, 1571}; 1572 1573static const TCGOutOpDivRem outop_divu2 = { 1574 .base.static_constraint = C_NotImplemented, 1575}; 1576 1577static const TCGOutOpBinary outop_eqv = { 1578 .base.static_constraint = C_NotImplemented, 1579}; 1580 1581static void tgen_extrh_i64_i32(TCGContext *s, TCGType t, TCGReg a0, TCGReg a1) 1582{ 1583 tcg_out_arithi(s, a0, a1, 32, SHIFT_SRLX); 1584} 1585 1586static const TCGOutOpUnary outop_extrh_i64_i32 = { 1587 .base.static_constraint = C_O1_I1(r, r), 1588 .out_rr = tgen_extrh_i64_i32, 1589}; 1590 1591static void tgen_mul(TCGContext *s, TCGType type, 1592 TCGReg a0, TCGReg a1, TCGReg a2) 1593{ 1594 uint32_t insn = type == TCG_TYPE_I32 ? ARITH_UMUL : ARITH_MULX; 1595 tcg_out_arith(s, a0, a1, a2, insn); 1596} 1597 1598static void tgen_muli(TCGContext *s, TCGType type, 1599 TCGReg a0, TCGReg a1, tcg_target_long a2) 1600{ 1601 uint32_t insn = type == TCG_TYPE_I32 ? ARITH_UMUL : ARITH_MULX; 1602 tcg_out_arithi(s, a0, a1, a2, insn); 1603} 1604 1605static const TCGOutOpBinary outop_mul = { 1606 .base.static_constraint = C_O1_I2(r, r, rJ), 1607 .out_rrr = tgen_mul, 1608 .out_rri = tgen_muli, 1609}; 1610 1611/* 1612 * The 32-bit multiply insns produce a full 64-bit result. 1613 * Supporting 32-bit mul[us]2 opcodes avoids sign/zero-extensions 1614 * before the actual multiply; we only need extract the high part 1615 * into the separate operand. 1616 */ 1617static TCGConstraintSetIndex cset_mul2(TCGType type, unsigned flags) 1618{ 1619 return type == TCG_TYPE_I32 ? C_O2_I2(r, r, r, r) : C_NotImplemented; 1620} 1621 1622static void tgen_muls2(TCGContext *s, TCGType type, 1623 TCGReg a0, TCGReg a1, TCGReg a2, TCGReg a3) 1624{ 1625 tcg_out_arith(s, a0, a2, a3, ARITH_SMUL); 1626 tcg_out_arithi(s, a1, a0, 32, SHIFT_SRLX); 1627} 1628 1629static const TCGOutOpMul2 outop_muls2 = { 1630 .base.static_constraint = C_Dynamic, 1631 .base.dynamic_constraint = cset_mul2, 1632 .out_rrrr = tgen_muls2, 1633}; 1634 1635static const TCGOutOpBinary outop_mulsh = { 1636 .base.static_constraint = C_NotImplemented, 1637}; 1638 1639static void tgen_mulu2(TCGContext *s, TCGType type, 1640 TCGReg a0, TCGReg a1, TCGReg a2, TCGReg a3) 1641{ 1642 tcg_out_arith(s, a0, a2, a3, ARITH_UMUL); 1643 tcg_out_arithi(s, a1, a0, 32, SHIFT_SRLX); 1644} 1645 1646static const TCGOutOpMul2 outop_mulu2 = { 1647 .base.static_constraint = C_Dynamic, 1648 .base.dynamic_constraint = cset_mul2, 1649 .out_rrrr = tgen_mulu2, 1650}; 1651 1652static void tgen_muluh(TCGContext *s, TCGType type, 1653 TCGReg a0, TCGReg a1, TCGReg a2) 1654{ 1655 tcg_out_arith(s, a0, a1, a2, ARITH_UMULXHI); 1656} 1657 1658static TCGConstraintSetIndex cset_muluh(TCGType type, unsigned flags) 1659{ 1660 return (type == TCG_TYPE_I64 && use_vis3_instructions 1661 ? C_O1_I2(r, r, r) : C_NotImplemented); 1662} 1663 1664static const TCGOutOpBinary outop_muluh = { 1665 .base.static_constraint = C_Dynamic, 1666 .base.dynamic_constraint = cset_muluh, 1667 .out_rrr = tgen_muluh, 1668}; 1669 1670static const TCGOutOpBinary outop_nand = { 1671 .base.static_constraint = C_NotImplemented, 1672}; 1673 1674static const TCGOutOpBinary outop_nor = { 1675 .base.static_constraint = C_NotImplemented, 1676}; 1677 1678static void tgen_or(TCGContext *s, TCGType type, 1679 TCGReg a0, TCGReg a1, TCGReg a2) 1680{ 1681 tcg_out_arith(s, a0, a1, a2, ARITH_OR); 1682} 1683 1684static void tgen_ori(TCGContext *s, TCGType type, 1685 TCGReg a0, TCGReg a1, tcg_target_long a2) 1686{ 1687 tcg_out_arithi(s, a0, a1, a2, ARITH_OR); 1688} 1689 1690static const TCGOutOpBinary outop_or = { 1691 .base.static_constraint = C_O1_I2(r, r, rJ), 1692 .out_rrr = tgen_or, 1693 .out_rri = tgen_ori, 1694}; 1695 1696static void tgen_orc(TCGContext *s, TCGType type, 1697 TCGReg a0, TCGReg a1, TCGReg a2) 1698{ 1699 tcg_out_arith(s, a0, a1, a2, ARITH_ORN); 1700} 1701 1702static const TCGOutOpBinary outop_orc = { 1703 .base.static_constraint = C_O1_I2(r, r, r), 1704 .out_rrr = tgen_orc, 1705}; 1706 1707static const TCGOutOpBinary outop_rems = { 1708 .base.static_constraint = C_NotImplemented, 1709}; 1710 1711static const TCGOutOpBinary outop_remu = { 1712 .base.static_constraint = C_NotImplemented, 1713}; 1714 1715static const TCGOutOpBinary outop_rotl = { 1716 .base.static_constraint = C_NotImplemented, 1717}; 1718 1719static const TCGOutOpBinary outop_rotr = { 1720 .base.static_constraint = C_NotImplemented, 1721}; 1722 1723static void tgen_sar(TCGContext *s, TCGType type, 1724 TCGReg a0, TCGReg a1, TCGReg a2) 1725{ 1726 uint32_t insn = type == TCG_TYPE_I32 ? SHIFT_SRA : SHIFT_SRAX; 1727 tcg_out_arith(s, a0, a1, a2, insn); 1728} 1729 1730static void tgen_sari(TCGContext *s, TCGType type, 1731 TCGReg a0, TCGReg a1, tcg_target_long a2) 1732{ 1733 uint32_t insn = type == TCG_TYPE_I32 ? SHIFT_SRA : SHIFT_SRAX; 1734 uint32_t mask = type == TCG_TYPE_I32 ? 31 : 63; 1735 tcg_out_arithi(s, a0, a1, a2 & mask, insn); 1736} 1737 1738static const TCGOutOpBinary outop_sar = { 1739 .base.static_constraint = C_O1_I2(r, r, rJ), 1740 .out_rrr = tgen_sar, 1741 .out_rri = tgen_sari, 1742}; 1743 1744static void tgen_shl(TCGContext *s, TCGType type, 1745 TCGReg a0, TCGReg a1, TCGReg a2) 1746{ 1747 uint32_t insn = type == TCG_TYPE_I32 ? SHIFT_SLL : SHIFT_SLLX; 1748 tcg_out_arith(s, a0, a1, a2, insn); 1749} 1750 1751static void tgen_shli(TCGContext *s, TCGType type, 1752 TCGReg a0, TCGReg a1, tcg_target_long a2) 1753{ 1754 uint32_t insn = type == TCG_TYPE_I32 ? SHIFT_SLL : SHIFT_SLLX; 1755 uint32_t mask = type == TCG_TYPE_I32 ? 31 : 63; 1756 tcg_out_arithi(s, a0, a1, a2 & mask, insn); 1757} 1758 1759static const TCGOutOpBinary outop_shl = { 1760 .base.static_constraint = C_O1_I2(r, r, rJ), 1761 .out_rrr = tgen_shl, 1762 .out_rri = tgen_shli, 1763}; 1764 1765static void tgen_shr(TCGContext *s, TCGType type, 1766 TCGReg a0, TCGReg a1, TCGReg a2) 1767{ 1768 uint32_t insn = type == TCG_TYPE_I32 ? SHIFT_SRL : SHIFT_SRLX; 1769 tcg_out_arith(s, a0, a1, a2, insn); 1770} 1771 1772static void tgen_shri(TCGContext *s, TCGType type, 1773 TCGReg a0, TCGReg a1, tcg_target_long a2) 1774{ 1775 uint32_t insn = type == TCG_TYPE_I32 ? SHIFT_SRL : SHIFT_SRLX; 1776 uint32_t mask = type == TCG_TYPE_I32 ? 31 : 63; 1777 tcg_out_arithi(s, a0, a1, a2 & mask, insn); 1778} 1779 1780static const TCGOutOpBinary outop_shr = { 1781 .base.static_constraint = C_O1_I2(r, r, rJ), 1782 .out_rrr = tgen_shr, 1783 .out_rri = tgen_shri, 1784}; 1785 1786static void tgen_sub(TCGContext *s, TCGType type, 1787 TCGReg a0, TCGReg a1, TCGReg a2) 1788{ 1789 tcg_out_arith(s, a0, a1, a2, ARITH_SUB); 1790} 1791 1792static const TCGOutOpSubtract outop_sub = { 1793 .base.static_constraint = C_O1_I2(r, r, r), 1794 .out_rrr = tgen_sub, 1795}; 1796 1797static void tgen_subbo_rrr(TCGContext *s, TCGType type, 1798 TCGReg a0, TCGReg a1, TCGReg a2) 1799{ 1800 tcg_out_arith(s, a0, a1, a2, ARITH_SUBCC); 1801} 1802 1803static void tgen_subbo_rri(TCGContext *s, TCGType type, 1804 TCGReg a0, TCGReg a1, tcg_target_long a2) 1805{ 1806 tcg_out_arithi(s, a0, a1, a2, ARITH_SUBCC); 1807} 1808 1809static const TCGOutOpAddSubCarry outop_subbo = { 1810 .base.static_constraint = C_O1_I2(r, rz, rJ), 1811 .out_rrr = tgen_subbo_rrr, 1812 .out_rri = tgen_subbo_rri, 1813}; 1814 1815static void tgen_subbi_rrr(TCGContext *s, TCGType type, 1816 TCGReg a0, TCGReg a1, TCGReg a2) 1817{ 1818 /* TODO: OSA 2015 added SUBXC */ 1819 if (type == TCG_TYPE_I32) { 1820 tcg_out_arith(s, a0, a1, a2, ARITH_SUBC); 1821 } else { 1822 tcg_out_arith(s, TCG_REG_T1, a1, a2, ARITH_SUB); /* for CC */ 1823 tcg_out_arithi(s, a0, TCG_REG_T1, 1, ARITH_SUB); /* for CS */ 1824 /* Select the correct result based on actual borrow value. */ 1825 tcg_out_movcc(s, COND_CC, MOVCC_XCC, a0, TCG_REG_T1, false); 1826 } 1827} 1828 1829static void tgen_subbi_rri(TCGContext *s, TCGType type, 1830 TCGReg a0, TCGReg a1, tcg_target_long a2) 1831{ 1832 if (type == TCG_TYPE_I32) { 1833 tcg_out_arithi(s, a0, a1, a2, ARITH_SUBC); 1834 } else if (a2 != 0) { 1835 tcg_out_arithi(s, TCG_REG_T1, a1, a2, ARITH_SUB); /* for CC */ 1836 tcg_out_arithi(s, a0, TCG_REG_T1, 1, ARITH_SUB); /* for CS */ 1837 tcg_out_movcc(s, COND_CC, MOVCC_XCC, a0, TCG_REG_T1, false); 1838 } else if (a0 == a1) { 1839 tcg_out_arithi(s, TCG_REG_T1, a1, 1, ARITH_SUB); 1840 tcg_out_movcc(s, COND_CS, MOVCC_XCC, a0, TCG_REG_T1, false); 1841 } else { 1842 tcg_out_arithi(s, a0, a1, 1, ARITH_SUB); 1843 tcg_out_movcc(s, COND_CC, MOVCC_XCC, a0, a1, false); 1844 } 1845} 1846 1847static const TCGOutOpAddSubCarry outop_subbi = { 1848 .base.static_constraint = C_O1_I2(r, rz, rJ), 1849 .out_rrr = tgen_subbi_rrr, 1850 .out_rri = tgen_subbi_rri, 1851}; 1852 1853static void tgen_subbio_rrr(TCGContext *s, TCGType type, 1854 TCGReg a0, TCGReg a1, TCGReg a2) 1855{ 1856 if (type != TCG_TYPE_I32) { 1857 /* TODO: OSA 2015 added SUBXCCC */ 1858 tcg_out_dup_xcc_c(s); 1859 } 1860 tcg_out_arith(s, a0, a1, a2, ARITH_SUBCCC); 1861} 1862 1863static void tgen_subbio_rri(TCGContext *s, TCGType type, 1864 TCGReg a0, TCGReg a1, tcg_target_long a2) 1865{ 1866 if (type != TCG_TYPE_I32) { 1867 tcg_out_dup_xcc_c(s); 1868 } 1869 tcg_out_arithi(s, a0, a1, a2, ARITH_SUBCCC); 1870} 1871 1872static const TCGOutOpAddSubCarry outop_subbio = { 1873 .base.static_constraint = C_O1_I2(r, rz, rJ), 1874 .out_rrr = tgen_subbio_rrr, 1875 .out_rri = tgen_subbio_rri, 1876}; 1877 1878static void tcg_out_set_borrow(TCGContext *s) 1879{ 1880 tcg_out_set_carry(s); /* borrow == carry */ 1881} 1882 1883static void tgen_xor(TCGContext *s, TCGType type, 1884 TCGReg a0, TCGReg a1, TCGReg a2) 1885{ 1886 tcg_out_arith(s, a0, a1, a2, ARITH_XOR); 1887} 1888 1889static void tgen_xori(TCGContext *s, TCGType type, 1890 TCGReg a0, TCGReg a1, tcg_target_long a2) 1891{ 1892 tcg_out_arithi(s, a0, a1, a2, ARITH_XOR); 1893} 1894 1895static const TCGOutOpBinary outop_xor = { 1896 .base.static_constraint = C_O1_I2(r, r, rJ), 1897 .out_rrr = tgen_xor, 1898 .out_rri = tgen_xori, 1899}; 1900 1901static const TCGOutOpBswap outop_bswap16 = { 1902 .base.static_constraint = C_NotImplemented, 1903}; 1904 1905static const TCGOutOpBswap outop_bswap32 = { 1906 .base.static_constraint = C_NotImplemented, 1907}; 1908 1909static const TCGOutOpUnary outop_bswap64 = { 1910 .base.static_constraint = C_NotImplemented, 1911}; 1912 1913static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 1914{ 1915 tgen_sub(s, type, a0, TCG_REG_G0, a1); 1916} 1917 1918static const TCGOutOpUnary outop_neg = { 1919 .base.static_constraint = C_O1_I1(r, r), 1920 .out_rr = tgen_neg, 1921}; 1922 1923static void tgen_not(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 1924{ 1925 tgen_orc(s, type, a0, TCG_REG_G0, a1); 1926} 1927 1928static const TCGOutOpUnary outop_not = { 1929 .base.static_constraint = C_O1_I1(r, r), 1930 .out_rr = tgen_not, 1931}; 1932 1933static const TCGOutOpDeposit outop_deposit = { 1934 .base.static_constraint = C_NotImplemented, 1935}; 1936 1937static void tgen_extract(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, 1938 unsigned ofs, unsigned len) 1939{ 1940 tcg_debug_assert(ofs + len == 32); 1941 tcg_out_arithi(s, a0, a1, ofs, SHIFT_SRL); 1942} 1943 1944static const TCGOutOpExtract outop_extract = { 1945 .base.static_constraint = C_O1_I1(r, r), 1946 .out_rr = tgen_extract, 1947}; 1948 1949static void tgen_sextract(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, 1950 unsigned ofs, unsigned len) 1951{ 1952 tcg_debug_assert(ofs + len == 32); 1953 tcg_out_arithi(s, a0, a1, ofs, SHIFT_SRA); 1954} 1955 1956static const TCGOutOpExtract outop_sextract = { 1957 .base.static_constraint = C_O1_I1(r, r), 1958 .out_rr = tgen_sextract, 1959}; 1960 1961static const TCGOutOpExtract2 outop_extract2 = { 1962 .base.static_constraint = C_NotImplemented, 1963}; 1964 1965static void tgen_ld8u(TCGContext *s, TCGType type, TCGReg dest, 1966 TCGReg base, ptrdiff_t offset) 1967{ 1968 tcg_out_ldst(s, dest, base, offset, LDUB); 1969} 1970 1971static const TCGOutOpLoad outop_ld8u = { 1972 .base.static_constraint = C_O1_I1(r, r), 1973 .out = tgen_ld8u, 1974}; 1975 1976static void tgen_ld8s(TCGContext *s, TCGType type, TCGReg dest, 1977 TCGReg base, ptrdiff_t offset) 1978{ 1979 tcg_out_ldst(s, dest, base, offset, LDSB); 1980} 1981 1982static const TCGOutOpLoad outop_ld8s = { 1983 .base.static_constraint = C_O1_I1(r, r), 1984 .out = tgen_ld8s, 1985}; 1986 1987static void tgen_ld16u(TCGContext *s, TCGType type, TCGReg dest, 1988 TCGReg base, ptrdiff_t offset) 1989{ 1990 tcg_out_ldst(s, dest, base, offset, LDUH); 1991} 1992 1993static const TCGOutOpLoad outop_ld16u = { 1994 .base.static_constraint = C_O1_I1(r, r), 1995 .out = tgen_ld16u, 1996}; 1997 1998static void tgen_ld16s(TCGContext *s, TCGType type, TCGReg dest, 1999 TCGReg base, ptrdiff_t offset) 2000{ 2001 tcg_out_ldst(s, dest, base, offset, LDSH); 2002} 2003 2004static const TCGOutOpLoad outop_ld16s = { 2005 .base.static_constraint = C_O1_I1(r, r), 2006 .out = tgen_ld16s, 2007}; 2008 2009static void tgen_ld32u(TCGContext *s, TCGType type, TCGReg dest, 2010 TCGReg base, ptrdiff_t offset) 2011{ 2012 tcg_out_ldst(s, dest, base, offset, LDUW); 2013} 2014 2015static const TCGOutOpLoad outop_ld32u = { 2016 .base.static_constraint = C_O1_I1(r, r), 2017 .out = tgen_ld32u, 2018}; 2019 2020static void tgen_ld32s(TCGContext *s, TCGType type, TCGReg dest, 2021 TCGReg base, ptrdiff_t offset) 2022{ 2023 tcg_out_ldst(s, dest, base, offset, LDSW); 2024} 2025 2026static const TCGOutOpLoad outop_ld32s = { 2027 .base.static_constraint = C_O1_I1(r, r), 2028 .out = tgen_ld32s, 2029}; 2030 2031static void tgen_st8_r(TCGContext *s, TCGType type, TCGReg data, 2032 TCGReg base, ptrdiff_t offset) 2033{ 2034 tcg_out_ldst(s, data, base, offset, STB); 2035} 2036 2037static const TCGOutOpStore outop_st8 = { 2038 .base.static_constraint = C_O0_I2(rz, r), 2039 .out_r = tgen_st8_r, 2040}; 2041 2042static void tgen_st16_r(TCGContext *s, TCGType type, TCGReg data, 2043 TCGReg base, ptrdiff_t offset) 2044{ 2045 tcg_out_ldst(s, data, base, offset, STH); 2046} 2047 2048static const TCGOutOpStore outop_st16 = { 2049 .base.static_constraint = C_O0_I2(rz, r), 2050 .out_r = tgen_st16_r, 2051}; 2052 2053static const TCGOutOpStore outop_st = { 2054 .base.static_constraint = C_O0_I2(rz, r), 2055 .out_r = tcg_out_st, 2056}; 2057 2058 2059static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, 2060 const TCGArg args[TCG_MAX_OP_ARGS], 2061 const int const_args[TCG_MAX_OP_ARGS]) 2062{ 2063 TCGArg a0, a1, a2; 2064 2065 /* Hoist the loads of the most common arguments. */ 2066 a0 = args[0]; 2067 a1 = args[1]; 2068 a2 = args[2]; 2069 2070 switch (opc) { 2071 case INDEX_op_qemu_ld_i32: 2072 tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32); 2073 break; 2074 case INDEX_op_qemu_ld_i64: 2075 tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64); 2076 break; 2077 case INDEX_op_qemu_st_i32: 2078 tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32); 2079 break; 2080 case INDEX_op_qemu_st_i64: 2081 tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64); 2082 break; 2083 2084 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2085 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 2086 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 2087 default: 2088 g_assert_not_reached(); 2089 } 2090} 2091 2092static TCGConstraintSetIndex 2093tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) 2094{ 2095 switch (op) { 2096 case INDEX_op_qemu_ld_i32: 2097 case INDEX_op_qemu_ld_i64: 2098 return C_O1_I1(r, r); 2099 2100 case INDEX_op_qemu_st_i32: 2101 case INDEX_op_qemu_st_i64: 2102 return C_O0_I2(rz, r); 2103 2104 default: 2105 return C_NotImplemented; 2106 } 2107} 2108 2109static void tcg_target_init(TCGContext *s) 2110{ 2111 /* 2112 * Only probe for the platform and capabilities if we haven't already 2113 * determined maximum values at compile time. 2114 */ 2115#ifndef use_vis3_instructions 2116 { 2117 unsigned long hwcap = qemu_getauxval(AT_HWCAP); 2118 use_vis3_instructions = (hwcap & HWCAP_SPARC_VIS3) != 0; 2119 } 2120#endif 2121 2122 tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS; 2123 tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS; 2124 2125 tcg_target_call_clobber_regs = 0; 2126 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G1); 2127 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G2); 2128 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G3); 2129 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G4); 2130 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G5); 2131 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G6); 2132 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G7); 2133 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O0); 2134 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O1); 2135 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O2); 2136 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O3); 2137 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O4); 2138 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O5); 2139 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O6); 2140 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O7); 2141 2142 s->reserved_regs = 0; 2143 tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0); /* zero */ 2144 tcg_regset_set_reg(s->reserved_regs, TCG_REG_G6); /* reserved for os */ 2145 tcg_regset_set_reg(s->reserved_regs, TCG_REG_G7); /* thread pointer */ 2146 tcg_regset_set_reg(s->reserved_regs, TCG_REG_I6); /* frame pointer */ 2147 tcg_regset_set_reg(s->reserved_regs, TCG_REG_I7); /* return address */ 2148 tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6); /* stack pointer */ 2149 tcg_regset_set_reg(s->reserved_regs, TCG_REG_T1); /* for internal use */ 2150 tcg_regset_set_reg(s->reserved_regs, TCG_REG_T2); /* for internal use */ 2151 tcg_regset_set_reg(s->reserved_regs, TCG_REG_T3); /* for internal use */ 2152} 2153 2154#define ELF_HOST_MACHINE EM_SPARCV9 2155 2156typedef struct { 2157 DebugFrameHeader h; 2158 uint8_t fde_def_cfa[4]; 2159 uint8_t fde_win_save; 2160 uint8_t fde_ret_save[3]; 2161} DebugFrame; 2162 2163static const DebugFrame debug_frame = { 2164 .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ 2165 .h.cie.id = -1, 2166 .h.cie.version = 1, 2167 .h.cie.code_align = 1, 2168 .h.cie.data_align = -sizeof(void *) & 0x7f, 2169 .h.cie.return_column = 15, /* o7 */ 2170 2171 /* Total FDE size does not include the "len" member. */ 2172 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 2173 2174 .fde_def_cfa = { 2175 12, 30, /* DW_CFA_def_cfa i6, 2047 */ 2176 (2047 & 0x7f) | 0x80, (2047 >> 7) 2177 }, 2178 .fde_win_save = 0x2d, /* DW_CFA_GNU_window_save */ 2179 .fde_ret_save = { 9, 15, 31 }, /* DW_CFA_register o7, i7 */ 2180}; 2181 2182void tcg_register_jit(const void *buf, size_t buf_size) 2183{ 2184 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 2185} 2186