1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25/* We only support generating code for 64-bit mode. */ 26#ifndef __arch64__ 27#error "unsupported code generation mode" 28#endif 29 30/* Used for function call generation. */ 31#define TCG_REG_CALL_STACK TCG_REG_O6 32#define TCG_TARGET_STACK_BIAS 2047 33#define TCG_TARGET_STACK_ALIGN 16 34#define TCG_TARGET_CALL_STACK_OFFSET (128 + 6 * 8 + TCG_TARGET_STACK_BIAS) 35#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EXTEND 36#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL 37#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL 38#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL 39 40#ifdef CONFIG_DEBUG_TCG 41static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 42 "%g0", 43 "%g1", 44 "%g2", 45 "%g3", 46 "%g4", 47 "%g5", 48 "%g6", 49 "%g7", 50 "%o0", 51 "%o1", 52 "%o2", 53 "%o3", 54 "%o4", 55 "%o5", 56 "%o6", 57 "%o7", 58 "%l0", 59 "%l1", 60 "%l2", 61 "%l3", 62 "%l4", 63 "%l5", 64 "%l6", 65 "%l7", 66 "%i0", 67 "%i1", 68 "%i2", 69 "%i3", 70 "%i4", 71 "%i5", 72 "%i6", 73 "%i7", 74}; 75#endif 76 77#define TCG_CT_CONST_S11 0x100 78#define TCG_CT_CONST_S13 0x200 79 80#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) 81 82/* Define some temporary registers. T3 is used for constant generation. */ 83#define TCG_REG_T1 TCG_REG_G1 84#define TCG_REG_T2 TCG_REG_G2 85#define TCG_REG_T3 TCG_REG_O7 86 87#ifndef CONFIG_SOFTMMU 88# define TCG_GUEST_BASE_REG TCG_REG_I5 89#endif 90 91#define TCG_REG_TB TCG_REG_I1 92 93static const int tcg_target_reg_alloc_order[] = { 94 TCG_REG_L0, 95 TCG_REG_L1, 96 TCG_REG_L2, 97 TCG_REG_L3, 98 TCG_REG_L4, 99 TCG_REG_L5, 100 TCG_REG_L6, 101 TCG_REG_L7, 102 103 TCG_REG_I0, 104 TCG_REG_I1, 105 TCG_REG_I2, 106 TCG_REG_I3, 107 TCG_REG_I4, 108 TCG_REG_I5, 109 110 TCG_REG_G3, 111 TCG_REG_G4, 112 TCG_REG_G5, 113 114 TCG_REG_O0, 115 TCG_REG_O1, 116 TCG_REG_O2, 117 TCG_REG_O3, 118 TCG_REG_O4, 119 TCG_REG_O5, 120}; 121 122static const int tcg_target_call_iarg_regs[6] = { 123 TCG_REG_O0, 124 TCG_REG_O1, 125 TCG_REG_O2, 126 TCG_REG_O3, 127 TCG_REG_O4, 128 TCG_REG_O5, 129}; 130 131static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 132{ 133 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 134 tcg_debug_assert(slot >= 0 && slot <= 3); 135 return TCG_REG_O0 + slot; 136} 137 138#define INSN_OP(x) ((x) << 30) 139#define INSN_OP2(x) ((x) << 22) 140#define INSN_OP3(x) ((x) << 19) 141#define INSN_OPF(x) ((x) << 5) 142#define INSN_RD(x) ((x) << 25) 143#define INSN_RS1(x) ((x) << 14) 144#define INSN_RS2(x) (x) 145#define INSN_ASI(x) ((x) << 5) 146 147#define INSN_IMM10(x) ((1 << 13) | ((x) & 0x3ff)) 148#define INSN_IMM11(x) ((1 << 13) | ((x) & 0x7ff)) 149#define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff)) 150#define INSN_OFF16(x) ((((x) >> 2) & 0x3fff) | ((((x) >> 16) & 3) << 20)) 151#define INSN_OFF19(x) (((x) >> 2) & 0x07ffff) 152#define INSN_COND(x) ((x) << 25) 153 154#define COND_N 0x0 155#define COND_E 0x1 156#define COND_LE 0x2 157#define COND_L 0x3 158#define COND_LEU 0x4 159#define COND_CS 0x5 160#define COND_NEG 0x6 161#define COND_VS 0x7 162#define COND_A 0x8 163#define COND_NE 0x9 164#define COND_G 0xa 165#define COND_GE 0xb 166#define COND_GU 0xc 167#define COND_CC 0xd 168#define COND_POS 0xe 169#define COND_VC 0xf 170#define BA (INSN_OP(0) | INSN_COND(COND_A) | INSN_OP2(0x2)) 171 172#define RCOND_Z 1 173#define RCOND_LEZ 2 174#define RCOND_LZ 3 175#define RCOND_NZ 5 176#define RCOND_GZ 6 177#define RCOND_GEZ 7 178 179#define MOVCC_ICC (1 << 18) 180#define MOVCC_XCC (1 << 18 | 1 << 12) 181 182#define BPCC_ICC 0 183#define BPCC_XCC (2 << 20) 184#define BPCC_PT (1 << 19) 185#define BPCC_PN 0 186#define BPCC_A (1 << 29) 187 188#define BPR_PT BPCC_PT 189 190#define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00)) 191#define ARITH_ADDCC (INSN_OP(2) | INSN_OP3(0x10)) 192#define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01)) 193#define ARITH_ANDCC (INSN_OP(2) | INSN_OP3(0x11)) 194#define ARITH_ANDN (INSN_OP(2) | INSN_OP3(0x05)) 195#define ARITH_OR (INSN_OP(2) | INSN_OP3(0x02)) 196#define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12)) 197#define ARITH_ORN (INSN_OP(2) | INSN_OP3(0x06)) 198#define ARITH_XOR (INSN_OP(2) | INSN_OP3(0x03)) 199#define ARITH_SUB (INSN_OP(2) | INSN_OP3(0x04)) 200#define ARITH_SUBCC (INSN_OP(2) | INSN_OP3(0x14)) 201#define ARITH_ADDC (INSN_OP(2) | INSN_OP3(0x08)) 202#define ARITH_SUBC (INSN_OP(2) | INSN_OP3(0x0c)) 203#define ARITH_UMUL (INSN_OP(2) | INSN_OP3(0x0a)) 204#define ARITH_SMUL (INSN_OP(2) | INSN_OP3(0x0b)) 205#define ARITH_UDIV (INSN_OP(2) | INSN_OP3(0x0e)) 206#define ARITH_SDIV (INSN_OP(2) | INSN_OP3(0x0f)) 207#define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09)) 208#define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d)) 209#define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d)) 210#define ARITH_MOVCC (INSN_OP(2) | INSN_OP3(0x2c)) 211#define ARITH_MOVR (INSN_OP(2) | INSN_OP3(0x2f)) 212 213#define ARITH_ADDXC (INSN_OP(2) | INSN_OP3(0x36) | INSN_OPF(0x11)) 214#define ARITH_UMULXHI (INSN_OP(2) | INSN_OP3(0x36) | INSN_OPF(0x16)) 215 216#define SHIFT_SLL (INSN_OP(2) | INSN_OP3(0x25)) 217#define SHIFT_SRL (INSN_OP(2) | INSN_OP3(0x26)) 218#define SHIFT_SRA (INSN_OP(2) | INSN_OP3(0x27)) 219 220#define SHIFT_SLLX (INSN_OP(2) | INSN_OP3(0x25) | (1 << 12)) 221#define SHIFT_SRLX (INSN_OP(2) | INSN_OP3(0x26) | (1 << 12)) 222#define SHIFT_SRAX (INSN_OP(2) | INSN_OP3(0x27) | (1 << 12)) 223 224#define RDY (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(0)) 225#define WRY (INSN_OP(2) | INSN_OP3(0x30) | INSN_RD(0)) 226#define JMPL (INSN_OP(2) | INSN_OP3(0x38)) 227#define RETURN (INSN_OP(2) | INSN_OP3(0x39)) 228#define SAVE (INSN_OP(2) | INSN_OP3(0x3c)) 229#define RESTORE (INSN_OP(2) | INSN_OP3(0x3d)) 230#define SETHI (INSN_OP(0) | INSN_OP2(0x4)) 231#define CALL INSN_OP(1) 232#define LDUB (INSN_OP(3) | INSN_OP3(0x01)) 233#define LDSB (INSN_OP(3) | INSN_OP3(0x09)) 234#define LDUH (INSN_OP(3) | INSN_OP3(0x02)) 235#define LDSH (INSN_OP(3) | INSN_OP3(0x0a)) 236#define LDUW (INSN_OP(3) | INSN_OP3(0x00)) 237#define LDSW (INSN_OP(3) | INSN_OP3(0x08)) 238#define LDX (INSN_OP(3) | INSN_OP3(0x0b)) 239#define STB (INSN_OP(3) | INSN_OP3(0x05)) 240#define STH (INSN_OP(3) | INSN_OP3(0x06)) 241#define STW (INSN_OP(3) | INSN_OP3(0x04)) 242#define STX (INSN_OP(3) | INSN_OP3(0x0e)) 243#define LDUBA (INSN_OP(3) | INSN_OP3(0x11)) 244#define LDSBA (INSN_OP(3) | INSN_OP3(0x19)) 245#define LDUHA (INSN_OP(3) | INSN_OP3(0x12)) 246#define LDSHA (INSN_OP(3) | INSN_OP3(0x1a)) 247#define LDUWA (INSN_OP(3) | INSN_OP3(0x10)) 248#define LDSWA (INSN_OP(3) | INSN_OP3(0x18)) 249#define LDXA (INSN_OP(3) | INSN_OP3(0x1b)) 250#define STBA (INSN_OP(3) | INSN_OP3(0x15)) 251#define STHA (INSN_OP(3) | INSN_OP3(0x16)) 252#define STWA (INSN_OP(3) | INSN_OP3(0x14)) 253#define STXA (INSN_OP(3) | INSN_OP3(0x1e)) 254 255#define MEMBAR (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(15) | (1 << 13)) 256 257#define NOP (SETHI | INSN_RD(TCG_REG_G0) | 0) 258 259#ifndef ASI_PRIMARY_LITTLE 260#define ASI_PRIMARY_LITTLE 0x88 261#endif 262 263#define LDUH_LE (LDUHA | INSN_ASI(ASI_PRIMARY_LITTLE)) 264#define LDSH_LE (LDSHA | INSN_ASI(ASI_PRIMARY_LITTLE)) 265#define LDUW_LE (LDUWA | INSN_ASI(ASI_PRIMARY_LITTLE)) 266#define LDSW_LE (LDSWA | INSN_ASI(ASI_PRIMARY_LITTLE)) 267#define LDX_LE (LDXA | INSN_ASI(ASI_PRIMARY_LITTLE)) 268 269#define STH_LE (STHA | INSN_ASI(ASI_PRIMARY_LITTLE)) 270#define STW_LE (STWA | INSN_ASI(ASI_PRIMARY_LITTLE)) 271#define STX_LE (STXA | INSN_ASI(ASI_PRIMARY_LITTLE)) 272 273#ifndef use_vis3_instructions 274bool use_vis3_instructions; 275#endif 276 277static bool check_fit_i64(int64_t val, unsigned int bits) 278{ 279 return val == sextract64(val, 0, bits); 280} 281 282static bool check_fit_i32(int32_t val, unsigned int bits) 283{ 284 return val == sextract32(val, 0, bits); 285} 286 287#define check_fit_tl check_fit_i64 288#define check_fit_ptr check_fit_i64 289 290static bool patch_reloc(tcg_insn_unit *src_rw, int type, 291 intptr_t value, intptr_t addend) 292{ 293 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 294 uint32_t insn = *src_rw; 295 intptr_t pcrel; 296 297 value += addend; 298 pcrel = tcg_ptr_byte_diff((tcg_insn_unit *)value, src_rx); 299 300 switch (type) { 301 case R_SPARC_WDISP16: 302 if (!check_fit_ptr(pcrel >> 2, 16)) { 303 return false; 304 } 305 insn &= ~INSN_OFF16(-1); 306 insn |= INSN_OFF16(pcrel); 307 break; 308 case R_SPARC_WDISP19: 309 if (!check_fit_ptr(pcrel >> 2, 19)) { 310 return false; 311 } 312 insn &= ~INSN_OFF19(-1); 313 insn |= INSN_OFF19(pcrel); 314 break; 315 case R_SPARC_13: 316 if (!check_fit_ptr(value, 13)) { 317 return false; 318 } 319 insn &= ~INSN_IMM13(-1); 320 insn |= INSN_IMM13(value); 321 break; 322 default: 323 g_assert_not_reached(); 324 } 325 326 *src_rw = insn; 327 return true; 328} 329 330/* test if a constant matches the constraint */ 331static bool tcg_target_const_match(int64_t val, int ct, 332 TCGType type, TCGCond cond, int vece) 333{ 334 if (ct & TCG_CT_CONST) { 335 return 1; 336 } 337 338 if (type == TCG_TYPE_I32) { 339 val = (int32_t)val; 340 } 341 342 if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11)) { 343 return 1; 344 } else if ((ct & TCG_CT_CONST_S13) && check_fit_tl(val, 13)) { 345 return 1; 346 } else { 347 return 0; 348 } 349} 350 351static void tcg_out_nop(TCGContext *s) 352{ 353 tcg_out32(s, NOP); 354} 355 356static void tcg_out_arith(TCGContext *s, TCGReg rd, TCGReg rs1, 357 TCGReg rs2, int op) 358{ 359 tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | INSN_RS2(rs2)); 360} 361 362static void tcg_out_arithi(TCGContext *s, TCGReg rd, TCGReg rs1, 363 int32_t offset, int op) 364{ 365 tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | INSN_IMM13(offset)); 366} 367 368static void tcg_out_arithc(TCGContext *s, TCGReg rd, TCGReg rs1, 369 int32_t val2, int val2const, int op) 370{ 371 tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) 372 | (val2const ? INSN_IMM13(val2) : INSN_RS2(val2))); 373} 374 375static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 376{ 377 if (ret != arg) { 378 tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR); 379 } 380 return true; 381} 382 383static void tcg_out_mov_delay(TCGContext *s, TCGReg ret, TCGReg arg) 384{ 385 if (ret != arg) { 386 tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR); 387 } else { 388 tcg_out_nop(s); 389 } 390} 391 392static void tcg_out_sethi(TCGContext *s, TCGReg ret, uint32_t arg) 393{ 394 tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10)); 395} 396 397/* A 13-bit constant sign-extended to 64 bits. */ 398static void tcg_out_movi_s13(TCGContext *s, TCGReg ret, int32_t arg) 399{ 400 tcg_out_arithi(s, ret, TCG_REG_G0, arg, ARITH_OR); 401} 402 403/* A 32-bit constant sign-extended to 64 bits. */ 404static void tcg_out_movi_s32(TCGContext *s, TCGReg ret, int32_t arg) 405{ 406 tcg_out_sethi(s, ret, ~arg); 407 tcg_out_arithi(s, ret, ret, (arg & 0x3ff) | -0x400, ARITH_XOR); 408} 409 410/* A 32-bit constant zero-extended to 64 bits. */ 411static void tcg_out_movi_u32(TCGContext *s, TCGReg ret, uint32_t arg) 412{ 413 tcg_out_sethi(s, ret, arg); 414 if (arg & 0x3ff) { 415 tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR); 416 } 417} 418 419static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, 420 tcg_target_long arg, bool in_prologue, 421 TCGReg scratch) 422{ 423 tcg_target_long hi, lo = (int32_t)arg; 424 tcg_target_long test, lsb; 425 426 /* A 13-bit constant sign-extended to 64-bits. */ 427 if (check_fit_tl(arg, 13)) { 428 tcg_out_movi_s13(s, ret, arg); 429 return; 430 } 431 432 /* A 32-bit constant, or 32-bit zero-extended to 64-bits. */ 433 if (type == TCG_TYPE_I32 || arg == (uint32_t)arg) { 434 tcg_out_movi_u32(s, ret, arg); 435 return; 436 } 437 438 /* A 13-bit constant relative to the TB. */ 439 if (!in_prologue) { 440 test = tcg_tbrel_diff(s, (void *)arg); 441 if (check_fit_ptr(test, 13)) { 442 tcg_out_arithi(s, ret, TCG_REG_TB, test, ARITH_ADD); 443 return; 444 } 445 } 446 447 /* A 32-bit constant sign-extended to 64-bits. */ 448 if (arg == lo) { 449 tcg_out_movi_s32(s, ret, arg); 450 return; 451 } 452 453 /* A 32-bit constant, shifted. */ 454 lsb = ctz64(arg); 455 test = (tcg_target_long)arg >> lsb; 456 if (lsb > 10 && test == extract64(test, 0, 21)) { 457 tcg_out_sethi(s, ret, test << 10); 458 tcg_out_arithi(s, ret, ret, lsb - 10, SHIFT_SLLX); 459 return; 460 } else if (test == (uint32_t)test || test == (int32_t)test) { 461 tcg_out_movi_int(s, TCG_TYPE_I64, ret, test, in_prologue, scratch); 462 tcg_out_arithi(s, ret, ret, lsb, SHIFT_SLLX); 463 return; 464 } 465 466 /* Use the constant pool, if possible. */ 467 if (!in_prologue) { 468 new_pool_label(s, arg, R_SPARC_13, s->code_ptr, 469 tcg_tbrel_diff(s, NULL)); 470 tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(TCG_REG_TB)); 471 return; 472 } 473 474 /* A 64-bit constant decomposed into 2 32-bit pieces. */ 475 if (check_fit_i32(lo, 13)) { 476 hi = (arg - lo) >> 32; 477 tcg_out_movi_u32(s, ret, hi); 478 tcg_out_arithi(s, ret, ret, 32, SHIFT_SLLX); 479 tcg_out_arithi(s, ret, ret, lo, ARITH_ADD); 480 } else { 481 hi = arg >> 32; 482 tcg_out_movi_u32(s, ret, hi); 483 tcg_out_movi_u32(s, scratch, lo); 484 tcg_out_arithi(s, ret, ret, 32, SHIFT_SLLX); 485 tcg_out_arith(s, ret, ret, scratch, ARITH_OR); 486 } 487} 488 489static void tcg_out_movi(TCGContext *s, TCGType type, 490 TCGReg ret, tcg_target_long arg) 491{ 492 tcg_debug_assert(ret != TCG_REG_T3); 493 tcg_out_movi_int(s, type, ret, arg, false, TCG_REG_T3); 494} 495 496static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) 497{ 498 g_assert_not_reached(); 499} 500 501static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) 502{ 503 g_assert_not_reached(); 504} 505 506static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rs) 507{ 508 tcg_out_arithi(s, rd, rs, 0xff, ARITH_AND); 509} 510 511static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rs) 512{ 513 tcg_out_arithi(s, rd, rs, 16, SHIFT_SLL); 514 tcg_out_arithi(s, rd, rd, 16, SHIFT_SRL); 515} 516 517static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rs) 518{ 519 tcg_out_arithi(s, rd, rs, 0, SHIFT_SRA); 520} 521 522static void tcg_out_ext32u(TCGContext *s, TCGReg rd, TCGReg rs) 523{ 524 tcg_out_arithi(s, rd, rs, 0, SHIFT_SRL); 525} 526 527static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) 528{ 529 tcg_out_ext32s(s, rd, rs); 530} 531 532static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) 533{ 534 tcg_out_ext32u(s, rd, rs); 535} 536 537static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rs) 538{ 539 tcg_out_ext32u(s, rd, rs); 540} 541 542static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 543{ 544 return false; 545} 546 547static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 548 tcg_target_long imm) 549{ 550 /* This function is only used for passing structs by reference. */ 551 g_assert_not_reached(); 552} 553 554static void tcg_out_ldst_rr(TCGContext *s, TCGReg data, TCGReg a1, 555 TCGReg a2, int op) 556{ 557 tcg_out32(s, op | INSN_RD(data) | INSN_RS1(a1) | INSN_RS2(a2)); 558} 559 560static void tcg_out_ldst(TCGContext *s, TCGReg ret, TCGReg addr, 561 intptr_t offset, int op) 562{ 563 if (check_fit_ptr(offset, 13)) { 564 tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(addr) | 565 INSN_IMM13(offset)); 566 } else { 567 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, offset); 568 tcg_out_ldst_rr(s, ret, addr, TCG_REG_T1, op); 569 } 570} 571 572static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, 573 TCGReg arg1, intptr_t arg2) 574{ 575 tcg_out_ldst(s, ret, arg1, arg2, (type == TCG_TYPE_I32 ? LDUW : LDX)); 576} 577 578static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 579 TCGReg arg1, intptr_t arg2) 580{ 581 tcg_out_ldst(s, arg, arg1, arg2, (type == TCG_TYPE_I32 ? STW : STX)); 582} 583 584static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 585 TCGReg base, intptr_t ofs) 586{ 587 if (val == 0) { 588 tcg_out_st(s, type, TCG_REG_G0, base, ofs); 589 return true; 590 } 591 return false; 592} 593 594static void tcg_out_sety(TCGContext *s, TCGReg rs) 595{ 596 tcg_out32(s, WRY | INSN_RS1(TCG_REG_G0) | INSN_RS2(rs)); 597} 598 599static void tcg_out_div32(TCGContext *s, TCGReg rd, TCGReg rs1, 600 int32_t val2, int val2const, int uns) 601{ 602 /* Load Y with the sign/zero extension of RS1 to 64-bits. */ 603 if (uns) { 604 tcg_out_sety(s, TCG_REG_G0); 605 } else { 606 tcg_out_arithi(s, TCG_REG_T1, rs1, 31, SHIFT_SRA); 607 tcg_out_sety(s, TCG_REG_T1); 608 } 609 610 tcg_out_arithc(s, rd, rs1, val2, val2const, 611 uns ? ARITH_UDIV : ARITH_SDIV); 612} 613 614static const uint8_t tcg_cond_to_bcond[16] = { 615 [TCG_COND_EQ] = COND_E, 616 [TCG_COND_NE] = COND_NE, 617 [TCG_COND_TSTEQ] = COND_E, 618 [TCG_COND_TSTNE] = COND_NE, 619 [TCG_COND_LT] = COND_L, 620 [TCG_COND_GE] = COND_GE, 621 [TCG_COND_LE] = COND_LE, 622 [TCG_COND_GT] = COND_G, 623 [TCG_COND_LTU] = COND_CS, 624 [TCG_COND_GEU] = COND_CC, 625 [TCG_COND_LEU] = COND_LEU, 626 [TCG_COND_GTU] = COND_GU, 627}; 628 629static const uint8_t tcg_cond_to_rcond[16] = { 630 [TCG_COND_EQ] = RCOND_Z, 631 [TCG_COND_NE] = RCOND_NZ, 632 [TCG_COND_LT] = RCOND_LZ, 633 [TCG_COND_GT] = RCOND_GZ, 634 [TCG_COND_LE] = RCOND_LEZ, 635 [TCG_COND_GE] = RCOND_GEZ 636}; 637 638static void tcg_out_bpcc0(TCGContext *s, int scond, int flags, int off19) 639{ 640 tcg_out32(s, INSN_OP(0) | INSN_OP2(1) | INSN_COND(scond) | flags | off19); 641} 642 643static void tcg_out_bpcc(TCGContext *s, int scond, int flags, TCGLabel *l) 644{ 645 int off19 = 0; 646 647 if (l->has_value) { 648 off19 = INSN_OFF19(tcg_pcrel_diff(s, l->u.value_ptr)); 649 } else { 650 tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP19, l, 0); 651 } 652 tcg_out_bpcc0(s, scond, flags, off19); 653} 654 655static void tcg_out_cmp(TCGContext *s, TCGCond cond, 656 TCGReg c1, int32_t c2, int c2const) 657{ 658 tcg_out_arithc(s, TCG_REG_G0, c1, c2, c2const, 659 is_tst_cond(cond) ? ARITH_ANDCC : ARITH_SUBCC); 660} 661 662static void tcg_out_brcond_i32(TCGContext *s, TCGCond cond, TCGReg arg1, 663 int32_t arg2, int const_arg2, TCGLabel *l) 664{ 665 tcg_out_cmp(s, cond, arg1, arg2, const_arg2); 666 tcg_out_bpcc(s, tcg_cond_to_bcond[cond], BPCC_ICC | BPCC_PT, l); 667 tcg_out_nop(s); 668} 669 670static void tcg_out_movcc(TCGContext *s, TCGCond cond, int cc, TCGReg ret, 671 int32_t v1, int v1const) 672{ 673 tcg_out32(s, ARITH_MOVCC | cc | INSN_RD(ret) 674 | INSN_RS1(tcg_cond_to_bcond[cond]) 675 | (v1const ? INSN_IMM11(v1) : INSN_RS2(v1))); 676} 677 678static void tcg_out_movcond_i32(TCGContext *s, TCGCond cond, TCGReg ret, 679 TCGReg c1, int32_t c2, int c2const, 680 int32_t v1, int v1const) 681{ 682 tcg_out_cmp(s, cond, c1, c2, c2const); 683 tcg_out_movcc(s, cond, MOVCC_ICC, ret, v1, v1const); 684} 685 686static void tcg_out_brcond_i64(TCGContext *s, TCGCond cond, TCGReg arg1, 687 int32_t arg2, int const_arg2, TCGLabel *l) 688{ 689 /* For 64-bit signed comparisons vs zero, we can avoid the compare. */ 690 int rcond = tcg_cond_to_rcond[cond]; 691 if (arg2 == 0 && rcond) { 692 int off16 = 0; 693 694 if (l->has_value) { 695 off16 = INSN_OFF16(tcg_pcrel_diff(s, l->u.value_ptr)); 696 } else { 697 tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP16, l, 0); 698 } 699 tcg_out32(s, INSN_OP(0) | INSN_OP2(3) | BPR_PT | INSN_RS1(arg1) 700 | INSN_COND(rcond) | off16); 701 } else { 702 tcg_out_cmp(s, cond, arg1, arg2, const_arg2); 703 tcg_out_bpcc(s, tcg_cond_to_bcond[cond], BPCC_XCC | BPCC_PT, l); 704 } 705 tcg_out_nop(s); 706} 707 708static void tcg_out_movr(TCGContext *s, int rcond, TCGReg ret, TCGReg c1, 709 int32_t v1, int v1const) 710{ 711 tcg_out32(s, ARITH_MOVR | INSN_RD(ret) | INSN_RS1(c1) | (rcond << 10) 712 | (v1const ? INSN_IMM10(v1) : INSN_RS2(v1))); 713} 714 715static void tcg_out_movcond_i64(TCGContext *s, TCGCond cond, TCGReg ret, 716 TCGReg c1, int32_t c2, int c2const, 717 int32_t v1, int v1const) 718{ 719 /* For 64-bit signed comparisons vs zero, we can avoid the compare. 720 Note that the immediate range is one bit smaller, so we must check 721 for that as well. */ 722 int rcond = tcg_cond_to_rcond[cond]; 723 if (c2 == 0 && rcond && (!v1const || check_fit_i32(v1, 10))) { 724 tcg_out_movr(s, rcond, ret, c1, v1, v1const); 725 } else { 726 tcg_out_cmp(s, cond, c1, c2, c2const); 727 tcg_out_movcc(s, cond, MOVCC_XCC, ret, v1, v1const); 728 } 729} 730 731static void tcg_out_setcond_i32(TCGContext *s, TCGCond cond, TCGReg ret, 732 TCGReg c1, int32_t c2, int c2const, bool neg) 733{ 734 /* For 32-bit comparisons, we can play games with ADDC/SUBC. */ 735 switch (cond) { 736 case TCG_COND_LTU: 737 case TCG_COND_GEU: 738 /* The result of the comparison is in the carry bit. */ 739 break; 740 741 case TCG_COND_EQ: 742 case TCG_COND_NE: 743 /* For equality, we can transform to inequality vs zero. */ 744 if (c2 != 0) { 745 tcg_out_arithc(s, TCG_REG_T1, c1, c2, c2const, ARITH_XOR); 746 c2 = TCG_REG_T1; 747 } else { 748 c2 = c1; 749 } 750 c1 = TCG_REG_G0, c2const = 0; 751 cond = (cond == TCG_COND_EQ ? TCG_COND_GEU : TCG_COND_LTU); 752 break; 753 754 case TCG_COND_TSTEQ: 755 case TCG_COND_TSTNE: 756 /* Transform to inequality vs zero. */ 757 tcg_out_arithc(s, TCG_REG_T1, c1, c2, c2const, ARITH_AND); 758 c1 = TCG_REG_G0; 759 c2 = TCG_REG_T1, c2const = 0; 760 cond = (cond == TCG_COND_TSTEQ ? TCG_COND_GEU : TCG_COND_LTU); 761 break; 762 763 case TCG_COND_GTU: 764 case TCG_COND_LEU: 765 /* If we don't need to load a constant into a register, we can 766 swap the operands on GTU/LEU. There's no benefit to loading 767 the constant into a temporary register. */ 768 if (!c2const || c2 == 0) { 769 TCGReg t = c1; 770 c1 = c2; 771 c2 = t; 772 c2const = 0; 773 cond = tcg_swap_cond(cond); 774 break; 775 } 776 /* FALLTHRU */ 777 778 default: 779 tcg_out_cmp(s, cond, c1, c2, c2const); 780 tcg_out_movi_s13(s, ret, 0); 781 tcg_out_movcc(s, cond, MOVCC_ICC, ret, neg ? -1 : 1, 1); 782 return; 783 } 784 785 tcg_out_cmp(s, cond, c1, c2, c2const); 786 if (cond == TCG_COND_LTU) { 787 if (neg) { 788 /* 0 - 0 - C = -C = (C ? -1 : 0) */ 789 tcg_out_arithi(s, ret, TCG_REG_G0, 0, ARITH_SUBC); 790 } else { 791 /* 0 + 0 + C = C = (C ? 1 : 0) */ 792 tcg_out_arithi(s, ret, TCG_REG_G0, 0, ARITH_ADDC); 793 } 794 } else { 795 if (neg) { 796 /* 0 + -1 + C = C - 1 = (C ? 0 : -1) */ 797 tcg_out_arithi(s, ret, TCG_REG_G0, -1, ARITH_ADDC); 798 } else { 799 /* 0 - -1 - C = 1 - C = (C ? 0 : 1) */ 800 tcg_out_arithi(s, ret, TCG_REG_G0, -1, ARITH_SUBC); 801 } 802 } 803} 804 805static void tcg_out_setcond_i64(TCGContext *s, TCGCond cond, TCGReg ret, 806 TCGReg c1, int32_t c2, int c2const, bool neg) 807{ 808 int rcond; 809 810 if (use_vis3_instructions && !neg) { 811 switch (cond) { 812 case TCG_COND_NE: 813 if (c2 != 0) { 814 break; 815 } 816 c2 = c1, c2const = 0, c1 = TCG_REG_G0; 817 /* FALLTHRU */ 818 case TCG_COND_LTU: 819 tcg_out_cmp(s, cond, c1, c2, c2const); 820 tcg_out_arith(s, ret, TCG_REG_G0, TCG_REG_G0, ARITH_ADDXC); 821 return; 822 default: 823 break; 824 } 825 } 826 827 /* For 64-bit signed comparisons vs zero, we can avoid the compare 828 if the input does not overlap the output. */ 829 rcond = tcg_cond_to_rcond[cond]; 830 if (c2 == 0 && rcond && c1 != ret) { 831 tcg_out_movi_s13(s, ret, 0); 832 tcg_out_movr(s, rcond, ret, c1, neg ? -1 : 1, 1); 833 } else { 834 tcg_out_cmp(s, cond, c1, c2, c2const); 835 tcg_out_movi_s13(s, ret, 0); 836 tcg_out_movcc(s, cond, MOVCC_XCC, ret, neg ? -1 : 1, 1); 837 } 838} 839 840static void tcg_out_addsub2_i32(TCGContext *s, TCGReg rl, TCGReg rh, 841 TCGReg al, TCGReg ah, int32_t bl, int blconst, 842 int32_t bh, int bhconst, int opl, int oph) 843{ 844 TCGReg tmp = TCG_REG_T1; 845 846 /* Note that the low parts are fully consumed before tmp is set. */ 847 if (rl != ah && (bhconst || rl != bh)) { 848 tmp = rl; 849 } 850 851 tcg_out_arithc(s, tmp, al, bl, blconst, opl); 852 tcg_out_arithc(s, rh, ah, bh, bhconst, oph); 853 tcg_out_mov(s, TCG_TYPE_I32, rl, tmp); 854} 855 856static void tcg_out_addsub2_i64(TCGContext *s, TCGReg rl, TCGReg rh, 857 TCGReg al, TCGReg ah, int32_t bl, int blconst, 858 int32_t bh, int bhconst, bool is_sub) 859{ 860 TCGReg tmp = TCG_REG_T1; 861 862 /* Note that the low parts are fully consumed before tmp is set. */ 863 if (rl != ah && (bhconst || rl != bh)) { 864 tmp = rl; 865 } 866 867 tcg_out_arithc(s, tmp, al, bl, blconst, is_sub ? ARITH_SUBCC : ARITH_ADDCC); 868 869 if (use_vis3_instructions && !is_sub) { 870 /* Note that ADDXC doesn't accept immediates. */ 871 if (bhconst && bh != 0) { 872 tcg_out_movi_s13(s, TCG_REG_T2, bh); 873 bh = TCG_REG_T2; 874 } 875 tcg_out_arith(s, rh, ah, bh, ARITH_ADDXC); 876 } else if (bh == TCG_REG_G0) { 877 /* If we have a zero, we can perform the operation in two insns, 878 with the arithmetic first, and a conditional move into place. */ 879 if (rh == ah) { 880 tcg_out_arithi(s, TCG_REG_T2, ah, 1, 881 is_sub ? ARITH_SUB : ARITH_ADD); 882 tcg_out_movcc(s, TCG_COND_LTU, MOVCC_XCC, rh, TCG_REG_T2, 0); 883 } else { 884 tcg_out_arithi(s, rh, ah, 1, is_sub ? ARITH_SUB : ARITH_ADD); 885 tcg_out_movcc(s, TCG_COND_GEU, MOVCC_XCC, rh, ah, 0); 886 } 887 } else { 888 /* 889 * Otherwise adjust BH as if there is carry into T2. 890 * Note that constant BH is constrained to 11 bits for the MOVCC, 891 * so the adjustment fits 12 bits. 892 */ 893 if (bhconst) { 894 tcg_out_movi_s13(s, TCG_REG_T2, bh + (is_sub ? -1 : 1)); 895 } else { 896 tcg_out_arithi(s, TCG_REG_T2, bh, 1, 897 is_sub ? ARITH_SUB : ARITH_ADD); 898 } 899 /* ... smoosh T2 back to original BH if carry is clear ... */ 900 tcg_out_movcc(s, TCG_COND_GEU, MOVCC_XCC, TCG_REG_T2, bh, bhconst); 901 /* ... and finally perform the arithmetic with the new operand. */ 902 tcg_out_arith(s, rh, ah, TCG_REG_T2, is_sub ? ARITH_SUB : ARITH_ADD); 903 } 904 905 tcg_out_mov(s, TCG_TYPE_I64, rl, tmp); 906} 907 908static void tcg_out_jmpl_const(TCGContext *s, const tcg_insn_unit *dest, 909 bool in_prologue, bool tail_call) 910{ 911 uintptr_t desti = (uintptr_t)dest; 912 913 tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_REG_T1, 914 desti & ~0xfff, in_prologue, TCG_REG_T2); 915 tcg_out_arithi(s, tail_call ? TCG_REG_G0 : TCG_REG_O7, 916 TCG_REG_T1, desti & 0xfff, JMPL); 917} 918 919static void tcg_out_call_nodelay(TCGContext *s, const tcg_insn_unit *dest, 920 bool in_prologue) 921{ 922 ptrdiff_t disp = tcg_pcrel_diff(s, dest); 923 924 if (disp == (int32_t)disp) { 925 tcg_out32(s, CALL | (uint32_t)disp >> 2); 926 } else { 927 tcg_out_jmpl_const(s, dest, in_prologue, false); 928 } 929} 930 931static void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest, 932 const TCGHelperInfo *info) 933{ 934 tcg_out_call_nodelay(s, dest, false); 935 tcg_out_nop(s); 936} 937 938static void tcg_out_mb(TCGContext *s, TCGArg a0) 939{ 940 /* Note that the TCG memory order constants mirror the Sparc MEMBAR. */ 941 tcg_out32(s, MEMBAR | (a0 & TCG_MO_ALL)); 942} 943 944/* Generate global QEMU prologue and epilogue code */ 945static void tcg_target_qemu_prologue(TCGContext *s) 946{ 947 int tmp_buf_size, frame_size; 948 949 /* 950 * The TCG temp buffer is at the top of the frame, immediately 951 * below the frame pointer. Use the logical (aligned) offset here; 952 * the stack bias is applied in temp_allocate_frame(). 953 */ 954 tmp_buf_size = CPU_TEMP_BUF_NLONGS * (int)sizeof(long); 955 tcg_set_frame(s, TCG_REG_I6, -tmp_buf_size, tmp_buf_size); 956 957 /* 958 * TCG_TARGET_CALL_STACK_OFFSET includes the stack bias, but is 959 * otherwise the minimal frame usable by callees. 960 */ 961 frame_size = TCG_TARGET_CALL_STACK_OFFSET - TCG_TARGET_STACK_BIAS; 962 frame_size += TCG_STATIC_CALL_ARGS_SIZE + tmp_buf_size; 963 frame_size += TCG_TARGET_STACK_ALIGN - 1; 964 frame_size &= -TCG_TARGET_STACK_ALIGN; 965 tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) | 966 INSN_IMM13(-frame_size)); 967 968#ifndef CONFIG_SOFTMMU 969 if (guest_base != 0) { 970 tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, 971 guest_base, true, TCG_REG_T1); 972 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 973 } 974#endif 975 976 /* We choose TCG_REG_TB such that no move is required. */ 977 QEMU_BUILD_BUG_ON(TCG_REG_TB != TCG_REG_I1); 978 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); 979 980 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I1, 0, JMPL); 981 /* delay slot */ 982 tcg_out_nop(s); 983 984 /* Epilogue for goto_ptr. */ 985 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 986 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); 987 /* delay slot */ 988 tcg_out_movi_s13(s, TCG_REG_O0, 0); 989} 990 991static void tcg_out_tb_start(TCGContext *s) 992{ 993 /* nothing to do */ 994} 995 996static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 997{ 998 int i; 999 for (i = 0; i < count; ++i) { 1000 p[i] = NOP; 1001 } 1002} 1003 1004static const TCGLdstHelperParam ldst_helper_param = { 1005 .ntmp = 1, .tmp = { TCG_REG_T1 } 1006}; 1007 1008static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1009{ 1010 MemOp opc = get_memop(lb->oi); 1011 MemOp sgn; 1012 1013 if (!patch_reloc(lb->label_ptr[0], R_SPARC_WDISP19, 1014 (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 0)) { 1015 return false; 1016 } 1017 1018 /* Use inline tcg_out_ext32s; otherwise let the helper sign-extend. */ 1019 sgn = (opc & MO_SIZE) < MO_32 ? MO_SIGN : 0; 1020 1021 tcg_out_ld_helper_args(s, lb, &ldst_helper_param); 1022 tcg_out_call(s, qemu_ld_helpers[opc & (MO_SIZE | sgn)], NULL); 1023 tcg_out_ld_helper_ret(s, lb, sgn, &ldst_helper_param); 1024 1025 tcg_out_bpcc0(s, COND_A, BPCC_A | BPCC_PT, 0); 1026 return patch_reloc(s->code_ptr - 1, R_SPARC_WDISP19, 1027 (intptr_t)lb->raddr, 0); 1028} 1029 1030static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1031{ 1032 MemOp opc = get_memop(lb->oi); 1033 1034 if (!patch_reloc(lb->label_ptr[0], R_SPARC_WDISP19, 1035 (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 0)) { 1036 return false; 1037 } 1038 1039 tcg_out_st_helper_args(s, lb, &ldst_helper_param); 1040 tcg_out_call(s, qemu_st_helpers[opc & MO_SIZE], NULL); 1041 1042 tcg_out_bpcc0(s, COND_A, BPCC_A | BPCC_PT, 0); 1043 return patch_reloc(s->code_ptr - 1, R_SPARC_WDISP19, 1044 (intptr_t)lb->raddr, 0); 1045} 1046 1047typedef struct { 1048 TCGReg base; 1049 TCGReg index; 1050 TCGAtomAlign aa; 1051} HostAddress; 1052 1053bool tcg_target_has_memory_bswap(MemOp memop) 1054{ 1055 return true; 1056} 1057 1058/* We expect to use a 13-bit negative offset from ENV. */ 1059#define MIN_TLB_MASK_TABLE_OFS -(1 << 12) 1060 1061/* 1062 * For system-mode, perform the TLB load and compare. 1063 * For user-mode, perform any required alignment tests. 1064 * In both cases, return a TCGLabelQemuLdst structure if the slow path 1065 * is required and fill in @h with the host address for the fast path. 1066 */ 1067static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 1068 TCGReg addr_reg, MemOpIdx oi, 1069 bool is_ld) 1070{ 1071 TCGType addr_type = s->addr_type; 1072 TCGLabelQemuLdst *ldst = NULL; 1073 MemOp opc = get_memop(oi); 1074 MemOp s_bits = opc & MO_SIZE; 1075 unsigned a_mask; 1076 1077 /* We don't support unaligned accesses. */ 1078 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); 1079 h->aa.align = MAX(h->aa.align, s_bits); 1080 a_mask = (1u << h->aa.align) - 1; 1081 1082#ifdef CONFIG_SOFTMMU 1083 int mem_index = get_mmuidx(oi); 1084 int fast_off = tlb_mask_table_ofs(s, mem_index); 1085 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); 1086 int table_off = fast_off + offsetof(CPUTLBDescFast, table); 1087 int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read) 1088 : offsetof(CPUTLBEntry, addr_write); 1089 int add_off = offsetof(CPUTLBEntry, addend); 1090 int compare_mask; 1091 int cc; 1092 1093 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ 1094 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_T2, TCG_AREG0, mask_off); 1095 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_T3, TCG_AREG0, table_off); 1096 1097 /* Extract the page index, shifted into place for tlb index. */ 1098 tcg_out_arithi(s, TCG_REG_T1, addr_reg, 1099 s->page_bits - CPU_TLB_ENTRY_BITS, SHIFT_SRL); 1100 tcg_out_arith(s, TCG_REG_T1, TCG_REG_T1, TCG_REG_T2, ARITH_AND); 1101 1102 /* Add the tlb_table pointer, creating the CPUTLBEntry address into R2. */ 1103 tcg_out_arith(s, TCG_REG_T1, TCG_REG_T1, TCG_REG_T3, ARITH_ADD); 1104 1105 /* 1106 * Load the tlb comparator and the addend. 1107 * Always load the entire 64-bit comparator for simplicity. 1108 * We will ignore the high bits via BPCC_ICC below. 1109 */ 1110 tcg_out_ld(s, TCG_TYPE_I64, TCG_REG_T2, TCG_REG_T1, cmp_off); 1111 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_T1, TCG_REG_T1, add_off); 1112 h->base = TCG_REG_T1; 1113 1114 /* Mask out the page offset, except for the required alignment. */ 1115 compare_mask = s->page_mask | a_mask; 1116 if (check_fit_tl(compare_mask, 13)) { 1117 tcg_out_arithi(s, TCG_REG_T3, addr_reg, compare_mask, ARITH_AND); 1118 } else { 1119 tcg_out_movi_s32(s, TCG_REG_T3, compare_mask); 1120 tcg_out_arith(s, TCG_REG_T3, addr_reg, TCG_REG_T3, ARITH_AND); 1121 } 1122 tcg_out_cmp(s, TCG_COND_NE, TCG_REG_T2, TCG_REG_T3, 0); 1123 1124 ldst = new_ldst_label(s); 1125 ldst->is_ld = is_ld; 1126 ldst->oi = oi; 1127 ldst->addr_reg = addr_reg; 1128 ldst->label_ptr[0] = s->code_ptr; 1129 1130 /* bne,pn %[xi]cc, label0 */ 1131 cc = addr_type == TCG_TYPE_I32 ? BPCC_ICC : BPCC_XCC; 1132 tcg_out_bpcc0(s, COND_NE, BPCC_PN | cc, 0); 1133#else 1134 /* 1135 * If the size equals the required alignment, we can skip the test 1136 * and allow host SIGBUS to deliver SIGBUS to the guest. 1137 * Otherwise, test for at least natural alignment and defer 1138 * everything else to the helper functions. 1139 */ 1140 if (s_bits != memop_alignment_bits(opc)) { 1141 tcg_debug_assert(check_fit_tl(a_mask, 13)); 1142 tcg_out_arithi(s, TCG_REG_G0, addr_reg, a_mask, ARITH_ANDCC); 1143 1144 ldst = new_ldst_label(s); 1145 ldst->is_ld = is_ld; 1146 ldst->oi = oi; 1147 ldst->addr_reg = addr_reg; 1148 ldst->label_ptr[0] = s->code_ptr; 1149 1150 /* bne,pn %icc, label0 */ 1151 tcg_out_bpcc0(s, COND_NE, BPCC_PN | BPCC_ICC, 0); 1152 } 1153 h->base = guest_base ? TCG_GUEST_BASE_REG : TCG_REG_G0; 1154#endif 1155 1156 /* If the guest address must be zero-extended, do in the delay slot. */ 1157 if (addr_type == TCG_TYPE_I32) { 1158 tcg_out_ext32u(s, TCG_REG_T2, addr_reg); 1159 h->index = TCG_REG_T2; 1160 } else { 1161 if (ldst) { 1162 tcg_out_nop(s); 1163 } 1164 h->index = addr_reg; 1165 } 1166 return ldst; 1167} 1168 1169static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr, 1170 MemOpIdx oi, TCGType data_type) 1171{ 1172 static const int ld_opc[(MO_SSIZE | MO_BSWAP) + 1] = { 1173 [MO_UB] = LDUB, 1174 [MO_SB] = LDSB, 1175 [MO_UB | MO_LE] = LDUB, 1176 [MO_SB | MO_LE] = LDSB, 1177 1178 [MO_BEUW] = LDUH, 1179 [MO_BESW] = LDSH, 1180 [MO_BEUL] = LDUW, 1181 [MO_BESL] = LDSW, 1182 [MO_BEUQ] = LDX, 1183 [MO_BESQ] = LDX, 1184 1185 [MO_LEUW] = LDUH_LE, 1186 [MO_LESW] = LDSH_LE, 1187 [MO_LEUL] = LDUW_LE, 1188 [MO_LESL] = LDSW_LE, 1189 [MO_LEUQ] = LDX_LE, 1190 [MO_LESQ] = LDX_LE, 1191 }; 1192 1193 TCGLabelQemuLdst *ldst; 1194 HostAddress h; 1195 1196 ldst = prepare_host_addr(s, &h, addr, oi, true); 1197 1198 tcg_out_ldst_rr(s, data, h.base, h.index, 1199 ld_opc[get_memop(oi) & (MO_BSWAP | MO_SSIZE)]); 1200 1201 if (ldst) { 1202 ldst->type = data_type; 1203 ldst->datalo_reg = data; 1204 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1205 } 1206} 1207 1208static void tcg_out_qemu_st(TCGContext *s, TCGReg data, TCGReg addr, 1209 MemOpIdx oi, TCGType data_type) 1210{ 1211 static const int st_opc[(MO_SIZE | MO_BSWAP) + 1] = { 1212 [MO_UB] = STB, 1213 1214 [MO_BEUW] = STH, 1215 [MO_BEUL] = STW, 1216 [MO_BEUQ] = STX, 1217 1218 [MO_LEUW] = STH_LE, 1219 [MO_LEUL] = STW_LE, 1220 [MO_LEUQ] = STX_LE, 1221 }; 1222 1223 TCGLabelQemuLdst *ldst; 1224 HostAddress h; 1225 1226 ldst = prepare_host_addr(s, &h, addr, oi, false); 1227 1228 tcg_out_ldst_rr(s, data, h.base, h.index, 1229 st_opc[get_memop(oi) & (MO_BSWAP | MO_SIZE)]); 1230 1231 if (ldst) { 1232 ldst->type = data_type; 1233 ldst->datalo_reg = data; 1234 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1235 } 1236} 1237 1238static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) 1239{ 1240 if (check_fit_ptr(a0, 13)) { 1241 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); 1242 tcg_out_movi_s13(s, TCG_REG_O0, a0); 1243 return; 1244 } else { 1245 intptr_t tb_diff = tcg_tbrel_diff(s, (void *)a0); 1246 if (check_fit_ptr(tb_diff, 13)) { 1247 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); 1248 /* Note that TCG_REG_TB has been unwound to O1. */ 1249 tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O1, tb_diff, ARITH_ADD); 1250 return; 1251 } 1252 } 1253 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, a0 & ~0x3ff); 1254 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); 1255 tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O0, a0 & 0x3ff, ARITH_OR); 1256} 1257 1258static void tcg_out_goto_tb(TCGContext *s, int which) 1259{ 1260 ptrdiff_t off = tcg_tbrel_diff(s, (void *)get_jmp_target_addr(s, which)); 1261 1262 /* Load link and indirect branch. */ 1263 set_jmp_insn_offset(s, which); 1264 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TB, TCG_REG_TB, off); 1265 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_TB, 0, JMPL); 1266 /* delay slot */ 1267 tcg_out_nop(s); 1268 set_jmp_reset_offset(s, which); 1269 1270 /* 1271 * For the unlinked path of goto_tb, we need to reset TCG_REG_TB 1272 * to the beginning of this TB. 1273 */ 1274 off = -tcg_current_code_size(s); 1275 if (check_fit_i32(off, 13)) { 1276 tcg_out_arithi(s, TCG_REG_TB, TCG_REG_TB, off, ARITH_ADD); 1277 } else { 1278 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, off); 1279 tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB, TCG_REG_T1, ARITH_ADD); 1280 } 1281} 1282 1283void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1284 uintptr_t jmp_rx, uintptr_t jmp_rw) 1285{ 1286} 1287 1288static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, 1289 const TCGArg args[TCG_MAX_OP_ARGS], 1290 const int const_args[TCG_MAX_OP_ARGS]) 1291{ 1292 TCGArg a0, a1, a2; 1293 int c, c2; 1294 1295 /* Hoist the loads of the most common arguments. */ 1296 a0 = args[0]; 1297 a1 = args[1]; 1298 a2 = args[2]; 1299 c2 = const_args[2]; 1300 1301 switch (opc) { 1302 case INDEX_op_goto_ptr: 1303 tcg_out_arithi(s, TCG_REG_G0, a0, 0, JMPL); 1304 tcg_out_mov_delay(s, TCG_REG_TB, a0); 1305 break; 1306 case INDEX_op_br: 1307 tcg_out_bpcc(s, COND_A, BPCC_PT, arg_label(a0)); 1308 tcg_out_nop(s); 1309 break; 1310 1311#define OP_32_64(x) \ 1312 glue(glue(case INDEX_op_, x), _i32): \ 1313 glue(glue(case INDEX_op_, x), _i64) 1314 1315 OP_32_64(ld8u): 1316 tcg_out_ldst(s, a0, a1, a2, LDUB); 1317 break; 1318 OP_32_64(ld8s): 1319 tcg_out_ldst(s, a0, a1, a2, LDSB); 1320 break; 1321 OP_32_64(ld16u): 1322 tcg_out_ldst(s, a0, a1, a2, LDUH); 1323 break; 1324 OP_32_64(ld16s): 1325 tcg_out_ldst(s, a0, a1, a2, LDSH); 1326 break; 1327 case INDEX_op_ld_i32: 1328 case INDEX_op_ld32u_i64: 1329 tcg_out_ldst(s, a0, a1, a2, LDUW); 1330 break; 1331 OP_32_64(st8): 1332 tcg_out_ldst(s, a0, a1, a2, STB); 1333 break; 1334 OP_32_64(st16): 1335 tcg_out_ldst(s, a0, a1, a2, STH); 1336 break; 1337 case INDEX_op_st_i32: 1338 case INDEX_op_st32_i64: 1339 tcg_out_ldst(s, a0, a1, a2, STW); 1340 break; 1341 OP_32_64(add): 1342 c = ARITH_ADD; 1343 goto gen_arith; 1344 OP_32_64(sub): 1345 c = ARITH_SUB; 1346 goto gen_arith; 1347 OP_32_64(and): 1348 c = ARITH_AND; 1349 goto gen_arith; 1350 OP_32_64(andc): 1351 c = ARITH_ANDN; 1352 goto gen_arith; 1353 OP_32_64(or): 1354 c = ARITH_OR; 1355 goto gen_arith; 1356 OP_32_64(orc): 1357 c = ARITH_ORN; 1358 goto gen_arith; 1359 OP_32_64(xor): 1360 c = ARITH_XOR; 1361 goto gen_arith; 1362 case INDEX_op_shl_i32: 1363 c = SHIFT_SLL; 1364 do_shift32: 1365 /* Limit immediate shift count lest we create an illegal insn. */ 1366 tcg_out_arithc(s, a0, a1, a2 & 31, c2, c); 1367 break; 1368 case INDEX_op_shr_i32: 1369 c = SHIFT_SRL; 1370 goto do_shift32; 1371 case INDEX_op_sar_i32: 1372 c = SHIFT_SRA; 1373 goto do_shift32; 1374 case INDEX_op_mul_i32: 1375 c = ARITH_UMUL; 1376 goto gen_arith; 1377 1378 OP_32_64(neg): 1379 c = ARITH_SUB; 1380 goto gen_arith1; 1381 OP_32_64(not): 1382 c = ARITH_ORN; 1383 goto gen_arith1; 1384 1385 case INDEX_op_div_i32: 1386 tcg_out_div32(s, a0, a1, a2, c2, 0); 1387 break; 1388 case INDEX_op_divu_i32: 1389 tcg_out_div32(s, a0, a1, a2, c2, 1); 1390 break; 1391 1392 case INDEX_op_brcond_i32: 1393 tcg_out_brcond_i32(s, a2, a0, a1, const_args[1], arg_label(args[3])); 1394 break; 1395 case INDEX_op_setcond_i32: 1396 tcg_out_setcond_i32(s, args[3], a0, a1, a2, c2, false); 1397 break; 1398 case INDEX_op_negsetcond_i32: 1399 tcg_out_setcond_i32(s, args[3], a0, a1, a2, c2, true); 1400 break; 1401 case INDEX_op_movcond_i32: 1402 tcg_out_movcond_i32(s, args[5], a0, a1, a2, c2, args[3], const_args[3]); 1403 break; 1404 1405 case INDEX_op_add2_i32: 1406 tcg_out_addsub2_i32(s, args[0], args[1], args[2], args[3], 1407 args[4], const_args[4], args[5], const_args[5], 1408 ARITH_ADDCC, ARITH_ADDC); 1409 break; 1410 case INDEX_op_sub2_i32: 1411 tcg_out_addsub2_i32(s, args[0], args[1], args[2], args[3], 1412 args[4], const_args[4], args[5], const_args[5], 1413 ARITH_SUBCC, ARITH_SUBC); 1414 break; 1415 case INDEX_op_mulu2_i32: 1416 c = ARITH_UMUL; 1417 goto do_mul2; 1418 case INDEX_op_muls2_i32: 1419 c = ARITH_SMUL; 1420 do_mul2: 1421 /* The 32-bit multiply insns produce a full 64-bit result. */ 1422 tcg_out_arithc(s, a0, a2, args[3], const_args[3], c); 1423 tcg_out_arithi(s, a1, a0, 32, SHIFT_SRLX); 1424 break; 1425 1426 case INDEX_op_qemu_ld_i32: 1427 tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32); 1428 break; 1429 case INDEX_op_qemu_ld_i64: 1430 tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64); 1431 break; 1432 case INDEX_op_qemu_st_i32: 1433 tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32); 1434 break; 1435 case INDEX_op_qemu_st_i64: 1436 tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64); 1437 break; 1438 1439 case INDEX_op_ld32s_i64: 1440 tcg_out_ldst(s, a0, a1, a2, LDSW); 1441 break; 1442 case INDEX_op_ld_i64: 1443 tcg_out_ldst(s, a0, a1, a2, LDX); 1444 break; 1445 case INDEX_op_st_i64: 1446 tcg_out_ldst(s, a0, a1, a2, STX); 1447 break; 1448 case INDEX_op_shl_i64: 1449 c = SHIFT_SLLX; 1450 do_shift64: 1451 /* Limit immediate shift count lest we create an illegal insn. */ 1452 tcg_out_arithc(s, a0, a1, a2 & 63, c2, c); 1453 break; 1454 case INDEX_op_shr_i64: 1455 c = SHIFT_SRLX; 1456 goto do_shift64; 1457 case INDEX_op_sar_i64: 1458 c = SHIFT_SRAX; 1459 goto do_shift64; 1460 case INDEX_op_mul_i64: 1461 c = ARITH_MULX; 1462 goto gen_arith; 1463 case INDEX_op_div_i64: 1464 c = ARITH_SDIVX; 1465 goto gen_arith; 1466 case INDEX_op_divu_i64: 1467 c = ARITH_UDIVX; 1468 goto gen_arith; 1469 1470 case INDEX_op_brcond_i64: 1471 tcg_out_brcond_i64(s, a2, a0, a1, const_args[1], arg_label(args[3])); 1472 break; 1473 case INDEX_op_setcond_i64: 1474 tcg_out_setcond_i64(s, args[3], a0, a1, a2, c2, false); 1475 break; 1476 case INDEX_op_negsetcond_i64: 1477 tcg_out_setcond_i64(s, args[3], a0, a1, a2, c2, true); 1478 break; 1479 case INDEX_op_movcond_i64: 1480 tcg_out_movcond_i64(s, args[5], a0, a1, a2, c2, args[3], const_args[3]); 1481 break; 1482 case INDEX_op_add2_i64: 1483 tcg_out_addsub2_i64(s, args[0], args[1], args[2], args[3], args[4], 1484 const_args[4], args[5], const_args[5], false); 1485 break; 1486 case INDEX_op_sub2_i64: 1487 tcg_out_addsub2_i64(s, args[0], args[1], args[2], args[3], args[4], 1488 const_args[4], args[5], const_args[5], true); 1489 break; 1490 case INDEX_op_muluh_i64: 1491 tcg_out_arith(s, args[0], args[1], args[2], ARITH_UMULXHI); 1492 break; 1493 1494 gen_arith: 1495 tcg_out_arithc(s, a0, a1, a2, c2, c); 1496 break; 1497 1498 gen_arith1: 1499 tcg_out_arithc(s, a0, TCG_REG_G0, a1, const_args[1], c); 1500 break; 1501 1502 case INDEX_op_mb: 1503 tcg_out_mb(s, a0); 1504 break; 1505 1506 case INDEX_op_extract_i64: 1507 tcg_debug_assert(a2 + args[3] == 32); 1508 tcg_out_arithi(s, a0, a1, a2, SHIFT_SRL); 1509 break; 1510 case INDEX_op_sextract_i64: 1511 tcg_debug_assert(a2 + args[3] == 32); 1512 tcg_out_arithi(s, a0, a1, a2, SHIFT_SRA); 1513 break; 1514 1515 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ 1516 case INDEX_op_mov_i64: 1517 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 1518 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 1519 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 1520 case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ 1521 case INDEX_op_ext8s_i64: 1522 case INDEX_op_ext8u_i32: 1523 case INDEX_op_ext8u_i64: 1524 case INDEX_op_ext16s_i32: 1525 case INDEX_op_ext16s_i64: 1526 case INDEX_op_ext16u_i32: 1527 case INDEX_op_ext16u_i64: 1528 case INDEX_op_ext32s_i64: 1529 case INDEX_op_ext32u_i64: 1530 case INDEX_op_ext_i32_i64: 1531 case INDEX_op_extu_i32_i64: 1532 default: 1533 g_assert_not_reached(); 1534 } 1535} 1536 1537static TCGConstraintSetIndex 1538tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) 1539{ 1540 switch (op) { 1541 case INDEX_op_goto_ptr: 1542 return C_O0_I1(r); 1543 1544 case INDEX_op_ld8u_i32: 1545 case INDEX_op_ld8u_i64: 1546 case INDEX_op_ld8s_i32: 1547 case INDEX_op_ld8s_i64: 1548 case INDEX_op_ld16u_i32: 1549 case INDEX_op_ld16u_i64: 1550 case INDEX_op_ld16s_i32: 1551 case INDEX_op_ld16s_i64: 1552 case INDEX_op_ld_i32: 1553 case INDEX_op_ld32u_i64: 1554 case INDEX_op_ld32s_i64: 1555 case INDEX_op_ld_i64: 1556 case INDEX_op_neg_i32: 1557 case INDEX_op_neg_i64: 1558 case INDEX_op_not_i32: 1559 case INDEX_op_not_i64: 1560 case INDEX_op_ext32s_i64: 1561 case INDEX_op_ext32u_i64: 1562 case INDEX_op_ext_i32_i64: 1563 case INDEX_op_extu_i32_i64: 1564 case INDEX_op_extract_i64: 1565 case INDEX_op_sextract_i64: 1566 case INDEX_op_qemu_ld_i32: 1567 case INDEX_op_qemu_ld_i64: 1568 return C_O1_I1(r, r); 1569 1570 case INDEX_op_st8_i32: 1571 case INDEX_op_st8_i64: 1572 case INDEX_op_st16_i32: 1573 case INDEX_op_st16_i64: 1574 case INDEX_op_st_i32: 1575 case INDEX_op_st32_i64: 1576 case INDEX_op_st_i64: 1577 case INDEX_op_qemu_st_i32: 1578 case INDEX_op_qemu_st_i64: 1579 return C_O0_I2(rz, r); 1580 1581 case INDEX_op_add_i32: 1582 case INDEX_op_add_i64: 1583 case INDEX_op_mul_i32: 1584 case INDEX_op_mul_i64: 1585 case INDEX_op_div_i32: 1586 case INDEX_op_div_i64: 1587 case INDEX_op_divu_i32: 1588 case INDEX_op_divu_i64: 1589 case INDEX_op_sub_i32: 1590 case INDEX_op_sub_i64: 1591 case INDEX_op_and_i32: 1592 case INDEX_op_and_i64: 1593 case INDEX_op_andc_i32: 1594 case INDEX_op_andc_i64: 1595 case INDEX_op_or_i32: 1596 case INDEX_op_or_i64: 1597 case INDEX_op_orc_i32: 1598 case INDEX_op_orc_i64: 1599 case INDEX_op_xor_i32: 1600 case INDEX_op_xor_i64: 1601 case INDEX_op_shl_i32: 1602 case INDEX_op_shl_i64: 1603 case INDEX_op_shr_i32: 1604 case INDEX_op_shr_i64: 1605 case INDEX_op_sar_i32: 1606 case INDEX_op_sar_i64: 1607 case INDEX_op_setcond_i32: 1608 case INDEX_op_setcond_i64: 1609 case INDEX_op_negsetcond_i32: 1610 case INDEX_op_negsetcond_i64: 1611 return C_O1_I2(r, rz, rJ); 1612 1613 case INDEX_op_brcond_i32: 1614 case INDEX_op_brcond_i64: 1615 return C_O0_I2(rz, rJ); 1616 case INDEX_op_movcond_i32: 1617 case INDEX_op_movcond_i64: 1618 return C_O1_I4(r, rz, rJ, rI, 0); 1619 case INDEX_op_add2_i32: 1620 case INDEX_op_add2_i64: 1621 case INDEX_op_sub2_i32: 1622 case INDEX_op_sub2_i64: 1623 return C_O2_I4(r, r, rz, rz, rJ, rJ); 1624 case INDEX_op_mulu2_i32: 1625 case INDEX_op_muls2_i32: 1626 return C_O2_I2(r, r, rz, rJ); 1627 case INDEX_op_muluh_i64: 1628 return C_O1_I2(r, r, r); 1629 1630 default: 1631 return C_NotImplemented; 1632 } 1633} 1634 1635static void tcg_target_init(TCGContext *s) 1636{ 1637 /* 1638 * Only probe for the platform and capabilities if we haven't already 1639 * determined maximum values at compile time. 1640 */ 1641#ifndef use_vis3_instructions 1642 { 1643 unsigned long hwcap = qemu_getauxval(AT_HWCAP); 1644 use_vis3_instructions = (hwcap & HWCAP_SPARC_VIS3) != 0; 1645 } 1646#endif 1647 1648 tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS; 1649 tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS; 1650 1651 tcg_target_call_clobber_regs = 0; 1652 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G1); 1653 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G2); 1654 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G3); 1655 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G4); 1656 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G5); 1657 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G6); 1658 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G7); 1659 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O0); 1660 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O1); 1661 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O2); 1662 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O3); 1663 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O4); 1664 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O5); 1665 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O6); 1666 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O7); 1667 1668 s->reserved_regs = 0; 1669 tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0); /* zero */ 1670 tcg_regset_set_reg(s->reserved_regs, TCG_REG_G6); /* reserved for os */ 1671 tcg_regset_set_reg(s->reserved_regs, TCG_REG_G7); /* thread pointer */ 1672 tcg_regset_set_reg(s->reserved_regs, TCG_REG_I6); /* frame pointer */ 1673 tcg_regset_set_reg(s->reserved_regs, TCG_REG_I7); /* return address */ 1674 tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6); /* stack pointer */ 1675 tcg_regset_set_reg(s->reserved_regs, TCG_REG_T1); /* for internal use */ 1676 tcg_regset_set_reg(s->reserved_regs, TCG_REG_T2); /* for internal use */ 1677 tcg_regset_set_reg(s->reserved_regs, TCG_REG_T3); /* for internal use */ 1678} 1679 1680#define ELF_HOST_MACHINE EM_SPARCV9 1681 1682typedef struct { 1683 DebugFrameHeader h; 1684 uint8_t fde_def_cfa[4]; 1685 uint8_t fde_win_save; 1686 uint8_t fde_ret_save[3]; 1687} DebugFrame; 1688 1689static const DebugFrame debug_frame = { 1690 .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ 1691 .h.cie.id = -1, 1692 .h.cie.version = 1, 1693 .h.cie.code_align = 1, 1694 .h.cie.data_align = -sizeof(void *) & 0x7f, 1695 .h.cie.return_column = 15, /* o7 */ 1696 1697 /* Total FDE size does not include the "len" member. */ 1698 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 1699 1700 .fde_def_cfa = { 1701 12, 30, /* DW_CFA_def_cfa i6, 2047 */ 1702 (2047 & 0x7f) | 0x80, (2047 >> 7) 1703 }, 1704 .fde_win_save = 0x2d, /* DW_CFA_GNU_window_save */ 1705 .fde_ret_save = { 9, 15, 31 }, /* DW_CFA_register o7, i7 */ 1706}; 1707 1708void tcg_register_jit(const void *buf, size_t buf_size) 1709{ 1710 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 1711} 1712