1 /* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2009 Ulrich Hecht <uli@suse.de> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #ifndef S390_TCG_TARGET_H 26 #define S390_TCG_TARGET_H 27 28 #define TCG_TARGET_INSN_UNIT_SIZE 2 29 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 19 30 31 /* We have a +- 4GB range on the branches; leave some slop. */ 32 #define MAX_CODE_GEN_BUFFER_SIZE (3 * GiB) 33 34 typedef enum TCGReg { 35 TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3, 36 TCG_REG_R4, TCG_REG_R5, TCG_REG_R6, TCG_REG_R7, 37 TCG_REG_R8, TCG_REG_R9, TCG_REG_R10, TCG_REG_R11, 38 TCG_REG_R12, TCG_REG_R13, TCG_REG_R14, TCG_REG_R15, 39 40 TCG_REG_V0 = 32, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3, 41 TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7, 42 TCG_REG_V8, TCG_REG_V9, TCG_REG_V10, TCG_REG_V11, 43 TCG_REG_V12, TCG_REG_V13, TCG_REG_V14, TCG_REG_V15, 44 TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19, 45 TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23, 46 TCG_REG_V24, TCG_REG_V25, TCG_REG_V26, TCG_REG_V27, 47 TCG_REG_V28, TCG_REG_V29, TCG_REG_V30, TCG_REG_V31, 48 49 TCG_AREG0 = TCG_REG_R10, 50 TCG_REG_CALL_STACK = TCG_REG_R15 51 } TCGReg; 52 53 #define TCG_TARGET_NB_REGS 64 54 55 /* A list of relevant facilities used by this translator. Some of these 56 are required for proper operation, and these are checked at startup. */ 57 58 #define FACILITY_ZARCH_ACTIVE 2 59 #define FACILITY_LONG_DISP 18 60 #define FACILITY_EXT_IMM 21 61 #define FACILITY_GEN_INST_EXT 34 62 #define FACILITY_LOAD_ON_COND 45 63 #define FACILITY_FAST_BCR_SER FACILITY_LOAD_ON_COND 64 #define FACILITY_DISTINCT_OPS FACILITY_LOAD_ON_COND 65 #define FACILITY_LOAD_ON_COND2 53 66 #define FACILITY_VECTOR 129 67 #define FACILITY_VECTOR_ENH1 135 68 69 extern uint64_t s390_facilities[3]; 70 71 #define HAVE_FACILITY(X) \ 72 ((s390_facilities[FACILITY_##X / 64] >> (63 - FACILITY_##X % 64)) & 1) 73 74 /* optional instructions */ 75 #define TCG_TARGET_HAS_div2_i32 1 76 #define TCG_TARGET_HAS_rot_i32 1 77 #define TCG_TARGET_HAS_ext8s_i32 1 78 #define TCG_TARGET_HAS_ext16s_i32 1 79 #define TCG_TARGET_HAS_ext8u_i32 1 80 #define TCG_TARGET_HAS_ext16u_i32 1 81 #define TCG_TARGET_HAS_bswap16_i32 1 82 #define TCG_TARGET_HAS_bswap32_i32 1 83 #define TCG_TARGET_HAS_not_i32 0 84 #define TCG_TARGET_HAS_neg_i32 1 85 #define TCG_TARGET_HAS_andc_i32 0 86 #define TCG_TARGET_HAS_orc_i32 0 87 #define TCG_TARGET_HAS_eqv_i32 0 88 #define TCG_TARGET_HAS_nand_i32 0 89 #define TCG_TARGET_HAS_nor_i32 0 90 #define TCG_TARGET_HAS_clz_i32 0 91 #define TCG_TARGET_HAS_ctz_i32 0 92 #define TCG_TARGET_HAS_ctpop_i32 0 93 #define TCG_TARGET_HAS_deposit_i32 HAVE_FACILITY(GEN_INST_EXT) 94 #define TCG_TARGET_HAS_extract_i32 HAVE_FACILITY(GEN_INST_EXT) 95 #define TCG_TARGET_HAS_sextract_i32 0 96 #define TCG_TARGET_HAS_extract2_i32 0 97 #define TCG_TARGET_HAS_movcond_i32 1 98 #define TCG_TARGET_HAS_add2_i32 1 99 #define TCG_TARGET_HAS_sub2_i32 1 100 #define TCG_TARGET_HAS_mulu2_i32 0 101 #define TCG_TARGET_HAS_muls2_i32 0 102 #define TCG_TARGET_HAS_muluh_i32 0 103 #define TCG_TARGET_HAS_mulsh_i32 0 104 #define TCG_TARGET_HAS_extrl_i64_i32 0 105 #define TCG_TARGET_HAS_extrh_i64_i32 0 106 #define TCG_TARGET_HAS_direct_jump HAVE_FACILITY(GEN_INST_EXT) 107 #define TCG_TARGET_HAS_qemu_st8_i32 0 108 109 #define TCG_TARGET_HAS_div2_i64 1 110 #define TCG_TARGET_HAS_rot_i64 1 111 #define TCG_TARGET_HAS_ext8s_i64 1 112 #define TCG_TARGET_HAS_ext16s_i64 1 113 #define TCG_TARGET_HAS_ext32s_i64 1 114 #define TCG_TARGET_HAS_ext8u_i64 1 115 #define TCG_TARGET_HAS_ext16u_i64 1 116 #define TCG_TARGET_HAS_ext32u_i64 1 117 #define TCG_TARGET_HAS_bswap16_i64 1 118 #define TCG_TARGET_HAS_bswap32_i64 1 119 #define TCG_TARGET_HAS_bswap64_i64 1 120 #define TCG_TARGET_HAS_not_i64 0 121 #define TCG_TARGET_HAS_neg_i64 1 122 #define TCG_TARGET_HAS_andc_i64 0 123 #define TCG_TARGET_HAS_orc_i64 0 124 #define TCG_TARGET_HAS_eqv_i64 0 125 #define TCG_TARGET_HAS_nand_i64 0 126 #define TCG_TARGET_HAS_nor_i64 0 127 #define TCG_TARGET_HAS_clz_i64 HAVE_FACILITY(EXT_IMM) 128 #define TCG_TARGET_HAS_ctz_i64 0 129 #define TCG_TARGET_HAS_ctpop_i64 0 130 #define TCG_TARGET_HAS_deposit_i64 HAVE_FACILITY(GEN_INST_EXT) 131 #define TCG_TARGET_HAS_extract_i64 HAVE_FACILITY(GEN_INST_EXT) 132 #define TCG_TARGET_HAS_sextract_i64 0 133 #define TCG_TARGET_HAS_extract2_i64 0 134 #define TCG_TARGET_HAS_movcond_i64 1 135 #define TCG_TARGET_HAS_add2_i64 1 136 #define TCG_TARGET_HAS_sub2_i64 1 137 #define TCG_TARGET_HAS_mulu2_i64 1 138 #define TCG_TARGET_HAS_muls2_i64 0 139 #define TCG_TARGET_HAS_muluh_i64 0 140 #define TCG_TARGET_HAS_mulsh_i64 0 141 142 #define TCG_TARGET_HAS_v64 HAVE_FACILITY(VECTOR) 143 #define TCG_TARGET_HAS_v128 HAVE_FACILITY(VECTOR) 144 #define TCG_TARGET_HAS_v256 0 145 146 #define TCG_TARGET_HAS_andc_vec 1 147 #define TCG_TARGET_HAS_orc_vec HAVE_FACILITY(VECTOR_ENH1) 148 #define TCG_TARGET_HAS_not_vec 1 149 #define TCG_TARGET_HAS_neg_vec 1 150 #define TCG_TARGET_HAS_abs_vec 1 151 #define TCG_TARGET_HAS_roti_vec 1 152 #define TCG_TARGET_HAS_rots_vec 1 153 #define TCG_TARGET_HAS_rotv_vec 1 154 #define TCG_TARGET_HAS_shi_vec 1 155 #define TCG_TARGET_HAS_shs_vec 1 156 #define TCG_TARGET_HAS_shv_vec 1 157 #define TCG_TARGET_HAS_mul_vec 1 158 #define TCG_TARGET_HAS_sat_vec 0 159 #define TCG_TARGET_HAS_minmax_vec 1 160 #define TCG_TARGET_HAS_bitsel_vec 1 161 #define TCG_TARGET_HAS_cmpsel_vec 0 162 163 /* used for function call generation */ 164 #define TCG_TARGET_STACK_ALIGN 8 165 #define TCG_TARGET_CALL_STACK_OFFSET 160 166 167 #define TCG_TARGET_EXTEND_ARGS 1 168 #define TCG_TARGET_HAS_MEMORY_BSWAP 1 169 170 #define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) 171 172 static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, 173 uintptr_t jmp_rw, uintptr_t addr) 174 { 175 /* patch the branch destination */ 176 intptr_t disp = addr - (jmp_rx - 2); 177 qatomic_set((int32_t *)jmp_rw, disp / 2); 178 /* no need to flush icache explicitly */ 179 } 180 181 #ifdef CONFIG_SOFTMMU 182 #define TCG_TARGET_NEED_LDST_LABELS 183 #endif 184 #define TCG_TARGET_NEED_POOL_LABELS 185 186 #endif 187