1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2009 Ulrich Hecht <uli@suse.de> 5 * Copyright (c) 2009 Alexander Graf <agraf@suse.de> 6 * Copyright (c) 2010 Richard Henderson <rth@twiddle.net> 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27/* We only support generating code for 64-bit mode. */ 28#if TCG_TARGET_REG_BITS != 64 29#error "unsupported code generation mode" 30#endif 31 32#include "../tcg-ldst.c.inc" 33#include "../tcg-pool.c.inc" 34#include "elf.h" 35 36#define TCG_CT_CONST_S16 (1 << 8) 37#define TCG_CT_CONST_S32 (1 << 9) 38#define TCG_CT_CONST_S33 (1 << 10) 39#define TCG_CT_CONST_ZERO (1 << 11) 40#define TCG_CT_CONST_P32 (1 << 12) 41#define TCG_CT_CONST_INV (1 << 13) 42#define TCG_CT_CONST_INVRISBG (1 << 14) 43 44#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 16) 45#define ALL_VECTOR_REGS MAKE_64BIT_MASK(32, 32) 46 47/* Several places within the instruction set 0 means "no register" 48 rather than TCG_REG_R0. */ 49#define TCG_REG_NONE 0 50 51/* A scratch register that may be be used throughout the backend. */ 52#define TCG_TMP0 TCG_REG_R1 53 54#ifndef CONFIG_SOFTMMU 55#define TCG_GUEST_BASE_REG TCG_REG_R13 56#endif 57 58/* All of the following instructions are prefixed with their instruction 59 format, and are defined as 8- or 16-bit quantities, even when the two 60 halves of the 16-bit quantity may appear 32 bits apart in the insn. 61 This makes it easy to copy the values from the tables in Appendix B. */ 62typedef enum S390Opcode { 63 RIL_AFI = 0xc209, 64 RIL_AGFI = 0xc208, 65 RIL_ALFI = 0xc20b, 66 RIL_ALGFI = 0xc20a, 67 RIL_BRASL = 0xc005, 68 RIL_BRCL = 0xc004, 69 RIL_CFI = 0xc20d, 70 RIL_CGFI = 0xc20c, 71 RIL_CLFI = 0xc20f, 72 RIL_CLGFI = 0xc20e, 73 RIL_CLRL = 0xc60f, 74 RIL_CLGRL = 0xc60a, 75 RIL_CRL = 0xc60d, 76 RIL_CGRL = 0xc608, 77 RIL_IIHF = 0xc008, 78 RIL_IILF = 0xc009, 79 RIL_LARL = 0xc000, 80 RIL_LGFI = 0xc001, 81 RIL_LGRL = 0xc408, 82 RIL_LLIHF = 0xc00e, 83 RIL_LLILF = 0xc00f, 84 RIL_LRL = 0xc40d, 85 RIL_MSFI = 0xc201, 86 RIL_MSGFI = 0xc200, 87 RIL_NIHF = 0xc00a, 88 RIL_NILF = 0xc00b, 89 RIL_OIHF = 0xc00c, 90 RIL_OILF = 0xc00d, 91 RIL_SLFI = 0xc205, 92 RIL_SLGFI = 0xc204, 93 RIL_XIHF = 0xc006, 94 RIL_XILF = 0xc007, 95 96 RI_AGHI = 0xa70b, 97 RI_AHI = 0xa70a, 98 RI_BRC = 0xa704, 99 RI_CHI = 0xa70e, 100 RI_CGHI = 0xa70f, 101 RI_IIHH = 0xa500, 102 RI_IIHL = 0xa501, 103 RI_IILH = 0xa502, 104 RI_IILL = 0xa503, 105 RI_LGHI = 0xa709, 106 RI_LLIHH = 0xa50c, 107 RI_LLIHL = 0xa50d, 108 RI_LLILH = 0xa50e, 109 RI_LLILL = 0xa50f, 110 RI_MGHI = 0xa70d, 111 RI_MHI = 0xa70c, 112 RI_NIHH = 0xa504, 113 RI_NIHL = 0xa505, 114 RI_NILH = 0xa506, 115 RI_NILL = 0xa507, 116 RI_OIHH = 0xa508, 117 RI_OIHL = 0xa509, 118 RI_OILH = 0xa50a, 119 RI_OILL = 0xa50b, 120 RI_TMLL = 0xa701, 121 122 RIEb_CGRJ = 0xec64, 123 RIEb_CLGRJ = 0xec65, 124 RIEb_CLRJ = 0xec77, 125 RIEb_CRJ = 0xec76, 126 127 RIEc_CGIJ = 0xec7c, 128 RIEc_CIJ = 0xec7e, 129 RIEc_CLGIJ = 0xec7d, 130 RIEc_CLIJ = 0xec7f, 131 132 RIEf_RISBG = 0xec55, 133 134 RIEg_LOCGHI = 0xec46, 135 136 RRE_AGR = 0xb908, 137 RRE_ALGR = 0xb90a, 138 RRE_ALCR = 0xb998, 139 RRE_ALCGR = 0xb988, 140 RRE_ALGFR = 0xb91a, 141 RRE_CGR = 0xb920, 142 RRE_CLGR = 0xb921, 143 RRE_DLGR = 0xb987, 144 RRE_DLR = 0xb997, 145 RRE_DSGFR = 0xb91d, 146 RRE_DSGR = 0xb90d, 147 RRE_FLOGR = 0xb983, 148 RRE_LGBR = 0xb906, 149 RRE_LCGR = 0xb903, 150 RRE_LGFR = 0xb914, 151 RRE_LGHR = 0xb907, 152 RRE_LGR = 0xb904, 153 RRE_LLGCR = 0xb984, 154 RRE_LLGFR = 0xb916, 155 RRE_LLGHR = 0xb985, 156 RRE_LRVR = 0xb91f, 157 RRE_LRVGR = 0xb90f, 158 RRE_LTGR = 0xb902, 159 RRE_MLGR = 0xb986, 160 RRE_MSGR = 0xb90c, 161 RRE_MSR = 0xb252, 162 RRE_NGR = 0xb980, 163 RRE_OGR = 0xb981, 164 RRE_SGR = 0xb909, 165 RRE_SLGR = 0xb90b, 166 RRE_SLBR = 0xb999, 167 RRE_SLBGR = 0xb989, 168 RRE_XGR = 0xb982, 169 170 RRFa_MGRK = 0xb9ec, 171 RRFa_MSRKC = 0xb9fd, 172 RRFa_MSGRKC = 0xb9ed, 173 RRFa_NCRK = 0xb9f5, 174 RRFa_NCGRK = 0xb9e5, 175 RRFa_NNRK = 0xb974, 176 RRFa_NNGRK = 0xb964, 177 RRFa_NORK = 0xb976, 178 RRFa_NOGRK = 0xb966, 179 RRFa_NRK = 0xb9f4, 180 RRFa_NGRK = 0xb9e4, 181 RRFa_NXRK = 0xb977, 182 RRFa_NXGRK = 0xb967, 183 RRFa_OCRK = 0xb975, 184 RRFa_OCGRK = 0xb965, 185 RRFa_ORK = 0xb9f6, 186 RRFa_OGRK = 0xb9e6, 187 RRFa_SRK = 0xb9f9, 188 RRFa_SGRK = 0xb9e9, 189 RRFa_SLRK = 0xb9fb, 190 RRFa_SLGRK = 0xb9eb, 191 RRFa_XRK = 0xb9f7, 192 RRFa_XGRK = 0xb9e7, 193 194 RRFam_SELGR = 0xb9e3, 195 196 RRFc_LOCR = 0xb9f2, 197 RRFc_LOCGR = 0xb9e2, 198 RRFc_POPCNT = 0xb9e1, 199 200 RR_AR = 0x1a, 201 RR_ALR = 0x1e, 202 RR_BASR = 0x0d, 203 RR_BCR = 0x07, 204 RR_CLR = 0x15, 205 RR_CR = 0x19, 206 RR_DR = 0x1d, 207 RR_LCR = 0x13, 208 RR_LR = 0x18, 209 RR_LTR = 0x12, 210 RR_NR = 0x14, 211 RR_OR = 0x16, 212 RR_SR = 0x1b, 213 RR_SLR = 0x1f, 214 RR_XR = 0x17, 215 216 RSY_RLL = 0xeb1d, 217 RSY_RLLG = 0xeb1c, 218 RSY_SLLG = 0xeb0d, 219 RSY_SLLK = 0xebdf, 220 RSY_SRAG = 0xeb0a, 221 RSY_SRAK = 0xebdc, 222 RSY_SRLG = 0xeb0c, 223 RSY_SRLK = 0xebde, 224 225 RS_SLL = 0x89, 226 RS_SRA = 0x8a, 227 RS_SRL = 0x88, 228 229 RXY_AG = 0xe308, 230 RXY_AY = 0xe35a, 231 RXY_CG = 0xe320, 232 RXY_CLG = 0xe321, 233 RXY_CLY = 0xe355, 234 RXY_CY = 0xe359, 235 RXY_LAY = 0xe371, 236 RXY_LB = 0xe376, 237 RXY_LG = 0xe304, 238 RXY_LGB = 0xe377, 239 RXY_LGF = 0xe314, 240 RXY_LGH = 0xe315, 241 RXY_LHY = 0xe378, 242 RXY_LLGC = 0xe390, 243 RXY_LLGF = 0xe316, 244 RXY_LLGH = 0xe391, 245 RXY_LMG = 0xeb04, 246 RXY_LRV = 0xe31e, 247 RXY_LRVG = 0xe30f, 248 RXY_LRVH = 0xe31f, 249 RXY_LY = 0xe358, 250 RXY_NG = 0xe380, 251 RXY_OG = 0xe381, 252 RXY_STCY = 0xe372, 253 RXY_STG = 0xe324, 254 RXY_STHY = 0xe370, 255 RXY_STMG = 0xeb24, 256 RXY_STRV = 0xe33e, 257 RXY_STRVG = 0xe32f, 258 RXY_STRVH = 0xe33f, 259 RXY_STY = 0xe350, 260 RXY_XG = 0xe382, 261 262 RX_A = 0x5a, 263 RX_C = 0x59, 264 RX_L = 0x58, 265 RX_LA = 0x41, 266 RX_LH = 0x48, 267 RX_ST = 0x50, 268 RX_STC = 0x42, 269 RX_STH = 0x40, 270 271 VRIa_VGBM = 0xe744, 272 VRIa_VREPI = 0xe745, 273 VRIb_VGM = 0xe746, 274 VRIc_VREP = 0xe74d, 275 276 VRRa_VLC = 0xe7de, 277 VRRa_VLP = 0xe7df, 278 VRRa_VLR = 0xe756, 279 VRRc_VA = 0xe7f3, 280 VRRc_VCEQ = 0xe7f8, /* we leave the m5 cs field 0 */ 281 VRRc_VCH = 0xe7fb, /* " */ 282 VRRc_VCHL = 0xe7f9, /* " */ 283 VRRc_VERLLV = 0xe773, 284 VRRc_VESLV = 0xe770, 285 VRRc_VESRAV = 0xe77a, 286 VRRc_VESRLV = 0xe778, 287 VRRc_VML = 0xe7a2, 288 VRRc_VMN = 0xe7fe, 289 VRRc_VMNL = 0xe7fc, 290 VRRc_VMX = 0xe7ff, 291 VRRc_VMXL = 0xe7fd, 292 VRRc_VN = 0xe768, 293 VRRc_VNC = 0xe769, 294 VRRc_VNN = 0xe76e, 295 VRRc_VNO = 0xe76b, 296 VRRc_VNX = 0xe76c, 297 VRRc_VO = 0xe76a, 298 VRRc_VOC = 0xe76f, 299 VRRc_VPKS = 0xe797, /* we leave the m5 cs field 0 */ 300 VRRc_VS = 0xe7f7, 301 VRRa_VUPH = 0xe7d7, 302 VRRa_VUPL = 0xe7d6, 303 VRRc_VX = 0xe76d, 304 VRRe_VSEL = 0xe78d, 305 VRRf_VLVGP = 0xe762, 306 307 VRSa_VERLL = 0xe733, 308 VRSa_VESL = 0xe730, 309 VRSa_VESRA = 0xe73a, 310 VRSa_VESRL = 0xe738, 311 VRSb_VLVG = 0xe722, 312 VRSc_VLGV = 0xe721, 313 314 VRX_VL = 0xe706, 315 VRX_VLLEZ = 0xe704, 316 VRX_VLREP = 0xe705, 317 VRX_VST = 0xe70e, 318 VRX_VSTEF = 0xe70b, 319 VRX_VSTEG = 0xe70a, 320 321 NOP = 0x0707, 322} S390Opcode; 323 324#ifdef CONFIG_DEBUG_TCG 325static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 326 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", 327 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", 328 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 329 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7", 330 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15", 331 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23", 332 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31", 333}; 334#endif 335 336/* Since R6 is a potential argument register, choose it last of the 337 call-saved registers. Likewise prefer the call-clobbered registers 338 in reverse order to maximize the chance of avoiding the arguments. */ 339static const int tcg_target_reg_alloc_order[] = { 340 /* Call saved registers. */ 341 TCG_REG_R13, 342 TCG_REG_R12, 343 TCG_REG_R11, 344 TCG_REG_R10, 345 TCG_REG_R9, 346 TCG_REG_R8, 347 TCG_REG_R7, 348 TCG_REG_R6, 349 /* Call clobbered registers. */ 350 TCG_REG_R14, 351 TCG_REG_R0, 352 TCG_REG_R1, 353 /* Argument registers, in reverse order of allocation. */ 354 TCG_REG_R5, 355 TCG_REG_R4, 356 TCG_REG_R3, 357 TCG_REG_R2, 358 359 /* V8-V15 are call saved, and omitted. */ 360 TCG_REG_V0, 361 TCG_REG_V1, 362 TCG_REG_V2, 363 TCG_REG_V3, 364 TCG_REG_V4, 365 TCG_REG_V5, 366 TCG_REG_V6, 367 TCG_REG_V7, 368 TCG_REG_V16, 369 TCG_REG_V17, 370 TCG_REG_V18, 371 TCG_REG_V19, 372 TCG_REG_V20, 373 TCG_REG_V21, 374 TCG_REG_V22, 375 TCG_REG_V23, 376 TCG_REG_V24, 377 TCG_REG_V25, 378 TCG_REG_V26, 379 TCG_REG_V27, 380 TCG_REG_V28, 381 TCG_REG_V29, 382 TCG_REG_V30, 383 TCG_REG_V31, 384}; 385 386static const int tcg_target_call_iarg_regs[] = { 387 TCG_REG_R2, 388 TCG_REG_R3, 389 TCG_REG_R4, 390 TCG_REG_R5, 391 TCG_REG_R6, 392}; 393 394static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 395{ 396 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 397 tcg_debug_assert(slot == 0); 398 return TCG_REG_R2; 399} 400 401#define S390_CC_EQ 8 402#define S390_CC_LT 4 403#define S390_CC_GT 2 404#define S390_CC_OV 1 405#define S390_CC_NE (S390_CC_LT | S390_CC_GT) 406#define S390_CC_LE (S390_CC_LT | S390_CC_EQ) 407#define S390_CC_GE (S390_CC_GT | S390_CC_EQ) 408#define S390_CC_NEVER 0 409#define S390_CC_ALWAYS 15 410 411/* Condition codes that result from a COMPARE and COMPARE LOGICAL. */ 412static const uint8_t tcg_cond_to_s390_cond[] = { 413 [TCG_COND_EQ] = S390_CC_EQ, 414 [TCG_COND_NE] = S390_CC_NE, 415 [TCG_COND_LT] = S390_CC_LT, 416 [TCG_COND_LE] = S390_CC_LE, 417 [TCG_COND_GT] = S390_CC_GT, 418 [TCG_COND_GE] = S390_CC_GE, 419 [TCG_COND_LTU] = S390_CC_LT, 420 [TCG_COND_LEU] = S390_CC_LE, 421 [TCG_COND_GTU] = S390_CC_GT, 422 [TCG_COND_GEU] = S390_CC_GE, 423}; 424 425/* Condition codes that result from a LOAD AND TEST. Here, we have no 426 unsigned instruction variation, however since the test is vs zero we 427 can re-map the outcomes appropriately. */ 428static const uint8_t tcg_cond_to_ltr_cond[] = { 429 [TCG_COND_EQ] = S390_CC_EQ, 430 [TCG_COND_NE] = S390_CC_NE, 431 [TCG_COND_LT] = S390_CC_LT, 432 [TCG_COND_LE] = S390_CC_LE, 433 [TCG_COND_GT] = S390_CC_GT, 434 [TCG_COND_GE] = S390_CC_GE, 435 [TCG_COND_LTU] = S390_CC_NEVER, 436 [TCG_COND_LEU] = S390_CC_EQ, 437 [TCG_COND_GTU] = S390_CC_NE, 438 [TCG_COND_GEU] = S390_CC_ALWAYS, 439}; 440 441static const tcg_insn_unit *tb_ret_addr; 442uint64_t s390_facilities[3]; 443 444static inline bool is_general_reg(TCGReg r) 445{ 446 return r <= TCG_REG_R15; 447} 448 449static inline bool is_vector_reg(TCGReg r) 450{ 451 return r >= TCG_REG_V0 && r <= TCG_REG_V31; 452} 453 454static bool patch_reloc(tcg_insn_unit *src_rw, int type, 455 intptr_t value, intptr_t addend) 456{ 457 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 458 intptr_t pcrel2; 459 uint32_t old; 460 461 value += addend; 462 pcrel2 = (tcg_insn_unit *)value - src_rx; 463 464 switch (type) { 465 case R_390_PC16DBL: 466 if (pcrel2 == (int16_t)pcrel2) { 467 tcg_patch16(src_rw, pcrel2); 468 return true; 469 } 470 break; 471 case R_390_PC32DBL: 472 if (pcrel2 == (int32_t)pcrel2) { 473 tcg_patch32(src_rw, pcrel2); 474 return true; 475 } 476 break; 477 case R_390_20: 478 if (value == sextract64(value, 0, 20)) { 479 old = *(uint32_t *)src_rw & 0xf00000ff; 480 old |= ((value & 0xfff) << 16) | ((value & 0xff000) >> 4); 481 tcg_patch32(src_rw, old); 482 return true; 483 } 484 break; 485 default: 486 g_assert_not_reached(); 487 } 488 return false; 489} 490 491static int is_const_p16(uint64_t val) 492{ 493 for (int i = 0; i < 4; ++i) { 494 uint64_t mask = 0xffffull << (i * 16); 495 if ((val & ~mask) == 0) { 496 return i; 497 } 498 } 499 return -1; 500} 501 502static int is_const_p32(uint64_t val) 503{ 504 if ((val & 0xffffffff00000000ull) == 0) { 505 return 0; 506 } 507 if ((val & 0x00000000ffffffffull) == 0) { 508 return 1; 509 } 510 return -1; 511} 512 513/* 514 * Accept bit patterns like these: 515 * 0....01....1 516 * 1....10....0 517 * 1..10..01..1 518 * 0..01..10..0 519 * Copied from gcc sources. 520 */ 521static bool risbg_mask(uint64_t c) 522{ 523 uint64_t lsb; 524 /* We don't change the number of transitions by inverting, 525 so make sure we start with the LSB zero. */ 526 if (c & 1) { 527 c = ~c; 528 } 529 /* Reject all zeros or all ones. */ 530 if (c == 0) { 531 return false; 532 } 533 /* Find the first transition. */ 534 lsb = c & -c; 535 /* Invert to look for a second transition. */ 536 c = ~c; 537 /* Erase the first transition. */ 538 c &= -lsb; 539 /* Find the second transition, if any. */ 540 lsb = c & -c; 541 /* Match if all the bits are 1's, or if c is zero. */ 542 return c == -lsb; 543} 544 545/* Test if a constant matches the constraint. */ 546static bool tcg_target_const_match(int64_t val, TCGType type, int ct) 547{ 548 if (ct & TCG_CT_CONST) { 549 return 1; 550 } 551 552 if (type == TCG_TYPE_I32) { 553 val = (int32_t)val; 554 } 555 556 /* The following are mutually exclusive. */ 557 if (ct & TCG_CT_CONST_S16) { 558 return val == (int16_t)val; 559 } else if (ct & TCG_CT_CONST_S32) { 560 return val == (int32_t)val; 561 } else if (ct & TCG_CT_CONST_S33) { 562 return val >= -0xffffffffll && val <= 0xffffffffll; 563 } else if (ct & TCG_CT_CONST_ZERO) { 564 return val == 0; 565 } 566 567 if (ct & TCG_CT_CONST_INV) { 568 val = ~val; 569 } 570 /* 571 * Note that is_const_p16 is a subset of is_const_p32, 572 * so we don't need both constraints. 573 */ 574 if ((ct & TCG_CT_CONST_P32) && is_const_p32(val) >= 0) { 575 return true; 576 } 577 if ((ct & TCG_CT_CONST_INVRISBG) && risbg_mask(~val)) { 578 return true; 579 } 580 581 return 0; 582} 583 584/* Emit instructions according to the given instruction format. */ 585 586static void tcg_out_insn_RR(TCGContext *s, S390Opcode op, TCGReg r1, TCGReg r2) 587{ 588 tcg_out16(s, (op << 8) | (r1 << 4) | r2); 589} 590 591static void tcg_out_insn_RRE(TCGContext *s, S390Opcode op, 592 TCGReg r1, TCGReg r2) 593{ 594 tcg_out32(s, (op << 16) | (r1 << 4) | r2); 595} 596 597/* RRF-a without the m4 field */ 598static void tcg_out_insn_RRFa(TCGContext *s, S390Opcode op, 599 TCGReg r1, TCGReg r2, TCGReg r3) 600{ 601 tcg_out32(s, (op << 16) | (r3 << 12) | (r1 << 4) | r2); 602} 603 604/* RRF-a with the m4 field */ 605static void tcg_out_insn_RRFam(TCGContext *s, S390Opcode op, 606 TCGReg r1, TCGReg r2, TCGReg r3, int m4) 607{ 608 tcg_out32(s, (op << 16) | (r3 << 12) | (m4 << 8) | (r1 << 4) | r2); 609} 610 611static void tcg_out_insn_RRFc(TCGContext *s, S390Opcode op, 612 TCGReg r1, TCGReg r2, int m3) 613{ 614 tcg_out32(s, (op << 16) | (m3 << 12) | (r1 << 4) | r2); 615} 616 617static void tcg_out_insn_RI(TCGContext *s, S390Opcode op, TCGReg r1, int i2) 618{ 619 tcg_out32(s, (op << 16) | (r1 << 20) | (i2 & 0xffff)); 620} 621 622static void tcg_out_insn_RIEg(TCGContext *s, S390Opcode op, TCGReg r1, 623 int i2, int m3) 624{ 625 tcg_out16(s, (op & 0xff00) | (r1 << 4) | m3); 626 tcg_out32(s, (i2 << 16) | (op & 0xff)); 627} 628 629static void tcg_out_insn_RIL(TCGContext *s, S390Opcode op, TCGReg r1, int i2) 630{ 631 tcg_out16(s, op | (r1 << 4)); 632 tcg_out32(s, i2); 633} 634 635static void tcg_out_insn_RS(TCGContext *s, S390Opcode op, TCGReg r1, 636 TCGReg b2, TCGReg r3, int disp) 637{ 638 tcg_out32(s, (op << 24) | (r1 << 20) | (r3 << 16) | (b2 << 12) 639 | (disp & 0xfff)); 640} 641 642static void tcg_out_insn_RSY(TCGContext *s, S390Opcode op, TCGReg r1, 643 TCGReg b2, TCGReg r3, int disp) 644{ 645 tcg_out16(s, (op & 0xff00) | (r1 << 4) | r3); 646 tcg_out32(s, (op & 0xff) | (b2 << 28) 647 | ((disp & 0xfff) << 16) | ((disp & 0xff000) >> 4)); 648} 649 650#define tcg_out_insn_RX tcg_out_insn_RS 651#define tcg_out_insn_RXY tcg_out_insn_RSY 652 653static int RXB(TCGReg v1, TCGReg v2, TCGReg v3, TCGReg v4) 654{ 655 /* 656 * Shift bit 4 of each regno to its corresponding bit of RXB. 657 * RXB itself begins at bit 8 of the instruction so 8 - 4 = 4 658 * is the left-shift of the 4th operand. 659 */ 660 return ((v1 & 0x10) << (4 + 3)) 661 | ((v2 & 0x10) << (4 + 2)) 662 | ((v3 & 0x10) << (4 + 1)) 663 | ((v4 & 0x10) << (4 + 0)); 664} 665 666static void tcg_out_insn_VRIa(TCGContext *s, S390Opcode op, 667 TCGReg v1, uint16_t i2, int m3) 668{ 669 tcg_debug_assert(is_vector_reg(v1)); 670 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4)); 671 tcg_out16(s, i2); 672 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m3 << 12)); 673} 674 675static void tcg_out_insn_VRIb(TCGContext *s, S390Opcode op, 676 TCGReg v1, uint8_t i2, uint8_t i3, int m4) 677{ 678 tcg_debug_assert(is_vector_reg(v1)); 679 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4)); 680 tcg_out16(s, (i2 << 8) | (i3 & 0xff)); 681 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m4 << 12)); 682} 683 684static void tcg_out_insn_VRIc(TCGContext *s, S390Opcode op, 685 TCGReg v1, uint16_t i2, TCGReg v3, int m4) 686{ 687 tcg_debug_assert(is_vector_reg(v1)); 688 tcg_debug_assert(is_vector_reg(v3)); 689 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v3 & 0xf)); 690 tcg_out16(s, i2); 691 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, v3, 0) | (m4 << 12)); 692} 693 694static void tcg_out_insn_VRRa(TCGContext *s, S390Opcode op, 695 TCGReg v1, TCGReg v2, int m3) 696{ 697 tcg_debug_assert(is_vector_reg(v1)); 698 tcg_debug_assert(is_vector_reg(v2)); 699 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v2 & 0xf)); 700 tcg_out32(s, (op & 0x00ff) | RXB(v1, v2, 0, 0) | (m3 << 12)); 701} 702 703static void tcg_out_insn_VRRc(TCGContext *s, S390Opcode op, 704 TCGReg v1, TCGReg v2, TCGReg v3, int m4) 705{ 706 tcg_debug_assert(is_vector_reg(v1)); 707 tcg_debug_assert(is_vector_reg(v2)); 708 tcg_debug_assert(is_vector_reg(v3)); 709 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v2 & 0xf)); 710 tcg_out16(s, v3 << 12); 711 tcg_out16(s, (op & 0x00ff) | RXB(v1, v2, v3, 0) | (m4 << 12)); 712} 713 714static void tcg_out_insn_VRRe(TCGContext *s, S390Opcode op, 715 TCGReg v1, TCGReg v2, TCGReg v3, TCGReg v4) 716{ 717 tcg_debug_assert(is_vector_reg(v1)); 718 tcg_debug_assert(is_vector_reg(v2)); 719 tcg_debug_assert(is_vector_reg(v3)); 720 tcg_debug_assert(is_vector_reg(v4)); 721 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v2 & 0xf)); 722 tcg_out16(s, v3 << 12); 723 tcg_out16(s, (op & 0x00ff) | RXB(v1, v2, v3, v4) | (v4 << 12)); 724} 725 726static void tcg_out_insn_VRRf(TCGContext *s, S390Opcode op, 727 TCGReg v1, TCGReg r2, TCGReg r3) 728{ 729 tcg_debug_assert(is_vector_reg(v1)); 730 tcg_debug_assert(is_general_reg(r2)); 731 tcg_debug_assert(is_general_reg(r3)); 732 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | r2); 733 tcg_out16(s, r3 << 12); 734 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0)); 735} 736 737static void tcg_out_insn_VRSa(TCGContext *s, S390Opcode op, TCGReg v1, 738 intptr_t d2, TCGReg b2, TCGReg v3, int m4) 739{ 740 tcg_debug_assert(is_vector_reg(v1)); 741 tcg_debug_assert(d2 >= 0 && d2 <= 0xfff); 742 tcg_debug_assert(is_general_reg(b2)); 743 tcg_debug_assert(is_vector_reg(v3)); 744 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v3 & 0xf)); 745 tcg_out16(s, b2 << 12 | d2); 746 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, v3, 0) | (m4 << 12)); 747} 748 749static void tcg_out_insn_VRSb(TCGContext *s, S390Opcode op, TCGReg v1, 750 intptr_t d2, TCGReg b2, TCGReg r3, int m4) 751{ 752 tcg_debug_assert(is_vector_reg(v1)); 753 tcg_debug_assert(d2 >= 0 && d2 <= 0xfff); 754 tcg_debug_assert(is_general_reg(b2)); 755 tcg_debug_assert(is_general_reg(r3)); 756 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | r3); 757 tcg_out16(s, b2 << 12 | d2); 758 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m4 << 12)); 759} 760 761static void tcg_out_insn_VRSc(TCGContext *s, S390Opcode op, TCGReg r1, 762 intptr_t d2, TCGReg b2, TCGReg v3, int m4) 763{ 764 tcg_debug_assert(is_general_reg(r1)); 765 tcg_debug_assert(d2 >= 0 && d2 <= 0xfff); 766 tcg_debug_assert(is_general_reg(b2)); 767 tcg_debug_assert(is_vector_reg(v3)); 768 tcg_out16(s, (op & 0xff00) | (r1 << 4) | (v3 & 0xf)); 769 tcg_out16(s, b2 << 12 | d2); 770 tcg_out16(s, (op & 0x00ff) | RXB(0, 0, v3, 0) | (m4 << 12)); 771} 772 773static void tcg_out_insn_VRX(TCGContext *s, S390Opcode op, TCGReg v1, 774 TCGReg b2, TCGReg x2, intptr_t d2, int m3) 775{ 776 tcg_debug_assert(is_vector_reg(v1)); 777 tcg_debug_assert(d2 >= 0 && d2 <= 0xfff); 778 tcg_debug_assert(is_general_reg(x2)); 779 tcg_debug_assert(is_general_reg(b2)); 780 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | x2); 781 tcg_out16(s, (b2 << 12) | d2); 782 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m3 << 12)); 783} 784 785/* Emit an opcode with "type-checking" of the format. */ 786#define tcg_out_insn(S, FMT, OP, ...) \ 787 glue(tcg_out_insn_,FMT)(S, glue(glue(FMT,_),OP), ## __VA_ARGS__) 788 789 790/* emit 64-bit shifts */ 791static void tcg_out_sh64(TCGContext* s, S390Opcode op, TCGReg dest, 792 TCGReg src, TCGReg sh_reg, int sh_imm) 793{ 794 tcg_out_insn_RSY(s, op, dest, sh_reg, src, sh_imm); 795} 796 797/* emit 32-bit shifts */ 798static void tcg_out_sh32(TCGContext* s, S390Opcode op, TCGReg dest, 799 TCGReg sh_reg, int sh_imm) 800{ 801 tcg_out_insn_RS(s, op, dest, sh_reg, 0, sh_imm); 802} 803 804static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg dst, TCGReg src) 805{ 806 if (src == dst) { 807 return true; 808 } 809 switch (type) { 810 case TCG_TYPE_I32: 811 if (likely(is_general_reg(dst) && is_general_reg(src))) { 812 tcg_out_insn(s, RR, LR, dst, src); 813 break; 814 } 815 /* fallthru */ 816 817 case TCG_TYPE_I64: 818 if (likely(is_general_reg(dst))) { 819 if (likely(is_general_reg(src))) { 820 tcg_out_insn(s, RRE, LGR, dst, src); 821 } else { 822 tcg_out_insn(s, VRSc, VLGV, dst, 0, 0, src, 3); 823 } 824 break; 825 } else if (is_general_reg(src)) { 826 tcg_out_insn(s, VRSb, VLVG, dst, 0, 0, src, 3); 827 break; 828 } 829 /* fallthru */ 830 831 case TCG_TYPE_V64: 832 case TCG_TYPE_V128: 833 tcg_out_insn(s, VRRa, VLR, dst, src, 0); 834 break; 835 836 default: 837 g_assert_not_reached(); 838 } 839 return true; 840} 841 842static const S390Opcode li_insns[4] = { 843 RI_LLILL, RI_LLILH, RI_LLIHL, RI_LLIHH 844}; 845static const S390Opcode oi_insns[4] = { 846 RI_OILL, RI_OILH, RI_OIHL, RI_OIHH 847}; 848static const S390Opcode lif_insns[2] = { 849 RIL_LLILF, RIL_LLIHF, 850}; 851 852/* load a register with an immediate value */ 853static void tcg_out_movi(TCGContext *s, TCGType type, 854 TCGReg ret, tcg_target_long sval) 855{ 856 tcg_target_ulong uval = sval; 857 ptrdiff_t pc_off; 858 int i; 859 860 if (type == TCG_TYPE_I32) { 861 uval = (uint32_t)sval; 862 sval = (int32_t)sval; 863 } 864 865 /* Try all 32-bit insns that can load it in one go. */ 866 if (sval >= -0x8000 && sval < 0x8000) { 867 tcg_out_insn(s, RI, LGHI, ret, sval); 868 return; 869 } 870 871 i = is_const_p16(uval); 872 if (i >= 0) { 873 tcg_out_insn_RI(s, li_insns[i], ret, uval >> (i * 16)); 874 return; 875 } 876 877 /* Try all 48-bit insns that can load it in one go. */ 878 if (sval == (int32_t)sval) { 879 tcg_out_insn(s, RIL, LGFI, ret, sval); 880 return; 881 } 882 883 i = is_const_p32(uval); 884 if (i >= 0) { 885 tcg_out_insn_RIL(s, lif_insns[i], ret, uval >> (i * 32)); 886 return; 887 } 888 889 /* Try for PC-relative address load. For odd addresses, add one. */ 890 pc_off = tcg_pcrel_diff(s, (void *)sval) >> 1; 891 if (pc_off == (int32_t)pc_off) { 892 tcg_out_insn(s, RIL, LARL, ret, pc_off); 893 if (sval & 1) { 894 tcg_out_insn(s, RI, AGHI, ret, 1); 895 } 896 return; 897 } 898 899 /* Otherwise, load it by parts. */ 900 i = is_const_p16((uint32_t)uval); 901 if (i >= 0) { 902 tcg_out_insn_RI(s, li_insns[i], ret, uval >> (i * 16)); 903 } else { 904 tcg_out_insn(s, RIL, LLILF, ret, uval); 905 } 906 uval >>= 32; 907 i = is_const_p16(uval); 908 if (i >= 0) { 909 tcg_out_insn_RI(s, oi_insns[i + 2], ret, uval >> (i * 16)); 910 } else { 911 tcg_out_insn(s, RIL, OIHF, ret, uval); 912 } 913} 914 915/* Emit a load/store type instruction. Inputs are: 916 DATA: The register to be loaded or stored. 917 BASE+OFS: The effective address. 918 OPC_RX: If the operation has an RX format opcode (e.g. STC), otherwise 0. 919 OPC_RXY: The RXY format opcode for the operation (e.g. STCY). */ 920 921static void tcg_out_mem(TCGContext *s, S390Opcode opc_rx, S390Opcode opc_rxy, 922 TCGReg data, TCGReg base, TCGReg index, 923 tcg_target_long ofs) 924{ 925 if (ofs < -0x80000 || ofs >= 0x80000) { 926 /* Combine the low 20 bits of the offset with the actual load insn; 927 the high 44 bits must come from an immediate load. */ 928 tcg_target_long low = ((ofs & 0xfffff) ^ 0x80000) - 0x80000; 929 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - low); 930 ofs = low; 931 932 /* If we were already given an index register, add it in. */ 933 if (index != TCG_REG_NONE) { 934 tcg_out_insn(s, RRE, AGR, TCG_TMP0, index); 935 } 936 index = TCG_TMP0; 937 } 938 939 if (opc_rx && ofs >= 0 && ofs < 0x1000) { 940 tcg_out_insn_RX(s, opc_rx, data, base, index, ofs); 941 } else { 942 tcg_out_insn_RXY(s, opc_rxy, data, base, index, ofs); 943 } 944} 945 946static void tcg_out_vrx_mem(TCGContext *s, S390Opcode opc_vrx, 947 TCGReg data, TCGReg base, TCGReg index, 948 tcg_target_long ofs, int m3) 949{ 950 if (ofs < 0 || ofs >= 0x1000) { 951 if (ofs >= -0x80000 && ofs < 0x80000) { 952 tcg_out_insn(s, RXY, LAY, TCG_TMP0, base, index, ofs); 953 base = TCG_TMP0; 954 index = TCG_REG_NONE; 955 ofs = 0; 956 } else { 957 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs); 958 if (index != TCG_REG_NONE) { 959 tcg_out_insn(s, RRE, AGR, TCG_TMP0, index); 960 } 961 index = TCG_TMP0; 962 ofs = 0; 963 } 964 } 965 tcg_out_insn_VRX(s, opc_vrx, data, base, index, ofs, m3); 966} 967 968/* load data without address translation or endianness conversion */ 969static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg data, 970 TCGReg base, intptr_t ofs) 971{ 972 switch (type) { 973 case TCG_TYPE_I32: 974 if (likely(is_general_reg(data))) { 975 tcg_out_mem(s, RX_L, RXY_LY, data, base, TCG_REG_NONE, ofs); 976 break; 977 } 978 tcg_out_vrx_mem(s, VRX_VLLEZ, data, base, TCG_REG_NONE, ofs, MO_32); 979 break; 980 981 case TCG_TYPE_I64: 982 if (likely(is_general_reg(data))) { 983 tcg_out_mem(s, 0, RXY_LG, data, base, TCG_REG_NONE, ofs); 984 break; 985 } 986 /* fallthru */ 987 988 case TCG_TYPE_V64: 989 tcg_out_vrx_mem(s, VRX_VLLEZ, data, base, TCG_REG_NONE, ofs, MO_64); 990 break; 991 992 case TCG_TYPE_V128: 993 /* Hint quadword aligned. */ 994 tcg_out_vrx_mem(s, VRX_VL, data, base, TCG_REG_NONE, ofs, 4); 995 break; 996 997 default: 998 g_assert_not_reached(); 999 } 1000} 1001 1002static void tcg_out_st(TCGContext *s, TCGType type, TCGReg data, 1003 TCGReg base, intptr_t ofs) 1004{ 1005 switch (type) { 1006 case TCG_TYPE_I32: 1007 if (likely(is_general_reg(data))) { 1008 tcg_out_mem(s, RX_ST, RXY_STY, data, base, TCG_REG_NONE, ofs); 1009 } else { 1010 tcg_out_vrx_mem(s, VRX_VSTEF, data, base, TCG_REG_NONE, ofs, 1); 1011 } 1012 break; 1013 1014 case TCG_TYPE_I64: 1015 if (likely(is_general_reg(data))) { 1016 tcg_out_mem(s, 0, RXY_STG, data, base, TCG_REG_NONE, ofs); 1017 break; 1018 } 1019 /* fallthru */ 1020 1021 case TCG_TYPE_V64: 1022 tcg_out_vrx_mem(s, VRX_VSTEG, data, base, TCG_REG_NONE, ofs, 0); 1023 break; 1024 1025 case TCG_TYPE_V128: 1026 /* Hint quadword aligned. */ 1027 tcg_out_vrx_mem(s, VRX_VST, data, base, TCG_REG_NONE, ofs, 4); 1028 break; 1029 1030 default: 1031 g_assert_not_reached(); 1032 } 1033} 1034 1035static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 1036 TCGReg base, intptr_t ofs) 1037{ 1038 return false; 1039} 1040 1041static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 1042{ 1043 return false; 1044} 1045 1046static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 1047 tcg_target_long imm) 1048{ 1049 /* This function is only used for passing structs by reference. */ 1050 tcg_out_mem(s, RX_LA, RXY_LAY, rd, rs, TCG_REG_NONE, imm); 1051} 1052 1053static inline void tcg_out_risbg(TCGContext *s, TCGReg dest, TCGReg src, 1054 int msb, int lsb, int ofs, int z) 1055{ 1056 /* Format RIE-f */ 1057 tcg_out16(s, (RIEf_RISBG & 0xff00) | (dest << 4) | src); 1058 tcg_out16(s, (msb << 8) | (z << 7) | lsb); 1059 tcg_out16(s, (ofs << 8) | (RIEf_RISBG & 0xff)); 1060} 1061 1062static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) 1063{ 1064 tcg_out_insn(s, RRE, LGBR, dest, src); 1065} 1066 1067static void tcg_out_ext8u(TCGContext *s, TCGReg dest, TCGReg src) 1068{ 1069 tcg_out_insn(s, RRE, LLGCR, dest, src); 1070} 1071 1072static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) 1073{ 1074 tcg_out_insn(s, RRE, LGHR, dest, src); 1075} 1076 1077static void tcg_out_ext16u(TCGContext *s, TCGReg dest, TCGReg src) 1078{ 1079 tcg_out_insn(s, RRE, LLGHR, dest, src); 1080} 1081 1082static void tcg_out_ext32s(TCGContext *s, TCGReg dest, TCGReg src) 1083{ 1084 tcg_out_insn(s, RRE, LGFR, dest, src); 1085} 1086 1087static void tcg_out_ext32u(TCGContext *s, TCGReg dest, TCGReg src) 1088{ 1089 tcg_out_insn(s, RRE, LLGFR, dest, src); 1090} 1091 1092static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg dest, TCGReg src) 1093{ 1094 tcg_out_ext32s(s, dest, src); 1095} 1096 1097static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg dest, TCGReg src) 1098{ 1099 tcg_out_ext32u(s, dest, src); 1100} 1101 1102static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg dest, TCGReg src) 1103{ 1104 tcg_out_mov(s, TCG_TYPE_I32, dest, src); 1105} 1106 1107static void tgen_andi_risbg(TCGContext *s, TCGReg out, TCGReg in, uint64_t val) 1108{ 1109 int msb, lsb; 1110 if ((val & 0x8000000000000001ull) == 0x8000000000000001ull) { 1111 /* Achieve wraparound by swapping msb and lsb. */ 1112 msb = 64 - ctz64(~val); 1113 lsb = clz64(~val) - 1; 1114 } else { 1115 msb = clz64(val); 1116 lsb = 63 - ctz64(val); 1117 } 1118 tcg_out_risbg(s, out, in, msb, lsb, 0, 1); 1119} 1120 1121static void tgen_andi(TCGContext *s, TCGType type, TCGReg dest, uint64_t val) 1122{ 1123 static const S390Opcode ni_insns[4] = { 1124 RI_NILL, RI_NILH, RI_NIHL, RI_NIHH 1125 }; 1126 static const S390Opcode nif_insns[2] = { 1127 RIL_NILF, RIL_NIHF 1128 }; 1129 uint64_t valid = (type == TCG_TYPE_I32 ? 0xffffffffull : -1ull); 1130 int i; 1131 1132 /* Look for the zero-extensions. */ 1133 if ((val & valid) == 0xffffffff) { 1134 tcg_out_ext32u(s, dest, dest); 1135 return; 1136 } 1137 if ((val & valid) == 0xff) { 1138 tcg_out_ext8u(s, dest, dest); 1139 return; 1140 } 1141 if ((val & valid) == 0xffff) { 1142 tcg_out_ext16u(s, dest, dest); 1143 return; 1144 } 1145 1146 i = is_const_p16(~val & valid); 1147 if (i >= 0) { 1148 tcg_out_insn_RI(s, ni_insns[i], dest, val >> (i * 16)); 1149 return; 1150 } 1151 1152 i = is_const_p32(~val & valid); 1153 tcg_debug_assert(i == 0 || type != TCG_TYPE_I32); 1154 if (i >= 0) { 1155 tcg_out_insn_RIL(s, nif_insns[i], dest, val >> (i * 32)); 1156 return; 1157 } 1158 1159 if (risbg_mask(val)) { 1160 tgen_andi_risbg(s, dest, dest, val); 1161 return; 1162 } 1163 1164 g_assert_not_reached(); 1165} 1166 1167static void tgen_ori(TCGContext *s, TCGReg dest, uint64_t val) 1168{ 1169 static const S390Opcode oif_insns[2] = { 1170 RIL_OILF, RIL_OIHF 1171 }; 1172 1173 int i; 1174 1175 i = is_const_p16(val); 1176 if (i >= 0) { 1177 tcg_out_insn_RI(s, oi_insns[i], dest, val >> (i * 16)); 1178 return; 1179 } 1180 1181 i = is_const_p32(val); 1182 if (i >= 0) { 1183 tcg_out_insn_RIL(s, oif_insns[i], dest, val >> (i * 32)); 1184 return; 1185 } 1186 1187 g_assert_not_reached(); 1188} 1189 1190static void tgen_xori(TCGContext *s, TCGReg dest, uint64_t val) 1191{ 1192 switch (is_const_p32(val)) { 1193 case 0: 1194 tcg_out_insn(s, RIL, XILF, dest, val); 1195 break; 1196 case 1: 1197 tcg_out_insn(s, RIL, XIHF, dest, val >> 32); 1198 break; 1199 default: 1200 g_assert_not_reached(); 1201 } 1202} 1203 1204static int tgen_cmp2(TCGContext *s, TCGType type, TCGCond c, TCGReg r1, 1205 TCGArg c2, bool c2const, bool need_carry, int *inv_cc) 1206{ 1207 bool is_unsigned = is_unsigned_cond(c); 1208 TCGCond inv_c = tcg_invert_cond(c); 1209 S390Opcode op; 1210 1211 if (c2const) { 1212 if (c2 == 0) { 1213 if (!(is_unsigned && need_carry)) { 1214 if (type == TCG_TYPE_I32) { 1215 tcg_out_insn(s, RR, LTR, r1, r1); 1216 } else { 1217 tcg_out_insn(s, RRE, LTGR, r1, r1); 1218 } 1219 *inv_cc = tcg_cond_to_ltr_cond[inv_c]; 1220 return tcg_cond_to_ltr_cond[c]; 1221 } 1222 } 1223 1224 if (!is_unsigned && c2 == (int16_t)c2) { 1225 op = (type == TCG_TYPE_I32 ? RI_CHI : RI_CGHI); 1226 tcg_out_insn_RI(s, op, r1, c2); 1227 goto exit; 1228 } 1229 1230 if (type == TCG_TYPE_I32) { 1231 op = (is_unsigned ? RIL_CLFI : RIL_CFI); 1232 tcg_out_insn_RIL(s, op, r1, c2); 1233 goto exit; 1234 } 1235 1236 /* 1237 * Constraints are for a signed 33-bit operand, which is a 1238 * convenient superset of this signed/unsigned test. 1239 */ 1240 if (c2 == (is_unsigned ? (TCGArg)(uint32_t)c2 : (TCGArg)(int32_t)c2)) { 1241 op = (is_unsigned ? RIL_CLGFI : RIL_CGFI); 1242 tcg_out_insn_RIL(s, op, r1, c2); 1243 goto exit; 1244 } 1245 1246 /* Load everything else into a register. */ 1247 tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, c2); 1248 c2 = TCG_TMP0; 1249 } 1250 1251 if (type == TCG_TYPE_I32) { 1252 op = (is_unsigned ? RR_CLR : RR_CR); 1253 tcg_out_insn_RR(s, op, r1, c2); 1254 } else { 1255 op = (is_unsigned ? RRE_CLGR : RRE_CGR); 1256 tcg_out_insn_RRE(s, op, r1, c2); 1257 } 1258 1259 exit: 1260 *inv_cc = tcg_cond_to_s390_cond[inv_c]; 1261 return tcg_cond_to_s390_cond[c]; 1262} 1263 1264static int tgen_cmp(TCGContext *s, TCGType type, TCGCond c, TCGReg r1, 1265 TCGArg c2, bool c2const, bool need_carry) 1266{ 1267 int inv_cc; 1268 return tgen_cmp2(s, type, c, r1, c2, c2const, need_carry, &inv_cc); 1269} 1270 1271static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, 1272 TCGReg dest, TCGReg c1, TCGArg c2, int c2const) 1273{ 1274 int cc; 1275 1276 /* With LOC2, we can always emit the minimum 3 insns. */ 1277 if (HAVE_FACILITY(LOAD_ON_COND2)) { 1278 /* Emit: d = 0, d = (cc ? 1 : d). */ 1279 cc = tgen_cmp(s, type, cond, c1, c2, c2const, false); 1280 tcg_out_movi(s, TCG_TYPE_I64, dest, 0); 1281 tcg_out_insn(s, RIEg, LOCGHI, dest, 1, cc); 1282 return; 1283 } 1284 1285 restart: 1286 switch (cond) { 1287 case TCG_COND_NE: 1288 /* X != 0 is X > 0. */ 1289 if (c2const && c2 == 0) { 1290 cond = TCG_COND_GTU; 1291 } else { 1292 break; 1293 } 1294 /* fallthru */ 1295 1296 case TCG_COND_GTU: 1297 case TCG_COND_GT: 1298 /* The result of a compare has CC=2 for GT and CC=3 unused. 1299 ADD LOGICAL WITH CARRY considers (CC & 2) the carry bit. */ 1300 tgen_cmp(s, type, cond, c1, c2, c2const, true); 1301 tcg_out_movi(s, type, dest, 0); 1302 tcg_out_insn(s, RRE, ALCGR, dest, dest); 1303 return; 1304 1305 case TCG_COND_EQ: 1306 /* X == 0 is X <= 0. */ 1307 if (c2const && c2 == 0) { 1308 cond = TCG_COND_LEU; 1309 } else { 1310 break; 1311 } 1312 /* fallthru */ 1313 1314 case TCG_COND_LEU: 1315 case TCG_COND_LE: 1316 /* As above, but we're looking for borrow, or !carry. 1317 The second insn computes d - d - borrow, or -1 for true 1318 and 0 for false. So we must mask to 1 bit afterward. */ 1319 tgen_cmp(s, type, cond, c1, c2, c2const, true); 1320 tcg_out_insn(s, RRE, SLBGR, dest, dest); 1321 tgen_andi(s, type, dest, 1); 1322 return; 1323 1324 case TCG_COND_GEU: 1325 case TCG_COND_LTU: 1326 case TCG_COND_LT: 1327 case TCG_COND_GE: 1328 /* Swap operands so that we can use LEU/GTU/GT/LE. */ 1329 if (!c2const) { 1330 TCGReg t = c1; 1331 c1 = c2; 1332 c2 = t; 1333 cond = tcg_swap_cond(cond); 1334 goto restart; 1335 } 1336 break; 1337 1338 default: 1339 g_assert_not_reached(); 1340 } 1341 1342 cc = tgen_cmp(s, type, cond, c1, c2, c2const, false); 1343 /* Emit: d = 0, t = 1, d = (cc ? t : d). */ 1344 tcg_out_movi(s, TCG_TYPE_I64, dest, 0); 1345 tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 1); 1346 tcg_out_insn(s, RRFc, LOCGR, dest, TCG_TMP0, cc); 1347} 1348 1349static void tgen_movcond_int(TCGContext *s, TCGType type, TCGReg dest, 1350 TCGArg v3, int v3const, TCGReg v4, 1351 int cc, int inv_cc) 1352{ 1353 TCGReg src; 1354 1355 if (v3const) { 1356 if (dest == v4) { 1357 if (HAVE_FACILITY(LOAD_ON_COND2)) { 1358 /* Emit: if (cc) dest = v3. */ 1359 tcg_out_insn(s, RIEg, LOCGHI, dest, v3, cc); 1360 return; 1361 } 1362 tcg_out_insn(s, RI, LGHI, TCG_TMP0, v3); 1363 src = TCG_TMP0; 1364 } else { 1365 /* LGR+LOCGHI is larger than LGHI+LOCGR. */ 1366 tcg_out_insn(s, RI, LGHI, dest, v3); 1367 cc = inv_cc; 1368 src = v4; 1369 } 1370 } else { 1371 if (HAVE_FACILITY(MISC_INSN_EXT3)) { 1372 /* Emit: dest = cc ? v3 : v4. */ 1373 tcg_out_insn(s, RRFam, SELGR, dest, v3, v4, cc); 1374 return; 1375 } 1376 if (dest == v4) { 1377 src = v3; 1378 } else { 1379 tcg_out_mov(s, type, dest, v3); 1380 cc = inv_cc; 1381 src = v4; 1382 } 1383 } 1384 1385 /* Emit: if (cc) dest = src. */ 1386 tcg_out_insn(s, RRFc, LOCGR, dest, src, cc); 1387} 1388 1389static void tgen_movcond(TCGContext *s, TCGType type, TCGCond c, TCGReg dest, 1390 TCGReg c1, TCGArg c2, int c2const, 1391 TCGArg v3, int v3const, TCGReg v4) 1392{ 1393 int cc, inv_cc; 1394 1395 cc = tgen_cmp2(s, type, c, c1, c2, c2const, false, &inv_cc); 1396 tgen_movcond_int(s, type, dest, v3, v3const, v4, cc, inv_cc); 1397} 1398 1399static void tgen_clz(TCGContext *s, TCGReg dest, TCGReg a1, 1400 TCGArg a2, int a2const) 1401{ 1402 /* Since this sets both R and R+1, we have no choice but to store the 1403 result into R0, allowing R1 == TCG_TMP0 to be clobbered as well. */ 1404 QEMU_BUILD_BUG_ON(TCG_TMP0 != TCG_REG_R1); 1405 tcg_out_insn(s, RRE, FLOGR, TCG_REG_R0, a1); 1406 1407 if (a2const && a2 == 64) { 1408 tcg_out_mov(s, TCG_TYPE_I64, dest, TCG_REG_R0); 1409 return; 1410 } 1411 1412 /* 1413 * Conditions from FLOGR are: 1414 * 2 -> one bit found 1415 * 8 -> no one bit found 1416 */ 1417 tgen_movcond_int(s, TCG_TYPE_I64, dest, a2, a2const, TCG_REG_R0, 8, 2); 1418} 1419 1420static void tgen_ctpop(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) 1421{ 1422 /* With MIE3, and bit 0 of m4 set, we get the complete result. */ 1423 if (HAVE_FACILITY(MISC_INSN_EXT3)) { 1424 if (type == TCG_TYPE_I32) { 1425 tcg_out_ext32u(s, dest, src); 1426 src = dest; 1427 } 1428 tcg_out_insn(s, RRFc, POPCNT, dest, src, 8); 1429 return; 1430 } 1431 1432 /* Without MIE3, each byte gets the count of bits for the byte. */ 1433 tcg_out_insn(s, RRFc, POPCNT, dest, src, 0); 1434 1435 /* Multiply to sum each byte at the top of the word. */ 1436 if (type == TCG_TYPE_I32) { 1437 tcg_out_insn(s, RIL, MSFI, dest, 0x01010101); 1438 tcg_out_sh32(s, RS_SRL, dest, TCG_REG_NONE, 24); 1439 } else { 1440 tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 0x0101010101010101ull); 1441 tcg_out_insn(s, RRE, MSGR, dest, TCG_TMP0); 1442 tcg_out_sh64(s, RSY_SRLG, dest, dest, TCG_REG_NONE, 56); 1443 } 1444} 1445 1446static void tgen_deposit(TCGContext *s, TCGReg dest, TCGReg src, 1447 int ofs, int len, int z) 1448{ 1449 int lsb = (63 - ofs); 1450 int msb = lsb - (len - 1); 1451 tcg_out_risbg(s, dest, src, msb, lsb, ofs, z); 1452} 1453 1454static void tgen_extract(TCGContext *s, TCGReg dest, TCGReg src, 1455 int ofs, int len) 1456{ 1457 tcg_out_risbg(s, dest, src, 64 - len, 63, 64 - ofs, 1); 1458} 1459 1460static void tgen_gotoi(TCGContext *s, int cc, const tcg_insn_unit *dest) 1461{ 1462 ptrdiff_t off = tcg_pcrel_diff(s, dest) >> 1; 1463 if (off == (int16_t)off) { 1464 tcg_out_insn(s, RI, BRC, cc, off); 1465 } else if (off == (int32_t)off) { 1466 tcg_out_insn(s, RIL, BRCL, cc, off); 1467 } else { 1468 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)dest); 1469 tcg_out_insn(s, RR, BCR, cc, TCG_TMP0); 1470 } 1471} 1472 1473static void tgen_branch(TCGContext *s, int cc, TCGLabel *l) 1474{ 1475 if (l->has_value) { 1476 tgen_gotoi(s, cc, l->u.value_ptr); 1477 } else { 1478 tcg_out16(s, RI_BRC | (cc << 4)); 1479 tcg_out_reloc(s, s->code_ptr, R_390_PC16DBL, l, 2); 1480 s->code_ptr += 1; 1481 } 1482} 1483 1484static void tgen_compare_branch(TCGContext *s, S390Opcode opc, int cc, 1485 TCGReg r1, TCGReg r2, TCGLabel *l) 1486{ 1487 tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2); 1488 /* Format RIE-b */ 1489 tcg_out16(s, (opc & 0xff00) | (r1 << 4) | r2); 1490 tcg_out16(s, 0); 1491 tcg_out16(s, cc << 12 | (opc & 0xff)); 1492} 1493 1494static void tgen_compare_imm_branch(TCGContext *s, S390Opcode opc, int cc, 1495 TCGReg r1, int i2, TCGLabel *l) 1496{ 1497 tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2); 1498 /* Format RIE-c */ 1499 tcg_out16(s, (opc & 0xff00) | (r1 << 4) | cc); 1500 tcg_out16(s, 0); 1501 tcg_out16(s, (i2 << 8) | (opc & 0xff)); 1502} 1503 1504static void tgen_brcond(TCGContext *s, TCGType type, TCGCond c, 1505 TCGReg r1, TCGArg c2, int c2const, TCGLabel *l) 1506{ 1507 int cc; 1508 bool is_unsigned = is_unsigned_cond(c); 1509 bool in_range; 1510 S390Opcode opc; 1511 1512 cc = tcg_cond_to_s390_cond[c]; 1513 1514 if (!c2const) { 1515 opc = (type == TCG_TYPE_I32 1516 ? (is_unsigned ? RIEb_CLRJ : RIEb_CRJ) 1517 : (is_unsigned ? RIEb_CLGRJ : RIEb_CGRJ)); 1518 tgen_compare_branch(s, opc, cc, r1, c2, l); 1519 return; 1520 } 1521 1522 /* 1523 * COMPARE IMMEDIATE AND BRANCH RELATIVE has an 8-bit immediate field. 1524 * If the immediate we've been given does not fit that range, we'll 1525 * fall back to separate compare and branch instructions using the 1526 * larger comparison range afforded by COMPARE IMMEDIATE. 1527 */ 1528 if (type == TCG_TYPE_I32) { 1529 if (is_unsigned) { 1530 opc = RIEc_CLIJ; 1531 in_range = (uint32_t)c2 == (uint8_t)c2; 1532 } else { 1533 opc = RIEc_CIJ; 1534 in_range = (int32_t)c2 == (int8_t)c2; 1535 } 1536 } else { 1537 if (is_unsigned) { 1538 opc = RIEc_CLGIJ; 1539 in_range = (uint64_t)c2 == (uint8_t)c2; 1540 } else { 1541 opc = RIEc_CGIJ; 1542 in_range = (int64_t)c2 == (int8_t)c2; 1543 } 1544 } 1545 if (in_range) { 1546 tgen_compare_imm_branch(s, opc, cc, r1, c2, l); 1547 return; 1548 } 1549 1550 cc = tgen_cmp(s, type, c, r1, c2, c2const, false); 1551 tgen_branch(s, cc, l); 1552} 1553 1554static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *dest) 1555{ 1556 ptrdiff_t off = tcg_pcrel_diff(s, dest) >> 1; 1557 if (off == (int32_t)off) { 1558 tcg_out_insn(s, RIL, BRASL, TCG_REG_R14, off); 1559 } else { 1560 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)dest); 1561 tcg_out_insn(s, RR, BASR, TCG_REG_R14, TCG_TMP0); 1562 } 1563} 1564 1565static void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest, 1566 const TCGHelperInfo *info) 1567{ 1568 tcg_out_call_int(s, dest); 1569} 1570 1571typedef struct { 1572 TCGReg base; 1573 TCGReg index; 1574 int disp; 1575 TCGAtomAlign aa; 1576} HostAddress; 1577 1578bool tcg_target_has_memory_bswap(MemOp memop) 1579{ 1580 return true; 1581} 1582 1583static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg data, 1584 HostAddress h) 1585{ 1586 switch (opc & (MO_SSIZE | MO_BSWAP)) { 1587 case MO_UB: 1588 tcg_out_insn(s, RXY, LLGC, data, h.base, h.index, h.disp); 1589 break; 1590 case MO_SB: 1591 tcg_out_insn(s, RXY, LGB, data, h.base, h.index, h.disp); 1592 break; 1593 1594 case MO_UW | MO_BSWAP: 1595 /* swapped unsigned halfword load with upper bits zeroed */ 1596 tcg_out_insn(s, RXY, LRVH, data, h.base, h.index, h.disp); 1597 tcg_out_ext16u(s, data, data); 1598 break; 1599 case MO_UW: 1600 tcg_out_insn(s, RXY, LLGH, data, h.base, h.index, h.disp); 1601 break; 1602 1603 case MO_SW | MO_BSWAP: 1604 /* swapped sign-extended halfword load */ 1605 tcg_out_insn(s, RXY, LRVH, data, h.base, h.index, h.disp); 1606 tcg_out_ext16s(s, TCG_TYPE_REG, data, data); 1607 break; 1608 case MO_SW: 1609 tcg_out_insn(s, RXY, LGH, data, h.base, h.index, h.disp); 1610 break; 1611 1612 case MO_UL | MO_BSWAP: 1613 /* swapped unsigned int load with upper bits zeroed */ 1614 tcg_out_insn(s, RXY, LRV, data, h.base, h.index, h.disp); 1615 tcg_out_ext32u(s, data, data); 1616 break; 1617 case MO_UL: 1618 tcg_out_insn(s, RXY, LLGF, data, h.base, h.index, h.disp); 1619 break; 1620 1621 case MO_SL | MO_BSWAP: 1622 /* swapped sign-extended int load */ 1623 tcg_out_insn(s, RXY, LRV, data, h.base, h.index, h.disp); 1624 tcg_out_ext32s(s, data, data); 1625 break; 1626 case MO_SL: 1627 tcg_out_insn(s, RXY, LGF, data, h.base, h.index, h.disp); 1628 break; 1629 1630 case MO_UQ | MO_BSWAP: 1631 tcg_out_insn(s, RXY, LRVG, data, h.base, h.index, h.disp); 1632 break; 1633 case MO_UQ: 1634 tcg_out_insn(s, RXY, LG, data, h.base, h.index, h.disp); 1635 break; 1636 1637 default: 1638 g_assert_not_reached(); 1639 } 1640} 1641 1642static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg data, 1643 HostAddress h) 1644{ 1645 switch (opc & (MO_SIZE | MO_BSWAP)) { 1646 case MO_UB: 1647 if (h.disp >= 0 && h.disp < 0x1000) { 1648 tcg_out_insn(s, RX, STC, data, h.base, h.index, h.disp); 1649 } else { 1650 tcg_out_insn(s, RXY, STCY, data, h.base, h.index, h.disp); 1651 } 1652 break; 1653 1654 case MO_UW | MO_BSWAP: 1655 tcg_out_insn(s, RXY, STRVH, data, h.base, h.index, h.disp); 1656 break; 1657 case MO_UW: 1658 if (h.disp >= 0 && h.disp < 0x1000) { 1659 tcg_out_insn(s, RX, STH, data, h.base, h.index, h.disp); 1660 } else { 1661 tcg_out_insn(s, RXY, STHY, data, h.base, h.index, h.disp); 1662 } 1663 break; 1664 1665 case MO_UL | MO_BSWAP: 1666 tcg_out_insn(s, RXY, STRV, data, h.base, h.index, h.disp); 1667 break; 1668 case MO_UL: 1669 if (h.disp >= 0 && h.disp < 0x1000) { 1670 tcg_out_insn(s, RX, ST, data, h.base, h.index, h.disp); 1671 } else { 1672 tcg_out_insn(s, RXY, STY, data, h.base, h.index, h.disp); 1673 } 1674 break; 1675 1676 case MO_UQ | MO_BSWAP: 1677 tcg_out_insn(s, RXY, STRVG, data, h.base, h.index, h.disp); 1678 break; 1679 case MO_UQ: 1680 tcg_out_insn(s, RXY, STG, data, h.base, h.index, h.disp); 1681 break; 1682 1683 default: 1684 g_assert_not_reached(); 1685 } 1686} 1687 1688static const TCGLdstHelperParam ldst_helper_param = { 1689 .ntmp = 1, .tmp = { TCG_TMP0 } 1690}; 1691 1692static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1693{ 1694 MemOp opc = get_memop(lb->oi); 1695 1696 if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL, 1697 (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 2)) { 1698 return false; 1699 } 1700 1701 tcg_out_ld_helper_args(s, lb, &ldst_helper_param); 1702 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE]); 1703 tcg_out_ld_helper_ret(s, lb, false, &ldst_helper_param); 1704 1705 tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr); 1706 return true; 1707} 1708 1709static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1710{ 1711 MemOp opc = get_memop(lb->oi); 1712 1713 if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL, 1714 (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 2)) { 1715 return false; 1716 } 1717 1718 tcg_out_st_helper_args(s, lb, &ldst_helper_param); 1719 tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE]); 1720 1721 tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr); 1722 return true; 1723} 1724 1725/* 1726 * For softmmu, perform the TLB load and compare. 1727 * For useronly, perform any required alignment tests. 1728 * In both cases, return a TCGLabelQemuLdst structure if the slow path 1729 * is required and fill in @h with the host address for the fast path. 1730 */ 1731static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 1732 TCGReg addr_reg, MemOpIdx oi, 1733 bool is_ld) 1734{ 1735 TCGLabelQemuLdst *ldst = NULL; 1736 MemOp opc = get_memop(oi); 1737 unsigned a_mask; 1738 1739 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); 1740 a_mask = (1 << h->aa.align) - 1; 1741 1742#ifdef CONFIG_SOFTMMU 1743 unsigned s_bits = opc & MO_SIZE; 1744 unsigned s_mask = (1 << s_bits) - 1; 1745 int mem_index = get_mmuidx(oi); 1746 int fast_off = TLB_MASK_TABLE_OFS(mem_index); 1747 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); 1748 int table_off = fast_off + offsetof(CPUTLBDescFast, table); 1749 int ofs, a_off; 1750 uint64_t tlb_mask; 1751 1752 ldst = new_ldst_label(s); 1753 ldst->is_ld = is_ld; 1754 ldst->oi = oi; 1755 ldst->addrlo_reg = addr_reg; 1756 1757 tcg_out_sh64(s, RSY_SRLG, TCG_TMP0, addr_reg, TCG_REG_NONE, 1758 s->page_bits - CPU_TLB_ENTRY_BITS); 1759 1760 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); 1761 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 19)); 1762 tcg_out_insn(s, RXY, NG, TCG_TMP0, TCG_AREG0, TCG_REG_NONE, mask_off); 1763 tcg_out_insn(s, RXY, AG, TCG_TMP0, TCG_AREG0, TCG_REG_NONE, table_off); 1764 1765 /* 1766 * For aligned accesses, we check the first byte and include the alignment 1767 * bits within the address. For unaligned access, we check that we don't 1768 * cross pages using the address of the last byte of the access. 1769 */ 1770 a_off = (a_mask >= s_mask ? 0 : s_mask - a_mask); 1771 tlb_mask = (uint64_t)s->page_mask | a_mask; 1772 if (a_off == 0) { 1773 tgen_andi_risbg(s, TCG_REG_R0, addr_reg, tlb_mask); 1774 } else { 1775 tcg_out_insn(s, RX, LA, TCG_REG_R0, addr_reg, TCG_REG_NONE, a_off); 1776 tgen_andi(s, TCG_TYPE_TL, TCG_REG_R0, tlb_mask); 1777 } 1778 1779 if (is_ld) { 1780 ofs = offsetof(CPUTLBEntry, addr_read); 1781 } else { 1782 ofs = offsetof(CPUTLBEntry, addr_write); 1783 } 1784 if (TARGET_LONG_BITS == 32) { 1785 tcg_out_insn(s, RX, C, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs); 1786 } else { 1787 tcg_out_insn(s, RXY, CG, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs); 1788 } 1789 1790 tcg_out16(s, RI_BRC | (S390_CC_NE << 4)); 1791 ldst->label_ptr[0] = s->code_ptr++; 1792 1793 h->index = TCG_TMP0; 1794 tcg_out_insn(s, RXY, LG, h->index, TCG_TMP0, TCG_REG_NONE, 1795 offsetof(CPUTLBEntry, addend)); 1796 1797 if (TARGET_LONG_BITS == 32) { 1798 tcg_out_insn(s, RRE, ALGFR, h->index, addr_reg); 1799 h->base = TCG_REG_NONE; 1800 } else { 1801 h->base = addr_reg; 1802 } 1803 h->disp = 0; 1804#else 1805 if (a_mask) { 1806 ldst = new_ldst_label(s); 1807 ldst->is_ld = is_ld; 1808 ldst->oi = oi; 1809 ldst->addrlo_reg = addr_reg; 1810 1811 /* We are expecting a_bits to max out at 7, much lower than TMLL. */ 1812 tcg_debug_assert(a_mask <= 0xffff); 1813 tcg_out_insn(s, RI, TMLL, addr_reg, a_mask); 1814 1815 tcg_out16(s, RI_BRC | (7 << 4)); /* CC in {1,2,3} */ 1816 ldst->label_ptr[0] = s->code_ptr++; 1817 } 1818 1819 h->base = addr_reg; 1820 if (TARGET_LONG_BITS == 32) { 1821 tcg_out_ext32u(s, TCG_TMP0, addr_reg); 1822 h->base = TCG_TMP0; 1823 } 1824 if (guest_base < 0x80000) { 1825 h->index = TCG_REG_NONE; 1826 h->disp = guest_base; 1827 } else { 1828 h->index = TCG_GUEST_BASE_REG; 1829 h->disp = 0; 1830 } 1831#endif 1832 1833 return ldst; 1834} 1835 1836static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_reg, 1837 MemOpIdx oi, TCGType data_type) 1838{ 1839 TCGLabelQemuLdst *ldst; 1840 HostAddress h; 1841 1842 ldst = prepare_host_addr(s, &h, addr_reg, oi, true); 1843 tcg_out_qemu_ld_direct(s, get_memop(oi), data_reg, h); 1844 1845 if (ldst) { 1846 ldst->type = data_type; 1847 ldst->datalo_reg = data_reg; 1848 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1849 } 1850} 1851 1852static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_reg, 1853 MemOpIdx oi, TCGType data_type) 1854{ 1855 TCGLabelQemuLdst *ldst; 1856 HostAddress h; 1857 1858 ldst = prepare_host_addr(s, &h, addr_reg, oi, false); 1859 tcg_out_qemu_st_direct(s, get_memop(oi), data_reg, h); 1860 1861 if (ldst) { 1862 ldst->type = data_type; 1863 ldst->datalo_reg = data_reg; 1864 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1865 } 1866} 1867 1868static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) 1869{ 1870 /* Reuse the zeroing that exists for goto_ptr. */ 1871 if (a0 == 0) { 1872 tgen_gotoi(s, S390_CC_ALWAYS, tcg_code_gen_epilogue); 1873 } else { 1874 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, a0); 1875 tgen_gotoi(s, S390_CC_ALWAYS, tb_ret_addr); 1876 } 1877} 1878 1879static void tcg_out_goto_tb(TCGContext *s, int which) 1880{ 1881 /* 1882 * Branch displacement must be aligned for atomic patching; 1883 * see if we need to add extra nop before branch 1884 */ 1885 if (!QEMU_PTR_IS_ALIGNED(s->code_ptr + 1, 4)) { 1886 tcg_out16(s, NOP); 1887 } 1888 tcg_out16(s, RIL_BRCL | (S390_CC_ALWAYS << 4)); 1889 set_jmp_insn_offset(s, which); 1890 s->code_ptr += 2; 1891 set_jmp_reset_offset(s, which); 1892} 1893 1894void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1895 uintptr_t jmp_rx, uintptr_t jmp_rw) 1896{ 1897 if (!HAVE_FACILITY(GEN_INST_EXT)) { 1898 return; 1899 } 1900 /* patch the branch destination */ 1901 uintptr_t addr = tb->jmp_target_addr[n]; 1902 intptr_t disp = addr - (jmp_rx - 2); 1903 qatomic_set((int32_t *)jmp_rw, disp / 2); 1904 /* no need to flush icache explicitly */ 1905} 1906 1907# define OP_32_64(x) \ 1908 case glue(glue(INDEX_op_,x),_i32): \ 1909 case glue(glue(INDEX_op_,x),_i64) 1910 1911static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, 1912 const TCGArg args[TCG_MAX_OP_ARGS], 1913 const int const_args[TCG_MAX_OP_ARGS]) 1914{ 1915 S390Opcode op, op2; 1916 TCGArg a0, a1, a2; 1917 1918 switch (opc) { 1919 case INDEX_op_goto_ptr: 1920 a0 = args[0]; 1921 tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, a0); 1922 break; 1923 1924 OP_32_64(ld8u): 1925 /* ??? LLC (RXY format) is only present with the extended-immediate 1926 facility, whereas LLGC is always present. */ 1927 tcg_out_mem(s, 0, RXY_LLGC, args[0], args[1], TCG_REG_NONE, args[2]); 1928 break; 1929 1930 OP_32_64(ld8s): 1931 /* ??? LB is no smaller than LGB, so no point to using it. */ 1932 tcg_out_mem(s, 0, RXY_LGB, args[0], args[1], TCG_REG_NONE, args[2]); 1933 break; 1934 1935 OP_32_64(ld16u): 1936 /* ??? LLH (RXY format) is only present with the extended-immediate 1937 facility, whereas LLGH is always present. */ 1938 tcg_out_mem(s, 0, RXY_LLGH, args[0], args[1], TCG_REG_NONE, args[2]); 1939 break; 1940 1941 case INDEX_op_ld16s_i32: 1942 tcg_out_mem(s, RX_LH, RXY_LHY, args[0], args[1], TCG_REG_NONE, args[2]); 1943 break; 1944 1945 case INDEX_op_ld_i32: 1946 tcg_out_ld(s, TCG_TYPE_I32, args[0], args[1], args[2]); 1947 break; 1948 1949 OP_32_64(st8): 1950 tcg_out_mem(s, RX_STC, RXY_STCY, args[0], args[1], 1951 TCG_REG_NONE, args[2]); 1952 break; 1953 1954 OP_32_64(st16): 1955 tcg_out_mem(s, RX_STH, RXY_STHY, args[0], args[1], 1956 TCG_REG_NONE, args[2]); 1957 break; 1958 1959 case INDEX_op_st_i32: 1960 tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]); 1961 break; 1962 1963 case INDEX_op_add_i32: 1964 a0 = args[0], a1 = args[1], a2 = (int32_t)args[2]; 1965 if (const_args[2]) { 1966 do_addi_32: 1967 if (a0 == a1) { 1968 if (a2 == (int16_t)a2) { 1969 tcg_out_insn(s, RI, AHI, a0, a2); 1970 break; 1971 } 1972 tcg_out_insn(s, RIL, AFI, a0, a2); 1973 break; 1974 } 1975 tcg_out_mem(s, RX_LA, RXY_LAY, a0, a1, TCG_REG_NONE, a2); 1976 } else if (a0 == a1) { 1977 tcg_out_insn(s, RR, AR, a0, a2); 1978 } else { 1979 tcg_out_insn(s, RX, LA, a0, a1, a2, 0); 1980 } 1981 break; 1982 case INDEX_op_sub_i32: 1983 a0 = args[0], a1 = args[1], a2 = (int32_t)args[2]; 1984 if (const_args[2]) { 1985 a2 = -a2; 1986 goto do_addi_32; 1987 } else if (a0 == a1) { 1988 tcg_out_insn(s, RR, SR, a0, a2); 1989 } else { 1990 tcg_out_insn(s, RRFa, SRK, a0, a1, a2); 1991 } 1992 break; 1993 1994 case INDEX_op_and_i32: 1995 a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; 1996 if (const_args[2]) { 1997 tcg_out_mov(s, TCG_TYPE_I32, a0, a1); 1998 tgen_andi(s, TCG_TYPE_I32, a0, a2); 1999 } else if (a0 == a1) { 2000 tcg_out_insn(s, RR, NR, a0, a2); 2001 } else { 2002 tcg_out_insn(s, RRFa, NRK, a0, a1, a2); 2003 } 2004 break; 2005 case INDEX_op_or_i32: 2006 a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; 2007 if (const_args[2]) { 2008 tcg_out_mov(s, TCG_TYPE_I32, a0, a1); 2009 tgen_ori(s, a0, a2); 2010 } else if (a0 == a1) { 2011 tcg_out_insn(s, RR, OR, a0, a2); 2012 } else { 2013 tcg_out_insn(s, RRFa, ORK, a0, a1, a2); 2014 } 2015 break; 2016 case INDEX_op_xor_i32: 2017 a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; 2018 if (const_args[2]) { 2019 tcg_out_mov(s, TCG_TYPE_I32, a0, a1); 2020 tcg_out_insn(s, RIL, XILF, a0, a2); 2021 } else if (a0 == a1) { 2022 tcg_out_insn(s, RR, XR, args[0], args[2]); 2023 } else { 2024 tcg_out_insn(s, RRFa, XRK, a0, a1, a2); 2025 } 2026 break; 2027 2028 case INDEX_op_andc_i32: 2029 a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; 2030 if (const_args[2]) { 2031 tcg_out_mov(s, TCG_TYPE_I32, a0, a1); 2032 tgen_andi(s, TCG_TYPE_I32, a0, (uint32_t)~a2); 2033 } else { 2034 tcg_out_insn(s, RRFa, NCRK, a0, a1, a2); 2035 } 2036 break; 2037 case INDEX_op_orc_i32: 2038 a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; 2039 if (const_args[2]) { 2040 tcg_out_mov(s, TCG_TYPE_I32, a0, a1); 2041 tgen_ori(s, a0, (uint32_t)~a2); 2042 } else { 2043 tcg_out_insn(s, RRFa, OCRK, a0, a1, a2); 2044 } 2045 break; 2046 case INDEX_op_eqv_i32: 2047 a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; 2048 if (const_args[2]) { 2049 tcg_out_mov(s, TCG_TYPE_I32, a0, a1); 2050 tcg_out_insn(s, RIL, XILF, a0, ~a2); 2051 } else { 2052 tcg_out_insn(s, RRFa, NXRK, a0, a1, a2); 2053 } 2054 break; 2055 case INDEX_op_nand_i32: 2056 tcg_out_insn(s, RRFa, NNRK, args[0], args[1], args[2]); 2057 break; 2058 case INDEX_op_nor_i32: 2059 tcg_out_insn(s, RRFa, NORK, args[0], args[1], args[2]); 2060 break; 2061 2062 case INDEX_op_neg_i32: 2063 tcg_out_insn(s, RR, LCR, args[0], args[1]); 2064 break; 2065 case INDEX_op_not_i32: 2066 tcg_out_insn(s, RRFa, NORK, args[0], args[1], args[1]); 2067 break; 2068 2069 case INDEX_op_mul_i32: 2070 a0 = args[0], a1 = args[1], a2 = (int32_t)args[2]; 2071 if (const_args[2]) { 2072 tcg_out_mov(s, TCG_TYPE_I32, a0, a1); 2073 if (a2 == (int16_t)a2) { 2074 tcg_out_insn(s, RI, MHI, a0, a2); 2075 } else { 2076 tcg_out_insn(s, RIL, MSFI, a0, a2); 2077 } 2078 } else if (a0 == a1) { 2079 tcg_out_insn(s, RRE, MSR, a0, a2); 2080 } else { 2081 tcg_out_insn(s, RRFa, MSRKC, a0, a1, a2); 2082 } 2083 break; 2084 2085 case INDEX_op_div2_i32: 2086 tcg_debug_assert(args[0] == args[2]); 2087 tcg_debug_assert(args[1] == args[3]); 2088 tcg_debug_assert((args[1] & 1) == 0); 2089 tcg_debug_assert(args[0] == args[1] + 1); 2090 tcg_out_insn(s, RR, DR, args[1], args[4]); 2091 break; 2092 case INDEX_op_divu2_i32: 2093 tcg_debug_assert(args[0] == args[2]); 2094 tcg_debug_assert(args[1] == args[3]); 2095 tcg_debug_assert((args[1] & 1) == 0); 2096 tcg_debug_assert(args[0] == args[1] + 1); 2097 tcg_out_insn(s, RRE, DLR, args[1], args[4]); 2098 break; 2099 2100 case INDEX_op_shl_i32: 2101 op = RS_SLL; 2102 op2 = RSY_SLLK; 2103 do_shift32: 2104 a0 = args[0], a1 = args[1], a2 = (int32_t)args[2]; 2105 if (a0 == a1) { 2106 if (const_args[2]) { 2107 tcg_out_sh32(s, op, a0, TCG_REG_NONE, a2); 2108 } else { 2109 tcg_out_sh32(s, op, a0, a2, 0); 2110 } 2111 } else { 2112 /* Using tcg_out_sh64 here for the format; it is a 32-bit shift. */ 2113 if (const_args[2]) { 2114 tcg_out_sh64(s, op2, a0, a1, TCG_REG_NONE, a2); 2115 } else { 2116 tcg_out_sh64(s, op2, a0, a1, a2, 0); 2117 } 2118 } 2119 break; 2120 case INDEX_op_shr_i32: 2121 op = RS_SRL; 2122 op2 = RSY_SRLK; 2123 goto do_shift32; 2124 case INDEX_op_sar_i32: 2125 op = RS_SRA; 2126 op2 = RSY_SRAK; 2127 goto do_shift32; 2128 2129 case INDEX_op_rotl_i32: 2130 /* ??? Using tcg_out_sh64 here for the format; it is a 32-bit rol. */ 2131 if (const_args[2]) { 2132 tcg_out_sh64(s, RSY_RLL, args[0], args[1], TCG_REG_NONE, args[2]); 2133 } else { 2134 tcg_out_sh64(s, RSY_RLL, args[0], args[1], args[2], 0); 2135 } 2136 break; 2137 case INDEX_op_rotr_i32: 2138 if (const_args[2]) { 2139 tcg_out_sh64(s, RSY_RLL, args[0], args[1], 2140 TCG_REG_NONE, (32 - args[2]) & 31); 2141 } else { 2142 tcg_out_insn(s, RR, LCR, TCG_TMP0, args[2]); 2143 tcg_out_sh64(s, RSY_RLL, args[0], args[1], TCG_TMP0, 0); 2144 } 2145 break; 2146 2147 case INDEX_op_bswap16_i32: 2148 a0 = args[0], a1 = args[1], a2 = args[2]; 2149 tcg_out_insn(s, RRE, LRVR, a0, a1); 2150 if (a2 & TCG_BSWAP_OS) { 2151 tcg_out_sh32(s, RS_SRA, a0, TCG_REG_NONE, 16); 2152 } else { 2153 tcg_out_sh32(s, RS_SRL, a0, TCG_REG_NONE, 16); 2154 } 2155 break; 2156 case INDEX_op_bswap16_i64: 2157 a0 = args[0], a1 = args[1], a2 = args[2]; 2158 tcg_out_insn(s, RRE, LRVGR, a0, a1); 2159 if (a2 & TCG_BSWAP_OS) { 2160 tcg_out_sh64(s, RSY_SRAG, a0, a0, TCG_REG_NONE, 48); 2161 } else { 2162 tcg_out_sh64(s, RSY_SRLG, a0, a0, TCG_REG_NONE, 48); 2163 } 2164 break; 2165 2166 case INDEX_op_bswap32_i32: 2167 tcg_out_insn(s, RRE, LRVR, args[0], args[1]); 2168 break; 2169 case INDEX_op_bswap32_i64: 2170 a0 = args[0], a1 = args[1], a2 = args[2]; 2171 tcg_out_insn(s, RRE, LRVR, a0, a1); 2172 if (a2 & TCG_BSWAP_OS) { 2173 tcg_out_ext32s(s, a0, a0); 2174 } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 2175 tcg_out_ext32u(s, a0, a0); 2176 } 2177 break; 2178 2179 case INDEX_op_add2_i32: 2180 if (const_args[4]) { 2181 tcg_out_insn(s, RIL, ALFI, args[0], args[4]); 2182 } else { 2183 tcg_out_insn(s, RR, ALR, args[0], args[4]); 2184 } 2185 tcg_out_insn(s, RRE, ALCR, args[1], args[5]); 2186 break; 2187 case INDEX_op_sub2_i32: 2188 if (const_args[4]) { 2189 tcg_out_insn(s, RIL, SLFI, args[0], args[4]); 2190 } else { 2191 tcg_out_insn(s, RR, SLR, args[0], args[4]); 2192 } 2193 tcg_out_insn(s, RRE, SLBR, args[1], args[5]); 2194 break; 2195 2196 case INDEX_op_br: 2197 tgen_branch(s, S390_CC_ALWAYS, arg_label(args[0])); 2198 break; 2199 2200 case INDEX_op_brcond_i32: 2201 tgen_brcond(s, TCG_TYPE_I32, args[2], args[0], 2202 args[1], const_args[1], arg_label(args[3])); 2203 break; 2204 case INDEX_op_setcond_i32: 2205 tgen_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], 2206 args[2], const_args[2]); 2207 break; 2208 case INDEX_op_movcond_i32: 2209 tgen_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], 2210 args[2], const_args[2], args[3], const_args[3], args[4]); 2211 break; 2212 2213 case INDEX_op_qemu_ld_a32_i32: 2214 case INDEX_op_qemu_ld_a64_i32: 2215 tcg_out_qemu_ld(s, args[0], args[1], args[2], TCG_TYPE_I32); 2216 break; 2217 case INDEX_op_qemu_ld_a32_i64: 2218 case INDEX_op_qemu_ld_a64_i64: 2219 tcg_out_qemu_ld(s, args[0], args[1], args[2], TCG_TYPE_I64); 2220 break; 2221 case INDEX_op_qemu_st_a32_i32: 2222 case INDEX_op_qemu_st_a64_i32: 2223 tcg_out_qemu_st(s, args[0], args[1], args[2], TCG_TYPE_I32); 2224 break; 2225 case INDEX_op_qemu_st_a32_i64: 2226 case INDEX_op_qemu_st_a64_i64: 2227 tcg_out_qemu_st(s, args[0], args[1], args[2], TCG_TYPE_I64); 2228 break; 2229 2230 case INDEX_op_ld16s_i64: 2231 tcg_out_mem(s, 0, RXY_LGH, args[0], args[1], TCG_REG_NONE, args[2]); 2232 break; 2233 case INDEX_op_ld32u_i64: 2234 tcg_out_mem(s, 0, RXY_LLGF, args[0], args[1], TCG_REG_NONE, args[2]); 2235 break; 2236 case INDEX_op_ld32s_i64: 2237 tcg_out_mem(s, 0, RXY_LGF, args[0], args[1], TCG_REG_NONE, args[2]); 2238 break; 2239 case INDEX_op_ld_i64: 2240 tcg_out_ld(s, TCG_TYPE_I64, args[0], args[1], args[2]); 2241 break; 2242 2243 case INDEX_op_st32_i64: 2244 tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]); 2245 break; 2246 case INDEX_op_st_i64: 2247 tcg_out_st(s, TCG_TYPE_I64, args[0], args[1], args[2]); 2248 break; 2249 2250 case INDEX_op_add_i64: 2251 a0 = args[0], a1 = args[1], a2 = args[2]; 2252 if (const_args[2]) { 2253 do_addi_64: 2254 if (a0 == a1) { 2255 if (a2 == (int16_t)a2) { 2256 tcg_out_insn(s, RI, AGHI, a0, a2); 2257 break; 2258 } 2259 if (a2 == (int32_t)a2) { 2260 tcg_out_insn(s, RIL, AGFI, a0, a2); 2261 break; 2262 } 2263 if (a2 == (uint32_t)a2) { 2264 tcg_out_insn(s, RIL, ALGFI, a0, a2); 2265 break; 2266 } 2267 if (-a2 == (uint32_t)-a2) { 2268 tcg_out_insn(s, RIL, SLGFI, a0, -a2); 2269 break; 2270 } 2271 } 2272 tcg_out_mem(s, RX_LA, RXY_LAY, a0, a1, TCG_REG_NONE, a2); 2273 } else if (a0 == a1) { 2274 tcg_out_insn(s, RRE, AGR, a0, a2); 2275 } else { 2276 tcg_out_insn(s, RX, LA, a0, a1, a2, 0); 2277 } 2278 break; 2279 case INDEX_op_sub_i64: 2280 a0 = args[0], a1 = args[1], a2 = args[2]; 2281 if (const_args[2]) { 2282 a2 = -a2; 2283 goto do_addi_64; 2284 } else { 2285 tcg_out_insn(s, RRFa, SGRK, a0, a1, a2); 2286 } 2287 break; 2288 2289 case INDEX_op_and_i64: 2290 a0 = args[0], a1 = args[1], a2 = args[2]; 2291 if (const_args[2]) { 2292 tcg_out_mov(s, TCG_TYPE_I64, a0, a1); 2293 tgen_andi(s, TCG_TYPE_I64, args[0], args[2]); 2294 } else { 2295 tcg_out_insn(s, RRFa, NGRK, a0, a1, a2); 2296 } 2297 break; 2298 case INDEX_op_or_i64: 2299 a0 = args[0], a1 = args[1], a2 = args[2]; 2300 if (const_args[2]) { 2301 tcg_out_mov(s, TCG_TYPE_I64, a0, a1); 2302 tgen_ori(s, a0, a2); 2303 } else { 2304 tcg_out_insn(s, RRFa, OGRK, a0, a1, a2); 2305 } 2306 break; 2307 case INDEX_op_xor_i64: 2308 a0 = args[0], a1 = args[1], a2 = args[2]; 2309 if (const_args[2]) { 2310 tcg_out_mov(s, TCG_TYPE_I64, a0, a1); 2311 tgen_xori(s, a0, a2); 2312 } else { 2313 tcg_out_insn(s, RRFa, XGRK, a0, a1, a2); 2314 } 2315 break; 2316 2317 case INDEX_op_andc_i64: 2318 a0 = args[0], a1 = args[1], a2 = args[2]; 2319 if (const_args[2]) { 2320 tcg_out_mov(s, TCG_TYPE_I64, a0, a1); 2321 tgen_andi(s, TCG_TYPE_I64, a0, ~a2); 2322 } else { 2323 tcg_out_insn(s, RRFa, NCGRK, a0, a1, a2); 2324 } 2325 break; 2326 case INDEX_op_orc_i64: 2327 a0 = args[0], a1 = args[1], a2 = args[2]; 2328 if (const_args[2]) { 2329 tcg_out_mov(s, TCG_TYPE_I64, a0, a1); 2330 tgen_ori(s, a0, ~a2); 2331 } else { 2332 tcg_out_insn(s, RRFa, OCGRK, a0, a1, a2); 2333 } 2334 break; 2335 case INDEX_op_eqv_i64: 2336 a0 = args[0], a1 = args[1], a2 = args[2]; 2337 if (const_args[2]) { 2338 tcg_out_mov(s, TCG_TYPE_I64, a0, a1); 2339 tgen_xori(s, a0, ~a2); 2340 } else { 2341 tcg_out_insn(s, RRFa, NXGRK, a0, a1, a2); 2342 } 2343 break; 2344 case INDEX_op_nand_i64: 2345 tcg_out_insn(s, RRFa, NNGRK, args[0], args[1], args[2]); 2346 break; 2347 case INDEX_op_nor_i64: 2348 tcg_out_insn(s, RRFa, NOGRK, args[0], args[1], args[2]); 2349 break; 2350 2351 case INDEX_op_neg_i64: 2352 tcg_out_insn(s, RRE, LCGR, args[0], args[1]); 2353 break; 2354 case INDEX_op_not_i64: 2355 tcg_out_insn(s, RRFa, NOGRK, args[0], args[1], args[1]); 2356 break; 2357 case INDEX_op_bswap64_i64: 2358 tcg_out_insn(s, RRE, LRVGR, args[0], args[1]); 2359 break; 2360 2361 case INDEX_op_mul_i64: 2362 a0 = args[0], a1 = args[1], a2 = args[2]; 2363 if (const_args[2]) { 2364 tcg_out_mov(s, TCG_TYPE_I64, a0, a1); 2365 if (a2 == (int16_t)a2) { 2366 tcg_out_insn(s, RI, MGHI, a0, a2); 2367 } else { 2368 tcg_out_insn(s, RIL, MSGFI, a0, a2); 2369 } 2370 } else if (a0 == a1) { 2371 tcg_out_insn(s, RRE, MSGR, a0, a2); 2372 } else { 2373 tcg_out_insn(s, RRFa, MSGRKC, a0, a1, a2); 2374 } 2375 break; 2376 2377 case INDEX_op_div2_i64: 2378 /* 2379 * ??? We get an unnecessary sign-extension of the dividend 2380 * into op0 with this definition, but as we do in fact always 2381 * produce both quotient and remainder using INDEX_op_div_i64 2382 * instead requires jumping through even more hoops. 2383 */ 2384 tcg_debug_assert(args[0] == args[2]); 2385 tcg_debug_assert(args[1] == args[3]); 2386 tcg_debug_assert((args[1] & 1) == 0); 2387 tcg_debug_assert(args[0] == args[1] + 1); 2388 tcg_out_insn(s, RRE, DSGR, args[1], args[4]); 2389 break; 2390 case INDEX_op_divu2_i64: 2391 tcg_debug_assert(args[0] == args[2]); 2392 tcg_debug_assert(args[1] == args[3]); 2393 tcg_debug_assert((args[1] & 1) == 0); 2394 tcg_debug_assert(args[0] == args[1] + 1); 2395 tcg_out_insn(s, RRE, DLGR, args[1], args[4]); 2396 break; 2397 case INDEX_op_mulu2_i64: 2398 tcg_debug_assert(args[0] == args[2]); 2399 tcg_debug_assert((args[1] & 1) == 0); 2400 tcg_debug_assert(args[0] == args[1] + 1); 2401 tcg_out_insn(s, RRE, MLGR, args[1], args[3]); 2402 break; 2403 case INDEX_op_muls2_i64: 2404 tcg_debug_assert((args[1] & 1) == 0); 2405 tcg_debug_assert(args[0] == args[1] + 1); 2406 tcg_out_insn(s, RRFa, MGRK, args[1], args[2], args[3]); 2407 break; 2408 2409 case INDEX_op_shl_i64: 2410 op = RSY_SLLG; 2411 do_shift64: 2412 if (const_args[2]) { 2413 tcg_out_sh64(s, op, args[0], args[1], TCG_REG_NONE, args[2]); 2414 } else { 2415 tcg_out_sh64(s, op, args[0], args[1], args[2], 0); 2416 } 2417 break; 2418 case INDEX_op_shr_i64: 2419 op = RSY_SRLG; 2420 goto do_shift64; 2421 case INDEX_op_sar_i64: 2422 op = RSY_SRAG; 2423 goto do_shift64; 2424 2425 case INDEX_op_rotl_i64: 2426 if (const_args[2]) { 2427 tcg_out_sh64(s, RSY_RLLG, args[0], args[1], 2428 TCG_REG_NONE, args[2]); 2429 } else { 2430 tcg_out_sh64(s, RSY_RLLG, args[0], args[1], args[2], 0); 2431 } 2432 break; 2433 case INDEX_op_rotr_i64: 2434 if (const_args[2]) { 2435 tcg_out_sh64(s, RSY_RLLG, args[0], args[1], 2436 TCG_REG_NONE, (64 - args[2]) & 63); 2437 } else { 2438 /* We can use the smaller 32-bit negate because only the 2439 low 6 bits are examined for the rotate. */ 2440 tcg_out_insn(s, RR, LCR, TCG_TMP0, args[2]); 2441 tcg_out_sh64(s, RSY_RLLG, args[0], args[1], TCG_TMP0, 0); 2442 } 2443 break; 2444 2445 case INDEX_op_add2_i64: 2446 if (const_args[4]) { 2447 if ((int64_t)args[4] >= 0) { 2448 tcg_out_insn(s, RIL, ALGFI, args[0], args[4]); 2449 } else { 2450 tcg_out_insn(s, RIL, SLGFI, args[0], -args[4]); 2451 } 2452 } else { 2453 tcg_out_insn(s, RRE, ALGR, args[0], args[4]); 2454 } 2455 tcg_out_insn(s, RRE, ALCGR, args[1], args[5]); 2456 break; 2457 case INDEX_op_sub2_i64: 2458 if (const_args[4]) { 2459 if ((int64_t)args[4] >= 0) { 2460 tcg_out_insn(s, RIL, SLGFI, args[0], args[4]); 2461 } else { 2462 tcg_out_insn(s, RIL, ALGFI, args[0], -args[4]); 2463 } 2464 } else { 2465 tcg_out_insn(s, RRE, SLGR, args[0], args[4]); 2466 } 2467 tcg_out_insn(s, RRE, SLBGR, args[1], args[5]); 2468 break; 2469 2470 case INDEX_op_brcond_i64: 2471 tgen_brcond(s, TCG_TYPE_I64, args[2], args[0], 2472 args[1], const_args[1], arg_label(args[3])); 2473 break; 2474 case INDEX_op_setcond_i64: 2475 tgen_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], 2476 args[2], const_args[2]); 2477 break; 2478 case INDEX_op_movcond_i64: 2479 tgen_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], 2480 args[2], const_args[2], args[3], const_args[3], args[4]); 2481 break; 2482 2483 OP_32_64(deposit): 2484 a0 = args[0], a1 = args[1], a2 = args[2]; 2485 if (const_args[1]) { 2486 tgen_deposit(s, a0, a2, args[3], args[4], 1); 2487 } else { 2488 /* Since we can't support "0Z" as a constraint, we allow a1 in 2489 any register. Fix things up as if a matching constraint. */ 2490 if (a0 != a1) { 2491 TCGType type = (opc == INDEX_op_deposit_i64); 2492 if (a0 == a2) { 2493 tcg_out_mov(s, type, TCG_TMP0, a2); 2494 a2 = TCG_TMP0; 2495 } 2496 tcg_out_mov(s, type, a0, a1); 2497 } 2498 tgen_deposit(s, a0, a2, args[3], args[4], 0); 2499 } 2500 break; 2501 2502 OP_32_64(extract): 2503 tgen_extract(s, args[0], args[1], args[2], args[3]); 2504 break; 2505 2506 case INDEX_op_clz_i64: 2507 tgen_clz(s, args[0], args[1], args[2], const_args[2]); 2508 break; 2509 2510 case INDEX_op_ctpop_i32: 2511 tgen_ctpop(s, TCG_TYPE_I32, args[0], args[1]); 2512 break; 2513 case INDEX_op_ctpop_i64: 2514 tgen_ctpop(s, TCG_TYPE_I64, args[0], args[1]); 2515 break; 2516 2517 case INDEX_op_mb: 2518 /* The host memory model is quite strong, we simply need to 2519 serialize the instruction stream. */ 2520 if (args[0] & TCG_MO_ST_LD) { 2521 /* fast-bcr-serialization facility (45) is present */ 2522 tcg_out_insn(s, RR, BCR, 14, 0); 2523 } 2524 break; 2525 2526 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ 2527 case INDEX_op_mov_i64: 2528 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2529 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 2530 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 2531 case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ 2532 case INDEX_op_ext8s_i64: 2533 case INDEX_op_ext8u_i32: 2534 case INDEX_op_ext8u_i64: 2535 case INDEX_op_ext16s_i32: 2536 case INDEX_op_ext16s_i64: 2537 case INDEX_op_ext16u_i32: 2538 case INDEX_op_ext16u_i64: 2539 case INDEX_op_ext32s_i64: 2540 case INDEX_op_ext32u_i64: 2541 case INDEX_op_ext_i32_i64: 2542 case INDEX_op_extu_i32_i64: 2543 case INDEX_op_extrl_i64_i32: 2544 default: 2545 g_assert_not_reached(); 2546 } 2547} 2548 2549static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 2550 TCGReg dst, TCGReg src) 2551{ 2552 if (is_general_reg(src)) { 2553 /* Replicate general register into two MO_64. */ 2554 tcg_out_insn(s, VRRf, VLVGP, dst, src, src); 2555 if (vece == MO_64) { 2556 return true; 2557 } 2558 src = dst; 2559 } 2560 2561 /* 2562 * Recall that the "standard" integer, within a vector, is the 2563 * rightmost element of the leftmost doubleword, a-la VLLEZ. 2564 */ 2565 tcg_out_insn(s, VRIc, VREP, dst, (8 >> vece) - 1, src, vece); 2566 return true; 2567} 2568 2569static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 2570 TCGReg dst, TCGReg base, intptr_t offset) 2571{ 2572 tcg_out_vrx_mem(s, VRX_VLREP, dst, base, TCG_REG_NONE, offset, vece); 2573 return true; 2574} 2575 2576static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 2577 TCGReg dst, int64_t val) 2578{ 2579 int i, mask, msb, lsb; 2580 2581 /* Look for int16_t elements. */ 2582 if (vece <= MO_16 || 2583 (vece == MO_32 ? (int32_t)val : val) == (int16_t)val) { 2584 tcg_out_insn(s, VRIa, VREPI, dst, val, vece); 2585 return; 2586 } 2587 2588 /* Look for bit masks. */ 2589 if (vece == MO_32) { 2590 if (risbg_mask((int32_t)val)) { 2591 /* Handle wraparound by swapping msb and lsb. */ 2592 if ((val & 0x80000001u) == 0x80000001u) { 2593 msb = 32 - ctz32(~val); 2594 lsb = clz32(~val) - 1; 2595 } else { 2596 msb = clz32(val); 2597 lsb = 31 - ctz32(val); 2598 } 2599 tcg_out_insn(s, VRIb, VGM, dst, msb, lsb, MO_32); 2600 return; 2601 } 2602 } else { 2603 if (risbg_mask(val)) { 2604 /* Handle wraparound by swapping msb and lsb. */ 2605 if ((val & 0x8000000000000001ull) == 0x8000000000000001ull) { 2606 /* Handle wraparound by swapping msb and lsb. */ 2607 msb = 64 - ctz64(~val); 2608 lsb = clz64(~val) - 1; 2609 } else { 2610 msb = clz64(val); 2611 lsb = 63 - ctz64(val); 2612 } 2613 tcg_out_insn(s, VRIb, VGM, dst, msb, lsb, MO_64); 2614 return; 2615 } 2616 } 2617 2618 /* Look for all bytes 0x00 or 0xff. */ 2619 for (i = mask = 0; i < 8; i++) { 2620 uint8_t byte = val >> (i * 8); 2621 if (byte == 0xff) { 2622 mask |= 1 << i; 2623 } else if (byte != 0) { 2624 break; 2625 } 2626 } 2627 if (i == 8) { 2628 tcg_out_insn(s, VRIa, VGBM, dst, mask * 0x0101, 0); 2629 return; 2630 } 2631 2632 /* Otherwise, stuff it in the constant pool. */ 2633 tcg_out_insn(s, RIL, LARL, TCG_TMP0, 0); 2634 new_pool_label(s, val, R_390_PC32DBL, s->code_ptr - 2, 2); 2635 tcg_out_insn(s, VRX, VLREP, dst, TCG_TMP0, TCG_REG_NONE, 0, MO_64); 2636} 2637 2638static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 2639 unsigned vecl, unsigned vece, 2640 const TCGArg args[TCG_MAX_OP_ARGS], 2641 const int const_args[TCG_MAX_OP_ARGS]) 2642{ 2643 TCGType type = vecl + TCG_TYPE_V64; 2644 TCGArg a0 = args[0], a1 = args[1], a2 = args[2]; 2645 2646 switch (opc) { 2647 case INDEX_op_ld_vec: 2648 tcg_out_ld(s, type, a0, a1, a2); 2649 break; 2650 case INDEX_op_st_vec: 2651 tcg_out_st(s, type, a0, a1, a2); 2652 break; 2653 case INDEX_op_dupm_vec: 2654 tcg_out_dupm_vec(s, type, vece, a0, a1, a2); 2655 break; 2656 2657 case INDEX_op_abs_vec: 2658 tcg_out_insn(s, VRRa, VLP, a0, a1, vece); 2659 break; 2660 case INDEX_op_neg_vec: 2661 tcg_out_insn(s, VRRa, VLC, a0, a1, vece); 2662 break; 2663 case INDEX_op_not_vec: 2664 tcg_out_insn(s, VRRc, VNO, a0, a1, a1, 0); 2665 break; 2666 2667 case INDEX_op_add_vec: 2668 tcg_out_insn(s, VRRc, VA, a0, a1, a2, vece); 2669 break; 2670 case INDEX_op_sub_vec: 2671 tcg_out_insn(s, VRRc, VS, a0, a1, a2, vece); 2672 break; 2673 case INDEX_op_and_vec: 2674 tcg_out_insn(s, VRRc, VN, a0, a1, a2, 0); 2675 break; 2676 case INDEX_op_andc_vec: 2677 tcg_out_insn(s, VRRc, VNC, a0, a1, a2, 0); 2678 break; 2679 case INDEX_op_mul_vec: 2680 tcg_out_insn(s, VRRc, VML, a0, a1, a2, vece); 2681 break; 2682 case INDEX_op_or_vec: 2683 tcg_out_insn(s, VRRc, VO, a0, a1, a2, 0); 2684 break; 2685 case INDEX_op_orc_vec: 2686 tcg_out_insn(s, VRRc, VOC, a0, a1, a2, 0); 2687 break; 2688 case INDEX_op_xor_vec: 2689 tcg_out_insn(s, VRRc, VX, a0, a1, a2, 0); 2690 break; 2691 case INDEX_op_nand_vec: 2692 tcg_out_insn(s, VRRc, VNN, a0, a1, a2, 0); 2693 break; 2694 case INDEX_op_nor_vec: 2695 tcg_out_insn(s, VRRc, VNO, a0, a1, a2, 0); 2696 break; 2697 case INDEX_op_eqv_vec: 2698 tcg_out_insn(s, VRRc, VNX, a0, a1, a2, 0); 2699 break; 2700 2701 case INDEX_op_shli_vec: 2702 tcg_out_insn(s, VRSa, VESL, a0, a2, TCG_REG_NONE, a1, vece); 2703 break; 2704 case INDEX_op_shri_vec: 2705 tcg_out_insn(s, VRSa, VESRL, a0, a2, TCG_REG_NONE, a1, vece); 2706 break; 2707 case INDEX_op_sari_vec: 2708 tcg_out_insn(s, VRSa, VESRA, a0, a2, TCG_REG_NONE, a1, vece); 2709 break; 2710 case INDEX_op_rotli_vec: 2711 tcg_out_insn(s, VRSa, VERLL, a0, a2, TCG_REG_NONE, a1, vece); 2712 break; 2713 case INDEX_op_shls_vec: 2714 tcg_out_insn(s, VRSa, VESL, a0, 0, a2, a1, vece); 2715 break; 2716 case INDEX_op_shrs_vec: 2717 tcg_out_insn(s, VRSa, VESRL, a0, 0, a2, a1, vece); 2718 break; 2719 case INDEX_op_sars_vec: 2720 tcg_out_insn(s, VRSa, VESRA, a0, 0, a2, a1, vece); 2721 break; 2722 case INDEX_op_rotls_vec: 2723 tcg_out_insn(s, VRSa, VERLL, a0, 0, a2, a1, vece); 2724 break; 2725 case INDEX_op_shlv_vec: 2726 tcg_out_insn(s, VRRc, VESLV, a0, a1, a2, vece); 2727 break; 2728 case INDEX_op_shrv_vec: 2729 tcg_out_insn(s, VRRc, VESRLV, a0, a1, a2, vece); 2730 break; 2731 case INDEX_op_sarv_vec: 2732 tcg_out_insn(s, VRRc, VESRAV, a0, a1, a2, vece); 2733 break; 2734 case INDEX_op_rotlv_vec: 2735 tcg_out_insn(s, VRRc, VERLLV, a0, a1, a2, vece); 2736 break; 2737 2738 case INDEX_op_smin_vec: 2739 tcg_out_insn(s, VRRc, VMN, a0, a1, a2, vece); 2740 break; 2741 case INDEX_op_smax_vec: 2742 tcg_out_insn(s, VRRc, VMX, a0, a1, a2, vece); 2743 break; 2744 case INDEX_op_umin_vec: 2745 tcg_out_insn(s, VRRc, VMNL, a0, a1, a2, vece); 2746 break; 2747 case INDEX_op_umax_vec: 2748 tcg_out_insn(s, VRRc, VMXL, a0, a1, a2, vece); 2749 break; 2750 2751 case INDEX_op_bitsel_vec: 2752 tcg_out_insn(s, VRRe, VSEL, a0, a2, args[3], a1); 2753 break; 2754 2755 case INDEX_op_cmp_vec: 2756 switch ((TCGCond)args[3]) { 2757 case TCG_COND_EQ: 2758 tcg_out_insn(s, VRRc, VCEQ, a0, a1, a2, vece); 2759 break; 2760 case TCG_COND_GT: 2761 tcg_out_insn(s, VRRc, VCH, a0, a1, a2, vece); 2762 break; 2763 case TCG_COND_GTU: 2764 tcg_out_insn(s, VRRc, VCHL, a0, a1, a2, vece); 2765 break; 2766 default: 2767 g_assert_not_reached(); 2768 } 2769 break; 2770 2771 case INDEX_op_s390_vuph_vec: 2772 tcg_out_insn(s, VRRa, VUPH, a0, a1, vece); 2773 break; 2774 case INDEX_op_s390_vupl_vec: 2775 tcg_out_insn(s, VRRa, VUPL, a0, a1, vece); 2776 break; 2777 case INDEX_op_s390_vpks_vec: 2778 tcg_out_insn(s, VRRc, VPKS, a0, a1, a2, vece); 2779 break; 2780 2781 case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ 2782 case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ 2783 default: 2784 g_assert_not_reached(); 2785 } 2786} 2787 2788int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) 2789{ 2790 switch (opc) { 2791 case INDEX_op_abs_vec: 2792 case INDEX_op_add_vec: 2793 case INDEX_op_and_vec: 2794 case INDEX_op_andc_vec: 2795 case INDEX_op_bitsel_vec: 2796 case INDEX_op_eqv_vec: 2797 case INDEX_op_nand_vec: 2798 case INDEX_op_neg_vec: 2799 case INDEX_op_nor_vec: 2800 case INDEX_op_not_vec: 2801 case INDEX_op_or_vec: 2802 case INDEX_op_orc_vec: 2803 case INDEX_op_rotli_vec: 2804 case INDEX_op_rotls_vec: 2805 case INDEX_op_rotlv_vec: 2806 case INDEX_op_sari_vec: 2807 case INDEX_op_sars_vec: 2808 case INDEX_op_sarv_vec: 2809 case INDEX_op_shli_vec: 2810 case INDEX_op_shls_vec: 2811 case INDEX_op_shlv_vec: 2812 case INDEX_op_shri_vec: 2813 case INDEX_op_shrs_vec: 2814 case INDEX_op_shrv_vec: 2815 case INDEX_op_smax_vec: 2816 case INDEX_op_smin_vec: 2817 case INDEX_op_sub_vec: 2818 case INDEX_op_umax_vec: 2819 case INDEX_op_umin_vec: 2820 case INDEX_op_xor_vec: 2821 return 1; 2822 case INDEX_op_cmp_vec: 2823 case INDEX_op_cmpsel_vec: 2824 case INDEX_op_rotrv_vec: 2825 return -1; 2826 case INDEX_op_mul_vec: 2827 return vece < MO_64; 2828 case INDEX_op_ssadd_vec: 2829 case INDEX_op_sssub_vec: 2830 return vece < MO_64 ? -1 : 0; 2831 default: 2832 return 0; 2833 } 2834} 2835 2836static bool expand_vec_cmp_noinv(TCGType type, unsigned vece, TCGv_vec v0, 2837 TCGv_vec v1, TCGv_vec v2, TCGCond cond) 2838{ 2839 bool need_swap = false, need_inv = false; 2840 2841 switch (cond) { 2842 case TCG_COND_EQ: 2843 case TCG_COND_GT: 2844 case TCG_COND_GTU: 2845 break; 2846 case TCG_COND_NE: 2847 case TCG_COND_LE: 2848 case TCG_COND_LEU: 2849 need_inv = true; 2850 break; 2851 case TCG_COND_LT: 2852 case TCG_COND_LTU: 2853 need_swap = true; 2854 break; 2855 case TCG_COND_GE: 2856 case TCG_COND_GEU: 2857 need_swap = need_inv = true; 2858 break; 2859 default: 2860 g_assert_not_reached(); 2861 } 2862 2863 if (need_inv) { 2864 cond = tcg_invert_cond(cond); 2865 } 2866 if (need_swap) { 2867 TCGv_vec t1; 2868 t1 = v1, v1 = v2, v2 = t1; 2869 cond = tcg_swap_cond(cond); 2870 } 2871 2872 vec_gen_4(INDEX_op_cmp_vec, type, vece, tcgv_vec_arg(v0), 2873 tcgv_vec_arg(v1), tcgv_vec_arg(v2), cond); 2874 2875 return need_inv; 2876} 2877 2878static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0, 2879 TCGv_vec v1, TCGv_vec v2, TCGCond cond) 2880{ 2881 if (expand_vec_cmp_noinv(type, vece, v0, v1, v2, cond)) { 2882 tcg_gen_not_vec(vece, v0, v0); 2883 } 2884} 2885 2886static void expand_vec_cmpsel(TCGType type, unsigned vece, TCGv_vec v0, 2887 TCGv_vec c1, TCGv_vec c2, 2888 TCGv_vec v3, TCGv_vec v4, TCGCond cond) 2889{ 2890 TCGv_vec t = tcg_temp_new_vec(type); 2891 2892 if (expand_vec_cmp_noinv(type, vece, t, c1, c2, cond)) { 2893 /* Invert the sense of the compare by swapping arguments. */ 2894 tcg_gen_bitsel_vec(vece, v0, t, v4, v3); 2895 } else { 2896 tcg_gen_bitsel_vec(vece, v0, t, v3, v4); 2897 } 2898 tcg_temp_free_vec(t); 2899} 2900 2901static void expand_vec_sat(TCGType type, unsigned vece, TCGv_vec v0, 2902 TCGv_vec v1, TCGv_vec v2, TCGOpcode add_sub_opc) 2903{ 2904 TCGv_vec h1 = tcg_temp_new_vec(type); 2905 TCGv_vec h2 = tcg_temp_new_vec(type); 2906 TCGv_vec l1 = tcg_temp_new_vec(type); 2907 TCGv_vec l2 = tcg_temp_new_vec(type); 2908 2909 tcg_debug_assert (vece < MO_64); 2910 2911 /* Unpack with sign-extension. */ 2912 vec_gen_2(INDEX_op_s390_vuph_vec, type, vece, 2913 tcgv_vec_arg(h1), tcgv_vec_arg(v1)); 2914 vec_gen_2(INDEX_op_s390_vuph_vec, type, vece, 2915 tcgv_vec_arg(h2), tcgv_vec_arg(v2)); 2916 2917 vec_gen_2(INDEX_op_s390_vupl_vec, type, vece, 2918 tcgv_vec_arg(l1), tcgv_vec_arg(v1)); 2919 vec_gen_2(INDEX_op_s390_vupl_vec, type, vece, 2920 tcgv_vec_arg(l2), tcgv_vec_arg(v2)); 2921 2922 /* Arithmetic on a wider element size. */ 2923 vec_gen_3(add_sub_opc, type, vece + 1, tcgv_vec_arg(h1), 2924 tcgv_vec_arg(h1), tcgv_vec_arg(h2)); 2925 vec_gen_3(add_sub_opc, type, vece + 1, tcgv_vec_arg(l1), 2926 tcgv_vec_arg(l1), tcgv_vec_arg(l2)); 2927 2928 /* Pack with saturation. */ 2929 vec_gen_3(INDEX_op_s390_vpks_vec, type, vece + 1, 2930 tcgv_vec_arg(v0), tcgv_vec_arg(h1), tcgv_vec_arg(l1)); 2931 2932 tcg_temp_free_vec(h1); 2933 tcg_temp_free_vec(h2); 2934 tcg_temp_free_vec(l1); 2935 tcg_temp_free_vec(l2); 2936} 2937 2938void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, 2939 TCGArg a0, ...) 2940{ 2941 va_list va; 2942 TCGv_vec v0, v1, v2, v3, v4, t0; 2943 2944 va_start(va, a0); 2945 v0 = temp_tcgv_vec(arg_temp(a0)); 2946 v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); 2947 v2 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); 2948 2949 switch (opc) { 2950 case INDEX_op_cmp_vec: 2951 expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg)); 2952 break; 2953 2954 case INDEX_op_cmpsel_vec: 2955 v3 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); 2956 v4 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); 2957 expand_vec_cmpsel(type, vece, v0, v1, v2, v3, v4, va_arg(va, TCGArg)); 2958 break; 2959 2960 case INDEX_op_rotrv_vec: 2961 t0 = tcg_temp_new_vec(type); 2962 tcg_gen_neg_vec(vece, t0, v2); 2963 tcg_gen_rotlv_vec(vece, v0, v1, t0); 2964 tcg_temp_free_vec(t0); 2965 break; 2966 2967 case INDEX_op_ssadd_vec: 2968 expand_vec_sat(type, vece, v0, v1, v2, INDEX_op_add_vec); 2969 break; 2970 case INDEX_op_sssub_vec: 2971 expand_vec_sat(type, vece, v0, v1, v2, INDEX_op_sub_vec); 2972 break; 2973 2974 default: 2975 g_assert_not_reached(); 2976 } 2977 va_end(va); 2978} 2979 2980static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) 2981{ 2982 switch (op) { 2983 case INDEX_op_goto_ptr: 2984 return C_O0_I1(r); 2985 2986 case INDEX_op_ld8u_i32: 2987 case INDEX_op_ld8u_i64: 2988 case INDEX_op_ld8s_i32: 2989 case INDEX_op_ld8s_i64: 2990 case INDEX_op_ld16u_i32: 2991 case INDEX_op_ld16u_i64: 2992 case INDEX_op_ld16s_i32: 2993 case INDEX_op_ld16s_i64: 2994 case INDEX_op_ld_i32: 2995 case INDEX_op_ld32u_i64: 2996 case INDEX_op_ld32s_i64: 2997 case INDEX_op_ld_i64: 2998 return C_O1_I1(r, r); 2999 3000 case INDEX_op_st8_i32: 3001 case INDEX_op_st8_i64: 3002 case INDEX_op_st16_i32: 3003 case INDEX_op_st16_i64: 3004 case INDEX_op_st_i32: 3005 case INDEX_op_st32_i64: 3006 case INDEX_op_st_i64: 3007 return C_O0_I2(r, r); 3008 3009 case INDEX_op_add_i32: 3010 case INDEX_op_add_i64: 3011 case INDEX_op_shl_i64: 3012 case INDEX_op_shr_i64: 3013 case INDEX_op_sar_i64: 3014 case INDEX_op_rotl_i32: 3015 case INDEX_op_rotl_i64: 3016 case INDEX_op_rotr_i32: 3017 case INDEX_op_rotr_i64: 3018 case INDEX_op_setcond_i32: 3019 return C_O1_I2(r, r, ri); 3020 case INDEX_op_setcond_i64: 3021 return C_O1_I2(r, r, rA); 3022 3023 case INDEX_op_clz_i64: 3024 return C_O1_I2(r, r, rI); 3025 3026 case INDEX_op_sub_i32: 3027 case INDEX_op_sub_i64: 3028 case INDEX_op_and_i32: 3029 case INDEX_op_or_i32: 3030 case INDEX_op_xor_i32: 3031 return C_O1_I2(r, r, ri); 3032 case INDEX_op_and_i64: 3033 return C_O1_I2(r, r, rNKR); 3034 case INDEX_op_or_i64: 3035 case INDEX_op_xor_i64: 3036 return C_O1_I2(r, r, rK); 3037 3038 case INDEX_op_andc_i32: 3039 case INDEX_op_orc_i32: 3040 case INDEX_op_eqv_i32: 3041 return C_O1_I2(r, r, ri); 3042 case INDEX_op_andc_i64: 3043 return C_O1_I2(r, r, rKR); 3044 case INDEX_op_orc_i64: 3045 case INDEX_op_eqv_i64: 3046 return C_O1_I2(r, r, rNK); 3047 3048 case INDEX_op_nand_i32: 3049 case INDEX_op_nand_i64: 3050 case INDEX_op_nor_i32: 3051 case INDEX_op_nor_i64: 3052 return C_O1_I2(r, r, r); 3053 3054 case INDEX_op_mul_i32: 3055 return (HAVE_FACILITY(MISC_INSN_EXT2) 3056 ? C_O1_I2(r, r, ri) 3057 : C_O1_I2(r, 0, ri)); 3058 case INDEX_op_mul_i64: 3059 return (HAVE_FACILITY(MISC_INSN_EXT2) 3060 ? C_O1_I2(r, r, rJ) 3061 : C_O1_I2(r, 0, rJ)); 3062 3063 case INDEX_op_shl_i32: 3064 case INDEX_op_shr_i32: 3065 case INDEX_op_sar_i32: 3066 return C_O1_I2(r, r, ri); 3067 3068 case INDEX_op_brcond_i32: 3069 return C_O0_I2(r, ri); 3070 case INDEX_op_brcond_i64: 3071 return C_O0_I2(r, rA); 3072 3073 case INDEX_op_bswap16_i32: 3074 case INDEX_op_bswap16_i64: 3075 case INDEX_op_bswap32_i32: 3076 case INDEX_op_bswap32_i64: 3077 case INDEX_op_bswap64_i64: 3078 case INDEX_op_neg_i32: 3079 case INDEX_op_neg_i64: 3080 case INDEX_op_not_i32: 3081 case INDEX_op_not_i64: 3082 case INDEX_op_ext8s_i32: 3083 case INDEX_op_ext8s_i64: 3084 case INDEX_op_ext8u_i32: 3085 case INDEX_op_ext8u_i64: 3086 case INDEX_op_ext16s_i32: 3087 case INDEX_op_ext16s_i64: 3088 case INDEX_op_ext16u_i32: 3089 case INDEX_op_ext16u_i64: 3090 case INDEX_op_ext32s_i64: 3091 case INDEX_op_ext32u_i64: 3092 case INDEX_op_ext_i32_i64: 3093 case INDEX_op_extu_i32_i64: 3094 case INDEX_op_extract_i32: 3095 case INDEX_op_extract_i64: 3096 case INDEX_op_ctpop_i32: 3097 case INDEX_op_ctpop_i64: 3098 return C_O1_I1(r, r); 3099 3100 case INDEX_op_qemu_ld_a32_i32: 3101 case INDEX_op_qemu_ld_a64_i32: 3102 case INDEX_op_qemu_ld_a32_i64: 3103 case INDEX_op_qemu_ld_a64_i64: 3104 return C_O1_I1(r, r); 3105 case INDEX_op_qemu_st_a32_i64: 3106 case INDEX_op_qemu_st_a64_i64: 3107 case INDEX_op_qemu_st_a32_i32: 3108 case INDEX_op_qemu_st_a64_i32: 3109 return C_O0_I2(r, r); 3110 3111 case INDEX_op_deposit_i32: 3112 case INDEX_op_deposit_i64: 3113 return C_O1_I2(r, rZ, r); 3114 3115 case INDEX_op_movcond_i32: 3116 return C_O1_I4(r, r, ri, rI, r); 3117 case INDEX_op_movcond_i64: 3118 return C_O1_I4(r, r, rA, rI, r); 3119 3120 case INDEX_op_div2_i32: 3121 case INDEX_op_div2_i64: 3122 case INDEX_op_divu2_i32: 3123 case INDEX_op_divu2_i64: 3124 return C_O2_I3(o, m, 0, 1, r); 3125 3126 case INDEX_op_mulu2_i64: 3127 return C_O2_I2(o, m, 0, r); 3128 case INDEX_op_muls2_i64: 3129 return C_O2_I2(o, m, r, r); 3130 3131 case INDEX_op_add2_i32: 3132 case INDEX_op_sub2_i32: 3133 return C_O2_I4(r, r, 0, 1, ri, r); 3134 3135 case INDEX_op_add2_i64: 3136 case INDEX_op_sub2_i64: 3137 return C_O2_I4(r, r, 0, 1, rA, r); 3138 3139 case INDEX_op_st_vec: 3140 return C_O0_I2(v, r); 3141 case INDEX_op_ld_vec: 3142 case INDEX_op_dupm_vec: 3143 return C_O1_I1(v, r); 3144 case INDEX_op_dup_vec: 3145 return C_O1_I1(v, vr); 3146 case INDEX_op_abs_vec: 3147 case INDEX_op_neg_vec: 3148 case INDEX_op_not_vec: 3149 case INDEX_op_rotli_vec: 3150 case INDEX_op_sari_vec: 3151 case INDEX_op_shli_vec: 3152 case INDEX_op_shri_vec: 3153 case INDEX_op_s390_vuph_vec: 3154 case INDEX_op_s390_vupl_vec: 3155 return C_O1_I1(v, v); 3156 case INDEX_op_add_vec: 3157 case INDEX_op_sub_vec: 3158 case INDEX_op_and_vec: 3159 case INDEX_op_andc_vec: 3160 case INDEX_op_or_vec: 3161 case INDEX_op_orc_vec: 3162 case INDEX_op_xor_vec: 3163 case INDEX_op_nand_vec: 3164 case INDEX_op_nor_vec: 3165 case INDEX_op_eqv_vec: 3166 case INDEX_op_cmp_vec: 3167 case INDEX_op_mul_vec: 3168 case INDEX_op_rotlv_vec: 3169 case INDEX_op_rotrv_vec: 3170 case INDEX_op_shlv_vec: 3171 case INDEX_op_shrv_vec: 3172 case INDEX_op_sarv_vec: 3173 case INDEX_op_smax_vec: 3174 case INDEX_op_smin_vec: 3175 case INDEX_op_umax_vec: 3176 case INDEX_op_umin_vec: 3177 case INDEX_op_s390_vpks_vec: 3178 return C_O1_I2(v, v, v); 3179 case INDEX_op_rotls_vec: 3180 case INDEX_op_shls_vec: 3181 case INDEX_op_shrs_vec: 3182 case INDEX_op_sars_vec: 3183 return C_O1_I2(v, v, r); 3184 case INDEX_op_bitsel_vec: 3185 return C_O1_I3(v, v, v, v); 3186 3187 default: 3188 g_assert_not_reached(); 3189 } 3190} 3191 3192/* 3193 * Mainline glibc added HWCAP_S390_VX before it was kernel abi. 3194 * Some distros have fixed this up locally, others have not. 3195 */ 3196#ifndef HWCAP_S390_VXRS 3197#define HWCAP_S390_VXRS 2048 3198#endif 3199 3200static void query_s390_facilities(void) 3201{ 3202 unsigned long hwcap = qemu_getauxval(AT_HWCAP); 3203 const char *which; 3204 3205 /* Is STORE FACILITY LIST EXTENDED available? Honestly, I believe this 3206 is present on all 64-bit systems, but let's check for it anyway. */ 3207 if (hwcap & HWCAP_S390_STFLE) { 3208 register int r0 __asm__("0") = ARRAY_SIZE(s390_facilities) - 1; 3209 register void *r1 __asm__("1") = s390_facilities; 3210 3211 /* stfle 0(%r1) */ 3212 asm volatile(".word 0xb2b0,0x1000" 3213 : "=r"(r0) : "r"(r0), "r"(r1) : "memory", "cc"); 3214 } 3215 3216 /* 3217 * Use of vector registers requires os support beyond the facility bit. 3218 * If the kernel does not advertise support, disable the facility bits. 3219 * There is nothing else we currently care about in the 3rd word, so 3220 * disable VECTOR with one store. 3221 */ 3222 if (!(hwcap & HWCAP_S390_VXRS)) { 3223 s390_facilities[2] = 0; 3224 } 3225 3226 /* 3227 * Minimum supported cpu revision is z196. 3228 * Check for all required facilities. 3229 * ZARCH_ACTIVE is done via preprocessor check for 64-bit. 3230 */ 3231 if (!HAVE_FACILITY(LONG_DISP)) { 3232 which = "long-displacement"; 3233 goto fail; 3234 } 3235 if (!HAVE_FACILITY(EXT_IMM)) { 3236 which = "extended-immediate"; 3237 goto fail; 3238 } 3239 if (!HAVE_FACILITY(GEN_INST_EXT)) { 3240 which = "general-instructions-extension"; 3241 goto fail; 3242 } 3243 /* 3244 * Facility 45 is a big bin that contains: distinct-operands, 3245 * fast-BCR-serialization, high-word, population-count, 3246 * interlocked-access-1, and load/store-on-condition-1 3247 */ 3248 if (!HAVE_FACILITY(45)) { 3249 which = "45"; 3250 goto fail; 3251 } 3252 return; 3253 3254 fail: 3255 error_report("%s: missing required facility %s", __func__, which); 3256 exit(EXIT_FAILURE); 3257} 3258 3259static void tcg_target_init(TCGContext *s) 3260{ 3261 query_s390_facilities(); 3262 3263 tcg_target_available_regs[TCG_TYPE_I32] = 0xffff; 3264 tcg_target_available_regs[TCG_TYPE_I64] = 0xffff; 3265 if (HAVE_FACILITY(VECTOR)) { 3266 tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull; 3267 tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull; 3268 } 3269 3270 tcg_target_call_clobber_regs = 0; 3271 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0); 3272 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1); 3273 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2); 3274 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3); 3275 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R4); 3276 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R5); 3277 /* The r6 register is technically call-saved, but it's also a parameter 3278 register, so it can get killed by setup for the qemu_st helper. */ 3279 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R6); 3280 /* The return register can be considered call-clobbered. */ 3281 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14); 3282 3283 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); 3284 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); 3285 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V2); 3286 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V3); 3287 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V4); 3288 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V5); 3289 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V6); 3290 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V7); 3291 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V16); 3292 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V17); 3293 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V18); 3294 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V19); 3295 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V20); 3296 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V21); 3297 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V22); 3298 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V23); 3299 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V24); 3300 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V25); 3301 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V26); 3302 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V27); 3303 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V28); 3304 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V29); 3305 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V30); 3306 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V31); 3307 3308 s->reserved_regs = 0; 3309 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); 3310 /* XXX many insns can't be used with R0, so we better avoid it for now */ 3311 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); 3312 tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); 3313} 3314 3315#define FRAME_SIZE ((int)(TCG_TARGET_CALL_STACK_OFFSET \ 3316 + TCG_STATIC_CALL_ARGS_SIZE \ 3317 + CPU_TEMP_BUF_NLONGS * sizeof(long))) 3318 3319static void tcg_target_qemu_prologue(TCGContext *s) 3320{ 3321 /* stmg %r6,%r15,48(%r15) (save registers) */ 3322 tcg_out_insn(s, RXY, STMG, TCG_REG_R6, TCG_REG_R15, TCG_REG_R15, 48); 3323 3324 /* aghi %r15,-frame_size */ 3325 tcg_out_insn(s, RI, AGHI, TCG_REG_R15, -FRAME_SIZE); 3326 3327 tcg_set_frame(s, TCG_REG_CALL_STACK, 3328 TCG_STATIC_CALL_ARGS_SIZE + TCG_TARGET_CALL_STACK_OFFSET, 3329 CPU_TEMP_BUF_NLONGS * sizeof(long)); 3330 3331#ifndef CONFIG_SOFTMMU 3332 if (guest_base >= 0x80000) { 3333 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); 3334 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 3335 } 3336#endif 3337 3338 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 3339 3340 /* br %r3 (go to TB) */ 3341 tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, tcg_target_call_iarg_regs[1]); 3342 3343 /* 3344 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 3345 * and fall through to the rest of the epilogue. 3346 */ 3347 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 3348 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, 0); 3349 3350 /* TB epilogue */ 3351 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 3352 3353 /* lmg %r6,%r15,fs+48(%r15) (restore registers) */ 3354 tcg_out_insn(s, RXY, LMG, TCG_REG_R6, TCG_REG_R15, TCG_REG_R15, 3355 FRAME_SIZE + 48); 3356 3357 /* br %r14 (return) */ 3358 tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_R14); 3359} 3360 3361static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 3362{ 3363 memset(p, 0x07, count * sizeof(tcg_insn_unit)); 3364} 3365 3366typedef struct { 3367 DebugFrameHeader h; 3368 uint8_t fde_def_cfa[4]; 3369 uint8_t fde_reg_ofs[18]; 3370} DebugFrame; 3371 3372/* We're expecting a 2 byte uleb128 encoded value. */ 3373QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14)); 3374 3375#define ELF_HOST_MACHINE EM_S390 3376 3377static const DebugFrame debug_frame = { 3378 .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ 3379 .h.cie.id = -1, 3380 .h.cie.version = 1, 3381 .h.cie.code_align = 1, 3382 .h.cie.data_align = 8, /* sleb128 8 */ 3383 .h.cie.return_column = TCG_REG_R14, 3384 3385 /* Total FDE size does not include the "len" member. */ 3386 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 3387 3388 .fde_def_cfa = { 3389 12, TCG_REG_CALL_STACK, /* DW_CFA_def_cfa %r15, ... */ 3390 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 3391 (FRAME_SIZE >> 7) 3392 }, 3393 .fde_reg_ofs = { 3394 0x86, 6, /* DW_CFA_offset, %r6, 48 */ 3395 0x87, 7, /* DW_CFA_offset, %r7, 56 */ 3396 0x88, 8, /* DW_CFA_offset, %r8, 64 */ 3397 0x89, 9, /* DW_CFA_offset, %r92, 72 */ 3398 0x8a, 10, /* DW_CFA_offset, %r10, 80 */ 3399 0x8b, 11, /* DW_CFA_offset, %r11, 88 */ 3400 0x8c, 12, /* DW_CFA_offset, %r12, 96 */ 3401 0x8d, 13, /* DW_CFA_offset, %r13, 104 */ 3402 0x8e, 14, /* DW_CFA_offset, %r14, 112 */ 3403 } 3404}; 3405 3406void tcg_register_jit(const void *buf, size_t buf_size) 3407{ 3408 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 3409} 3410