1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2009 Ulrich Hecht <uli@suse.de> 5 * Copyright (c) 2009 Alexander Graf <agraf@suse.de> 6 * Copyright (c) 2010 Richard Henderson <rth@twiddle.net> 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27#include "elf.h" 28 29/* Used for function call generation. */ 30#define TCG_TARGET_STACK_ALIGN 8 31#define TCG_TARGET_CALL_STACK_OFFSET 160 32#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EXTEND 33#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL 34#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_BY_REF 35#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF 36 37#define TCG_CT_CONST_S16 (1 << 8) 38#define TCG_CT_CONST_S32 (1 << 9) 39#define TCG_CT_CONST_U32 (1 << 10) 40#define TCG_CT_CONST_ZERO (1 << 11) 41#define TCG_CT_CONST_P32 (1 << 12) 42#define TCG_CT_CONST_INV (1 << 13) 43#define TCG_CT_CONST_INVRISBG (1 << 14) 44#define TCG_CT_CONST_CMP (1 << 15) 45#define TCG_CT_CONST_M1 (1 << 16) 46 47#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 16) 48#define ALL_VECTOR_REGS MAKE_64BIT_MASK(32, 32) 49 50/* Several places within the instruction set 0 means "no register" 51 rather than TCG_REG_R0. */ 52#define TCG_REG_NONE 0 53 54/* A scratch register that may be be used throughout the backend. */ 55#define TCG_TMP0 TCG_REG_R1 56#define TCG_VEC_TMP0 TCG_REG_V31 57 58#define TCG_GUEST_BASE_REG TCG_REG_R13 59 60/* All of the following instructions are prefixed with their instruction 61 format, and are defined as 8- or 16-bit quantities, even when the two 62 halves of the 16-bit quantity may appear 32 bits apart in the insn. 63 This makes it easy to copy the values from the tables in Appendix B. */ 64typedef enum S390Opcode { 65 RIL_AFI = 0xc209, 66 RIL_AGFI = 0xc208, 67 RIL_ALFI = 0xc20b, 68 RIL_ALGFI = 0xc20a, 69 RIL_BRASL = 0xc005, 70 RIL_BRCL = 0xc004, 71 RIL_CFI = 0xc20d, 72 RIL_CGFI = 0xc20c, 73 RIL_CLFI = 0xc20f, 74 RIL_CLGFI = 0xc20e, 75 RIL_CLRL = 0xc60f, 76 RIL_CLGRL = 0xc60a, 77 RIL_CRL = 0xc60d, 78 RIL_CGRL = 0xc608, 79 RIL_IIHF = 0xc008, 80 RIL_IILF = 0xc009, 81 RIL_LARL = 0xc000, 82 RIL_LGFI = 0xc001, 83 RIL_LGRL = 0xc408, 84 RIL_LLIHF = 0xc00e, 85 RIL_LLILF = 0xc00f, 86 RIL_LRL = 0xc40d, 87 RIL_MSFI = 0xc201, 88 RIL_MSGFI = 0xc200, 89 RIL_NIHF = 0xc00a, 90 RIL_NILF = 0xc00b, 91 RIL_OIHF = 0xc00c, 92 RIL_OILF = 0xc00d, 93 RIL_SLFI = 0xc205, 94 RIL_SLGFI = 0xc204, 95 RIL_XIHF = 0xc006, 96 RIL_XILF = 0xc007, 97 98 RI_AGHI = 0xa70b, 99 RI_AHI = 0xa70a, 100 RI_BRC = 0xa704, 101 RI_CHI = 0xa70e, 102 RI_CGHI = 0xa70f, 103 RI_IIHH = 0xa500, 104 RI_IIHL = 0xa501, 105 RI_IILH = 0xa502, 106 RI_IILL = 0xa503, 107 RI_LGHI = 0xa709, 108 RI_LLIHH = 0xa50c, 109 RI_LLIHL = 0xa50d, 110 RI_LLILH = 0xa50e, 111 RI_LLILL = 0xa50f, 112 RI_MGHI = 0xa70d, 113 RI_MHI = 0xa70c, 114 RI_NIHH = 0xa504, 115 RI_NIHL = 0xa505, 116 RI_NILH = 0xa506, 117 RI_NILL = 0xa507, 118 RI_OIHH = 0xa508, 119 RI_OIHL = 0xa509, 120 RI_OILH = 0xa50a, 121 RI_OILL = 0xa50b, 122 RI_TMLL = 0xa701, 123 RI_TMLH = 0xa700, 124 RI_TMHL = 0xa703, 125 RI_TMHH = 0xa702, 126 127 RIEb_CGRJ = 0xec64, 128 RIEb_CLGRJ = 0xec65, 129 RIEb_CLRJ = 0xec77, 130 RIEb_CRJ = 0xec76, 131 132 RIEc_CGIJ = 0xec7c, 133 RIEc_CIJ = 0xec7e, 134 RIEc_CLGIJ = 0xec7d, 135 RIEc_CLIJ = 0xec7f, 136 137 RIEf_RISBG = 0xec55, 138 139 RIEg_LOCGHI = 0xec46, 140 141 RRE_AGR = 0xb908, 142 RRE_ALGR = 0xb90a, 143 RRE_ALCR = 0xb998, 144 RRE_ALCGR = 0xb988, 145 RRE_ALGFR = 0xb91a, 146 RRE_CGR = 0xb920, 147 RRE_CLGR = 0xb921, 148 RRE_DLGR = 0xb987, 149 RRE_DLR = 0xb997, 150 RRE_DSGFR = 0xb91d, 151 RRE_DSGR = 0xb90d, 152 RRE_FLOGR = 0xb983, 153 RRE_LGBR = 0xb906, 154 RRE_LCGR = 0xb903, 155 RRE_LGFR = 0xb914, 156 RRE_LGHR = 0xb907, 157 RRE_LGR = 0xb904, 158 RRE_LLGCR = 0xb984, 159 RRE_LLGFR = 0xb916, 160 RRE_LLGHR = 0xb985, 161 RRE_LRVR = 0xb91f, 162 RRE_LRVGR = 0xb90f, 163 RRE_LTGR = 0xb902, 164 RRE_MLGR = 0xb986, 165 RRE_MSGR = 0xb90c, 166 RRE_MSR = 0xb252, 167 RRE_NGR = 0xb980, 168 RRE_OGR = 0xb981, 169 RRE_SGR = 0xb909, 170 RRE_SLGR = 0xb90b, 171 RRE_SLBR = 0xb999, 172 RRE_SLBGR = 0xb989, 173 RRE_XGR = 0xb982, 174 175 RRFa_MGRK = 0xb9ec, 176 RRFa_MSRKC = 0xb9fd, 177 RRFa_MSGRKC = 0xb9ed, 178 RRFa_NCRK = 0xb9f5, 179 RRFa_NCGRK = 0xb9e5, 180 RRFa_NNRK = 0xb974, 181 RRFa_NNGRK = 0xb964, 182 RRFa_NORK = 0xb976, 183 RRFa_NOGRK = 0xb966, 184 RRFa_NRK = 0xb9f4, 185 RRFa_NGRK = 0xb9e4, 186 RRFa_NXRK = 0xb977, 187 RRFa_NXGRK = 0xb967, 188 RRFa_OCRK = 0xb975, 189 RRFa_OCGRK = 0xb965, 190 RRFa_ORK = 0xb9f6, 191 RRFa_OGRK = 0xb9e6, 192 RRFa_SRK = 0xb9f9, 193 RRFa_SGRK = 0xb9e9, 194 RRFa_SLRK = 0xb9fb, 195 RRFa_SLGRK = 0xb9eb, 196 RRFa_XRK = 0xb9f7, 197 RRFa_XGRK = 0xb9e7, 198 199 RRFam_SELGR = 0xb9e3, 200 201 RRFc_LOCR = 0xb9f2, 202 RRFc_LOCGR = 0xb9e2, 203 RRFc_POPCNT = 0xb9e1, 204 205 RR_AR = 0x1a, 206 RR_ALR = 0x1e, 207 RR_BASR = 0x0d, 208 RR_BCR = 0x07, 209 RR_CLR = 0x15, 210 RR_CR = 0x19, 211 RR_DR = 0x1d, 212 RR_LCR = 0x13, 213 RR_LR = 0x18, 214 RR_LTR = 0x12, 215 RR_NR = 0x14, 216 RR_OR = 0x16, 217 RR_SR = 0x1b, 218 RR_SLR = 0x1f, 219 RR_XR = 0x17, 220 221 RSY_RLL = 0xeb1d, 222 RSY_RLLG = 0xeb1c, 223 RSY_SLLG = 0xeb0d, 224 RSY_SLLK = 0xebdf, 225 RSY_SRAG = 0xeb0a, 226 RSY_SRAK = 0xebdc, 227 RSY_SRLG = 0xeb0c, 228 RSY_SRLK = 0xebde, 229 230 RS_SLL = 0x89, 231 RS_SRA = 0x8a, 232 RS_SRL = 0x88, 233 234 RXY_AG = 0xe308, 235 RXY_AY = 0xe35a, 236 RXY_CG = 0xe320, 237 RXY_CLG = 0xe321, 238 RXY_CLY = 0xe355, 239 RXY_CY = 0xe359, 240 RXY_LAY = 0xe371, 241 RXY_LB = 0xe376, 242 RXY_LG = 0xe304, 243 RXY_LGB = 0xe377, 244 RXY_LGF = 0xe314, 245 RXY_LGH = 0xe315, 246 RXY_LHY = 0xe378, 247 RXY_LLGC = 0xe390, 248 RXY_LLGF = 0xe316, 249 RXY_LLGH = 0xe391, 250 RXY_LMG = 0xeb04, 251 RXY_LPQ = 0xe38f, 252 RXY_LRV = 0xe31e, 253 RXY_LRVG = 0xe30f, 254 RXY_LRVH = 0xe31f, 255 RXY_LY = 0xe358, 256 RXY_NG = 0xe380, 257 RXY_OG = 0xe381, 258 RXY_STCY = 0xe372, 259 RXY_STG = 0xe324, 260 RXY_STHY = 0xe370, 261 RXY_STMG = 0xeb24, 262 RXY_STPQ = 0xe38e, 263 RXY_STRV = 0xe33e, 264 RXY_STRVG = 0xe32f, 265 RXY_STRVH = 0xe33f, 266 RXY_STY = 0xe350, 267 RXY_XG = 0xe382, 268 269 RX_A = 0x5a, 270 RX_C = 0x59, 271 RX_L = 0x58, 272 RX_LA = 0x41, 273 RX_LH = 0x48, 274 RX_ST = 0x50, 275 RX_STC = 0x42, 276 RX_STH = 0x40, 277 278 VRIa_VGBM = 0xe744, 279 VRIa_VREPI = 0xe745, 280 VRIb_VGM = 0xe746, 281 VRIc_VREP = 0xe74d, 282 283 VRRa_VLC = 0xe7de, 284 VRRa_VLP = 0xe7df, 285 VRRa_VLR = 0xe756, 286 VRRc_VA = 0xe7f3, 287 VRRc_VCEQ = 0xe7f8, /* we leave the m5 cs field 0 */ 288 VRRc_VCH = 0xe7fb, /* " */ 289 VRRc_VCHL = 0xe7f9, /* " */ 290 VRRc_VERLLV = 0xe773, 291 VRRc_VESLV = 0xe770, 292 VRRc_VESRAV = 0xe77a, 293 VRRc_VESRLV = 0xe778, 294 VRRc_VML = 0xe7a2, 295 VRRc_VMN = 0xe7fe, 296 VRRc_VMNL = 0xe7fc, 297 VRRc_VMX = 0xe7ff, 298 VRRc_VMXL = 0xe7fd, 299 VRRc_VN = 0xe768, 300 VRRc_VNC = 0xe769, 301 VRRc_VNN = 0xe76e, 302 VRRc_VNO = 0xe76b, 303 VRRc_VNX = 0xe76c, 304 VRRc_VO = 0xe76a, 305 VRRc_VOC = 0xe76f, 306 VRRc_VPKS = 0xe797, /* we leave the m5 cs field 0 */ 307 VRRc_VS = 0xe7f7, 308 VRRa_VUPH = 0xe7d7, 309 VRRa_VUPL = 0xe7d6, 310 VRRc_VX = 0xe76d, 311 VRRe_VSEL = 0xe78d, 312 VRRf_VLVGP = 0xe762, 313 314 VRSa_VERLL = 0xe733, 315 VRSa_VESL = 0xe730, 316 VRSa_VESRA = 0xe73a, 317 VRSa_VESRL = 0xe738, 318 VRSb_VLVG = 0xe722, 319 VRSc_VLGV = 0xe721, 320 321 VRX_VL = 0xe706, 322 VRX_VLLEZ = 0xe704, 323 VRX_VLREP = 0xe705, 324 VRX_VST = 0xe70e, 325 VRX_VSTEF = 0xe70b, 326 VRX_VSTEG = 0xe70a, 327 328 NOP = 0x0707, 329} S390Opcode; 330 331#ifdef CONFIG_DEBUG_TCG 332static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 333 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", 334 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", 335 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 336 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7", 337 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15", 338 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23", 339 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31", 340}; 341#endif 342 343/* Since R6 is a potential argument register, choose it last of the 344 call-saved registers. Likewise prefer the call-clobbered registers 345 in reverse order to maximize the chance of avoiding the arguments. */ 346static const int tcg_target_reg_alloc_order[] = { 347 /* Call saved registers. */ 348 TCG_REG_R13, 349 TCG_REG_R12, 350 TCG_REG_R11, 351 TCG_REG_R10, 352 TCG_REG_R9, 353 TCG_REG_R8, 354 TCG_REG_R7, 355 TCG_REG_R6, 356 /* Call clobbered registers. */ 357 TCG_REG_R14, 358 TCG_REG_R0, 359 TCG_REG_R1, 360 /* Argument registers, in reverse order of allocation. */ 361 TCG_REG_R5, 362 TCG_REG_R4, 363 TCG_REG_R3, 364 TCG_REG_R2, 365 366 /* V8-V15 are call saved, and omitted. */ 367 TCG_REG_V0, 368 TCG_REG_V1, 369 TCG_REG_V2, 370 TCG_REG_V3, 371 TCG_REG_V4, 372 TCG_REG_V5, 373 TCG_REG_V6, 374 TCG_REG_V7, 375 TCG_REG_V16, 376 TCG_REG_V17, 377 TCG_REG_V18, 378 TCG_REG_V19, 379 TCG_REG_V20, 380 TCG_REG_V21, 381 TCG_REG_V22, 382 TCG_REG_V23, 383 TCG_REG_V24, 384 TCG_REG_V25, 385 TCG_REG_V26, 386 TCG_REG_V27, 387 TCG_REG_V28, 388 TCG_REG_V29, 389 TCG_REG_V30, 390 TCG_REG_V31, 391}; 392 393static const int tcg_target_call_iarg_regs[] = { 394 TCG_REG_R2, 395 TCG_REG_R3, 396 TCG_REG_R4, 397 TCG_REG_R5, 398 TCG_REG_R6, 399}; 400 401static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 402{ 403 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 404 tcg_debug_assert(slot == 0); 405 return TCG_REG_R2; 406} 407 408#define S390_CC_EQ 8 409#define S390_CC_LT 4 410#define S390_CC_GT 2 411#define S390_CC_OV 1 412#define S390_CC_NE (S390_CC_LT | S390_CC_GT) 413#define S390_CC_LE (S390_CC_LT | S390_CC_EQ) 414#define S390_CC_GE (S390_CC_GT | S390_CC_EQ) 415#define S390_CC_NEVER 0 416#define S390_CC_ALWAYS 15 417 418#define S390_TM_EQ 8 /* CC == 0 */ 419#define S390_TM_NE 7 /* CC in {1,2,3} */ 420 421/* Condition codes that result from a COMPARE and COMPARE LOGICAL. */ 422static const uint8_t tcg_cond_to_s390_cond[16] = { 423 [TCG_COND_EQ] = S390_CC_EQ, 424 [TCG_COND_NE] = S390_CC_NE, 425 [TCG_COND_TSTEQ] = S390_CC_EQ, 426 [TCG_COND_TSTNE] = S390_CC_NE, 427 [TCG_COND_LT] = S390_CC_LT, 428 [TCG_COND_LE] = S390_CC_LE, 429 [TCG_COND_GT] = S390_CC_GT, 430 [TCG_COND_GE] = S390_CC_GE, 431 [TCG_COND_LTU] = S390_CC_LT, 432 [TCG_COND_LEU] = S390_CC_LE, 433 [TCG_COND_GTU] = S390_CC_GT, 434 [TCG_COND_GEU] = S390_CC_GE, 435}; 436 437/* Condition codes that result from a LOAD AND TEST. Here, we have no 438 unsigned instruction variation, however since the test is vs zero we 439 can re-map the outcomes appropriately. */ 440static const uint8_t tcg_cond_to_ltr_cond[16] = { 441 [TCG_COND_EQ] = S390_CC_EQ, 442 [TCG_COND_NE] = S390_CC_NE, 443 [TCG_COND_TSTEQ] = S390_CC_ALWAYS, 444 [TCG_COND_TSTNE] = S390_CC_NEVER, 445 [TCG_COND_LT] = S390_CC_LT, 446 [TCG_COND_LE] = S390_CC_LE, 447 [TCG_COND_GT] = S390_CC_GT, 448 [TCG_COND_GE] = S390_CC_GE, 449 [TCG_COND_LTU] = S390_CC_NEVER, 450 [TCG_COND_LEU] = S390_CC_EQ, 451 [TCG_COND_GTU] = S390_CC_NE, 452 [TCG_COND_GEU] = S390_CC_ALWAYS, 453}; 454 455static const tcg_insn_unit *tb_ret_addr; 456uint64_t s390_facilities[3]; 457 458static inline bool is_general_reg(TCGReg r) 459{ 460 return r <= TCG_REG_R15; 461} 462 463static inline bool is_vector_reg(TCGReg r) 464{ 465 return r >= TCG_REG_V0 && r <= TCG_REG_V31; 466} 467 468static bool patch_reloc(tcg_insn_unit *src_rw, int type, 469 intptr_t value, intptr_t addend) 470{ 471 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 472 intptr_t pcrel2; 473 uint32_t old; 474 475 value += addend; 476 pcrel2 = (tcg_insn_unit *)value - src_rx; 477 478 switch (type) { 479 case R_390_PC16DBL: 480 if (pcrel2 == (int16_t)pcrel2) { 481 tcg_patch16(src_rw, pcrel2); 482 return true; 483 } 484 break; 485 case R_390_PC32DBL: 486 if (pcrel2 == (int32_t)pcrel2) { 487 tcg_patch32(src_rw, pcrel2); 488 return true; 489 } 490 break; 491 case R_390_20: 492 if (value == sextract64(value, 0, 20)) { 493 old = *(uint32_t *)src_rw & 0xf00000ff; 494 old |= ((value & 0xfff) << 16) | ((value & 0xff000) >> 4); 495 tcg_patch32(src_rw, old); 496 return true; 497 } 498 break; 499 default: 500 g_assert_not_reached(); 501 } 502 return false; 503} 504 505static int is_const_p16(uint64_t val) 506{ 507 for (int i = 0; i < 4; ++i) { 508 uint64_t mask = 0xffffull << (i * 16); 509 if ((val & ~mask) == 0) { 510 return i; 511 } 512 } 513 return -1; 514} 515 516static int is_const_p32(uint64_t val) 517{ 518 if ((val & 0xffffffff00000000ull) == 0) { 519 return 0; 520 } 521 if ((val & 0x00000000ffffffffull) == 0) { 522 return 1; 523 } 524 return -1; 525} 526 527/* 528 * Accept bit patterns like these: 529 * 0....01....1 530 * 1....10....0 531 * 1..10..01..1 532 * 0..01..10..0 533 * Copied from gcc sources. 534 */ 535static bool risbg_mask(uint64_t c) 536{ 537 uint64_t lsb; 538 /* We don't change the number of transitions by inverting, 539 so make sure we start with the LSB zero. */ 540 if (c & 1) { 541 c = ~c; 542 } 543 /* Reject all zeros or all ones. */ 544 if (c == 0) { 545 return false; 546 } 547 /* Find the first transition. */ 548 lsb = c & -c; 549 /* Invert to look for a second transition. */ 550 c = ~c; 551 /* Erase the first transition. */ 552 c &= -lsb; 553 /* Find the second transition, if any. */ 554 lsb = c & -c; 555 /* Match if all the bits are 1's, or if c is zero. */ 556 return c == -lsb; 557} 558 559/* Test if a constant matches the constraint. */ 560static bool tcg_target_const_match(int64_t val, int ct, 561 TCGType type, TCGCond cond, int vece) 562{ 563 uint64_t uval = val; 564 565 if (ct & TCG_CT_CONST) { 566 return true; 567 } 568 if (type == TCG_TYPE_I32) { 569 uval = (uint32_t)val; 570 val = (int32_t)val; 571 } 572 573 if (ct & TCG_CT_CONST_CMP) { 574 if (is_tst_cond(cond)) { 575 if (is_const_p16(uval) >= 0) { 576 return true; /* TMxx */ 577 } 578 if (risbg_mask(uval)) { 579 return true; /* RISBG */ 580 } 581 return false; 582 } 583 584 if (type == TCG_TYPE_I32) { 585 return true; 586 } 587 588 switch (cond) { 589 case TCG_COND_EQ: 590 case TCG_COND_NE: 591 ct |= TCG_CT_CONST_S32 | TCG_CT_CONST_U32; /* CGFI or CLGFI */ 592 break; 593 case TCG_COND_LT: 594 case TCG_COND_GE: 595 case TCG_COND_LE: 596 case TCG_COND_GT: 597 ct |= TCG_CT_CONST_S32; /* CGFI */ 598 break; 599 case TCG_COND_LTU: 600 case TCG_COND_GEU: 601 case TCG_COND_LEU: 602 case TCG_COND_GTU: 603 ct |= TCG_CT_CONST_U32; /* CLGFI */ 604 break; 605 case TCG_COND_TSTNE: 606 case TCG_COND_TSTEQ: 607 /* checked above, fallthru */ 608 default: 609 g_assert_not_reached(); 610 } 611 } 612 613 if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) { 614 return true; 615 } 616 if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) { 617 return true; 618 } 619 if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) { 620 return true; 621 } 622 if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 623 return true; 624 } 625 if ((ct & TCG_CT_CONST_M1) && val == -1) { 626 return true; 627 } 628 629 if (ct & TCG_CT_CONST_INV) { 630 val = ~val; 631 } 632 if ((ct & TCG_CT_CONST_P32) && is_const_p32(val) >= 0) { 633 return true; 634 } 635 if ((ct & TCG_CT_CONST_INVRISBG) && risbg_mask(~val)) { 636 return true; 637 } 638 return false; 639} 640 641/* Emit instructions according to the given instruction format. */ 642 643static void tcg_out_insn_RR(TCGContext *s, S390Opcode op, TCGReg r1, TCGReg r2) 644{ 645 tcg_out16(s, (op << 8) | (r1 << 4) | r2); 646} 647 648static void tcg_out_insn_RRE(TCGContext *s, S390Opcode op, 649 TCGReg r1, TCGReg r2) 650{ 651 tcg_out32(s, (op << 16) | (r1 << 4) | r2); 652} 653 654/* RRF-a without the m4 field */ 655static void tcg_out_insn_RRFa(TCGContext *s, S390Opcode op, 656 TCGReg r1, TCGReg r2, TCGReg r3) 657{ 658 tcg_out32(s, (op << 16) | (r3 << 12) | (r1 << 4) | r2); 659} 660 661/* RRF-a with the m4 field */ 662static void tcg_out_insn_RRFam(TCGContext *s, S390Opcode op, 663 TCGReg r1, TCGReg r2, TCGReg r3, int m4) 664{ 665 tcg_out32(s, (op << 16) | (r3 << 12) | (m4 << 8) | (r1 << 4) | r2); 666} 667 668static void tcg_out_insn_RRFc(TCGContext *s, S390Opcode op, 669 TCGReg r1, TCGReg r2, int m3) 670{ 671 tcg_out32(s, (op << 16) | (m3 << 12) | (r1 << 4) | r2); 672} 673 674static void tcg_out_insn_RI(TCGContext *s, S390Opcode op, TCGReg r1, int i2) 675{ 676 tcg_out32(s, (op << 16) | (r1 << 20) | (i2 & 0xffff)); 677} 678 679static void tcg_out_insn_RIEg(TCGContext *s, S390Opcode op, TCGReg r1, 680 int i2, int m3) 681{ 682 tcg_out16(s, (op & 0xff00) | (r1 << 4) | m3); 683 tcg_out32(s, (i2 << 16) | (op & 0xff)); 684} 685 686static void tcg_out_insn_RIL(TCGContext *s, S390Opcode op, TCGReg r1, int i2) 687{ 688 tcg_out16(s, op | (r1 << 4)); 689 tcg_out32(s, i2); 690} 691 692static void tcg_out_insn_RS(TCGContext *s, S390Opcode op, TCGReg r1, 693 TCGReg b2, TCGReg r3, int disp) 694{ 695 tcg_out32(s, (op << 24) | (r1 << 20) | (r3 << 16) | (b2 << 12) 696 | (disp & 0xfff)); 697} 698 699static void tcg_out_insn_RSY(TCGContext *s, S390Opcode op, TCGReg r1, 700 TCGReg b2, TCGReg r3, int disp) 701{ 702 tcg_out16(s, (op & 0xff00) | (r1 << 4) | r3); 703 tcg_out32(s, (op & 0xff) | (b2 << 28) 704 | ((disp & 0xfff) << 16) | ((disp & 0xff000) >> 4)); 705} 706 707#define tcg_out_insn_RX tcg_out_insn_RS 708#define tcg_out_insn_RXY tcg_out_insn_RSY 709 710static int RXB(TCGReg v1, TCGReg v2, TCGReg v3, TCGReg v4) 711{ 712 /* 713 * Shift bit 4 of each regno to its corresponding bit of RXB. 714 * RXB itself begins at bit 8 of the instruction so 8 - 4 = 4 715 * is the left-shift of the 4th operand. 716 */ 717 return ((v1 & 0x10) << (4 + 3)) 718 | ((v2 & 0x10) << (4 + 2)) 719 | ((v3 & 0x10) << (4 + 1)) 720 | ((v4 & 0x10) << (4 + 0)); 721} 722 723static void tcg_out_insn_VRIa(TCGContext *s, S390Opcode op, 724 TCGReg v1, uint16_t i2, int m3) 725{ 726 tcg_debug_assert(is_vector_reg(v1)); 727 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4)); 728 tcg_out16(s, i2); 729 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m3 << 12)); 730} 731 732static void tcg_out_insn_VRIb(TCGContext *s, S390Opcode op, 733 TCGReg v1, uint8_t i2, uint8_t i3, int m4) 734{ 735 tcg_debug_assert(is_vector_reg(v1)); 736 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4)); 737 tcg_out16(s, (i2 << 8) | (i3 & 0xff)); 738 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m4 << 12)); 739} 740 741static void tcg_out_insn_VRIc(TCGContext *s, S390Opcode op, 742 TCGReg v1, uint16_t i2, TCGReg v3, int m4) 743{ 744 tcg_debug_assert(is_vector_reg(v1)); 745 tcg_debug_assert(is_vector_reg(v3)); 746 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v3 & 0xf)); 747 tcg_out16(s, i2); 748 tcg_out16(s, (op & 0x00ff) | RXB(v1, v3, 0, 0) | (m4 << 12)); 749} 750 751static void tcg_out_insn_VRRa(TCGContext *s, S390Opcode op, 752 TCGReg v1, TCGReg v2, int m3) 753{ 754 tcg_debug_assert(is_vector_reg(v1)); 755 tcg_debug_assert(is_vector_reg(v2)); 756 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v2 & 0xf)); 757 tcg_out32(s, (op & 0x00ff) | RXB(v1, v2, 0, 0) | (m3 << 12)); 758} 759 760static void tcg_out_insn_VRRc(TCGContext *s, S390Opcode op, 761 TCGReg v1, TCGReg v2, TCGReg v3, int m4) 762{ 763 tcg_debug_assert(is_vector_reg(v1)); 764 tcg_debug_assert(is_vector_reg(v2)); 765 tcg_debug_assert(is_vector_reg(v3)); 766 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v2 & 0xf)); 767 tcg_out16(s, v3 << 12); 768 tcg_out16(s, (op & 0x00ff) | RXB(v1, v2, v3, 0) | (m4 << 12)); 769} 770 771static void tcg_out_insn_VRRe(TCGContext *s, S390Opcode op, 772 TCGReg v1, TCGReg v2, TCGReg v3, TCGReg v4) 773{ 774 tcg_debug_assert(is_vector_reg(v1)); 775 tcg_debug_assert(is_vector_reg(v2)); 776 tcg_debug_assert(is_vector_reg(v3)); 777 tcg_debug_assert(is_vector_reg(v4)); 778 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v2 & 0xf)); 779 tcg_out16(s, v3 << 12); 780 tcg_out16(s, (op & 0x00ff) | RXB(v1, v2, v3, v4) | (v4 << 12)); 781} 782 783static void tcg_out_insn_VRRf(TCGContext *s, S390Opcode op, 784 TCGReg v1, TCGReg r2, TCGReg r3) 785{ 786 tcg_debug_assert(is_vector_reg(v1)); 787 tcg_debug_assert(is_general_reg(r2)); 788 tcg_debug_assert(is_general_reg(r3)); 789 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | r2); 790 tcg_out16(s, r3 << 12); 791 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0)); 792} 793 794static void tcg_out_insn_VRSa(TCGContext *s, S390Opcode op, TCGReg v1, 795 intptr_t d2, TCGReg b2, TCGReg v3, int m4) 796{ 797 tcg_debug_assert(is_vector_reg(v1)); 798 tcg_debug_assert(d2 >= 0 && d2 <= 0xfff); 799 tcg_debug_assert(is_general_reg(b2)); 800 tcg_debug_assert(is_vector_reg(v3)); 801 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v3 & 0xf)); 802 tcg_out16(s, b2 << 12 | d2); 803 tcg_out16(s, (op & 0x00ff) | RXB(v1, v3, 0, 0) | (m4 << 12)); 804} 805 806static void tcg_out_insn_VRSb(TCGContext *s, S390Opcode op, TCGReg v1, 807 intptr_t d2, TCGReg b2, TCGReg r3, int m4) 808{ 809 tcg_debug_assert(is_vector_reg(v1)); 810 tcg_debug_assert(d2 >= 0 && d2 <= 0xfff); 811 tcg_debug_assert(is_general_reg(b2)); 812 tcg_debug_assert(is_general_reg(r3)); 813 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | r3); 814 tcg_out16(s, b2 << 12 | d2); 815 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m4 << 12)); 816} 817 818static void tcg_out_insn_VRSc(TCGContext *s, S390Opcode op, TCGReg r1, 819 intptr_t d2, TCGReg b2, TCGReg v3, int m4) 820{ 821 tcg_debug_assert(is_general_reg(r1)); 822 tcg_debug_assert(d2 >= 0 && d2 <= 0xfff); 823 tcg_debug_assert(is_general_reg(b2)); 824 tcg_debug_assert(is_vector_reg(v3)); 825 tcg_out16(s, (op & 0xff00) | (r1 << 4) | (v3 & 0xf)); 826 tcg_out16(s, b2 << 12 | d2); 827 tcg_out16(s, (op & 0x00ff) | RXB(0, v3, 0, 0) | (m4 << 12)); 828} 829 830static void tcg_out_insn_VRX(TCGContext *s, S390Opcode op, TCGReg v1, 831 TCGReg b2, TCGReg x2, intptr_t d2, int m3) 832{ 833 tcg_debug_assert(is_vector_reg(v1)); 834 tcg_debug_assert(d2 >= 0 && d2 <= 0xfff); 835 tcg_debug_assert(is_general_reg(x2)); 836 tcg_debug_assert(is_general_reg(b2)); 837 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | x2); 838 tcg_out16(s, (b2 << 12) | d2); 839 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m3 << 12)); 840} 841 842/* Emit an opcode with "type-checking" of the format. */ 843#define tcg_out_insn(S, FMT, OP, ...) \ 844 glue(tcg_out_insn_,FMT)(S, glue(glue(FMT,_),OP), ## __VA_ARGS__) 845 846 847/* emit 64-bit shifts */ 848static void tcg_out_sh64(TCGContext* s, S390Opcode op, TCGReg dest, 849 TCGReg src, TCGReg sh_reg, int sh_imm) 850{ 851 tcg_out_insn_RSY(s, op, dest, sh_reg, src, sh_imm); 852} 853 854/* emit 32-bit shifts */ 855static void tcg_out_sh32(TCGContext* s, S390Opcode op, TCGReg dest, 856 TCGReg sh_reg, int sh_imm) 857{ 858 tcg_out_insn_RS(s, op, dest, sh_reg, 0, sh_imm); 859} 860 861static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg dst, TCGReg src) 862{ 863 if (src == dst) { 864 return true; 865 } 866 switch (type) { 867 case TCG_TYPE_I32: 868 if (likely(is_general_reg(dst) && is_general_reg(src))) { 869 tcg_out_insn(s, RR, LR, dst, src); 870 break; 871 } 872 /* fallthru */ 873 874 case TCG_TYPE_I64: 875 if (likely(is_general_reg(dst))) { 876 if (likely(is_general_reg(src))) { 877 tcg_out_insn(s, RRE, LGR, dst, src); 878 } else { 879 tcg_out_insn(s, VRSc, VLGV, dst, 0, 0, src, 3); 880 } 881 break; 882 } else if (is_general_reg(src)) { 883 tcg_out_insn(s, VRSb, VLVG, dst, 0, 0, src, 3); 884 break; 885 } 886 /* fallthru */ 887 888 case TCG_TYPE_V64: 889 case TCG_TYPE_V128: 890 tcg_out_insn(s, VRRa, VLR, dst, src, 0); 891 break; 892 893 default: 894 g_assert_not_reached(); 895 } 896 return true; 897} 898 899static const S390Opcode li_insns[4] = { 900 RI_LLILL, RI_LLILH, RI_LLIHL, RI_LLIHH 901}; 902static const S390Opcode oi_insns[4] = { 903 RI_OILL, RI_OILH, RI_OIHL, RI_OIHH 904}; 905static const S390Opcode lif_insns[2] = { 906 RIL_LLILF, RIL_LLIHF, 907}; 908static const S390Opcode tm_insns[4] = { 909 RI_TMLL, RI_TMLH, RI_TMHL, RI_TMHH 910}; 911 912/* load a register with an immediate value */ 913static void tcg_out_movi(TCGContext *s, TCGType type, 914 TCGReg ret, tcg_target_long sval) 915{ 916 tcg_target_ulong uval = sval; 917 ptrdiff_t pc_off; 918 int i; 919 920 if (type == TCG_TYPE_I32) { 921 uval = (uint32_t)sval; 922 sval = (int32_t)sval; 923 } 924 925 /* Try all 32-bit insns that can load it in one go. */ 926 if (sval >= -0x8000 && sval < 0x8000) { 927 tcg_out_insn(s, RI, LGHI, ret, sval); 928 return; 929 } 930 931 i = is_const_p16(uval); 932 if (i >= 0) { 933 tcg_out_insn_RI(s, li_insns[i], ret, uval >> (i * 16)); 934 return; 935 } 936 937 /* Try all 48-bit insns that can load it in one go. */ 938 if (sval == (int32_t)sval) { 939 tcg_out_insn(s, RIL, LGFI, ret, sval); 940 return; 941 } 942 943 i = is_const_p32(uval); 944 if (i >= 0) { 945 tcg_out_insn_RIL(s, lif_insns[i], ret, uval >> (i * 32)); 946 return; 947 } 948 949 /* Try for PC-relative address load. For odd addresses, add one. */ 950 pc_off = tcg_pcrel_diff(s, (void *)sval) >> 1; 951 if (pc_off == (int32_t)pc_off) { 952 tcg_out_insn(s, RIL, LARL, ret, pc_off); 953 if (sval & 1) { 954 tcg_out_insn(s, RI, AGHI, ret, 1); 955 } 956 return; 957 } 958 959 /* Otherwise, load it by parts. */ 960 i = is_const_p16((uint32_t)uval); 961 if (i >= 0) { 962 tcg_out_insn_RI(s, li_insns[i], ret, uval >> (i * 16)); 963 } else { 964 tcg_out_insn(s, RIL, LLILF, ret, uval); 965 } 966 uval >>= 32; 967 i = is_const_p16(uval); 968 if (i >= 0) { 969 tcg_out_insn_RI(s, oi_insns[i + 2], ret, uval >> (i * 16)); 970 } else { 971 tcg_out_insn(s, RIL, OIHF, ret, uval); 972 } 973} 974 975/* Emit a load/store type instruction. Inputs are: 976 DATA: The register to be loaded or stored. 977 BASE+OFS: The effective address. 978 OPC_RX: If the operation has an RX format opcode (e.g. STC), otherwise 0. 979 OPC_RXY: The RXY format opcode for the operation (e.g. STCY). */ 980 981static void tcg_out_mem(TCGContext *s, S390Opcode opc_rx, S390Opcode opc_rxy, 982 TCGReg data, TCGReg base, TCGReg index, 983 tcg_target_long ofs) 984{ 985 if (ofs < -0x80000 || ofs >= 0x80000) { 986 /* Combine the low 20 bits of the offset with the actual load insn; 987 the high 44 bits must come from an immediate load. */ 988 tcg_target_long low = ((ofs & 0xfffff) ^ 0x80000) - 0x80000; 989 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - low); 990 ofs = low; 991 992 /* If we were already given an index register, add it in. */ 993 if (index != TCG_REG_NONE) { 994 tcg_out_insn(s, RRE, AGR, TCG_TMP0, index); 995 } 996 index = TCG_TMP0; 997 } 998 999 if (opc_rx && ofs >= 0 && ofs < 0x1000) { 1000 tcg_out_insn_RX(s, opc_rx, data, base, index, ofs); 1001 } else { 1002 tcg_out_insn_RXY(s, opc_rxy, data, base, index, ofs); 1003 } 1004} 1005 1006static void tcg_out_vrx_mem(TCGContext *s, S390Opcode opc_vrx, 1007 TCGReg data, TCGReg base, TCGReg index, 1008 tcg_target_long ofs, int m3) 1009{ 1010 if (ofs < 0 || ofs >= 0x1000) { 1011 if (ofs >= -0x80000 && ofs < 0x80000) { 1012 tcg_out_insn(s, RXY, LAY, TCG_TMP0, base, index, ofs); 1013 base = TCG_TMP0; 1014 index = TCG_REG_NONE; 1015 ofs = 0; 1016 } else { 1017 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs); 1018 if (index != TCG_REG_NONE) { 1019 tcg_out_insn(s, RRE, AGR, TCG_TMP0, index); 1020 } 1021 index = TCG_TMP0; 1022 ofs = 0; 1023 } 1024 } 1025 tcg_out_insn_VRX(s, opc_vrx, data, base, index, ofs, m3); 1026} 1027 1028/* load data without address translation or endianness conversion */ 1029static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg data, 1030 TCGReg base, intptr_t ofs) 1031{ 1032 switch (type) { 1033 case TCG_TYPE_I32: 1034 if (likely(is_general_reg(data))) { 1035 tcg_out_mem(s, RX_L, RXY_LY, data, base, TCG_REG_NONE, ofs); 1036 break; 1037 } 1038 tcg_out_vrx_mem(s, VRX_VLLEZ, data, base, TCG_REG_NONE, ofs, MO_32); 1039 break; 1040 1041 case TCG_TYPE_I64: 1042 if (likely(is_general_reg(data))) { 1043 tcg_out_mem(s, 0, RXY_LG, data, base, TCG_REG_NONE, ofs); 1044 break; 1045 } 1046 /* fallthru */ 1047 1048 case TCG_TYPE_V64: 1049 tcg_out_vrx_mem(s, VRX_VLLEZ, data, base, TCG_REG_NONE, ofs, MO_64); 1050 break; 1051 1052 case TCG_TYPE_V128: 1053 /* Hint quadword aligned. */ 1054 tcg_out_vrx_mem(s, VRX_VL, data, base, TCG_REG_NONE, ofs, 4); 1055 break; 1056 1057 default: 1058 g_assert_not_reached(); 1059 } 1060} 1061 1062static void tcg_out_st(TCGContext *s, TCGType type, TCGReg data, 1063 TCGReg base, intptr_t ofs) 1064{ 1065 switch (type) { 1066 case TCG_TYPE_I32: 1067 if (likely(is_general_reg(data))) { 1068 tcg_out_mem(s, RX_ST, RXY_STY, data, base, TCG_REG_NONE, ofs); 1069 } else { 1070 tcg_out_vrx_mem(s, VRX_VSTEF, data, base, TCG_REG_NONE, ofs, 1); 1071 } 1072 break; 1073 1074 case TCG_TYPE_I64: 1075 if (likely(is_general_reg(data))) { 1076 tcg_out_mem(s, 0, RXY_STG, data, base, TCG_REG_NONE, ofs); 1077 break; 1078 } 1079 /* fallthru */ 1080 1081 case TCG_TYPE_V64: 1082 tcg_out_vrx_mem(s, VRX_VSTEG, data, base, TCG_REG_NONE, ofs, 0); 1083 break; 1084 1085 case TCG_TYPE_V128: 1086 /* Hint quadword aligned. */ 1087 tcg_out_vrx_mem(s, VRX_VST, data, base, TCG_REG_NONE, ofs, 4); 1088 break; 1089 1090 default: 1091 g_assert_not_reached(); 1092 } 1093} 1094 1095static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 1096 TCGReg base, intptr_t ofs) 1097{ 1098 return false; 1099} 1100 1101static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 1102{ 1103 return false; 1104} 1105 1106static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 1107 tcg_target_long imm) 1108{ 1109 /* This function is only used for passing structs by reference. */ 1110 tcg_out_mem(s, RX_LA, RXY_LAY, rd, rs, TCG_REG_NONE, imm); 1111} 1112 1113static inline void tcg_out_risbg(TCGContext *s, TCGReg dest, TCGReg src, 1114 int msb, int lsb, int ofs, int z) 1115{ 1116 /* Format RIE-f */ 1117 tcg_out16(s, (RIEf_RISBG & 0xff00) | (dest << 4) | src); 1118 tcg_out16(s, (msb << 8) | (z << 7) | lsb); 1119 tcg_out16(s, (ofs << 8) | (RIEf_RISBG & 0xff)); 1120} 1121 1122static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) 1123{ 1124 tcg_out_insn(s, RRE, LGBR, dest, src); 1125} 1126 1127static void tcg_out_ext8u(TCGContext *s, TCGReg dest, TCGReg src) 1128{ 1129 tcg_out_insn(s, RRE, LLGCR, dest, src); 1130} 1131 1132static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) 1133{ 1134 tcg_out_insn(s, RRE, LGHR, dest, src); 1135} 1136 1137static void tcg_out_ext16u(TCGContext *s, TCGReg dest, TCGReg src) 1138{ 1139 tcg_out_insn(s, RRE, LLGHR, dest, src); 1140} 1141 1142static void tcg_out_ext32s(TCGContext *s, TCGReg dest, TCGReg src) 1143{ 1144 tcg_out_insn(s, RRE, LGFR, dest, src); 1145} 1146 1147static void tcg_out_ext32u(TCGContext *s, TCGReg dest, TCGReg src) 1148{ 1149 tcg_out_insn(s, RRE, LLGFR, dest, src); 1150} 1151 1152static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg dest, TCGReg src) 1153{ 1154 tcg_out_ext32s(s, dest, src); 1155} 1156 1157static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg dest, TCGReg src) 1158{ 1159 tcg_out_ext32u(s, dest, src); 1160} 1161 1162static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg dest, TCGReg src) 1163{ 1164 tcg_out_mov(s, TCG_TYPE_I32, dest, src); 1165} 1166 1167static void tgen_andi_risbg(TCGContext *s, TCGReg out, TCGReg in, uint64_t val) 1168{ 1169 int msb, lsb; 1170 if ((val & 0x8000000000000001ull) == 0x8000000000000001ull) { 1171 /* Achieve wraparound by swapping msb and lsb. */ 1172 msb = 64 - ctz64(~val); 1173 lsb = clz64(~val) - 1; 1174 } else { 1175 msb = clz64(val); 1176 lsb = 63 - ctz64(val); 1177 } 1178 tcg_out_risbg(s, out, in, msb, lsb, 0, 1); 1179} 1180 1181static void tgen_andi(TCGContext *s, TCGType type, TCGReg dest, uint64_t val) 1182{ 1183 static const S390Opcode ni_insns[4] = { 1184 RI_NILL, RI_NILH, RI_NIHL, RI_NIHH 1185 }; 1186 static const S390Opcode nif_insns[2] = { 1187 RIL_NILF, RIL_NIHF 1188 }; 1189 uint64_t valid = (type == TCG_TYPE_I32 ? 0xffffffffull : -1ull); 1190 int i; 1191 1192 /* Look for the zero-extensions. */ 1193 if ((val & valid) == 0xffffffff) { 1194 tcg_out_ext32u(s, dest, dest); 1195 return; 1196 } 1197 if ((val & valid) == 0xff) { 1198 tcg_out_ext8u(s, dest, dest); 1199 return; 1200 } 1201 if ((val & valid) == 0xffff) { 1202 tcg_out_ext16u(s, dest, dest); 1203 return; 1204 } 1205 1206 i = is_const_p16(~val & valid); 1207 if (i >= 0) { 1208 tcg_out_insn_RI(s, ni_insns[i], dest, val >> (i * 16)); 1209 return; 1210 } 1211 1212 i = is_const_p32(~val & valid); 1213 tcg_debug_assert(i == 0 || type != TCG_TYPE_I32); 1214 if (i >= 0) { 1215 tcg_out_insn_RIL(s, nif_insns[i], dest, val >> (i * 32)); 1216 return; 1217 } 1218 1219 if (risbg_mask(val)) { 1220 tgen_andi_risbg(s, dest, dest, val); 1221 return; 1222 } 1223 1224 g_assert_not_reached(); 1225} 1226 1227static void tgen_ori(TCGContext *s, TCGReg dest, uint64_t val) 1228{ 1229 static const S390Opcode oif_insns[2] = { 1230 RIL_OILF, RIL_OIHF 1231 }; 1232 1233 int i; 1234 1235 i = is_const_p16(val); 1236 if (i >= 0) { 1237 tcg_out_insn_RI(s, oi_insns[i], dest, val >> (i * 16)); 1238 return; 1239 } 1240 1241 i = is_const_p32(val); 1242 if (i >= 0) { 1243 tcg_out_insn_RIL(s, oif_insns[i], dest, val >> (i * 32)); 1244 return; 1245 } 1246 1247 g_assert_not_reached(); 1248} 1249 1250static void tgen_xori(TCGContext *s, TCGReg dest, uint64_t val) 1251{ 1252 switch (is_const_p32(val)) { 1253 case 0: 1254 tcg_out_insn(s, RIL, XILF, dest, val); 1255 break; 1256 case 1: 1257 tcg_out_insn(s, RIL, XIHF, dest, val >> 32); 1258 break; 1259 default: 1260 g_assert_not_reached(); 1261 } 1262} 1263 1264static int tgen_cmp2(TCGContext *s, TCGType type, TCGCond c, TCGReg r1, 1265 TCGArg c2, bool c2const, bool need_carry, int *inv_cc) 1266{ 1267 bool is_unsigned = is_unsigned_cond(c); 1268 TCGCond inv_c = tcg_invert_cond(c); 1269 S390Opcode op; 1270 1271 if (is_tst_cond(c)) { 1272 tcg_debug_assert(!need_carry); 1273 1274 if (!c2const) { 1275 if (type == TCG_TYPE_I32) { 1276 tcg_out_insn(s, RRFa, NRK, TCG_REG_R0, r1, c2); 1277 } else { 1278 tcg_out_insn(s, RRFa, NGRK, TCG_REG_R0, r1, c2); 1279 } 1280 goto exit; 1281 } 1282 1283 if (type == TCG_TYPE_I32) { 1284 c2 = (uint32_t)c2; 1285 } 1286 1287 int i = is_const_p16(c2); 1288 if (i >= 0) { 1289 tcg_out_insn_RI(s, tm_insns[i], r1, c2 >> (i * 16)); 1290 *inv_cc = c == TCG_COND_TSTEQ ? S390_TM_NE : S390_TM_EQ; 1291 return *inv_cc ^ 15; 1292 } 1293 1294 if (risbg_mask(c2)) { 1295 tgen_andi_risbg(s, TCG_REG_R0, r1, c2); 1296 goto exit; 1297 } 1298 g_assert_not_reached(); 1299 } 1300 1301 if (c2const) { 1302 if (c2 == 0) { 1303 if (!(is_unsigned && need_carry)) { 1304 if (type == TCG_TYPE_I32) { 1305 tcg_out_insn(s, RR, LTR, r1, r1); 1306 } else { 1307 tcg_out_insn(s, RRE, LTGR, r1, r1); 1308 } 1309 *inv_cc = tcg_cond_to_ltr_cond[inv_c]; 1310 return tcg_cond_to_ltr_cond[c]; 1311 } 1312 } 1313 1314 if (!is_unsigned && c2 == (int16_t)c2) { 1315 op = (type == TCG_TYPE_I32 ? RI_CHI : RI_CGHI); 1316 tcg_out_insn_RI(s, op, r1, c2); 1317 goto exit; 1318 } 1319 1320 if (type == TCG_TYPE_I32) { 1321 op = (is_unsigned ? RIL_CLFI : RIL_CFI); 1322 tcg_out_insn_RIL(s, op, r1, c2); 1323 goto exit; 1324 } 1325 1326 /* Should match TCG_CT_CONST_CMP. */ 1327 switch (c) { 1328 case TCG_COND_LT: 1329 case TCG_COND_GE: 1330 case TCG_COND_LE: 1331 case TCG_COND_GT: 1332 tcg_debug_assert(c2 == (int32_t)c2); 1333 op = RIL_CGFI; 1334 break; 1335 case TCG_COND_EQ: 1336 case TCG_COND_NE: 1337 if (c2 == (int32_t)c2) { 1338 op = RIL_CGFI; 1339 break; 1340 } 1341 /* fall through */ 1342 case TCG_COND_LTU: 1343 case TCG_COND_GEU: 1344 case TCG_COND_LEU: 1345 case TCG_COND_GTU: 1346 tcg_debug_assert(c2 == (uint32_t)c2); 1347 op = RIL_CLGFI; 1348 break; 1349 default: 1350 g_assert_not_reached(); 1351 } 1352 tcg_out_insn_RIL(s, op, r1, c2); 1353 } else if (type == TCG_TYPE_I32) { 1354 op = (is_unsigned ? RR_CLR : RR_CR); 1355 tcg_out_insn_RR(s, op, r1, c2); 1356 } else { 1357 op = (is_unsigned ? RRE_CLGR : RRE_CGR); 1358 tcg_out_insn_RRE(s, op, r1, c2); 1359 } 1360 1361 exit: 1362 *inv_cc = tcg_cond_to_s390_cond[inv_c]; 1363 return tcg_cond_to_s390_cond[c]; 1364} 1365 1366static int tgen_cmp(TCGContext *s, TCGType type, TCGCond c, TCGReg r1, 1367 TCGArg c2, bool c2const, bool need_carry) 1368{ 1369 int inv_cc; 1370 return tgen_cmp2(s, type, c, r1, c2, c2const, need_carry, &inv_cc); 1371} 1372 1373static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, 1374 TCGReg dest, TCGReg c1, TCGArg c2, 1375 bool c2const, bool neg) 1376{ 1377 int cc; 1378 1379 /* With LOC2, we can always emit the minimum 3 insns. */ 1380 if (HAVE_FACILITY(LOAD_ON_COND2)) { 1381 /* Emit: d = 0, d = (cc ? 1 : d). */ 1382 cc = tgen_cmp(s, type, cond, c1, c2, c2const, false); 1383 tcg_out_movi(s, TCG_TYPE_I64, dest, 0); 1384 tcg_out_insn(s, RIEg, LOCGHI, dest, neg ? -1 : 1, cc); 1385 return; 1386 } 1387 1388 switch (cond) { 1389 case TCG_COND_GEU: 1390 case TCG_COND_LTU: 1391 case TCG_COND_LT: 1392 case TCG_COND_GE: 1393 /* Swap operands so that we can use LEU/GTU/GT/LE. */ 1394 if (!c2const) { 1395 TCGReg t = c1; 1396 c1 = c2; 1397 c2 = t; 1398 cond = tcg_swap_cond(cond); 1399 } 1400 break; 1401 default: 1402 break; 1403 } 1404 1405 switch (cond) { 1406 case TCG_COND_NE: 1407 /* X != 0 is X > 0. */ 1408 if (c2const && c2 == 0) { 1409 cond = TCG_COND_GTU; 1410 } else { 1411 break; 1412 } 1413 /* fallthru */ 1414 1415 case TCG_COND_GTU: 1416 case TCG_COND_GT: 1417 /* 1418 * The result of a compare has CC=2 for GT and CC=3 unused. 1419 * ADD LOGICAL WITH CARRY considers (CC & 2) the carry bit. 1420 */ 1421 tgen_cmp(s, type, cond, c1, c2, c2const, true); 1422 tcg_out_movi(s, type, dest, 0); 1423 tcg_out_insn(s, RRE, ALCGR, dest, dest); 1424 if (neg) { 1425 if (type == TCG_TYPE_I32) { 1426 tcg_out_insn(s, RR, LCR, dest, dest); 1427 } else { 1428 tcg_out_insn(s, RRE, LCGR, dest, dest); 1429 } 1430 } 1431 return; 1432 1433 case TCG_COND_EQ: 1434 /* X == 0 is X <= 0. */ 1435 if (c2const && c2 == 0) { 1436 cond = TCG_COND_LEU; 1437 } else { 1438 break; 1439 } 1440 /* fallthru */ 1441 1442 case TCG_COND_LEU: 1443 case TCG_COND_LE: 1444 /* 1445 * As above, but we're looking for borrow, or !carry. 1446 * The second insn computes d - d - borrow, or -1 for true 1447 * and 0 for false. So we must mask to 1 bit afterward. 1448 */ 1449 tgen_cmp(s, type, cond, c1, c2, c2const, true); 1450 tcg_out_insn(s, RRE, SLBGR, dest, dest); 1451 if (!neg) { 1452 tgen_andi(s, type, dest, 1); 1453 } 1454 return; 1455 1456 default: 1457 g_assert_not_reached(); 1458 } 1459 1460 cc = tgen_cmp(s, type, cond, c1, c2, c2const, false); 1461 /* Emit: d = 0, t = 1, d = (cc ? t : d). */ 1462 tcg_out_movi(s, TCG_TYPE_I64, dest, 0); 1463 tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, neg ? -1 : 1); 1464 tcg_out_insn(s, RRFc, LOCGR, dest, TCG_TMP0, cc); 1465} 1466 1467static void tgen_movcond_int(TCGContext *s, TCGType type, TCGReg dest, 1468 TCGArg v3, int v3const, TCGReg v4, 1469 int cc, int inv_cc) 1470{ 1471 TCGReg src; 1472 1473 if (v3const) { 1474 if (dest == v4) { 1475 if (HAVE_FACILITY(LOAD_ON_COND2)) { 1476 /* Emit: if (cc) dest = v3. */ 1477 tcg_out_insn(s, RIEg, LOCGHI, dest, v3, cc); 1478 return; 1479 } 1480 tcg_out_insn(s, RI, LGHI, TCG_TMP0, v3); 1481 src = TCG_TMP0; 1482 } else { 1483 /* LGR+LOCGHI is larger than LGHI+LOCGR. */ 1484 tcg_out_insn(s, RI, LGHI, dest, v3); 1485 cc = inv_cc; 1486 src = v4; 1487 } 1488 } else { 1489 if (HAVE_FACILITY(MISC_INSN_EXT3)) { 1490 /* Emit: dest = cc ? v3 : v4. */ 1491 tcg_out_insn(s, RRFam, SELGR, dest, v3, v4, cc); 1492 return; 1493 } 1494 if (dest == v4) { 1495 src = v3; 1496 } else { 1497 tcg_out_mov(s, type, dest, v3); 1498 cc = inv_cc; 1499 src = v4; 1500 } 1501 } 1502 1503 /* Emit: if (cc) dest = src. */ 1504 tcg_out_insn(s, RRFc, LOCGR, dest, src, cc); 1505} 1506 1507static void tgen_movcond(TCGContext *s, TCGType type, TCGCond c, TCGReg dest, 1508 TCGReg c1, TCGArg c2, int c2const, 1509 TCGArg v3, int v3const, TCGReg v4) 1510{ 1511 int cc, inv_cc; 1512 1513 cc = tgen_cmp2(s, type, c, c1, c2, c2const, false, &inv_cc); 1514 tgen_movcond_int(s, type, dest, v3, v3const, v4, cc, inv_cc); 1515} 1516 1517static void tgen_clz(TCGContext *s, TCGReg dest, TCGReg a1, 1518 TCGArg a2, int a2const) 1519{ 1520 /* Since this sets both R and R+1, we have no choice but to store the 1521 result into R0, allowing R1 == TCG_TMP0 to be clobbered as well. */ 1522 QEMU_BUILD_BUG_ON(TCG_TMP0 != TCG_REG_R1); 1523 tcg_out_insn(s, RRE, FLOGR, TCG_REG_R0, a1); 1524 1525 if (a2const && a2 == 64) { 1526 tcg_out_mov(s, TCG_TYPE_I64, dest, TCG_REG_R0); 1527 return; 1528 } 1529 1530 /* 1531 * Conditions from FLOGR are: 1532 * 2 -> one bit found 1533 * 8 -> no one bit found 1534 */ 1535 tgen_movcond_int(s, TCG_TYPE_I64, dest, a2, a2const, TCG_REG_R0, 8, 2); 1536} 1537 1538static void tgen_ctpop(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) 1539{ 1540 /* With MIE3, and bit 0 of m4 set, we get the complete result. */ 1541 if (HAVE_FACILITY(MISC_INSN_EXT3)) { 1542 if (type == TCG_TYPE_I32) { 1543 tcg_out_ext32u(s, dest, src); 1544 src = dest; 1545 } 1546 tcg_out_insn(s, RRFc, POPCNT, dest, src, 8); 1547 return; 1548 } 1549 1550 /* Without MIE3, each byte gets the count of bits for the byte. */ 1551 tcg_out_insn(s, RRFc, POPCNT, dest, src, 0); 1552 1553 /* Multiply to sum each byte at the top of the word. */ 1554 if (type == TCG_TYPE_I32) { 1555 tcg_out_insn(s, RIL, MSFI, dest, 0x01010101); 1556 tcg_out_sh32(s, RS_SRL, dest, TCG_REG_NONE, 24); 1557 } else { 1558 tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 0x0101010101010101ull); 1559 tcg_out_insn(s, RRE, MSGR, dest, TCG_TMP0); 1560 tcg_out_sh64(s, RSY_SRLG, dest, dest, TCG_REG_NONE, 56); 1561 } 1562} 1563 1564static void tgen_deposit(TCGContext *s, TCGReg dest, TCGReg src, 1565 int ofs, int len, int z) 1566{ 1567 int lsb = (63 - ofs); 1568 int msb = lsb - (len - 1); 1569 tcg_out_risbg(s, dest, src, msb, lsb, ofs, z); 1570} 1571 1572static void tgen_extract(TCGContext *s, TCGReg dest, TCGReg src, 1573 int ofs, int len) 1574{ 1575 if (ofs == 0) { 1576 switch (len) { 1577 case 8: 1578 tcg_out_ext8u(s, dest, src); 1579 return; 1580 case 16: 1581 tcg_out_ext16u(s, dest, src); 1582 return; 1583 case 32: 1584 tcg_out_ext32u(s, dest, src); 1585 return; 1586 } 1587 } 1588 tcg_out_risbg(s, dest, src, 64 - len, 63, 64 - ofs, 1); 1589} 1590 1591static void tgen_sextract(TCGContext *s, TCGReg dest, TCGReg src, 1592 int ofs, int len) 1593{ 1594 if (ofs == 0) { 1595 switch (len) { 1596 case 8: 1597 tcg_out_ext8s(s, TCG_TYPE_REG, dest, src); 1598 return; 1599 case 16: 1600 tcg_out_ext16s(s, TCG_TYPE_REG, dest, src); 1601 return; 1602 case 32: 1603 tcg_out_ext32s(s, dest, src); 1604 return; 1605 } 1606 } 1607 g_assert_not_reached(); 1608} 1609 1610static void tgen_gotoi(TCGContext *s, int cc, const tcg_insn_unit *dest) 1611{ 1612 ptrdiff_t off = tcg_pcrel_diff(s, dest) >> 1; 1613 if (off == (int16_t)off) { 1614 tcg_out_insn(s, RI, BRC, cc, off); 1615 } else if (off == (int32_t)off) { 1616 tcg_out_insn(s, RIL, BRCL, cc, off); 1617 } else { 1618 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)dest); 1619 tcg_out_insn(s, RR, BCR, cc, TCG_TMP0); 1620 } 1621} 1622 1623static void tgen_branch(TCGContext *s, int cc, TCGLabel *l) 1624{ 1625 if (l->has_value) { 1626 tgen_gotoi(s, cc, l->u.value_ptr); 1627 } else { 1628 tcg_out16(s, RI_BRC | (cc << 4)); 1629 tcg_out_reloc(s, s->code_ptr, R_390_PC16DBL, l, 2); 1630 s->code_ptr += 1; 1631 } 1632} 1633 1634static void tgen_compare_branch(TCGContext *s, S390Opcode opc, int cc, 1635 TCGReg r1, TCGReg r2, TCGLabel *l) 1636{ 1637 tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2); 1638 /* Format RIE-b */ 1639 tcg_out16(s, (opc & 0xff00) | (r1 << 4) | r2); 1640 tcg_out16(s, 0); 1641 tcg_out16(s, cc << 12 | (opc & 0xff)); 1642} 1643 1644static void tgen_compare_imm_branch(TCGContext *s, S390Opcode opc, int cc, 1645 TCGReg r1, int i2, TCGLabel *l) 1646{ 1647 tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2); 1648 /* Format RIE-c */ 1649 tcg_out16(s, (opc & 0xff00) | (r1 << 4) | cc); 1650 tcg_out16(s, 0); 1651 tcg_out16(s, (i2 << 8) | (opc & 0xff)); 1652} 1653 1654static void tgen_brcond(TCGContext *s, TCGType type, TCGCond c, 1655 TCGReg r1, TCGArg c2, int c2const, TCGLabel *l) 1656{ 1657 int cc; 1658 1659 if (!is_tst_cond(c)) { 1660 bool is_unsigned = is_unsigned_cond(c); 1661 bool in_range; 1662 S390Opcode opc; 1663 1664 cc = tcg_cond_to_s390_cond[c]; 1665 1666 if (!c2const) { 1667 opc = (type == TCG_TYPE_I32 1668 ? (is_unsigned ? RIEb_CLRJ : RIEb_CRJ) 1669 : (is_unsigned ? RIEb_CLGRJ : RIEb_CGRJ)); 1670 tgen_compare_branch(s, opc, cc, r1, c2, l); 1671 return; 1672 } 1673 1674 /* 1675 * COMPARE IMMEDIATE AND BRANCH RELATIVE has an 8-bit immediate field. 1676 * If the immediate we've been given does not fit that range, we'll 1677 * fall back to separate compare and branch instructions using the 1678 * larger comparison range afforded by COMPARE IMMEDIATE. 1679 */ 1680 if (type == TCG_TYPE_I32) { 1681 if (is_unsigned) { 1682 opc = RIEc_CLIJ; 1683 in_range = (uint32_t)c2 == (uint8_t)c2; 1684 } else { 1685 opc = RIEc_CIJ; 1686 in_range = (int32_t)c2 == (int8_t)c2; 1687 } 1688 } else { 1689 if (is_unsigned) { 1690 opc = RIEc_CLGIJ; 1691 in_range = (uint64_t)c2 == (uint8_t)c2; 1692 } else { 1693 opc = RIEc_CGIJ; 1694 in_range = (int64_t)c2 == (int8_t)c2; 1695 } 1696 } 1697 if (in_range) { 1698 tgen_compare_imm_branch(s, opc, cc, r1, c2, l); 1699 return; 1700 } 1701 } 1702 1703 cc = tgen_cmp(s, type, c, r1, c2, c2const, false); 1704 tgen_branch(s, cc, l); 1705} 1706 1707static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *dest) 1708{ 1709 ptrdiff_t off = tcg_pcrel_diff(s, dest) >> 1; 1710 if (off == (int32_t)off) { 1711 tcg_out_insn(s, RIL, BRASL, TCG_REG_R14, off); 1712 } else { 1713 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)dest); 1714 tcg_out_insn(s, RR, BASR, TCG_REG_R14, TCG_TMP0); 1715 } 1716} 1717 1718static void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest, 1719 const TCGHelperInfo *info) 1720{ 1721 tcg_out_call_int(s, dest); 1722} 1723 1724typedef struct { 1725 TCGReg base; 1726 TCGReg index; 1727 int disp; 1728 TCGAtomAlign aa; 1729} HostAddress; 1730 1731bool tcg_target_has_memory_bswap(MemOp memop) 1732{ 1733 TCGAtomAlign aa; 1734 1735 if ((memop & MO_SIZE) <= MO_64) { 1736 return true; 1737 } 1738 1739 /* 1740 * Reject 16-byte memop with 16-byte atomicity, 1741 * but do allow a pair of 64-bit operations. 1742 */ 1743 aa = atom_and_align_for_opc(tcg_ctx, memop, MO_ATOM_IFALIGN, true); 1744 return aa.atom <= MO_64; 1745} 1746 1747static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg data, 1748 HostAddress h) 1749{ 1750 switch (opc & (MO_SSIZE | MO_BSWAP)) { 1751 case MO_UB: 1752 tcg_out_insn(s, RXY, LLGC, data, h.base, h.index, h.disp); 1753 break; 1754 case MO_SB: 1755 tcg_out_insn(s, RXY, LGB, data, h.base, h.index, h.disp); 1756 break; 1757 1758 case MO_UW | MO_BSWAP: 1759 /* swapped unsigned halfword load with upper bits zeroed */ 1760 tcg_out_insn(s, RXY, LRVH, data, h.base, h.index, h.disp); 1761 tcg_out_ext16u(s, data, data); 1762 break; 1763 case MO_UW: 1764 tcg_out_insn(s, RXY, LLGH, data, h.base, h.index, h.disp); 1765 break; 1766 1767 case MO_SW | MO_BSWAP: 1768 /* swapped sign-extended halfword load */ 1769 tcg_out_insn(s, RXY, LRVH, data, h.base, h.index, h.disp); 1770 tcg_out_ext16s(s, TCG_TYPE_REG, data, data); 1771 break; 1772 case MO_SW: 1773 tcg_out_insn(s, RXY, LGH, data, h.base, h.index, h.disp); 1774 break; 1775 1776 case MO_UL | MO_BSWAP: 1777 /* swapped unsigned int load with upper bits zeroed */ 1778 tcg_out_insn(s, RXY, LRV, data, h.base, h.index, h.disp); 1779 tcg_out_ext32u(s, data, data); 1780 break; 1781 case MO_UL: 1782 tcg_out_insn(s, RXY, LLGF, data, h.base, h.index, h.disp); 1783 break; 1784 1785 case MO_SL | MO_BSWAP: 1786 /* swapped sign-extended int load */ 1787 tcg_out_insn(s, RXY, LRV, data, h.base, h.index, h.disp); 1788 tcg_out_ext32s(s, data, data); 1789 break; 1790 case MO_SL: 1791 tcg_out_insn(s, RXY, LGF, data, h.base, h.index, h.disp); 1792 break; 1793 1794 case MO_UQ | MO_BSWAP: 1795 tcg_out_insn(s, RXY, LRVG, data, h.base, h.index, h.disp); 1796 break; 1797 case MO_UQ: 1798 tcg_out_insn(s, RXY, LG, data, h.base, h.index, h.disp); 1799 break; 1800 1801 default: 1802 g_assert_not_reached(); 1803 } 1804} 1805 1806static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg data, 1807 HostAddress h) 1808{ 1809 switch (opc & (MO_SIZE | MO_BSWAP)) { 1810 case MO_UB: 1811 if (h.disp >= 0 && h.disp < 0x1000) { 1812 tcg_out_insn(s, RX, STC, data, h.base, h.index, h.disp); 1813 } else { 1814 tcg_out_insn(s, RXY, STCY, data, h.base, h.index, h.disp); 1815 } 1816 break; 1817 1818 case MO_UW | MO_BSWAP: 1819 tcg_out_insn(s, RXY, STRVH, data, h.base, h.index, h.disp); 1820 break; 1821 case MO_UW: 1822 if (h.disp >= 0 && h.disp < 0x1000) { 1823 tcg_out_insn(s, RX, STH, data, h.base, h.index, h.disp); 1824 } else { 1825 tcg_out_insn(s, RXY, STHY, data, h.base, h.index, h.disp); 1826 } 1827 break; 1828 1829 case MO_UL | MO_BSWAP: 1830 tcg_out_insn(s, RXY, STRV, data, h.base, h.index, h.disp); 1831 break; 1832 case MO_UL: 1833 if (h.disp >= 0 && h.disp < 0x1000) { 1834 tcg_out_insn(s, RX, ST, data, h.base, h.index, h.disp); 1835 } else { 1836 tcg_out_insn(s, RXY, STY, data, h.base, h.index, h.disp); 1837 } 1838 break; 1839 1840 case MO_UQ | MO_BSWAP: 1841 tcg_out_insn(s, RXY, STRVG, data, h.base, h.index, h.disp); 1842 break; 1843 case MO_UQ: 1844 tcg_out_insn(s, RXY, STG, data, h.base, h.index, h.disp); 1845 break; 1846 1847 default: 1848 g_assert_not_reached(); 1849 } 1850} 1851 1852static const TCGLdstHelperParam ldst_helper_param = { 1853 .ntmp = 1, .tmp = { TCG_TMP0 } 1854}; 1855 1856static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1857{ 1858 MemOp opc = get_memop(lb->oi); 1859 1860 if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL, 1861 (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 2)) { 1862 return false; 1863 } 1864 1865 tcg_out_ld_helper_args(s, lb, &ldst_helper_param); 1866 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE]); 1867 tcg_out_ld_helper_ret(s, lb, false, &ldst_helper_param); 1868 1869 tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr); 1870 return true; 1871} 1872 1873static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1874{ 1875 MemOp opc = get_memop(lb->oi); 1876 1877 if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL, 1878 (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 2)) { 1879 return false; 1880 } 1881 1882 tcg_out_st_helper_args(s, lb, &ldst_helper_param); 1883 tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE]); 1884 1885 tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr); 1886 return true; 1887} 1888 1889/* We're expecting to use a 20-bit negative offset on the tlb memory ops. */ 1890#define MIN_TLB_MASK_TABLE_OFS -(1 << 19) 1891 1892/* 1893 * For system-mode, perform the TLB load and compare. 1894 * For user-mode, perform any required alignment tests. 1895 * In both cases, return a TCGLabelQemuLdst structure if the slow path 1896 * is required and fill in @h with the host address for the fast path. 1897 */ 1898static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 1899 TCGReg addr_reg, MemOpIdx oi, 1900 bool is_ld) 1901{ 1902 TCGType addr_type = s->addr_type; 1903 TCGLabelQemuLdst *ldst = NULL; 1904 MemOp opc = get_memop(oi); 1905 MemOp s_bits = opc & MO_SIZE; 1906 unsigned a_mask; 1907 1908 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, s_bits == MO_128); 1909 a_mask = (1 << h->aa.align) - 1; 1910 1911 if (tcg_use_softmmu) { 1912 unsigned s_mask = (1 << s_bits) - 1; 1913 int mem_index = get_mmuidx(oi); 1914 int fast_off = tlb_mask_table_ofs(s, mem_index); 1915 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); 1916 int table_off = fast_off + offsetof(CPUTLBDescFast, table); 1917 int ofs, a_off; 1918 uint64_t tlb_mask; 1919 1920 ldst = new_ldst_label(s); 1921 ldst->is_ld = is_ld; 1922 ldst->oi = oi; 1923 ldst->addr_reg = addr_reg; 1924 1925 tcg_out_sh64(s, RSY_SRLG, TCG_TMP0, addr_reg, TCG_REG_NONE, 1926 s->page_bits - CPU_TLB_ENTRY_BITS); 1927 1928 tcg_out_insn(s, RXY, NG, TCG_TMP0, TCG_AREG0, TCG_REG_NONE, mask_off); 1929 tcg_out_insn(s, RXY, AG, TCG_TMP0, TCG_AREG0, TCG_REG_NONE, table_off); 1930 1931 /* 1932 * For aligned accesses, we check the first byte and include the 1933 * alignment bits within the address. For unaligned access, we 1934 * check that we don't cross pages using the address of the last 1935 * byte of the access. 1936 */ 1937 a_off = (a_mask >= s_mask ? 0 : s_mask - a_mask); 1938 tlb_mask = (uint64_t)s->page_mask | a_mask; 1939 if (a_off == 0) { 1940 tgen_andi_risbg(s, TCG_REG_R0, addr_reg, tlb_mask); 1941 } else { 1942 tcg_out_insn(s, RX, LA, TCG_REG_R0, addr_reg, TCG_REG_NONE, a_off); 1943 tgen_andi(s, addr_type, TCG_REG_R0, tlb_mask); 1944 } 1945 1946 if (is_ld) { 1947 ofs = offsetof(CPUTLBEntry, addr_read); 1948 } else { 1949 ofs = offsetof(CPUTLBEntry, addr_write); 1950 } 1951 if (addr_type == TCG_TYPE_I32) { 1952 ofs += HOST_BIG_ENDIAN * 4; 1953 tcg_out_insn(s, RX, C, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs); 1954 } else { 1955 tcg_out_insn(s, RXY, CG, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs); 1956 } 1957 1958 tcg_out16(s, RI_BRC | (S390_CC_NE << 4)); 1959 ldst->label_ptr[0] = s->code_ptr++; 1960 1961 h->index = TCG_TMP0; 1962 tcg_out_insn(s, RXY, LG, h->index, TCG_TMP0, TCG_REG_NONE, 1963 offsetof(CPUTLBEntry, addend)); 1964 1965 if (addr_type == TCG_TYPE_I32) { 1966 tcg_out_insn(s, RRE, ALGFR, h->index, addr_reg); 1967 h->base = TCG_REG_NONE; 1968 } else { 1969 h->base = addr_reg; 1970 } 1971 h->disp = 0; 1972 } else { 1973 if (a_mask) { 1974 ldst = new_ldst_label(s); 1975 ldst->is_ld = is_ld; 1976 ldst->oi = oi; 1977 ldst->addr_reg = addr_reg; 1978 1979 tcg_debug_assert(a_mask <= 0xffff); 1980 tcg_out_insn(s, RI, TMLL, addr_reg, a_mask); 1981 1982 tcg_out16(s, RI_BRC | (S390_TM_NE << 4)); 1983 ldst->label_ptr[0] = s->code_ptr++; 1984 } 1985 1986 h->base = addr_reg; 1987 if (addr_type == TCG_TYPE_I32) { 1988 tcg_out_ext32u(s, TCG_TMP0, addr_reg); 1989 h->base = TCG_TMP0; 1990 } 1991 if (guest_base < 0x80000) { 1992 h->index = TCG_REG_NONE; 1993 h->disp = guest_base; 1994 } else { 1995 h->index = TCG_GUEST_BASE_REG; 1996 h->disp = 0; 1997 } 1998 } 1999 2000 return ldst; 2001} 2002 2003static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_reg, 2004 MemOpIdx oi, TCGType data_type) 2005{ 2006 TCGLabelQemuLdst *ldst; 2007 HostAddress h; 2008 2009 ldst = prepare_host_addr(s, &h, addr_reg, oi, true); 2010 tcg_out_qemu_ld_direct(s, get_memop(oi), data_reg, h); 2011 2012 if (ldst) { 2013 ldst->type = data_type; 2014 ldst->datalo_reg = data_reg; 2015 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 2016 } 2017} 2018 2019static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_reg, 2020 MemOpIdx oi, TCGType data_type) 2021{ 2022 TCGLabelQemuLdst *ldst; 2023 HostAddress h; 2024 2025 ldst = prepare_host_addr(s, &h, addr_reg, oi, false); 2026 tcg_out_qemu_st_direct(s, get_memop(oi), data_reg, h); 2027 2028 if (ldst) { 2029 ldst->type = data_type; 2030 ldst->datalo_reg = data_reg; 2031 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 2032 } 2033} 2034 2035static void tcg_out_qemu_ldst_i128(TCGContext *s, TCGReg datalo, TCGReg datahi, 2036 TCGReg addr_reg, MemOpIdx oi, bool is_ld) 2037{ 2038 TCGLabel *l1 = NULL, *l2 = NULL; 2039 TCGLabelQemuLdst *ldst; 2040 HostAddress h; 2041 bool need_bswap; 2042 bool use_pair; 2043 S390Opcode insn; 2044 2045 ldst = prepare_host_addr(s, &h, addr_reg, oi, is_ld); 2046 2047 use_pair = h.aa.atom < MO_128; 2048 need_bswap = get_memop(oi) & MO_BSWAP; 2049 2050 if (!use_pair) { 2051 /* 2052 * Atomicity requires we use LPQ. If we've already checked for 2053 * 16-byte alignment, that's all we need. If we arrive with 2054 * lesser alignment, we have determined that less than 16-byte 2055 * alignment can be satisfied with two 8-byte loads. 2056 */ 2057 if (h.aa.align < MO_128) { 2058 use_pair = true; 2059 l1 = gen_new_label(); 2060 l2 = gen_new_label(); 2061 2062 tcg_out_insn(s, RI, TMLL, addr_reg, 15); 2063 tgen_branch(s, S390_TM_NE, l1); 2064 } 2065 2066 tcg_debug_assert(!need_bswap); 2067 tcg_debug_assert(datalo & 1); 2068 tcg_debug_assert(datahi == datalo - 1); 2069 insn = is_ld ? RXY_LPQ : RXY_STPQ; 2070 tcg_out_insn_RXY(s, insn, datahi, h.base, h.index, h.disp); 2071 2072 if (use_pair) { 2073 tgen_branch(s, S390_CC_ALWAYS, l2); 2074 tcg_out_label(s, l1); 2075 } 2076 } 2077 if (use_pair) { 2078 TCGReg d1, d2; 2079 2080 if (need_bswap) { 2081 d1 = datalo, d2 = datahi; 2082 insn = is_ld ? RXY_LRVG : RXY_STRVG; 2083 } else { 2084 d1 = datahi, d2 = datalo; 2085 insn = is_ld ? RXY_LG : RXY_STG; 2086 } 2087 2088 if (h.base == d1 || h.index == d1) { 2089 tcg_out_insn(s, RXY, LAY, TCG_TMP0, h.base, h.index, h.disp); 2090 h.base = TCG_TMP0; 2091 h.index = TCG_REG_NONE; 2092 h.disp = 0; 2093 } 2094 tcg_out_insn_RXY(s, insn, d1, h.base, h.index, h.disp); 2095 tcg_out_insn_RXY(s, insn, d2, h.base, h.index, h.disp + 8); 2096 } 2097 if (l2) { 2098 tcg_out_label(s, l2); 2099 } 2100 2101 if (ldst) { 2102 ldst->type = TCG_TYPE_I128; 2103 ldst->datalo_reg = datalo; 2104 ldst->datahi_reg = datahi; 2105 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 2106 } 2107} 2108 2109static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) 2110{ 2111 /* Reuse the zeroing that exists for goto_ptr. */ 2112 if (a0 == 0) { 2113 tgen_gotoi(s, S390_CC_ALWAYS, tcg_code_gen_epilogue); 2114 } else { 2115 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, a0); 2116 tgen_gotoi(s, S390_CC_ALWAYS, tb_ret_addr); 2117 } 2118} 2119 2120static void tcg_out_goto_tb(TCGContext *s, int which) 2121{ 2122 /* 2123 * Branch displacement must be aligned for atomic patching; 2124 * see if we need to add extra nop before branch 2125 */ 2126 if (!QEMU_PTR_IS_ALIGNED(s->code_ptr + 1, 4)) { 2127 tcg_out16(s, NOP); 2128 } 2129 tcg_out16(s, RIL_BRCL | (S390_CC_ALWAYS << 4)); 2130 set_jmp_insn_offset(s, which); 2131 s->code_ptr += 2; 2132 set_jmp_reset_offset(s, which); 2133} 2134 2135void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 2136 uintptr_t jmp_rx, uintptr_t jmp_rw) 2137{ 2138 if (!HAVE_FACILITY(GEN_INST_EXT)) { 2139 return; 2140 } 2141 /* patch the branch destination */ 2142 uintptr_t addr = tb->jmp_target_addr[n]; 2143 intptr_t disp = addr - (jmp_rx - 2); 2144 qatomic_set((int32_t *)jmp_rw, disp / 2); 2145 /* no need to flush icache explicitly */ 2146} 2147 2148 2149static void tgen_add(TCGContext *s, TCGType type, 2150 TCGReg a0, TCGReg a1, TCGReg a2) 2151{ 2152 if (a0 != a1) { 2153 tcg_out_insn(s, RX, LA, a0, a1, a2, 0); 2154 } else if (type == TCG_TYPE_I32) { 2155 tcg_out_insn(s, RR, AR, a0, a2); 2156 } else { 2157 tcg_out_insn(s, RRE, AGR, a0, a2); 2158 } 2159} 2160 2161static void tgen_addi(TCGContext *s, TCGType type, 2162 TCGReg a0, TCGReg a1, tcg_target_long a2) 2163{ 2164 if (a0 == a1) { 2165 if (type == TCG_TYPE_I32) { 2166 if (a2 == (int16_t)a2) { 2167 tcg_out_insn(s, RI, AHI, a0, a2); 2168 } else { 2169 tcg_out_insn(s, RIL, AFI, a0, a2); 2170 } 2171 return; 2172 } 2173 if (a2 == (int16_t)a2) { 2174 tcg_out_insn(s, RI, AGHI, a0, a2); 2175 return; 2176 } 2177 if (a2 == (int32_t)a2) { 2178 tcg_out_insn(s, RIL, AGFI, a0, a2); 2179 return; 2180 } 2181 if (a2 == (uint32_t)a2) { 2182 tcg_out_insn(s, RIL, ALGFI, a0, a2); 2183 return; 2184 } 2185 if (-a2 == (uint32_t)-a2) { 2186 tcg_out_insn(s, RIL, SLGFI, a0, -a2); 2187 return; 2188 } 2189 } 2190 tcg_out_mem(s, RX_LA, RXY_LAY, a0, a1, TCG_REG_NONE, a2); 2191} 2192 2193static const TCGOutOpBinary outop_add = { 2194 .base.static_constraint = C_O1_I2(r, r, ri), 2195 .out_rrr = tgen_add, 2196 .out_rri = tgen_addi, 2197}; 2198 2199static void tgen_and(TCGContext *s, TCGType type, 2200 TCGReg a0, TCGReg a1, TCGReg a2) 2201{ 2202 if (type != TCG_TYPE_I32) { 2203 tcg_out_insn(s, RRFa, NGRK, a0, a1, a2); 2204 } else if (a0 == a1) { 2205 tcg_out_insn(s, RR, NR, a0, a2); 2206 } else { 2207 tcg_out_insn(s, RRFa, NRK, a0, a1, a2); 2208 } 2209} 2210 2211static void tgen_andi_3(TCGContext *s, TCGType type, 2212 TCGReg a0, TCGReg a1, tcg_target_long a2) 2213{ 2214 tcg_out_mov(s, type, a0, a1); 2215 tgen_andi(s, type, a0, a2); 2216} 2217 2218static const TCGOutOpBinary outop_and = { 2219 .base.static_constraint = C_O1_I2(r, r, rNKR), 2220 .out_rrr = tgen_and, 2221 .out_rri = tgen_andi_3, 2222}; 2223 2224static void tgen_andc(TCGContext *s, TCGType type, 2225 TCGReg a0, TCGReg a1, TCGReg a2) 2226{ 2227 if (type == TCG_TYPE_I32) { 2228 tcg_out_insn(s, RRFa, NCRK, a0, a1, a2); 2229 } else { 2230 tcg_out_insn(s, RRFa, NCGRK, a0, a1, a2); 2231 } 2232} 2233 2234static TCGConstraintSetIndex cset_misc3_rrr(TCGType type, unsigned flags) 2235{ 2236 return HAVE_FACILITY(MISC_INSN_EXT3) ? C_O1_I2(r, r, r) : C_NotImplemented; 2237} 2238 2239static const TCGOutOpBinary outop_andc = { 2240 .base.static_constraint = C_Dynamic, 2241 .base.dynamic_constraint = cset_misc3_rrr, 2242 .out_rrr = tgen_andc, 2243}; 2244 2245static const TCGOutOpBinary outop_divs = { 2246 .base.static_constraint = C_NotImplemented, 2247}; 2248 2249static void tgen_divs2(TCGContext *s, TCGType type, 2250 TCGReg a0, TCGReg a1, TCGReg a4) 2251{ 2252 tcg_debug_assert((a1 & 1) == 0); 2253 tcg_debug_assert(a0 == a1 + 1); 2254 if (type == TCG_TYPE_I32) { 2255 tcg_out_insn(s, RR, DR, a1, a4); 2256 } else { 2257 /* 2258 * TODO: Move the sign-extend of the numerator from a2 into a3 2259 * into the tcg backend, instead of in early expansion. It is 2260 * required for 32-bit DR, but not 64-bit DSGR. 2261 */ 2262 tcg_out_insn(s, RRE, DSGR, a1, a4); 2263 } 2264} 2265 2266static const TCGOutOpDivRem outop_divs2 = { 2267 .base.static_constraint = C_O2_I3(o, m, 0, 1, r), 2268 .out_rr01r = tgen_divs2, 2269}; 2270 2271static const TCGOutOpBinary outop_divu = { 2272 .base.static_constraint = C_NotImplemented, 2273}; 2274 2275static void tgen_divu2(TCGContext *s, TCGType type, 2276 TCGReg a0, TCGReg a1, TCGReg a4) 2277{ 2278 tcg_debug_assert((a1 & 1) == 0); 2279 tcg_debug_assert(a0 == a1 + 1); 2280 if (type == TCG_TYPE_I32) { 2281 tcg_out_insn(s, RRE, DLR, a1, a4); 2282 } else { 2283 tcg_out_insn(s, RRE, DLGR, a1, a4); 2284 } 2285} 2286 2287static const TCGOutOpDivRem outop_divu2 = { 2288 .base.static_constraint = C_O2_I3(o, m, 0, 1, r), 2289 .out_rr01r = tgen_divu2, 2290}; 2291 2292static void tgen_eqv(TCGContext *s, TCGType type, 2293 TCGReg a0, TCGReg a1, TCGReg a2) 2294{ 2295 if (type == TCG_TYPE_I32) { 2296 tcg_out_insn(s, RRFa, NXRK, a0, a1, a2); 2297 } else { 2298 tcg_out_insn(s, RRFa, NXGRK, a0, a1, a2); 2299 } 2300} 2301 2302static const TCGOutOpBinary outop_eqv = { 2303 .base.static_constraint = C_Dynamic, 2304 .base.dynamic_constraint = cset_misc3_rrr, 2305 .out_rrr = tgen_eqv, 2306}; 2307 2308static void tgen_mul(TCGContext *s, TCGType type, 2309 TCGReg a0, TCGReg a1, TCGReg a2) 2310{ 2311 if (type == TCG_TYPE_I32) { 2312 if (a0 == a1) { 2313 tcg_out_insn(s, RRE, MSR, a0, a2); 2314 } else { 2315 tcg_out_insn(s, RRFa, MSRKC, a0, a1, a2); 2316 } 2317 } else { 2318 if (a0 == a1) { 2319 tcg_out_insn(s, RRE, MSGR, a0, a2); 2320 } else { 2321 tcg_out_insn(s, RRFa, MSGRKC, a0, a1, a2); 2322 } 2323 } 2324} 2325 2326static void tgen_muli(TCGContext *s, TCGType type, 2327 TCGReg a0, TCGReg a1, tcg_target_long a2) 2328{ 2329 tcg_out_mov(s, type, a0, a1); 2330 if (type == TCG_TYPE_I32) { 2331 if (a2 == (int16_t)a2) { 2332 tcg_out_insn(s, RI, MHI, a0, a2); 2333 } else { 2334 tcg_out_insn(s, RIL, MSFI, a0, a2); 2335 } 2336 } else { 2337 if (a2 == (int16_t)a2) { 2338 tcg_out_insn(s, RI, MGHI, a0, a2); 2339 } else { 2340 tcg_out_insn(s, RIL, MSGFI, a0, a2); 2341 } 2342 } 2343} 2344 2345static TCGConstraintSetIndex cset_mul(TCGType type, unsigned flags) 2346{ 2347 return (HAVE_FACILITY(MISC_INSN_EXT2) 2348 ? C_O1_I2(r, r, rJ) 2349 : C_O1_I2(r, 0, rJ)); 2350} 2351 2352static const TCGOutOpBinary outop_mul = { 2353 .base.static_constraint = C_Dynamic, 2354 .base.dynamic_constraint = cset_mul, 2355 .out_rrr = tgen_mul, 2356 .out_rri = tgen_muli, 2357}; 2358 2359static const TCGOutOpBinary outop_mulsh = { 2360 .base.static_constraint = C_NotImplemented, 2361}; 2362 2363static const TCGOutOpBinary outop_muluh = { 2364 .base.static_constraint = C_NotImplemented, 2365}; 2366 2367static void tgen_nand(TCGContext *s, TCGType type, 2368 TCGReg a0, TCGReg a1, TCGReg a2) 2369{ 2370 if (type == TCG_TYPE_I32) { 2371 tcg_out_insn(s, RRFa, NNRK, a0, a1, a2); 2372 } else { 2373 tcg_out_insn(s, RRFa, NNGRK, a0, a1, a2); 2374 } 2375} 2376 2377static const TCGOutOpBinary outop_nand = { 2378 .base.static_constraint = C_Dynamic, 2379 .base.dynamic_constraint = cset_misc3_rrr, 2380 .out_rrr = tgen_nand, 2381}; 2382 2383static void tgen_nor(TCGContext *s, TCGType type, 2384 TCGReg a0, TCGReg a1, TCGReg a2) 2385{ 2386 if (type == TCG_TYPE_I32) { 2387 tcg_out_insn(s, RRFa, NORK, a0, a1, a2); 2388 } else { 2389 tcg_out_insn(s, RRFa, NOGRK, a0, a1, a2); 2390 } 2391} 2392 2393static const TCGOutOpBinary outop_nor = { 2394 .base.static_constraint = C_Dynamic, 2395 .base.dynamic_constraint = cset_misc3_rrr, 2396 .out_rrr = tgen_nor, 2397}; 2398 2399static void tgen_or(TCGContext *s, TCGType type, 2400 TCGReg a0, TCGReg a1, TCGReg a2) 2401{ 2402 if (type != TCG_TYPE_I32) { 2403 tcg_out_insn(s, RRFa, OGRK, a0, a1, a2); 2404 } else if (a0 == a1) { 2405 tcg_out_insn(s, RR, OR, a0, a2); 2406 } else { 2407 tcg_out_insn(s, RRFa, ORK, a0, a1, a2); 2408 } 2409} 2410 2411static void tgen_ori_3(TCGContext *s, TCGType type, 2412 TCGReg a0, TCGReg a1, tcg_target_long a2) 2413{ 2414 tcg_out_mov(s, type, a0, a1); 2415 tgen_ori(s, a0, type == TCG_TYPE_I32 ? (uint32_t)a2 : a2); 2416} 2417 2418static const TCGOutOpBinary outop_or = { 2419 .base.static_constraint = C_O1_I2(r, r, rK), 2420 .out_rrr = tgen_or, 2421 .out_rri = tgen_ori_3, 2422}; 2423 2424static void tgen_orc(TCGContext *s, TCGType type, 2425 TCGReg a0, TCGReg a1, TCGReg a2) 2426{ 2427 if (type == TCG_TYPE_I32) { 2428 tcg_out_insn(s, RRFa, OCRK, a0, a1, a2); 2429 } else { 2430 tcg_out_insn(s, RRFa, OCGRK, a0, a1, a2); 2431 } 2432} 2433 2434static const TCGOutOpBinary outop_orc = { 2435 .base.static_constraint = C_Dynamic, 2436 .base.dynamic_constraint = cset_misc3_rrr, 2437 .out_rrr = tgen_orc, 2438}; 2439 2440static const TCGOutOpBinary outop_rems = { 2441 .base.static_constraint = C_NotImplemented, 2442}; 2443 2444static void tgen_sub(TCGContext *s, TCGType type, 2445 TCGReg a0, TCGReg a1, TCGReg a2) 2446{ 2447 if (type != TCG_TYPE_I32) { 2448 tcg_out_insn(s, RRFa, SGRK, a0, a1, a2); 2449 } else if (a0 == a1) { 2450 tcg_out_insn(s, RR, SR, a0, a2); 2451 } else { 2452 tcg_out_insn(s, RRFa, SRK, a0, a1, a2); 2453 } 2454} 2455 2456static const TCGOutOpSubtract outop_sub = { 2457 .base.static_constraint = C_O1_I2(r, r, r), 2458 .out_rrr = tgen_sub, 2459}; 2460 2461static void tgen_xor(TCGContext *s, TCGType type, 2462 TCGReg a0, TCGReg a1, TCGReg a2) 2463{ 2464 if (type != TCG_TYPE_I32) { 2465 tcg_out_insn(s, RRFa, XGRK, a0, a1, a2); 2466 } else if (a0 == a1) { 2467 tcg_out_insn(s, RR, XR, a0, a2); 2468 } else { 2469 tcg_out_insn(s, RRFa, XRK, a0, a1, a2); 2470 } 2471} 2472 2473static void tgen_xori_3(TCGContext *s, TCGType type, 2474 TCGReg a0, TCGReg a1, tcg_target_long a2) 2475{ 2476 tcg_out_mov(s, type, a0, a1); 2477 tgen_xori(s, a0, type == TCG_TYPE_I32 ? (uint32_t)a2 : a2); 2478} 2479 2480static const TCGOutOpBinary outop_xor = { 2481 .base.static_constraint = C_O1_I2(r, r, rK), 2482 .out_rrr = tgen_xor, 2483 .out_rri = tgen_xori_3, 2484}; 2485 2486static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2487{ 2488 if (type == TCG_TYPE_I32) { 2489 tcg_out_insn(s, RR, LCR, a0, a1); 2490 } else { 2491 tcg_out_insn(s, RRE, LCGR, a0, a1); 2492 } 2493} 2494 2495static const TCGOutOpUnary outop_neg = { 2496 .base.static_constraint = C_O1_I1(r, r), 2497 .out_rr = tgen_neg, 2498}; 2499 2500static void tgen_not(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2501{ 2502 tgen_nor(s, type, a0, a1, a1); 2503} 2504 2505static TCGConstraintSetIndex cset_not(TCGType type, unsigned flags) 2506{ 2507 return HAVE_FACILITY(MISC_INSN_EXT3) ? C_O1_I1(r, r) : C_NotImplemented; 2508} 2509 2510static const TCGOutOpUnary outop_not = { 2511 .base.static_constraint = C_Dynamic, 2512 .base.dynamic_constraint = cset_not, 2513 .out_rr = tgen_not, 2514}; 2515 2516 2517# define OP_32_64(x) \ 2518 case glue(glue(INDEX_op_,x),_i32): \ 2519 case glue(glue(INDEX_op_,x),_i64) 2520 2521static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, 2522 const TCGArg args[TCG_MAX_OP_ARGS], 2523 const int const_args[TCG_MAX_OP_ARGS]) 2524{ 2525 S390Opcode op, op2; 2526 TCGArg a0, a1, a2; 2527 2528 switch (opc) { 2529 case INDEX_op_goto_ptr: 2530 a0 = args[0]; 2531 tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, a0); 2532 break; 2533 2534 OP_32_64(ld8u): 2535 /* ??? LLC (RXY format) is only present with the extended-immediate 2536 facility, whereas LLGC is always present. */ 2537 tcg_out_mem(s, 0, RXY_LLGC, args[0], args[1], TCG_REG_NONE, args[2]); 2538 break; 2539 2540 OP_32_64(ld8s): 2541 /* ??? LB is no smaller than LGB, so no point to using it. */ 2542 tcg_out_mem(s, 0, RXY_LGB, args[0], args[1], TCG_REG_NONE, args[2]); 2543 break; 2544 2545 OP_32_64(ld16u): 2546 /* ??? LLH (RXY format) is only present with the extended-immediate 2547 facility, whereas LLGH is always present. */ 2548 tcg_out_mem(s, 0, RXY_LLGH, args[0], args[1], TCG_REG_NONE, args[2]); 2549 break; 2550 2551 case INDEX_op_ld16s_i32: 2552 tcg_out_mem(s, RX_LH, RXY_LHY, args[0], args[1], TCG_REG_NONE, args[2]); 2553 break; 2554 2555 case INDEX_op_ld_i32: 2556 tcg_out_ld(s, TCG_TYPE_I32, args[0], args[1], args[2]); 2557 break; 2558 2559 OP_32_64(st8): 2560 tcg_out_mem(s, RX_STC, RXY_STCY, args[0], args[1], 2561 TCG_REG_NONE, args[2]); 2562 break; 2563 2564 OP_32_64(st16): 2565 tcg_out_mem(s, RX_STH, RXY_STHY, args[0], args[1], 2566 TCG_REG_NONE, args[2]); 2567 break; 2568 2569 case INDEX_op_st_i32: 2570 tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]); 2571 break; 2572 2573 case INDEX_op_shl_i32: 2574 op = RS_SLL; 2575 op2 = RSY_SLLK; 2576 do_shift32: 2577 a0 = args[0], a1 = args[1], a2 = (int32_t)args[2]; 2578 if (a0 == a1) { 2579 if (const_args[2]) { 2580 tcg_out_sh32(s, op, a0, TCG_REG_NONE, a2); 2581 } else { 2582 tcg_out_sh32(s, op, a0, a2, 0); 2583 } 2584 } else { 2585 /* Using tcg_out_sh64 here for the format; it is a 32-bit shift. */ 2586 if (const_args[2]) { 2587 tcg_out_sh64(s, op2, a0, a1, TCG_REG_NONE, a2); 2588 } else { 2589 tcg_out_sh64(s, op2, a0, a1, a2, 0); 2590 } 2591 } 2592 break; 2593 case INDEX_op_shr_i32: 2594 op = RS_SRL; 2595 op2 = RSY_SRLK; 2596 goto do_shift32; 2597 case INDEX_op_sar_i32: 2598 op = RS_SRA; 2599 op2 = RSY_SRAK; 2600 goto do_shift32; 2601 2602 case INDEX_op_rotl_i32: 2603 /* ??? Using tcg_out_sh64 here for the format; it is a 32-bit rol. */ 2604 if (const_args[2]) { 2605 tcg_out_sh64(s, RSY_RLL, args[0], args[1], TCG_REG_NONE, args[2]); 2606 } else { 2607 tcg_out_sh64(s, RSY_RLL, args[0], args[1], args[2], 0); 2608 } 2609 break; 2610 case INDEX_op_rotr_i32: 2611 if (const_args[2]) { 2612 tcg_out_sh64(s, RSY_RLL, args[0], args[1], 2613 TCG_REG_NONE, (32 - args[2]) & 31); 2614 } else { 2615 tcg_out_insn(s, RR, LCR, TCG_TMP0, args[2]); 2616 tcg_out_sh64(s, RSY_RLL, args[0], args[1], TCG_TMP0, 0); 2617 } 2618 break; 2619 2620 case INDEX_op_bswap16_i32: 2621 a0 = args[0], a1 = args[1], a2 = args[2]; 2622 tcg_out_insn(s, RRE, LRVR, a0, a1); 2623 if (a2 & TCG_BSWAP_OS) { 2624 tcg_out_sh32(s, RS_SRA, a0, TCG_REG_NONE, 16); 2625 } else { 2626 tcg_out_sh32(s, RS_SRL, a0, TCG_REG_NONE, 16); 2627 } 2628 break; 2629 case INDEX_op_bswap16_i64: 2630 a0 = args[0], a1 = args[1], a2 = args[2]; 2631 tcg_out_insn(s, RRE, LRVGR, a0, a1); 2632 if (a2 & TCG_BSWAP_OS) { 2633 tcg_out_sh64(s, RSY_SRAG, a0, a0, TCG_REG_NONE, 48); 2634 } else { 2635 tcg_out_sh64(s, RSY_SRLG, a0, a0, TCG_REG_NONE, 48); 2636 } 2637 break; 2638 2639 case INDEX_op_bswap32_i32: 2640 tcg_out_insn(s, RRE, LRVR, args[0], args[1]); 2641 break; 2642 case INDEX_op_bswap32_i64: 2643 a0 = args[0], a1 = args[1], a2 = args[2]; 2644 tcg_out_insn(s, RRE, LRVR, a0, a1); 2645 if (a2 & TCG_BSWAP_OS) { 2646 tcg_out_ext32s(s, a0, a0); 2647 } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 2648 tcg_out_ext32u(s, a0, a0); 2649 } 2650 break; 2651 2652 case INDEX_op_add2_i32: 2653 if (const_args[4]) { 2654 tcg_out_insn(s, RIL, ALFI, args[0], args[4]); 2655 } else { 2656 tcg_out_insn(s, RR, ALR, args[0], args[4]); 2657 } 2658 tcg_out_insn(s, RRE, ALCR, args[1], args[5]); 2659 break; 2660 case INDEX_op_sub2_i32: 2661 if (const_args[4]) { 2662 tcg_out_insn(s, RIL, SLFI, args[0], args[4]); 2663 } else { 2664 tcg_out_insn(s, RR, SLR, args[0], args[4]); 2665 } 2666 tcg_out_insn(s, RRE, SLBR, args[1], args[5]); 2667 break; 2668 2669 case INDEX_op_br: 2670 tgen_branch(s, S390_CC_ALWAYS, arg_label(args[0])); 2671 break; 2672 2673 case INDEX_op_brcond_i32: 2674 tgen_brcond(s, TCG_TYPE_I32, args[2], args[0], 2675 args[1], const_args[1], arg_label(args[3])); 2676 break; 2677 case INDEX_op_setcond_i32: 2678 tgen_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], 2679 args[2], const_args[2], false); 2680 break; 2681 case INDEX_op_negsetcond_i32: 2682 tgen_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], 2683 args[2], const_args[2], true); 2684 break; 2685 case INDEX_op_movcond_i32: 2686 tgen_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], 2687 args[2], const_args[2], args[3], const_args[3], args[4]); 2688 break; 2689 2690 case INDEX_op_qemu_ld_i32: 2691 tcg_out_qemu_ld(s, args[0], args[1], args[2], TCG_TYPE_I32); 2692 break; 2693 case INDEX_op_qemu_ld_i64: 2694 tcg_out_qemu_ld(s, args[0], args[1], args[2], TCG_TYPE_I64); 2695 break; 2696 case INDEX_op_qemu_st_i32: 2697 tcg_out_qemu_st(s, args[0], args[1], args[2], TCG_TYPE_I32); 2698 break; 2699 case INDEX_op_qemu_st_i64: 2700 tcg_out_qemu_st(s, args[0], args[1], args[2], TCG_TYPE_I64); 2701 break; 2702 case INDEX_op_qemu_ld_i128: 2703 tcg_out_qemu_ldst_i128(s, args[0], args[1], args[2], args[3], true); 2704 break; 2705 case INDEX_op_qemu_st_i128: 2706 tcg_out_qemu_ldst_i128(s, args[0], args[1], args[2], args[3], false); 2707 break; 2708 2709 case INDEX_op_ld16s_i64: 2710 tcg_out_mem(s, 0, RXY_LGH, args[0], args[1], TCG_REG_NONE, args[2]); 2711 break; 2712 case INDEX_op_ld32u_i64: 2713 tcg_out_mem(s, 0, RXY_LLGF, args[0], args[1], TCG_REG_NONE, args[2]); 2714 break; 2715 case INDEX_op_ld32s_i64: 2716 tcg_out_mem(s, 0, RXY_LGF, args[0], args[1], TCG_REG_NONE, args[2]); 2717 break; 2718 case INDEX_op_ld_i64: 2719 tcg_out_ld(s, TCG_TYPE_I64, args[0], args[1], args[2]); 2720 break; 2721 2722 case INDEX_op_st32_i64: 2723 tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]); 2724 break; 2725 case INDEX_op_st_i64: 2726 tcg_out_st(s, TCG_TYPE_I64, args[0], args[1], args[2]); 2727 break; 2728 2729 case INDEX_op_bswap64_i64: 2730 tcg_out_insn(s, RRE, LRVGR, args[0], args[1]); 2731 break; 2732 2733 case INDEX_op_mulu2_i64: 2734 tcg_debug_assert(args[0] == args[2]); 2735 tcg_debug_assert((args[1] & 1) == 0); 2736 tcg_debug_assert(args[0] == args[1] + 1); 2737 tcg_out_insn(s, RRE, MLGR, args[1], args[3]); 2738 break; 2739 case INDEX_op_muls2_i64: 2740 tcg_debug_assert((args[1] & 1) == 0); 2741 tcg_debug_assert(args[0] == args[1] + 1); 2742 tcg_out_insn(s, RRFa, MGRK, args[1], args[2], args[3]); 2743 break; 2744 2745 case INDEX_op_shl_i64: 2746 op = RSY_SLLG; 2747 do_shift64: 2748 if (const_args[2]) { 2749 tcg_out_sh64(s, op, args[0], args[1], TCG_REG_NONE, args[2]); 2750 } else { 2751 tcg_out_sh64(s, op, args[0], args[1], args[2], 0); 2752 } 2753 break; 2754 case INDEX_op_shr_i64: 2755 op = RSY_SRLG; 2756 goto do_shift64; 2757 case INDEX_op_sar_i64: 2758 op = RSY_SRAG; 2759 goto do_shift64; 2760 2761 case INDEX_op_rotl_i64: 2762 if (const_args[2]) { 2763 tcg_out_sh64(s, RSY_RLLG, args[0], args[1], 2764 TCG_REG_NONE, args[2]); 2765 } else { 2766 tcg_out_sh64(s, RSY_RLLG, args[0], args[1], args[2], 0); 2767 } 2768 break; 2769 case INDEX_op_rotr_i64: 2770 if (const_args[2]) { 2771 tcg_out_sh64(s, RSY_RLLG, args[0], args[1], 2772 TCG_REG_NONE, (64 - args[2]) & 63); 2773 } else { 2774 /* We can use the smaller 32-bit negate because only the 2775 low 6 bits are examined for the rotate. */ 2776 tcg_out_insn(s, RR, LCR, TCG_TMP0, args[2]); 2777 tcg_out_sh64(s, RSY_RLLG, args[0], args[1], TCG_TMP0, 0); 2778 } 2779 break; 2780 2781 case INDEX_op_add2_i64: 2782 if (const_args[4]) { 2783 if ((int64_t)args[4] >= 0) { 2784 tcg_out_insn(s, RIL, ALGFI, args[0], args[4]); 2785 } else { 2786 tcg_out_insn(s, RIL, SLGFI, args[0], -args[4]); 2787 } 2788 } else { 2789 tcg_out_insn(s, RRE, ALGR, args[0], args[4]); 2790 } 2791 tcg_out_insn(s, RRE, ALCGR, args[1], args[5]); 2792 break; 2793 case INDEX_op_sub2_i64: 2794 if (const_args[4]) { 2795 if ((int64_t)args[4] >= 0) { 2796 tcg_out_insn(s, RIL, SLGFI, args[0], args[4]); 2797 } else { 2798 tcg_out_insn(s, RIL, ALGFI, args[0], -args[4]); 2799 } 2800 } else { 2801 tcg_out_insn(s, RRE, SLGR, args[0], args[4]); 2802 } 2803 tcg_out_insn(s, RRE, SLBGR, args[1], args[5]); 2804 break; 2805 2806 case INDEX_op_brcond_i64: 2807 tgen_brcond(s, TCG_TYPE_I64, args[2], args[0], 2808 args[1], const_args[1], arg_label(args[3])); 2809 break; 2810 case INDEX_op_setcond_i64: 2811 tgen_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], 2812 args[2], const_args[2], false); 2813 break; 2814 case INDEX_op_negsetcond_i64: 2815 tgen_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], 2816 args[2], const_args[2], true); 2817 break; 2818 case INDEX_op_movcond_i64: 2819 tgen_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], 2820 args[2], const_args[2], args[3], const_args[3], args[4]); 2821 break; 2822 2823 OP_32_64(deposit): 2824 a0 = args[0], a1 = args[1], a2 = args[2]; 2825 if (const_args[1]) { 2826 tgen_deposit(s, a0, a2, args[3], args[4], 1); 2827 } else { 2828 /* Since we can't support "0Z" as a constraint, we allow a1 in 2829 any register. Fix things up as if a matching constraint. */ 2830 if (a0 != a1) { 2831 if (a0 == a2) { 2832 tcg_out_mov(s, type, TCG_TMP0, a2); 2833 a2 = TCG_TMP0; 2834 } 2835 tcg_out_mov(s, type, a0, a1); 2836 } 2837 tgen_deposit(s, a0, a2, args[3], args[4], 0); 2838 } 2839 break; 2840 2841 OP_32_64(extract): 2842 tgen_extract(s, args[0], args[1], args[2], args[3]); 2843 break; 2844 OP_32_64(sextract): 2845 tgen_sextract(s, args[0], args[1], args[2], args[3]); 2846 break; 2847 2848 case INDEX_op_clz_i64: 2849 tgen_clz(s, args[0], args[1], args[2], const_args[2]); 2850 break; 2851 2852 case INDEX_op_ctpop_i32: 2853 tgen_ctpop(s, TCG_TYPE_I32, args[0], args[1]); 2854 break; 2855 case INDEX_op_ctpop_i64: 2856 tgen_ctpop(s, TCG_TYPE_I64, args[0], args[1]); 2857 break; 2858 2859 case INDEX_op_mb: 2860 /* The host memory model is quite strong, we simply need to 2861 serialize the instruction stream. */ 2862 if (args[0] & TCG_MO_ST_LD) { 2863 /* fast-bcr-serialization facility (45) is present */ 2864 tcg_out_insn(s, RR, BCR, 14, 0); 2865 } 2866 break; 2867 2868 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2869 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 2870 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 2871 case INDEX_op_ext_i32_i64: /* Always emitted via tcg_reg_alloc_op. */ 2872 case INDEX_op_extu_i32_i64: 2873 case INDEX_op_extrl_i64_i32: 2874 default: 2875 g_assert_not_reached(); 2876 } 2877} 2878 2879static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 2880 TCGReg dst, TCGReg src) 2881{ 2882 if (is_general_reg(src)) { 2883 /* Replicate general register into two MO_64. */ 2884 tcg_out_insn(s, VRRf, VLVGP, dst, src, src); 2885 if (vece == MO_64) { 2886 return true; 2887 } 2888 src = dst; 2889 } 2890 2891 /* 2892 * Recall that the "standard" integer, within a vector, is the 2893 * rightmost element of the leftmost doubleword, a-la VLLEZ. 2894 */ 2895 tcg_out_insn(s, VRIc, VREP, dst, (8 >> vece) - 1, src, vece); 2896 return true; 2897} 2898 2899static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 2900 TCGReg dst, TCGReg base, intptr_t offset) 2901{ 2902 tcg_out_vrx_mem(s, VRX_VLREP, dst, base, TCG_REG_NONE, offset, vece); 2903 return true; 2904} 2905 2906static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 2907 TCGReg dst, int64_t val) 2908{ 2909 int i, mask, msb, lsb; 2910 2911 /* Look for int16_t elements. */ 2912 if (vece <= MO_16 || 2913 (vece == MO_32 ? (int32_t)val : val) == (int16_t)val) { 2914 tcg_out_insn(s, VRIa, VREPI, dst, val, vece); 2915 return; 2916 } 2917 2918 /* Look for bit masks. */ 2919 if (vece == MO_32) { 2920 if (risbg_mask((int32_t)val)) { 2921 /* Handle wraparound by swapping msb and lsb. */ 2922 if ((val & 0x80000001u) == 0x80000001u) { 2923 msb = 32 - ctz32(~val); 2924 lsb = clz32(~val) - 1; 2925 } else { 2926 msb = clz32(val); 2927 lsb = 31 - ctz32(val); 2928 } 2929 tcg_out_insn(s, VRIb, VGM, dst, msb, lsb, MO_32); 2930 return; 2931 } 2932 } else { 2933 if (risbg_mask(val)) { 2934 /* Handle wraparound by swapping msb and lsb. */ 2935 if ((val & 0x8000000000000001ull) == 0x8000000000000001ull) { 2936 /* Handle wraparound by swapping msb and lsb. */ 2937 msb = 64 - ctz64(~val); 2938 lsb = clz64(~val) - 1; 2939 } else { 2940 msb = clz64(val); 2941 lsb = 63 - ctz64(val); 2942 } 2943 tcg_out_insn(s, VRIb, VGM, dst, msb, lsb, MO_64); 2944 return; 2945 } 2946 } 2947 2948 /* Look for all bytes 0x00 or 0xff. */ 2949 for (i = mask = 0; i < 8; i++) { 2950 uint8_t byte = val >> (i * 8); 2951 if (byte == 0xff) { 2952 mask |= 1 << i; 2953 } else if (byte != 0) { 2954 break; 2955 } 2956 } 2957 if (i == 8) { 2958 tcg_out_insn(s, VRIa, VGBM, dst, mask * 0x0101, 0); 2959 return; 2960 } 2961 2962 /* Otherwise, stuff it in the constant pool. */ 2963 tcg_out_insn(s, RIL, LARL, TCG_TMP0, 0); 2964 new_pool_label(s, val, R_390_PC32DBL, s->code_ptr - 2, 2); 2965 tcg_out_insn(s, VRX, VLREP, dst, TCG_TMP0, TCG_REG_NONE, 0, MO_64); 2966} 2967 2968static bool tcg_out_cmp_vec_noinv(TCGContext *s, unsigned vece, TCGReg a0, 2969 TCGReg a1, TCGReg a2, TCGCond cond) 2970{ 2971 bool need_swap = false, need_inv = false; 2972 2973 switch (cond) { 2974 case TCG_COND_EQ: 2975 case TCG_COND_GT: 2976 case TCG_COND_GTU: 2977 break; 2978 case TCG_COND_NE: 2979 case TCG_COND_LE: 2980 case TCG_COND_LEU: 2981 need_inv = true; 2982 break; 2983 case TCG_COND_LT: 2984 case TCG_COND_LTU: 2985 need_swap = true; 2986 break; 2987 case TCG_COND_GE: 2988 case TCG_COND_GEU: 2989 need_swap = need_inv = true; 2990 break; 2991 default: 2992 g_assert_not_reached(); 2993 } 2994 2995 if (need_inv) { 2996 cond = tcg_invert_cond(cond); 2997 } 2998 if (need_swap) { 2999 TCGReg swap = a1; 3000 a1 = a2; 3001 a2 = swap; 3002 cond = tcg_swap_cond(cond); 3003 } 3004 3005 switch (cond) { 3006 case TCG_COND_EQ: 3007 tcg_out_insn(s, VRRc, VCEQ, a0, a1, a2, vece); 3008 break; 3009 case TCG_COND_GT: 3010 tcg_out_insn(s, VRRc, VCH, a0, a1, a2, vece); 3011 break; 3012 case TCG_COND_GTU: 3013 tcg_out_insn(s, VRRc, VCHL, a0, a1, a2, vece); 3014 break; 3015 default: 3016 g_assert_not_reached(); 3017 } 3018 return need_inv; 3019} 3020 3021static void tcg_out_cmp_vec(TCGContext *s, unsigned vece, TCGReg a0, 3022 TCGReg a1, TCGReg a2, TCGCond cond) 3023{ 3024 if (tcg_out_cmp_vec_noinv(s, vece, a0, a1, a2, cond)) { 3025 tcg_out_insn(s, VRRc, VNO, a0, a0, a0, 0); 3026 } 3027} 3028 3029static void tcg_out_cmpsel_vec(TCGContext *s, unsigned vece, TCGReg a0, 3030 TCGReg c1, TCGReg c2, TCGArg v3, 3031 int const_v3, TCGReg v4, TCGCond cond) 3032{ 3033 bool inv = tcg_out_cmp_vec_noinv(s, vece, TCG_VEC_TMP0, c1, c2, cond); 3034 3035 if (!const_v3) { 3036 if (inv) { 3037 tcg_out_insn(s, VRRe, VSEL, a0, v4, v3, TCG_VEC_TMP0); 3038 } else { 3039 tcg_out_insn(s, VRRe, VSEL, a0, v3, v4, TCG_VEC_TMP0); 3040 } 3041 } else if (v3) { 3042 if (inv) { 3043 tcg_out_insn(s, VRRc, VOC, a0, v4, TCG_VEC_TMP0, 0); 3044 } else { 3045 tcg_out_insn(s, VRRc, VO, a0, v4, TCG_VEC_TMP0, 0); 3046 } 3047 } else { 3048 if (inv) { 3049 tcg_out_insn(s, VRRc, VN, a0, v4, TCG_VEC_TMP0, 0); 3050 } else { 3051 tcg_out_insn(s, VRRc, VNC, a0, v4, TCG_VEC_TMP0, 0); 3052 } 3053 } 3054} 3055 3056static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 3057 unsigned vecl, unsigned vece, 3058 const TCGArg args[TCG_MAX_OP_ARGS], 3059 const int const_args[TCG_MAX_OP_ARGS]) 3060{ 3061 TCGType type = vecl + TCG_TYPE_V64; 3062 TCGArg a0 = args[0], a1 = args[1], a2 = args[2]; 3063 3064 switch (opc) { 3065 case INDEX_op_ld_vec: 3066 tcg_out_ld(s, type, a0, a1, a2); 3067 break; 3068 case INDEX_op_st_vec: 3069 tcg_out_st(s, type, a0, a1, a2); 3070 break; 3071 case INDEX_op_dupm_vec: 3072 tcg_out_dupm_vec(s, type, vece, a0, a1, a2); 3073 break; 3074 3075 case INDEX_op_abs_vec: 3076 tcg_out_insn(s, VRRa, VLP, a0, a1, vece); 3077 break; 3078 case INDEX_op_neg_vec: 3079 tcg_out_insn(s, VRRa, VLC, a0, a1, vece); 3080 break; 3081 case INDEX_op_not_vec: 3082 tcg_out_insn(s, VRRc, VNO, a0, a1, a1, 0); 3083 break; 3084 3085 case INDEX_op_add_vec: 3086 tcg_out_insn(s, VRRc, VA, a0, a1, a2, vece); 3087 break; 3088 case INDEX_op_sub_vec: 3089 tcg_out_insn(s, VRRc, VS, a0, a1, a2, vece); 3090 break; 3091 case INDEX_op_and_vec: 3092 tcg_out_insn(s, VRRc, VN, a0, a1, a2, 0); 3093 break; 3094 case INDEX_op_andc_vec: 3095 tcg_out_insn(s, VRRc, VNC, a0, a1, a2, 0); 3096 break; 3097 case INDEX_op_mul_vec: 3098 tcg_out_insn(s, VRRc, VML, a0, a1, a2, vece); 3099 break; 3100 case INDEX_op_or_vec: 3101 tcg_out_insn(s, VRRc, VO, a0, a1, a2, 0); 3102 break; 3103 case INDEX_op_orc_vec: 3104 tcg_out_insn(s, VRRc, VOC, a0, a1, a2, 0); 3105 break; 3106 case INDEX_op_xor_vec: 3107 tcg_out_insn(s, VRRc, VX, a0, a1, a2, 0); 3108 break; 3109 case INDEX_op_nand_vec: 3110 tcg_out_insn(s, VRRc, VNN, a0, a1, a2, 0); 3111 break; 3112 case INDEX_op_nor_vec: 3113 tcg_out_insn(s, VRRc, VNO, a0, a1, a2, 0); 3114 break; 3115 case INDEX_op_eqv_vec: 3116 tcg_out_insn(s, VRRc, VNX, a0, a1, a2, 0); 3117 break; 3118 3119 case INDEX_op_shli_vec: 3120 tcg_out_insn(s, VRSa, VESL, a0, a2, TCG_REG_NONE, a1, vece); 3121 break; 3122 case INDEX_op_shri_vec: 3123 tcg_out_insn(s, VRSa, VESRL, a0, a2, TCG_REG_NONE, a1, vece); 3124 break; 3125 case INDEX_op_sari_vec: 3126 tcg_out_insn(s, VRSa, VESRA, a0, a2, TCG_REG_NONE, a1, vece); 3127 break; 3128 case INDEX_op_rotli_vec: 3129 tcg_out_insn(s, VRSa, VERLL, a0, a2, TCG_REG_NONE, a1, vece); 3130 break; 3131 case INDEX_op_shls_vec: 3132 tcg_out_insn(s, VRSa, VESL, a0, 0, a2, a1, vece); 3133 break; 3134 case INDEX_op_shrs_vec: 3135 tcg_out_insn(s, VRSa, VESRL, a0, 0, a2, a1, vece); 3136 break; 3137 case INDEX_op_sars_vec: 3138 tcg_out_insn(s, VRSa, VESRA, a0, 0, a2, a1, vece); 3139 break; 3140 case INDEX_op_rotls_vec: 3141 tcg_out_insn(s, VRSa, VERLL, a0, 0, a2, a1, vece); 3142 break; 3143 case INDEX_op_shlv_vec: 3144 tcg_out_insn(s, VRRc, VESLV, a0, a1, a2, vece); 3145 break; 3146 case INDEX_op_shrv_vec: 3147 tcg_out_insn(s, VRRc, VESRLV, a0, a1, a2, vece); 3148 break; 3149 case INDEX_op_sarv_vec: 3150 tcg_out_insn(s, VRRc, VESRAV, a0, a1, a2, vece); 3151 break; 3152 case INDEX_op_rotlv_vec: 3153 tcg_out_insn(s, VRRc, VERLLV, a0, a1, a2, vece); 3154 break; 3155 3156 case INDEX_op_smin_vec: 3157 tcg_out_insn(s, VRRc, VMN, a0, a1, a2, vece); 3158 break; 3159 case INDEX_op_smax_vec: 3160 tcg_out_insn(s, VRRc, VMX, a0, a1, a2, vece); 3161 break; 3162 case INDEX_op_umin_vec: 3163 tcg_out_insn(s, VRRc, VMNL, a0, a1, a2, vece); 3164 break; 3165 case INDEX_op_umax_vec: 3166 tcg_out_insn(s, VRRc, VMXL, a0, a1, a2, vece); 3167 break; 3168 3169 case INDEX_op_bitsel_vec: 3170 tcg_out_insn(s, VRRe, VSEL, a0, a2, args[3], a1); 3171 break; 3172 3173 case INDEX_op_cmp_vec: 3174 tcg_out_cmp_vec(s, vece, a0, a1, a2, args[3]); 3175 break; 3176 case INDEX_op_cmpsel_vec: 3177 tcg_out_cmpsel_vec(s, vece, a0, a1, a2, args[3], const_args[3], 3178 args[4], args[5]); 3179 break; 3180 3181 case INDEX_op_s390_vuph_vec: 3182 tcg_out_insn(s, VRRa, VUPH, a0, a1, vece); 3183 break; 3184 case INDEX_op_s390_vupl_vec: 3185 tcg_out_insn(s, VRRa, VUPL, a0, a1, vece); 3186 break; 3187 case INDEX_op_s390_vpks_vec: 3188 tcg_out_insn(s, VRRc, VPKS, a0, a1, a2, vece); 3189 break; 3190 3191 case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ 3192 case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ 3193 default: 3194 g_assert_not_reached(); 3195 } 3196} 3197 3198int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) 3199{ 3200 switch (opc) { 3201 case INDEX_op_abs_vec: 3202 case INDEX_op_add_vec: 3203 case INDEX_op_and_vec: 3204 case INDEX_op_andc_vec: 3205 case INDEX_op_bitsel_vec: 3206 case INDEX_op_eqv_vec: 3207 case INDEX_op_nand_vec: 3208 case INDEX_op_neg_vec: 3209 case INDEX_op_nor_vec: 3210 case INDEX_op_not_vec: 3211 case INDEX_op_or_vec: 3212 case INDEX_op_orc_vec: 3213 case INDEX_op_rotli_vec: 3214 case INDEX_op_rotls_vec: 3215 case INDEX_op_rotlv_vec: 3216 case INDEX_op_sari_vec: 3217 case INDEX_op_sars_vec: 3218 case INDEX_op_sarv_vec: 3219 case INDEX_op_shli_vec: 3220 case INDEX_op_shls_vec: 3221 case INDEX_op_shlv_vec: 3222 case INDEX_op_shri_vec: 3223 case INDEX_op_shrs_vec: 3224 case INDEX_op_shrv_vec: 3225 case INDEX_op_smax_vec: 3226 case INDEX_op_smin_vec: 3227 case INDEX_op_sub_vec: 3228 case INDEX_op_umax_vec: 3229 case INDEX_op_umin_vec: 3230 case INDEX_op_xor_vec: 3231 case INDEX_op_cmp_vec: 3232 case INDEX_op_cmpsel_vec: 3233 return 1; 3234 case INDEX_op_rotrv_vec: 3235 return -1; 3236 case INDEX_op_mul_vec: 3237 return vece < MO_64; 3238 case INDEX_op_ssadd_vec: 3239 case INDEX_op_sssub_vec: 3240 return vece < MO_64 ? -1 : 0; 3241 default: 3242 return 0; 3243 } 3244} 3245 3246static void expand_vec_sat(TCGType type, unsigned vece, TCGv_vec v0, 3247 TCGv_vec v1, TCGv_vec v2, TCGOpcode add_sub_opc) 3248{ 3249 TCGv_vec h1 = tcg_temp_new_vec(type); 3250 TCGv_vec h2 = tcg_temp_new_vec(type); 3251 TCGv_vec l1 = tcg_temp_new_vec(type); 3252 TCGv_vec l2 = tcg_temp_new_vec(type); 3253 3254 tcg_debug_assert (vece < MO_64); 3255 3256 /* Unpack with sign-extension. */ 3257 vec_gen_2(INDEX_op_s390_vuph_vec, type, vece, 3258 tcgv_vec_arg(h1), tcgv_vec_arg(v1)); 3259 vec_gen_2(INDEX_op_s390_vuph_vec, type, vece, 3260 tcgv_vec_arg(h2), tcgv_vec_arg(v2)); 3261 3262 vec_gen_2(INDEX_op_s390_vupl_vec, type, vece, 3263 tcgv_vec_arg(l1), tcgv_vec_arg(v1)); 3264 vec_gen_2(INDEX_op_s390_vupl_vec, type, vece, 3265 tcgv_vec_arg(l2), tcgv_vec_arg(v2)); 3266 3267 /* Arithmetic on a wider element size. */ 3268 vec_gen_3(add_sub_opc, type, vece + 1, tcgv_vec_arg(h1), 3269 tcgv_vec_arg(h1), tcgv_vec_arg(h2)); 3270 vec_gen_3(add_sub_opc, type, vece + 1, tcgv_vec_arg(l1), 3271 tcgv_vec_arg(l1), tcgv_vec_arg(l2)); 3272 3273 /* Pack with saturation. */ 3274 vec_gen_3(INDEX_op_s390_vpks_vec, type, vece + 1, 3275 tcgv_vec_arg(v0), tcgv_vec_arg(h1), tcgv_vec_arg(l1)); 3276 3277 tcg_temp_free_vec(h1); 3278 tcg_temp_free_vec(h2); 3279 tcg_temp_free_vec(l1); 3280 tcg_temp_free_vec(l2); 3281} 3282 3283void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, 3284 TCGArg a0, ...) 3285{ 3286 va_list va; 3287 TCGv_vec v0, v1, v2, t0; 3288 3289 va_start(va, a0); 3290 v0 = temp_tcgv_vec(arg_temp(a0)); 3291 v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); 3292 v2 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); 3293 3294 switch (opc) { 3295 case INDEX_op_rotrv_vec: 3296 t0 = tcg_temp_new_vec(type); 3297 tcg_gen_neg_vec(vece, t0, v2); 3298 tcg_gen_rotlv_vec(vece, v0, v1, t0); 3299 tcg_temp_free_vec(t0); 3300 break; 3301 3302 case INDEX_op_ssadd_vec: 3303 expand_vec_sat(type, vece, v0, v1, v2, INDEX_op_add_vec); 3304 break; 3305 case INDEX_op_sssub_vec: 3306 expand_vec_sat(type, vece, v0, v1, v2, INDEX_op_sub_vec); 3307 break; 3308 3309 default: 3310 g_assert_not_reached(); 3311 } 3312 va_end(va); 3313} 3314 3315static TCGConstraintSetIndex 3316tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) 3317{ 3318 switch (op) { 3319 case INDEX_op_goto_ptr: 3320 return C_O0_I1(r); 3321 3322 case INDEX_op_ld8u_i32: 3323 case INDEX_op_ld8u_i64: 3324 case INDEX_op_ld8s_i32: 3325 case INDEX_op_ld8s_i64: 3326 case INDEX_op_ld16u_i32: 3327 case INDEX_op_ld16u_i64: 3328 case INDEX_op_ld16s_i32: 3329 case INDEX_op_ld16s_i64: 3330 case INDEX_op_ld_i32: 3331 case INDEX_op_ld32u_i64: 3332 case INDEX_op_ld32s_i64: 3333 case INDEX_op_ld_i64: 3334 return C_O1_I1(r, r); 3335 3336 case INDEX_op_st8_i32: 3337 case INDEX_op_st8_i64: 3338 case INDEX_op_st16_i32: 3339 case INDEX_op_st16_i64: 3340 case INDEX_op_st_i32: 3341 case INDEX_op_st32_i64: 3342 case INDEX_op_st_i64: 3343 return C_O0_I2(r, r); 3344 3345 case INDEX_op_shl_i64: 3346 case INDEX_op_shr_i64: 3347 case INDEX_op_sar_i64: 3348 case INDEX_op_rotl_i32: 3349 case INDEX_op_rotl_i64: 3350 case INDEX_op_rotr_i32: 3351 case INDEX_op_rotr_i64: 3352 return C_O1_I2(r, r, ri); 3353 case INDEX_op_setcond_i32: 3354 case INDEX_op_negsetcond_i32: 3355 case INDEX_op_setcond_i64: 3356 case INDEX_op_negsetcond_i64: 3357 return C_O1_I2(r, r, rC); 3358 3359 case INDEX_op_clz_i64: 3360 return C_O1_I2(r, r, rI); 3361 3362 case INDEX_op_shl_i32: 3363 case INDEX_op_shr_i32: 3364 case INDEX_op_sar_i32: 3365 return C_O1_I2(r, r, ri); 3366 3367 case INDEX_op_brcond_i32: 3368 return C_O0_I2(r, ri); 3369 case INDEX_op_brcond_i64: 3370 return C_O0_I2(r, rC); 3371 3372 case INDEX_op_bswap16_i32: 3373 case INDEX_op_bswap16_i64: 3374 case INDEX_op_bswap32_i32: 3375 case INDEX_op_bswap32_i64: 3376 case INDEX_op_bswap64_i64: 3377 case INDEX_op_ext_i32_i64: 3378 case INDEX_op_extu_i32_i64: 3379 case INDEX_op_extract_i32: 3380 case INDEX_op_extract_i64: 3381 case INDEX_op_sextract_i32: 3382 case INDEX_op_sextract_i64: 3383 case INDEX_op_ctpop_i32: 3384 case INDEX_op_ctpop_i64: 3385 return C_O1_I1(r, r); 3386 3387 case INDEX_op_qemu_ld_i32: 3388 case INDEX_op_qemu_ld_i64: 3389 return C_O1_I1(r, r); 3390 case INDEX_op_qemu_st_i64: 3391 case INDEX_op_qemu_st_i32: 3392 return C_O0_I2(r, r); 3393 case INDEX_op_qemu_ld_i128: 3394 return C_O2_I1(o, m, r); 3395 case INDEX_op_qemu_st_i128: 3396 return C_O0_I3(o, m, r); 3397 3398 case INDEX_op_deposit_i32: 3399 case INDEX_op_deposit_i64: 3400 return C_O1_I2(r, rZ, r); 3401 3402 case INDEX_op_movcond_i32: 3403 return C_O1_I4(r, r, ri, rI, r); 3404 case INDEX_op_movcond_i64: 3405 return C_O1_I4(r, r, rC, rI, r); 3406 3407 case INDEX_op_mulu2_i64: 3408 return C_O2_I2(o, m, 0, r); 3409 case INDEX_op_muls2_i64: 3410 return C_O2_I2(o, m, r, r); 3411 3412 case INDEX_op_add2_i32: 3413 case INDEX_op_sub2_i32: 3414 return C_N1_O1_I4(r, r, 0, 1, ri, r); 3415 3416 case INDEX_op_add2_i64: 3417 case INDEX_op_sub2_i64: 3418 return C_N1_O1_I4(r, r, 0, 1, rJU, r); 3419 3420 case INDEX_op_st_vec: 3421 return C_O0_I2(v, r); 3422 case INDEX_op_ld_vec: 3423 case INDEX_op_dupm_vec: 3424 return C_O1_I1(v, r); 3425 case INDEX_op_dup_vec: 3426 return C_O1_I1(v, vr); 3427 case INDEX_op_abs_vec: 3428 case INDEX_op_neg_vec: 3429 case INDEX_op_not_vec: 3430 case INDEX_op_rotli_vec: 3431 case INDEX_op_sari_vec: 3432 case INDEX_op_shli_vec: 3433 case INDEX_op_shri_vec: 3434 case INDEX_op_s390_vuph_vec: 3435 case INDEX_op_s390_vupl_vec: 3436 return C_O1_I1(v, v); 3437 case INDEX_op_add_vec: 3438 case INDEX_op_sub_vec: 3439 case INDEX_op_and_vec: 3440 case INDEX_op_andc_vec: 3441 case INDEX_op_or_vec: 3442 case INDEX_op_orc_vec: 3443 case INDEX_op_xor_vec: 3444 case INDEX_op_nand_vec: 3445 case INDEX_op_nor_vec: 3446 case INDEX_op_eqv_vec: 3447 case INDEX_op_cmp_vec: 3448 case INDEX_op_mul_vec: 3449 case INDEX_op_rotlv_vec: 3450 case INDEX_op_rotrv_vec: 3451 case INDEX_op_shlv_vec: 3452 case INDEX_op_shrv_vec: 3453 case INDEX_op_sarv_vec: 3454 case INDEX_op_smax_vec: 3455 case INDEX_op_smin_vec: 3456 case INDEX_op_umax_vec: 3457 case INDEX_op_umin_vec: 3458 case INDEX_op_s390_vpks_vec: 3459 return C_O1_I2(v, v, v); 3460 case INDEX_op_rotls_vec: 3461 case INDEX_op_shls_vec: 3462 case INDEX_op_shrs_vec: 3463 case INDEX_op_sars_vec: 3464 return C_O1_I2(v, v, r); 3465 case INDEX_op_bitsel_vec: 3466 return C_O1_I3(v, v, v, v); 3467 case INDEX_op_cmpsel_vec: 3468 return (TCG_TARGET_HAS_orc_vec 3469 ? C_O1_I4(v, v, v, vZM, v) 3470 : C_O1_I4(v, v, v, vZ, v)); 3471 3472 default: 3473 return C_NotImplemented; 3474 } 3475} 3476 3477/* 3478 * Mainline glibc added HWCAP_S390_VX before it was kernel abi. 3479 * Some distros have fixed this up locally, others have not. 3480 */ 3481#ifndef HWCAP_S390_VXRS 3482#define HWCAP_S390_VXRS 2048 3483#endif 3484 3485static void query_s390_facilities(void) 3486{ 3487 unsigned long hwcap = qemu_getauxval(AT_HWCAP); 3488 const char *which; 3489 3490 /* Is STORE FACILITY LIST EXTENDED available? Honestly, I believe this 3491 is present on all 64-bit systems, but let's check for it anyway. */ 3492 if (hwcap & HWCAP_S390_STFLE) { 3493 register int r0 __asm__("0") = ARRAY_SIZE(s390_facilities) - 1; 3494 register void *r1 __asm__("1") = s390_facilities; 3495 3496 /* stfle 0(%r1) */ 3497 asm volatile(".word 0xb2b0,0x1000" 3498 : "=r"(r0) : "r"(r0), "r"(r1) : "memory", "cc"); 3499 } 3500 3501 /* 3502 * Use of vector registers requires os support beyond the facility bit. 3503 * If the kernel does not advertise support, disable the facility bits. 3504 * There is nothing else we currently care about in the 3rd word, so 3505 * disable VECTOR with one store. 3506 */ 3507 if (!(hwcap & HWCAP_S390_VXRS)) { 3508 s390_facilities[2] = 0; 3509 } 3510 3511 /* 3512 * Minimum supported cpu revision is z196. 3513 * Check for all required facilities. 3514 * ZARCH_ACTIVE is done via preprocessor check for 64-bit. 3515 */ 3516 if (!HAVE_FACILITY(LONG_DISP)) { 3517 which = "long-displacement"; 3518 goto fail; 3519 } 3520 if (!HAVE_FACILITY(EXT_IMM)) { 3521 which = "extended-immediate"; 3522 goto fail; 3523 } 3524 if (!HAVE_FACILITY(GEN_INST_EXT)) { 3525 which = "general-instructions-extension"; 3526 goto fail; 3527 } 3528 /* 3529 * Facility 45 is a big bin that contains: distinct-operands, 3530 * fast-BCR-serialization, high-word, population-count, 3531 * interlocked-access-1, and load/store-on-condition-1 3532 */ 3533 if (!HAVE_FACILITY(45)) { 3534 which = "45"; 3535 goto fail; 3536 } 3537 return; 3538 3539 fail: 3540 error_report("%s: missing required facility %s", __func__, which); 3541 exit(EXIT_FAILURE); 3542} 3543 3544static void tcg_target_init(TCGContext *s) 3545{ 3546 query_s390_facilities(); 3547 3548 tcg_target_available_regs[TCG_TYPE_I32] = 0xffff; 3549 tcg_target_available_regs[TCG_TYPE_I64] = 0xffff; 3550 if (HAVE_FACILITY(VECTOR)) { 3551 tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull; 3552 tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull; 3553 } 3554 3555 tcg_target_call_clobber_regs = 0; 3556 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0); 3557 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1); 3558 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2); 3559 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3); 3560 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R4); 3561 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R5); 3562 /* The r6 register is technically call-saved, but it's also a parameter 3563 register, so it can get killed by setup for the qemu_st helper. */ 3564 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R6); 3565 /* The return register can be considered call-clobbered. */ 3566 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14); 3567 3568 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); 3569 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); 3570 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V2); 3571 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V3); 3572 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V4); 3573 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V5); 3574 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V6); 3575 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V7); 3576 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V16); 3577 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V17); 3578 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V18); 3579 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V19); 3580 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V20); 3581 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V21); 3582 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V22); 3583 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V23); 3584 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V24); 3585 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V25); 3586 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V26); 3587 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V27); 3588 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V28); 3589 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V29); 3590 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V30); 3591 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V31); 3592 3593 s->reserved_regs = 0; 3594 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); 3595 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP0); 3596 /* XXX many insns can't be used with R0, so we better avoid it for now */ 3597 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); 3598 tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); 3599} 3600 3601#define FRAME_SIZE ((int)(TCG_TARGET_CALL_STACK_OFFSET \ 3602 + TCG_STATIC_CALL_ARGS_SIZE \ 3603 + CPU_TEMP_BUF_NLONGS * sizeof(long))) 3604 3605static void tcg_target_qemu_prologue(TCGContext *s) 3606{ 3607 /* stmg %r6,%r15,48(%r15) (save registers) */ 3608 tcg_out_insn(s, RXY, STMG, TCG_REG_R6, TCG_REG_R15, TCG_REG_R15, 48); 3609 3610 /* aghi %r15,-frame_size */ 3611 tcg_out_insn(s, RI, AGHI, TCG_REG_R15, -FRAME_SIZE); 3612 3613 tcg_set_frame(s, TCG_REG_CALL_STACK, 3614 TCG_STATIC_CALL_ARGS_SIZE + TCG_TARGET_CALL_STACK_OFFSET, 3615 CPU_TEMP_BUF_NLONGS * sizeof(long)); 3616 3617 if (!tcg_use_softmmu && guest_base >= 0x80000) { 3618 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); 3619 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 3620 } 3621 3622 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 3623 3624 /* br %r3 (go to TB) */ 3625 tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, tcg_target_call_iarg_regs[1]); 3626 3627 /* 3628 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 3629 * and fall through to the rest of the epilogue. 3630 */ 3631 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 3632 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, 0); 3633 3634 /* TB epilogue */ 3635 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 3636 3637 /* lmg %r6,%r15,fs+48(%r15) (restore registers) */ 3638 tcg_out_insn(s, RXY, LMG, TCG_REG_R6, TCG_REG_R15, TCG_REG_R15, 3639 FRAME_SIZE + 48); 3640 3641 /* br %r14 (return) */ 3642 tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_R14); 3643} 3644 3645static void tcg_out_tb_start(TCGContext *s) 3646{ 3647 /* nothing to do */ 3648} 3649 3650static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 3651{ 3652 memset(p, 0x07, count * sizeof(tcg_insn_unit)); 3653} 3654 3655typedef struct { 3656 DebugFrameHeader h; 3657 uint8_t fde_def_cfa[4]; 3658 uint8_t fde_reg_ofs[18]; 3659} DebugFrame; 3660 3661/* We're expecting a 2 byte uleb128 encoded value. */ 3662QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14)); 3663 3664#define ELF_HOST_MACHINE EM_S390 3665 3666static const DebugFrame debug_frame = { 3667 .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ 3668 .h.cie.id = -1, 3669 .h.cie.version = 1, 3670 .h.cie.code_align = 1, 3671 .h.cie.data_align = 8, /* sleb128 8 */ 3672 .h.cie.return_column = TCG_REG_R14, 3673 3674 /* Total FDE size does not include the "len" member. */ 3675 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 3676 3677 .fde_def_cfa = { 3678 12, TCG_REG_CALL_STACK, /* DW_CFA_def_cfa %r15, ... */ 3679 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 3680 (FRAME_SIZE >> 7) 3681 }, 3682 .fde_reg_ofs = { 3683 0x86, 6, /* DW_CFA_offset, %r6, 48 */ 3684 0x87, 7, /* DW_CFA_offset, %r7, 56 */ 3685 0x88, 8, /* DW_CFA_offset, %r8, 64 */ 3686 0x89, 9, /* DW_CFA_offset, %r92, 72 */ 3687 0x8a, 10, /* DW_CFA_offset, %r10, 80 */ 3688 0x8b, 11, /* DW_CFA_offset, %r11, 88 */ 3689 0x8c, 12, /* DW_CFA_offset, %r12, 96 */ 3690 0x8d, 13, /* DW_CFA_offset, %r13, 104 */ 3691 0x8e, 14, /* DW_CFA_offset, %r14, 112 */ 3692 } 3693}; 3694 3695void tcg_register_jit(const void *buf, size_t buf_size) 3696{ 3697 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 3698} 3699