1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2009 Ulrich Hecht <uli@suse.de> 5 * Copyright (c) 2009 Alexander Graf <agraf@suse.de> 6 * Copyright (c) 2010 Richard Henderson <rth@twiddle.net> 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27#include "../tcg-ldst.c.inc" 28#include "../tcg-pool.c.inc" 29#include "elf.h" 30 31#define TCG_CT_CONST_S16 (1 << 8) 32#define TCG_CT_CONST_S32 (1 << 9) 33#define TCG_CT_CONST_S33 (1 << 10) 34#define TCG_CT_CONST_ZERO (1 << 11) 35#define TCG_CT_CONST_P32 (1 << 12) 36#define TCG_CT_CONST_INV (1 << 13) 37#define TCG_CT_CONST_INVRISBG (1 << 14) 38 39#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 16) 40#define ALL_VECTOR_REGS MAKE_64BIT_MASK(32, 32) 41 42/* Several places within the instruction set 0 means "no register" 43 rather than TCG_REG_R0. */ 44#define TCG_REG_NONE 0 45 46/* A scratch register that may be be used throughout the backend. */ 47#define TCG_TMP0 TCG_REG_R1 48 49#define TCG_GUEST_BASE_REG TCG_REG_R13 50 51/* All of the following instructions are prefixed with their instruction 52 format, and are defined as 8- or 16-bit quantities, even when the two 53 halves of the 16-bit quantity may appear 32 bits apart in the insn. 54 This makes it easy to copy the values from the tables in Appendix B. */ 55typedef enum S390Opcode { 56 RIL_AFI = 0xc209, 57 RIL_AGFI = 0xc208, 58 RIL_ALFI = 0xc20b, 59 RIL_ALGFI = 0xc20a, 60 RIL_BRASL = 0xc005, 61 RIL_BRCL = 0xc004, 62 RIL_CFI = 0xc20d, 63 RIL_CGFI = 0xc20c, 64 RIL_CLFI = 0xc20f, 65 RIL_CLGFI = 0xc20e, 66 RIL_CLRL = 0xc60f, 67 RIL_CLGRL = 0xc60a, 68 RIL_CRL = 0xc60d, 69 RIL_CGRL = 0xc608, 70 RIL_IIHF = 0xc008, 71 RIL_IILF = 0xc009, 72 RIL_LARL = 0xc000, 73 RIL_LGFI = 0xc001, 74 RIL_LGRL = 0xc408, 75 RIL_LLIHF = 0xc00e, 76 RIL_LLILF = 0xc00f, 77 RIL_LRL = 0xc40d, 78 RIL_MSFI = 0xc201, 79 RIL_MSGFI = 0xc200, 80 RIL_NIHF = 0xc00a, 81 RIL_NILF = 0xc00b, 82 RIL_OIHF = 0xc00c, 83 RIL_OILF = 0xc00d, 84 RIL_SLFI = 0xc205, 85 RIL_SLGFI = 0xc204, 86 RIL_XIHF = 0xc006, 87 RIL_XILF = 0xc007, 88 89 RI_AGHI = 0xa70b, 90 RI_AHI = 0xa70a, 91 RI_BRC = 0xa704, 92 RI_CHI = 0xa70e, 93 RI_CGHI = 0xa70f, 94 RI_IIHH = 0xa500, 95 RI_IIHL = 0xa501, 96 RI_IILH = 0xa502, 97 RI_IILL = 0xa503, 98 RI_LGHI = 0xa709, 99 RI_LLIHH = 0xa50c, 100 RI_LLIHL = 0xa50d, 101 RI_LLILH = 0xa50e, 102 RI_LLILL = 0xa50f, 103 RI_MGHI = 0xa70d, 104 RI_MHI = 0xa70c, 105 RI_NIHH = 0xa504, 106 RI_NIHL = 0xa505, 107 RI_NILH = 0xa506, 108 RI_NILL = 0xa507, 109 RI_OIHH = 0xa508, 110 RI_OIHL = 0xa509, 111 RI_OILH = 0xa50a, 112 RI_OILL = 0xa50b, 113 RI_TMLL = 0xa701, 114 115 RIEb_CGRJ = 0xec64, 116 RIEb_CLGRJ = 0xec65, 117 RIEb_CLRJ = 0xec77, 118 RIEb_CRJ = 0xec76, 119 120 RIEc_CGIJ = 0xec7c, 121 RIEc_CIJ = 0xec7e, 122 RIEc_CLGIJ = 0xec7d, 123 RIEc_CLIJ = 0xec7f, 124 125 RIEf_RISBG = 0xec55, 126 127 RIEg_LOCGHI = 0xec46, 128 129 RRE_AGR = 0xb908, 130 RRE_ALGR = 0xb90a, 131 RRE_ALCR = 0xb998, 132 RRE_ALCGR = 0xb988, 133 RRE_ALGFR = 0xb91a, 134 RRE_CGR = 0xb920, 135 RRE_CLGR = 0xb921, 136 RRE_DLGR = 0xb987, 137 RRE_DLR = 0xb997, 138 RRE_DSGFR = 0xb91d, 139 RRE_DSGR = 0xb90d, 140 RRE_FLOGR = 0xb983, 141 RRE_LGBR = 0xb906, 142 RRE_LCGR = 0xb903, 143 RRE_LGFR = 0xb914, 144 RRE_LGHR = 0xb907, 145 RRE_LGR = 0xb904, 146 RRE_LLGCR = 0xb984, 147 RRE_LLGFR = 0xb916, 148 RRE_LLGHR = 0xb985, 149 RRE_LRVR = 0xb91f, 150 RRE_LRVGR = 0xb90f, 151 RRE_LTGR = 0xb902, 152 RRE_MLGR = 0xb986, 153 RRE_MSGR = 0xb90c, 154 RRE_MSR = 0xb252, 155 RRE_NGR = 0xb980, 156 RRE_OGR = 0xb981, 157 RRE_SGR = 0xb909, 158 RRE_SLGR = 0xb90b, 159 RRE_SLBR = 0xb999, 160 RRE_SLBGR = 0xb989, 161 RRE_XGR = 0xb982, 162 163 RRFa_MGRK = 0xb9ec, 164 RRFa_MSRKC = 0xb9fd, 165 RRFa_MSGRKC = 0xb9ed, 166 RRFa_NCRK = 0xb9f5, 167 RRFa_NCGRK = 0xb9e5, 168 RRFa_NNRK = 0xb974, 169 RRFa_NNGRK = 0xb964, 170 RRFa_NORK = 0xb976, 171 RRFa_NOGRK = 0xb966, 172 RRFa_NRK = 0xb9f4, 173 RRFa_NGRK = 0xb9e4, 174 RRFa_NXRK = 0xb977, 175 RRFa_NXGRK = 0xb967, 176 RRFa_OCRK = 0xb975, 177 RRFa_OCGRK = 0xb965, 178 RRFa_ORK = 0xb9f6, 179 RRFa_OGRK = 0xb9e6, 180 RRFa_SRK = 0xb9f9, 181 RRFa_SGRK = 0xb9e9, 182 RRFa_SLRK = 0xb9fb, 183 RRFa_SLGRK = 0xb9eb, 184 RRFa_XRK = 0xb9f7, 185 RRFa_XGRK = 0xb9e7, 186 187 RRFam_SELGR = 0xb9e3, 188 189 RRFc_LOCR = 0xb9f2, 190 RRFc_LOCGR = 0xb9e2, 191 RRFc_POPCNT = 0xb9e1, 192 193 RR_AR = 0x1a, 194 RR_ALR = 0x1e, 195 RR_BASR = 0x0d, 196 RR_BCR = 0x07, 197 RR_CLR = 0x15, 198 RR_CR = 0x19, 199 RR_DR = 0x1d, 200 RR_LCR = 0x13, 201 RR_LR = 0x18, 202 RR_LTR = 0x12, 203 RR_NR = 0x14, 204 RR_OR = 0x16, 205 RR_SR = 0x1b, 206 RR_SLR = 0x1f, 207 RR_XR = 0x17, 208 209 RSY_RLL = 0xeb1d, 210 RSY_RLLG = 0xeb1c, 211 RSY_SLLG = 0xeb0d, 212 RSY_SLLK = 0xebdf, 213 RSY_SRAG = 0xeb0a, 214 RSY_SRAK = 0xebdc, 215 RSY_SRLG = 0xeb0c, 216 RSY_SRLK = 0xebde, 217 218 RS_SLL = 0x89, 219 RS_SRA = 0x8a, 220 RS_SRL = 0x88, 221 222 RXY_AG = 0xe308, 223 RXY_AY = 0xe35a, 224 RXY_CG = 0xe320, 225 RXY_CLG = 0xe321, 226 RXY_CLY = 0xe355, 227 RXY_CY = 0xe359, 228 RXY_LAY = 0xe371, 229 RXY_LB = 0xe376, 230 RXY_LG = 0xe304, 231 RXY_LGB = 0xe377, 232 RXY_LGF = 0xe314, 233 RXY_LGH = 0xe315, 234 RXY_LHY = 0xe378, 235 RXY_LLGC = 0xe390, 236 RXY_LLGF = 0xe316, 237 RXY_LLGH = 0xe391, 238 RXY_LMG = 0xeb04, 239 RXY_LPQ = 0xe38f, 240 RXY_LRV = 0xe31e, 241 RXY_LRVG = 0xe30f, 242 RXY_LRVH = 0xe31f, 243 RXY_LY = 0xe358, 244 RXY_NG = 0xe380, 245 RXY_OG = 0xe381, 246 RXY_STCY = 0xe372, 247 RXY_STG = 0xe324, 248 RXY_STHY = 0xe370, 249 RXY_STMG = 0xeb24, 250 RXY_STPQ = 0xe38e, 251 RXY_STRV = 0xe33e, 252 RXY_STRVG = 0xe32f, 253 RXY_STRVH = 0xe33f, 254 RXY_STY = 0xe350, 255 RXY_XG = 0xe382, 256 257 RX_A = 0x5a, 258 RX_C = 0x59, 259 RX_L = 0x58, 260 RX_LA = 0x41, 261 RX_LH = 0x48, 262 RX_ST = 0x50, 263 RX_STC = 0x42, 264 RX_STH = 0x40, 265 266 VRIa_VGBM = 0xe744, 267 VRIa_VREPI = 0xe745, 268 VRIb_VGM = 0xe746, 269 VRIc_VREP = 0xe74d, 270 271 VRRa_VLC = 0xe7de, 272 VRRa_VLP = 0xe7df, 273 VRRa_VLR = 0xe756, 274 VRRc_VA = 0xe7f3, 275 VRRc_VCEQ = 0xe7f8, /* we leave the m5 cs field 0 */ 276 VRRc_VCH = 0xe7fb, /* " */ 277 VRRc_VCHL = 0xe7f9, /* " */ 278 VRRc_VERLLV = 0xe773, 279 VRRc_VESLV = 0xe770, 280 VRRc_VESRAV = 0xe77a, 281 VRRc_VESRLV = 0xe778, 282 VRRc_VML = 0xe7a2, 283 VRRc_VMN = 0xe7fe, 284 VRRc_VMNL = 0xe7fc, 285 VRRc_VMX = 0xe7ff, 286 VRRc_VMXL = 0xe7fd, 287 VRRc_VN = 0xe768, 288 VRRc_VNC = 0xe769, 289 VRRc_VNN = 0xe76e, 290 VRRc_VNO = 0xe76b, 291 VRRc_VNX = 0xe76c, 292 VRRc_VO = 0xe76a, 293 VRRc_VOC = 0xe76f, 294 VRRc_VPKS = 0xe797, /* we leave the m5 cs field 0 */ 295 VRRc_VS = 0xe7f7, 296 VRRa_VUPH = 0xe7d7, 297 VRRa_VUPL = 0xe7d6, 298 VRRc_VX = 0xe76d, 299 VRRe_VSEL = 0xe78d, 300 VRRf_VLVGP = 0xe762, 301 302 VRSa_VERLL = 0xe733, 303 VRSa_VESL = 0xe730, 304 VRSa_VESRA = 0xe73a, 305 VRSa_VESRL = 0xe738, 306 VRSb_VLVG = 0xe722, 307 VRSc_VLGV = 0xe721, 308 309 VRX_VL = 0xe706, 310 VRX_VLLEZ = 0xe704, 311 VRX_VLREP = 0xe705, 312 VRX_VST = 0xe70e, 313 VRX_VSTEF = 0xe70b, 314 VRX_VSTEG = 0xe70a, 315 316 NOP = 0x0707, 317} S390Opcode; 318 319#ifdef CONFIG_DEBUG_TCG 320static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 321 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", 322 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", 323 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 324 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7", 325 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15", 326 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23", 327 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31", 328}; 329#endif 330 331/* Since R6 is a potential argument register, choose it last of the 332 call-saved registers. Likewise prefer the call-clobbered registers 333 in reverse order to maximize the chance of avoiding the arguments. */ 334static const int tcg_target_reg_alloc_order[] = { 335 /* Call saved registers. */ 336 TCG_REG_R13, 337 TCG_REG_R12, 338 TCG_REG_R11, 339 TCG_REG_R10, 340 TCG_REG_R9, 341 TCG_REG_R8, 342 TCG_REG_R7, 343 TCG_REG_R6, 344 /* Call clobbered registers. */ 345 TCG_REG_R14, 346 TCG_REG_R0, 347 TCG_REG_R1, 348 /* Argument registers, in reverse order of allocation. */ 349 TCG_REG_R5, 350 TCG_REG_R4, 351 TCG_REG_R3, 352 TCG_REG_R2, 353 354 /* V8-V15 are call saved, and omitted. */ 355 TCG_REG_V0, 356 TCG_REG_V1, 357 TCG_REG_V2, 358 TCG_REG_V3, 359 TCG_REG_V4, 360 TCG_REG_V5, 361 TCG_REG_V6, 362 TCG_REG_V7, 363 TCG_REG_V16, 364 TCG_REG_V17, 365 TCG_REG_V18, 366 TCG_REG_V19, 367 TCG_REG_V20, 368 TCG_REG_V21, 369 TCG_REG_V22, 370 TCG_REG_V23, 371 TCG_REG_V24, 372 TCG_REG_V25, 373 TCG_REG_V26, 374 TCG_REG_V27, 375 TCG_REG_V28, 376 TCG_REG_V29, 377 TCG_REG_V30, 378 TCG_REG_V31, 379}; 380 381static const int tcg_target_call_iarg_regs[] = { 382 TCG_REG_R2, 383 TCG_REG_R3, 384 TCG_REG_R4, 385 TCG_REG_R5, 386 TCG_REG_R6, 387}; 388 389static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 390{ 391 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 392 tcg_debug_assert(slot == 0); 393 return TCG_REG_R2; 394} 395 396#define S390_CC_EQ 8 397#define S390_CC_LT 4 398#define S390_CC_GT 2 399#define S390_CC_OV 1 400#define S390_CC_NE (S390_CC_LT | S390_CC_GT) 401#define S390_CC_LE (S390_CC_LT | S390_CC_EQ) 402#define S390_CC_GE (S390_CC_GT | S390_CC_EQ) 403#define S390_CC_NEVER 0 404#define S390_CC_ALWAYS 15 405 406/* Condition codes that result from a COMPARE and COMPARE LOGICAL. */ 407static const uint8_t tcg_cond_to_s390_cond[] = { 408 [TCG_COND_EQ] = S390_CC_EQ, 409 [TCG_COND_NE] = S390_CC_NE, 410 [TCG_COND_LT] = S390_CC_LT, 411 [TCG_COND_LE] = S390_CC_LE, 412 [TCG_COND_GT] = S390_CC_GT, 413 [TCG_COND_GE] = S390_CC_GE, 414 [TCG_COND_LTU] = S390_CC_LT, 415 [TCG_COND_LEU] = S390_CC_LE, 416 [TCG_COND_GTU] = S390_CC_GT, 417 [TCG_COND_GEU] = S390_CC_GE, 418}; 419 420/* Condition codes that result from a LOAD AND TEST. Here, we have no 421 unsigned instruction variation, however since the test is vs zero we 422 can re-map the outcomes appropriately. */ 423static const uint8_t tcg_cond_to_ltr_cond[] = { 424 [TCG_COND_EQ] = S390_CC_EQ, 425 [TCG_COND_NE] = S390_CC_NE, 426 [TCG_COND_LT] = S390_CC_LT, 427 [TCG_COND_LE] = S390_CC_LE, 428 [TCG_COND_GT] = S390_CC_GT, 429 [TCG_COND_GE] = S390_CC_GE, 430 [TCG_COND_LTU] = S390_CC_NEVER, 431 [TCG_COND_LEU] = S390_CC_EQ, 432 [TCG_COND_GTU] = S390_CC_NE, 433 [TCG_COND_GEU] = S390_CC_ALWAYS, 434}; 435 436static const tcg_insn_unit *tb_ret_addr; 437uint64_t s390_facilities[3]; 438 439static inline bool is_general_reg(TCGReg r) 440{ 441 return r <= TCG_REG_R15; 442} 443 444static inline bool is_vector_reg(TCGReg r) 445{ 446 return r >= TCG_REG_V0 && r <= TCG_REG_V31; 447} 448 449static bool patch_reloc(tcg_insn_unit *src_rw, int type, 450 intptr_t value, intptr_t addend) 451{ 452 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 453 intptr_t pcrel2; 454 uint32_t old; 455 456 value += addend; 457 pcrel2 = (tcg_insn_unit *)value - src_rx; 458 459 switch (type) { 460 case R_390_PC16DBL: 461 if (pcrel2 == (int16_t)pcrel2) { 462 tcg_patch16(src_rw, pcrel2); 463 return true; 464 } 465 break; 466 case R_390_PC32DBL: 467 if (pcrel2 == (int32_t)pcrel2) { 468 tcg_patch32(src_rw, pcrel2); 469 return true; 470 } 471 break; 472 case R_390_20: 473 if (value == sextract64(value, 0, 20)) { 474 old = *(uint32_t *)src_rw & 0xf00000ff; 475 old |= ((value & 0xfff) << 16) | ((value & 0xff000) >> 4); 476 tcg_patch32(src_rw, old); 477 return true; 478 } 479 break; 480 default: 481 g_assert_not_reached(); 482 } 483 return false; 484} 485 486static int is_const_p16(uint64_t val) 487{ 488 for (int i = 0; i < 4; ++i) { 489 uint64_t mask = 0xffffull << (i * 16); 490 if ((val & ~mask) == 0) { 491 return i; 492 } 493 } 494 return -1; 495} 496 497static int is_const_p32(uint64_t val) 498{ 499 if ((val & 0xffffffff00000000ull) == 0) { 500 return 0; 501 } 502 if ((val & 0x00000000ffffffffull) == 0) { 503 return 1; 504 } 505 return -1; 506} 507 508/* 509 * Accept bit patterns like these: 510 * 0....01....1 511 * 1....10....0 512 * 1..10..01..1 513 * 0..01..10..0 514 * Copied from gcc sources. 515 */ 516static bool risbg_mask(uint64_t c) 517{ 518 uint64_t lsb; 519 /* We don't change the number of transitions by inverting, 520 so make sure we start with the LSB zero. */ 521 if (c & 1) { 522 c = ~c; 523 } 524 /* Reject all zeros or all ones. */ 525 if (c == 0) { 526 return false; 527 } 528 /* Find the first transition. */ 529 lsb = c & -c; 530 /* Invert to look for a second transition. */ 531 c = ~c; 532 /* Erase the first transition. */ 533 c &= -lsb; 534 /* Find the second transition, if any. */ 535 lsb = c & -c; 536 /* Match if all the bits are 1's, or if c is zero. */ 537 return c == -lsb; 538} 539 540/* Test if a constant matches the constraint. */ 541static bool tcg_target_const_match(int64_t val, TCGType type, int ct, int vece) 542{ 543 if (ct & TCG_CT_CONST) { 544 return 1; 545 } 546 547 if (type == TCG_TYPE_I32) { 548 val = (int32_t)val; 549 } 550 551 /* The following are mutually exclusive. */ 552 if (ct & TCG_CT_CONST_S16) { 553 return val == (int16_t)val; 554 } else if (ct & TCG_CT_CONST_S32) { 555 return val == (int32_t)val; 556 } else if (ct & TCG_CT_CONST_S33) { 557 return val >= -0xffffffffll && val <= 0xffffffffll; 558 } else if (ct & TCG_CT_CONST_ZERO) { 559 return val == 0; 560 } 561 562 if (ct & TCG_CT_CONST_INV) { 563 val = ~val; 564 } 565 /* 566 * Note that is_const_p16 is a subset of is_const_p32, 567 * so we don't need both constraints. 568 */ 569 if ((ct & TCG_CT_CONST_P32) && is_const_p32(val) >= 0) { 570 return true; 571 } 572 if ((ct & TCG_CT_CONST_INVRISBG) && risbg_mask(~val)) { 573 return true; 574 } 575 576 return 0; 577} 578 579/* Emit instructions according to the given instruction format. */ 580 581static void tcg_out_insn_RR(TCGContext *s, S390Opcode op, TCGReg r1, TCGReg r2) 582{ 583 tcg_out16(s, (op << 8) | (r1 << 4) | r2); 584} 585 586static void tcg_out_insn_RRE(TCGContext *s, S390Opcode op, 587 TCGReg r1, TCGReg r2) 588{ 589 tcg_out32(s, (op << 16) | (r1 << 4) | r2); 590} 591 592/* RRF-a without the m4 field */ 593static void tcg_out_insn_RRFa(TCGContext *s, S390Opcode op, 594 TCGReg r1, TCGReg r2, TCGReg r3) 595{ 596 tcg_out32(s, (op << 16) | (r3 << 12) | (r1 << 4) | r2); 597} 598 599/* RRF-a with the m4 field */ 600static void tcg_out_insn_RRFam(TCGContext *s, S390Opcode op, 601 TCGReg r1, TCGReg r2, TCGReg r3, int m4) 602{ 603 tcg_out32(s, (op << 16) | (r3 << 12) | (m4 << 8) | (r1 << 4) | r2); 604} 605 606static void tcg_out_insn_RRFc(TCGContext *s, S390Opcode op, 607 TCGReg r1, TCGReg r2, int m3) 608{ 609 tcg_out32(s, (op << 16) | (m3 << 12) | (r1 << 4) | r2); 610} 611 612static void tcg_out_insn_RI(TCGContext *s, S390Opcode op, TCGReg r1, int i2) 613{ 614 tcg_out32(s, (op << 16) | (r1 << 20) | (i2 & 0xffff)); 615} 616 617static void tcg_out_insn_RIEg(TCGContext *s, S390Opcode op, TCGReg r1, 618 int i2, int m3) 619{ 620 tcg_out16(s, (op & 0xff00) | (r1 << 4) | m3); 621 tcg_out32(s, (i2 << 16) | (op & 0xff)); 622} 623 624static void tcg_out_insn_RIL(TCGContext *s, S390Opcode op, TCGReg r1, int i2) 625{ 626 tcg_out16(s, op | (r1 << 4)); 627 tcg_out32(s, i2); 628} 629 630static void tcg_out_insn_RS(TCGContext *s, S390Opcode op, TCGReg r1, 631 TCGReg b2, TCGReg r3, int disp) 632{ 633 tcg_out32(s, (op << 24) | (r1 << 20) | (r3 << 16) | (b2 << 12) 634 | (disp & 0xfff)); 635} 636 637static void tcg_out_insn_RSY(TCGContext *s, S390Opcode op, TCGReg r1, 638 TCGReg b2, TCGReg r3, int disp) 639{ 640 tcg_out16(s, (op & 0xff00) | (r1 << 4) | r3); 641 tcg_out32(s, (op & 0xff) | (b2 << 28) 642 | ((disp & 0xfff) << 16) | ((disp & 0xff000) >> 4)); 643} 644 645#define tcg_out_insn_RX tcg_out_insn_RS 646#define tcg_out_insn_RXY tcg_out_insn_RSY 647 648static int RXB(TCGReg v1, TCGReg v2, TCGReg v3, TCGReg v4) 649{ 650 /* 651 * Shift bit 4 of each regno to its corresponding bit of RXB. 652 * RXB itself begins at bit 8 of the instruction so 8 - 4 = 4 653 * is the left-shift of the 4th operand. 654 */ 655 return ((v1 & 0x10) << (4 + 3)) 656 | ((v2 & 0x10) << (4 + 2)) 657 | ((v3 & 0x10) << (4 + 1)) 658 | ((v4 & 0x10) << (4 + 0)); 659} 660 661static void tcg_out_insn_VRIa(TCGContext *s, S390Opcode op, 662 TCGReg v1, uint16_t i2, int m3) 663{ 664 tcg_debug_assert(is_vector_reg(v1)); 665 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4)); 666 tcg_out16(s, i2); 667 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m3 << 12)); 668} 669 670static void tcg_out_insn_VRIb(TCGContext *s, S390Opcode op, 671 TCGReg v1, uint8_t i2, uint8_t i3, int m4) 672{ 673 tcg_debug_assert(is_vector_reg(v1)); 674 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4)); 675 tcg_out16(s, (i2 << 8) | (i3 & 0xff)); 676 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m4 << 12)); 677} 678 679static void tcg_out_insn_VRIc(TCGContext *s, S390Opcode op, 680 TCGReg v1, uint16_t i2, TCGReg v3, int m4) 681{ 682 tcg_debug_assert(is_vector_reg(v1)); 683 tcg_debug_assert(is_vector_reg(v3)); 684 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v3 & 0xf)); 685 tcg_out16(s, i2); 686 tcg_out16(s, (op & 0x00ff) | RXB(v1, v3, 0, 0) | (m4 << 12)); 687} 688 689static void tcg_out_insn_VRRa(TCGContext *s, S390Opcode op, 690 TCGReg v1, TCGReg v2, int m3) 691{ 692 tcg_debug_assert(is_vector_reg(v1)); 693 tcg_debug_assert(is_vector_reg(v2)); 694 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v2 & 0xf)); 695 tcg_out32(s, (op & 0x00ff) | RXB(v1, v2, 0, 0) | (m3 << 12)); 696} 697 698static void tcg_out_insn_VRRc(TCGContext *s, S390Opcode op, 699 TCGReg v1, TCGReg v2, TCGReg v3, int m4) 700{ 701 tcg_debug_assert(is_vector_reg(v1)); 702 tcg_debug_assert(is_vector_reg(v2)); 703 tcg_debug_assert(is_vector_reg(v3)); 704 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v2 & 0xf)); 705 tcg_out16(s, v3 << 12); 706 tcg_out16(s, (op & 0x00ff) | RXB(v1, v2, v3, 0) | (m4 << 12)); 707} 708 709static void tcg_out_insn_VRRe(TCGContext *s, S390Opcode op, 710 TCGReg v1, TCGReg v2, TCGReg v3, TCGReg v4) 711{ 712 tcg_debug_assert(is_vector_reg(v1)); 713 tcg_debug_assert(is_vector_reg(v2)); 714 tcg_debug_assert(is_vector_reg(v3)); 715 tcg_debug_assert(is_vector_reg(v4)); 716 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v2 & 0xf)); 717 tcg_out16(s, v3 << 12); 718 tcg_out16(s, (op & 0x00ff) | RXB(v1, v2, v3, v4) | (v4 << 12)); 719} 720 721static void tcg_out_insn_VRRf(TCGContext *s, S390Opcode op, 722 TCGReg v1, TCGReg r2, TCGReg r3) 723{ 724 tcg_debug_assert(is_vector_reg(v1)); 725 tcg_debug_assert(is_general_reg(r2)); 726 tcg_debug_assert(is_general_reg(r3)); 727 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | r2); 728 tcg_out16(s, r3 << 12); 729 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0)); 730} 731 732static void tcg_out_insn_VRSa(TCGContext *s, S390Opcode op, TCGReg v1, 733 intptr_t d2, TCGReg b2, TCGReg v3, int m4) 734{ 735 tcg_debug_assert(is_vector_reg(v1)); 736 tcg_debug_assert(d2 >= 0 && d2 <= 0xfff); 737 tcg_debug_assert(is_general_reg(b2)); 738 tcg_debug_assert(is_vector_reg(v3)); 739 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v3 & 0xf)); 740 tcg_out16(s, b2 << 12 | d2); 741 tcg_out16(s, (op & 0x00ff) | RXB(v1, v3, 0, 0) | (m4 << 12)); 742} 743 744static void tcg_out_insn_VRSb(TCGContext *s, S390Opcode op, TCGReg v1, 745 intptr_t d2, TCGReg b2, TCGReg r3, int m4) 746{ 747 tcg_debug_assert(is_vector_reg(v1)); 748 tcg_debug_assert(d2 >= 0 && d2 <= 0xfff); 749 tcg_debug_assert(is_general_reg(b2)); 750 tcg_debug_assert(is_general_reg(r3)); 751 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | r3); 752 tcg_out16(s, b2 << 12 | d2); 753 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m4 << 12)); 754} 755 756static void tcg_out_insn_VRSc(TCGContext *s, S390Opcode op, TCGReg r1, 757 intptr_t d2, TCGReg b2, TCGReg v3, int m4) 758{ 759 tcg_debug_assert(is_general_reg(r1)); 760 tcg_debug_assert(d2 >= 0 && d2 <= 0xfff); 761 tcg_debug_assert(is_general_reg(b2)); 762 tcg_debug_assert(is_vector_reg(v3)); 763 tcg_out16(s, (op & 0xff00) | (r1 << 4) | (v3 & 0xf)); 764 tcg_out16(s, b2 << 12 | d2); 765 tcg_out16(s, (op & 0x00ff) | RXB(0, v3, 0, 0) | (m4 << 12)); 766} 767 768static void tcg_out_insn_VRX(TCGContext *s, S390Opcode op, TCGReg v1, 769 TCGReg b2, TCGReg x2, intptr_t d2, int m3) 770{ 771 tcg_debug_assert(is_vector_reg(v1)); 772 tcg_debug_assert(d2 >= 0 && d2 <= 0xfff); 773 tcg_debug_assert(is_general_reg(x2)); 774 tcg_debug_assert(is_general_reg(b2)); 775 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | x2); 776 tcg_out16(s, (b2 << 12) | d2); 777 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m3 << 12)); 778} 779 780/* Emit an opcode with "type-checking" of the format. */ 781#define tcg_out_insn(S, FMT, OP, ...) \ 782 glue(tcg_out_insn_,FMT)(S, glue(glue(FMT,_),OP), ## __VA_ARGS__) 783 784 785/* emit 64-bit shifts */ 786static void tcg_out_sh64(TCGContext* s, S390Opcode op, TCGReg dest, 787 TCGReg src, TCGReg sh_reg, int sh_imm) 788{ 789 tcg_out_insn_RSY(s, op, dest, sh_reg, src, sh_imm); 790} 791 792/* emit 32-bit shifts */ 793static void tcg_out_sh32(TCGContext* s, S390Opcode op, TCGReg dest, 794 TCGReg sh_reg, int sh_imm) 795{ 796 tcg_out_insn_RS(s, op, dest, sh_reg, 0, sh_imm); 797} 798 799static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg dst, TCGReg src) 800{ 801 if (src == dst) { 802 return true; 803 } 804 switch (type) { 805 case TCG_TYPE_I32: 806 if (likely(is_general_reg(dst) && is_general_reg(src))) { 807 tcg_out_insn(s, RR, LR, dst, src); 808 break; 809 } 810 /* fallthru */ 811 812 case TCG_TYPE_I64: 813 if (likely(is_general_reg(dst))) { 814 if (likely(is_general_reg(src))) { 815 tcg_out_insn(s, RRE, LGR, dst, src); 816 } else { 817 tcg_out_insn(s, VRSc, VLGV, dst, 0, 0, src, 3); 818 } 819 break; 820 } else if (is_general_reg(src)) { 821 tcg_out_insn(s, VRSb, VLVG, dst, 0, 0, src, 3); 822 break; 823 } 824 /* fallthru */ 825 826 case TCG_TYPE_V64: 827 case TCG_TYPE_V128: 828 tcg_out_insn(s, VRRa, VLR, dst, src, 0); 829 break; 830 831 default: 832 g_assert_not_reached(); 833 } 834 return true; 835} 836 837static const S390Opcode li_insns[4] = { 838 RI_LLILL, RI_LLILH, RI_LLIHL, RI_LLIHH 839}; 840static const S390Opcode oi_insns[4] = { 841 RI_OILL, RI_OILH, RI_OIHL, RI_OIHH 842}; 843static const S390Opcode lif_insns[2] = { 844 RIL_LLILF, RIL_LLIHF, 845}; 846 847/* load a register with an immediate value */ 848static void tcg_out_movi(TCGContext *s, TCGType type, 849 TCGReg ret, tcg_target_long sval) 850{ 851 tcg_target_ulong uval = sval; 852 ptrdiff_t pc_off; 853 int i; 854 855 if (type == TCG_TYPE_I32) { 856 uval = (uint32_t)sval; 857 sval = (int32_t)sval; 858 } 859 860 /* Try all 32-bit insns that can load it in one go. */ 861 if (sval >= -0x8000 && sval < 0x8000) { 862 tcg_out_insn(s, RI, LGHI, ret, sval); 863 return; 864 } 865 866 i = is_const_p16(uval); 867 if (i >= 0) { 868 tcg_out_insn_RI(s, li_insns[i], ret, uval >> (i * 16)); 869 return; 870 } 871 872 /* Try all 48-bit insns that can load it in one go. */ 873 if (sval == (int32_t)sval) { 874 tcg_out_insn(s, RIL, LGFI, ret, sval); 875 return; 876 } 877 878 i = is_const_p32(uval); 879 if (i >= 0) { 880 tcg_out_insn_RIL(s, lif_insns[i], ret, uval >> (i * 32)); 881 return; 882 } 883 884 /* Try for PC-relative address load. For odd addresses, add one. */ 885 pc_off = tcg_pcrel_diff(s, (void *)sval) >> 1; 886 if (pc_off == (int32_t)pc_off) { 887 tcg_out_insn(s, RIL, LARL, ret, pc_off); 888 if (sval & 1) { 889 tcg_out_insn(s, RI, AGHI, ret, 1); 890 } 891 return; 892 } 893 894 /* Otherwise, load it by parts. */ 895 i = is_const_p16((uint32_t)uval); 896 if (i >= 0) { 897 tcg_out_insn_RI(s, li_insns[i], ret, uval >> (i * 16)); 898 } else { 899 tcg_out_insn(s, RIL, LLILF, ret, uval); 900 } 901 uval >>= 32; 902 i = is_const_p16(uval); 903 if (i >= 0) { 904 tcg_out_insn_RI(s, oi_insns[i + 2], ret, uval >> (i * 16)); 905 } else { 906 tcg_out_insn(s, RIL, OIHF, ret, uval); 907 } 908} 909 910/* Emit a load/store type instruction. Inputs are: 911 DATA: The register to be loaded or stored. 912 BASE+OFS: The effective address. 913 OPC_RX: If the operation has an RX format opcode (e.g. STC), otherwise 0. 914 OPC_RXY: The RXY format opcode for the operation (e.g. STCY). */ 915 916static void tcg_out_mem(TCGContext *s, S390Opcode opc_rx, S390Opcode opc_rxy, 917 TCGReg data, TCGReg base, TCGReg index, 918 tcg_target_long ofs) 919{ 920 if (ofs < -0x80000 || ofs >= 0x80000) { 921 /* Combine the low 20 bits of the offset with the actual load insn; 922 the high 44 bits must come from an immediate load. */ 923 tcg_target_long low = ((ofs & 0xfffff) ^ 0x80000) - 0x80000; 924 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - low); 925 ofs = low; 926 927 /* If we were already given an index register, add it in. */ 928 if (index != TCG_REG_NONE) { 929 tcg_out_insn(s, RRE, AGR, TCG_TMP0, index); 930 } 931 index = TCG_TMP0; 932 } 933 934 if (opc_rx && ofs >= 0 && ofs < 0x1000) { 935 tcg_out_insn_RX(s, opc_rx, data, base, index, ofs); 936 } else { 937 tcg_out_insn_RXY(s, opc_rxy, data, base, index, ofs); 938 } 939} 940 941static void tcg_out_vrx_mem(TCGContext *s, S390Opcode opc_vrx, 942 TCGReg data, TCGReg base, TCGReg index, 943 tcg_target_long ofs, int m3) 944{ 945 if (ofs < 0 || ofs >= 0x1000) { 946 if (ofs >= -0x80000 && ofs < 0x80000) { 947 tcg_out_insn(s, RXY, LAY, TCG_TMP0, base, index, ofs); 948 base = TCG_TMP0; 949 index = TCG_REG_NONE; 950 ofs = 0; 951 } else { 952 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs); 953 if (index != TCG_REG_NONE) { 954 tcg_out_insn(s, RRE, AGR, TCG_TMP0, index); 955 } 956 index = TCG_TMP0; 957 ofs = 0; 958 } 959 } 960 tcg_out_insn_VRX(s, opc_vrx, data, base, index, ofs, m3); 961} 962 963/* load data without address translation or endianness conversion */ 964static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg data, 965 TCGReg base, intptr_t ofs) 966{ 967 switch (type) { 968 case TCG_TYPE_I32: 969 if (likely(is_general_reg(data))) { 970 tcg_out_mem(s, RX_L, RXY_LY, data, base, TCG_REG_NONE, ofs); 971 break; 972 } 973 tcg_out_vrx_mem(s, VRX_VLLEZ, data, base, TCG_REG_NONE, ofs, MO_32); 974 break; 975 976 case TCG_TYPE_I64: 977 if (likely(is_general_reg(data))) { 978 tcg_out_mem(s, 0, RXY_LG, data, base, TCG_REG_NONE, ofs); 979 break; 980 } 981 /* fallthru */ 982 983 case TCG_TYPE_V64: 984 tcg_out_vrx_mem(s, VRX_VLLEZ, data, base, TCG_REG_NONE, ofs, MO_64); 985 break; 986 987 case TCG_TYPE_V128: 988 /* Hint quadword aligned. */ 989 tcg_out_vrx_mem(s, VRX_VL, data, base, TCG_REG_NONE, ofs, 4); 990 break; 991 992 default: 993 g_assert_not_reached(); 994 } 995} 996 997static void tcg_out_st(TCGContext *s, TCGType type, TCGReg data, 998 TCGReg base, intptr_t ofs) 999{ 1000 switch (type) { 1001 case TCG_TYPE_I32: 1002 if (likely(is_general_reg(data))) { 1003 tcg_out_mem(s, RX_ST, RXY_STY, data, base, TCG_REG_NONE, ofs); 1004 } else { 1005 tcg_out_vrx_mem(s, VRX_VSTEF, data, base, TCG_REG_NONE, ofs, 1); 1006 } 1007 break; 1008 1009 case TCG_TYPE_I64: 1010 if (likely(is_general_reg(data))) { 1011 tcg_out_mem(s, 0, RXY_STG, data, base, TCG_REG_NONE, ofs); 1012 break; 1013 } 1014 /* fallthru */ 1015 1016 case TCG_TYPE_V64: 1017 tcg_out_vrx_mem(s, VRX_VSTEG, data, base, TCG_REG_NONE, ofs, 0); 1018 break; 1019 1020 case TCG_TYPE_V128: 1021 /* Hint quadword aligned. */ 1022 tcg_out_vrx_mem(s, VRX_VST, data, base, TCG_REG_NONE, ofs, 4); 1023 break; 1024 1025 default: 1026 g_assert_not_reached(); 1027 } 1028} 1029 1030static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 1031 TCGReg base, intptr_t ofs) 1032{ 1033 return false; 1034} 1035 1036static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 1037{ 1038 return false; 1039} 1040 1041static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 1042 tcg_target_long imm) 1043{ 1044 /* This function is only used for passing structs by reference. */ 1045 tcg_out_mem(s, RX_LA, RXY_LAY, rd, rs, TCG_REG_NONE, imm); 1046} 1047 1048static inline void tcg_out_risbg(TCGContext *s, TCGReg dest, TCGReg src, 1049 int msb, int lsb, int ofs, int z) 1050{ 1051 /* Format RIE-f */ 1052 tcg_out16(s, (RIEf_RISBG & 0xff00) | (dest << 4) | src); 1053 tcg_out16(s, (msb << 8) | (z << 7) | lsb); 1054 tcg_out16(s, (ofs << 8) | (RIEf_RISBG & 0xff)); 1055} 1056 1057static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) 1058{ 1059 tcg_out_insn(s, RRE, LGBR, dest, src); 1060} 1061 1062static void tcg_out_ext8u(TCGContext *s, TCGReg dest, TCGReg src) 1063{ 1064 tcg_out_insn(s, RRE, LLGCR, dest, src); 1065} 1066 1067static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) 1068{ 1069 tcg_out_insn(s, RRE, LGHR, dest, src); 1070} 1071 1072static void tcg_out_ext16u(TCGContext *s, TCGReg dest, TCGReg src) 1073{ 1074 tcg_out_insn(s, RRE, LLGHR, dest, src); 1075} 1076 1077static void tcg_out_ext32s(TCGContext *s, TCGReg dest, TCGReg src) 1078{ 1079 tcg_out_insn(s, RRE, LGFR, dest, src); 1080} 1081 1082static void tcg_out_ext32u(TCGContext *s, TCGReg dest, TCGReg src) 1083{ 1084 tcg_out_insn(s, RRE, LLGFR, dest, src); 1085} 1086 1087static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg dest, TCGReg src) 1088{ 1089 tcg_out_ext32s(s, dest, src); 1090} 1091 1092static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg dest, TCGReg src) 1093{ 1094 tcg_out_ext32u(s, dest, src); 1095} 1096 1097static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg dest, TCGReg src) 1098{ 1099 tcg_out_mov(s, TCG_TYPE_I32, dest, src); 1100} 1101 1102static void tgen_andi_risbg(TCGContext *s, TCGReg out, TCGReg in, uint64_t val) 1103{ 1104 int msb, lsb; 1105 if ((val & 0x8000000000000001ull) == 0x8000000000000001ull) { 1106 /* Achieve wraparound by swapping msb and lsb. */ 1107 msb = 64 - ctz64(~val); 1108 lsb = clz64(~val) - 1; 1109 } else { 1110 msb = clz64(val); 1111 lsb = 63 - ctz64(val); 1112 } 1113 tcg_out_risbg(s, out, in, msb, lsb, 0, 1); 1114} 1115 1116static void tgen_andi(TCGContext *s, TCGType type, TCGReg dest, uint64_t val) 1117{ 1118 static const S390Opcode ni_insns[4] = { 1119 RI_NILL, RI_NILH, RI_NIHL, RI_NIHH 1120 }; 1121 static const S390Opcode nif_insns[2] = { 1122 RIL_NILF, RIL_NIHF 1123 }; 1124 uint64_t valid = (type == TCG_TYPE_I32 ? 0xffffffffull : -1ull); 1125 int i; 1126 1127 /* Look for the zero-extensions. */ 1128 if ((val & valid) == 0xffffffff) { 1129 tcg_out_ext32u(s, dest, dest); 1130 return; 1131 } 1132 if ((val & valid) == 0xff) { 1133 tcg_out_ext8u(s, dest, dest); 1134 return; 1135 } 1136 if ((val & valid) == 0xffff) { 1137 tcg_out_ext16u(s, dest, dest); 1138 return; 1139 } 1140 1141 i = is_const_p16(~val & valid); 1142 if (i >= 0) { 1143 tcg_out_insn_RI(s, ni_insns[i], dest, val >> (i * 16)); 1144 return; 1145 } 1146 1147 i = is_const_p32(~val & valid); 1148 tcg_debug_assert(i == 0 || type != TCG_TYPE_I32); 1149 if (i >= 0) { 1150 tcg_out_insn_RIL(s, nif_insns[i], dest, val >> (i * 32)); 1151 return; 1152 } 1153 1154 if (risbg_mask(val)) { 1155 tgen_andi_risbg(s, dest, dest, val); 1156 return; 1157 } 1158 1159 g_assert_not_reached(); 1160} 1161 1162static void tgen_ori(TCGContext *s, TCGReg dest, uint64_t val) 1163{ 1164 static const S390Opcode oif_insns[2] = { 1165 RIL_OILF, RIL_OIHF 1166 }; 1167 1168 int i; 1169 1170 i = is_const_p16(val); 1171 if (i >= 0) { 1172 tcg_out_insn_RI(s, oi_insns[i], dest, val >> (i * 16)); 1173 return; 1174 } 1175 1176 i = is_const_p32(val); 1177 if (i >= 0) { 1178 tcg_out_insn_RIL(s, oif_insns[i], dest, val >> (i * 32)); 1179 return; 1180 } 1181 1182 g_assert_not_reached(); 1183} 1184 1185static void tgen_xori(TCGContext *s, TCGReg dest, uint64_t val) 1186{ 1187 switch (is_const_p32(val)) { 1188 case 0: 1189 tcg_out_insn(s, RIL, XILF, dest, val); 1190 break; 1191 case 1: 1192 tcg_out_insn(s, RIL, XIHF, dest, val >> 32); 1193 break; 1194 default: 1195 g_assert_not_reached(); 1196 } 1197} 1198 1199static int tgen_cmp2(TCGContext *s, TCGType type, TCGCond c, TCGReg r1, 1200 TCGArg c2, bool c2const, bool need_carry, int *inv_cc) 1201{ 1202 bool is_unsigned = is_unsigned_cond(c); 1203 TCGCond inv_c = tcg_invert_cond(c); 1204 S390Opcode op; 1205 1206 if (c2const) { 1207 if (c2 == 0) { 1208 if (!(is_unsigned && need_carry)) { 1209 if (type == TCG_TYPE_I32) { 1210 tcg_out_insn(s, RR, LTR, r1, r1); 1211 } else { 1212 tcg_out_insn(s, RRE, LTGR, r1, r1); 1213 } 1214 *inv_cc = tcg_cond_to_ltr_cond[inv_c]; 1215 return tcg_cond_to_ltr_cond[c]; 1216 } 1217 } 1218 1219 if (!is_unsigned && c2 == (int16_t)c2) { 1220 op = (type == TCG_TYPE_I32 ? RI_CHI : RI_CGHI); 1221 tcg_out_insn_RI(s, op, r1, c2); 1222 goto exit; 1223 } 1224 1225 if (type == TCG_TYPE_I32) { 1226 op = (is_unsigned ? RIL_CLFI : RIL_CFI); 1227 tcg_out_insn_RIL(s, op, r1, c2); 1228 goto exit; 1229 } 1230 1231 /* 1232 * Constraints are for a signed 33-bit operand, which is a 1233 * convenient superset of this signed/unsigned test. 1234 */ 1235 if (c2 == (is_unsigned ? (TCGArg)(uint32_t)c2 : (TCGArg)(int32_t)c2)) { 1236 op = (is_unsigned ? RIL_CLGFI : RIL_CGFI); 1237 tcg_out_insn_RIL(s, op, r1, c2); 1238 goto exit; 1239 } 1240 1241 /* Load everything else into a register. */ 1242 tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, c2); 1243 c2 = TCG_TMP0; 1244 } 1245 1246 if (type == TCG_TYPE_I32) { 1247 op = (is_unsigned ? RR_CLR : RR_CR); 1248 tcg_out_insn_RR(s, op, r1, c2); 1249 } else { 1250 op = (is_unsigned ? RRE_CLGR : RRE_CGR); 1251 tcg_out_insn_RRE(s, op, r1, c2); 1252 } 1253 1254 exit: 1255 *inv_cc = tcg_cond_to_s390_cond[inv_c]; 1256 return tcg_cond_to_s390_cond[c]; 1257} 1258 1259static int tgen_cmp(TCGContext *s, TCGType type, TCGCond c, TCGReg r1, 1260 TCGArg c2, bool c2const, bool need_carry) 1261{ 1262 int inv_cc; 1263 return tgen_cmp2(s, type, c, r1, c2, c2const, need_carry, &inv_cc); 1264} 1265 1266static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, 1267 TCGReg dest, TCGReg c1, TCGArg c2, 1268 bool c2const, bool neg) 1269{ 1270 int cc; 1271 1272 /* With LOC2, we can always emit the minimum 3 insns. */ 1273 if (HAVE_FACILITY(LOAD_ON_COND2)) { 1274 /* Emit: d = 0, d = (cc ? 1 : d). */ 1275 cc = tgen_cmp(s, type, cond, c1, c2, c2const, false); 1276 tcg_out_movi(s, TCG_TYPE_I64, dest, 0); 1277 tcg_out_insn(s, RIEg, LOCGHI, dest, neg ? -1 : 1, cc); 1278 return; 1279 } 1280 1281 switch (cond) { 1282 case TCG_COND_GEU: 1283 case TCG_COND_LTU: 1284 case TCG_COND_LT: 1285 case TCG_COND_GE: 1286 /* Swap operands so that we can use LEU/GTU/GT/LE. */ 1287 if (!c2const) { 1288 TCGReg t = c1; 1289 c1 = c2; 1290 c2 = t; 1291 cond = tcg_swap_cond(cond); 1292 } 1293 break; 1294 default: 1295 break; 1296 } 1297 1298 switch (cond) { 1299 case TCG_COND_NE: 1300 /* X != 0 is X > 0. */ 1301 if (c2const && c2 == 0) { 1302 cond = TCG_COND_GTU; 1303 } else { 1304 break; 1305 } 1306 /* fallthru */ 1307 1308 case TCG_COND_GTU: 1309 case TCG_COND_GT: 1310 /* 1311 * The result of a compare has CC=2 for GT and CC=3 unused. 1312 * ADD LOGICAL WITH CARRY considers (CC & 2) the carry bit. 1313 */ 1314 tgen_cmp(s, type, cond, c1, c2, c2const, true); 1315 tcg_out_movi(s, type, dest, 0); 1316 tcg_out_insn(s, RRE, ALCGR, dest, dest); 1317 if (neg) { 1318 if (type == TCG_TYPE_I32) { 1319 tcg_out_insn(s, RR, LCR, dest, dest); 1320 } else { 1321 tcg_out_insn(s, RRE, LCGR, dest, dest); 1322 } 1323 } 1324 return; 1325 1326 case TCG_COND_EQ: 1327 /* X == 0 is X <= 0. */ 1328 if (c2const && c2 == 0) { 1329 cond = TCG_COND_LEU; 1330 } else { 1331 break; 1332 } 1333 /* fallthru */ 1334 1335 case TCG_COND_LEU: 1336 case TCG_COND_LE: 1337 /* 1338 * As above, but we're looking for borrow, or !carry. 1339 * The second insn computes d - d - borrow, or -1 for true 1340 * and 0 for false. So we must mask to 1 bit afterward. 1341 */ 1342 tgen_cmp(s, type, cond, c1, c2, c2const, true); 1343 tcg_out_insn(s, RRE, SLBGR, dest, dest); 1344 if (!neg) { 1345 tgen_andi(s, type, dest, 1); 1346 } 1347 return; 1348 1349 default: 1350 g_assert_not_reached(); 1351 } 1352 1353 cc = tgen_cmp(s, type, cond, c1, c2, c2const, false); 1354 /* Emit: d = 0, t = 1, d = (cc ? t : d). */ 1355 tcg_out_movi(s, TCG_TYPE_I64, dest, 0); 1356 tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, neg ? -1 : 1); 1357 tcg_out_insn(s, RRFc, LOCGR, dest, TCG_TMP0, cc); 1358} 1359 1360static void tgen_movcond_int(TCGContext *s, TCGType type, TCGReg dest, 1361 TCGArg v3, int v3const, TCGReg v4, 1362 int cc, int inv_cc) 1363{ 1364 TCGReg src; 1365 1366 if (v3const) { 1367 if (dest == v4) { 1368 if (HAVE_FACILITY(LOAD_ON_COND2)) { 1369 /* Emit: if (cc) dest = v3. */ 1370 tcg_out_insn(s, RIEg, LOCGHI, dest, v3, cc); 1371 return; 1372 } 1373 tcg_out_insn(s, RI, LGHI, TCG_TMP0, v3); 1374 src = TCG_TMP0; 1375 } else { 1376 /* LGR+LOCGHI is larger than LGHI+LOCGR. */ 1377 tcg_out_insn(s, RI, LGHI, dest, v3); 1378 cc = inv_cc; 1379 src = v4; 1380 } 1381 } else { 1382 if (HAVE_FACILITY(MISC_INSN_EXT3)) { 1383 /* Emit: dest = cc ? v3 : v4. */ 1384 tcg_out_insn(s, RRFam, SELGR, dest, v3, v4, cc); 1385 return; 1386 } 1387 if (dest == v4) { 1388 src = v3; 1389 } else { 1390 tcg_out_mov(s, type, dest, v3); 1391 cc = inv_cc; 1392 src = v4; 1393 } 1394 } 1395 1396 /* Emit: if (cc) dest = src. */ 1397 tcg_out_insn(s, RRFc, LOCGR, dest, src, cc); 1398} 1399 1400static void tgen_movcond(TCGContext *s, TCGType type, TCGCond c, TCGReg dest, 1401 TCGReg c1, TCGArg c2, int c2const, 1402 TCGArg v3, int v3const, TCGReg v4) 1403{ 1404 int cc, inv_cc; 1405 1406 cc = tgen_cmp2(s, type, c, c1, c2, c2const, false, &inv_cc); 1407 tgen_movcond_int(s, type, dest, v3, v3const, v4, cc, inv_cc); 1408} 1409 1410static void tgen_clz(TCGContext *s, TCGReg dest, TCGReg a1, 1411 TCGArg a2, int a2const) 1412{ 1413 /* Since this sets both R and R+1, we have no choice but to store the 1414 result into R0, allowing R1 == TCG_TMP0 to be clobbered as well. */ 1415 QEMU_BUILD_BUG_ON(TCG_TMP0 != TCG_REG_R1); 1416 tcg_out_insn(s, RRE, FLOGR, TCG_REG_R0, a1); 1417 1418 if (a2const && a2 == 64) { 1419 tcg_out_mov(s, TCG_TYPE_I64, dest, TCG_REG_R0); 1420 return; 1421 } 1422 1423 /* 1424 * Conditions from FLOGR are: 1425 * 2 -> one bit found 1426 * 8 -> no one bit found 1427 */ 1428 tgen_movcond_int(s, TCG_TYPE_I64, dest, a2, a2const, TCG_REG_R0, 8, 2); 1429} 1430 1431static void tgen_ctpop(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) 1432{ 1433 /* With MIE3, and bit 0 of m4 set, we get the complete result. */ 1434 if (HAVE_FACILITY(MISC_INSN_EXT3)) { 1435 if (type == TCG_TYPE_I32) { 1436 tcg_out_ext32u(s, dest, src); 1437 src = dest; 1438 } 1439 tcg_out_insn(s, RRFc, POPCNT, dest, src, 8); 1440 return; 1441 } 1442 1443 /* Without MIE3, each byte gets the count of bits for the byte. */ 1444 tcg_out_insn(s, RRFc, POPCNT, dest, src, 0); 1445 1446 /* Multiply to sum each byte at the top of the word. */ 1447 if (type == TCG_TYPE_I32) { 1448 tcg_out_insn(s, RIL, MSFI, dest, 0x01010101); 1449 tcg_out_sh32(s, RS_SRL, dest, TCG_REG_NONE, 24); 1450 } else { 1451 tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 0x0101010101010101ull); 1452 tcg_out_insn(s, RRE, MSGR, dest, TCG_TMP0); 1453 tcg_out_sh64(s, RSY_SRLG, dest, dest, TCG_REG_NONE, 56); 1454 } 1455} 1456 1457static void tgen_deposit(TCGContext *s, TCGReg dest, TCGReg src, 1458 int ofs, int len, int z) 1459{ 1460 int lsb = (63 - ofs); 1461 int msb = lsb - (len - 1); 1462 tcg_out_risbg(s, dest, src, msb, lsb, ofs, z); 1463} 1464 1465static void tgen_extract(TCGContext *s, TCGReg dest, TCGReg src, 1466 int ofs, int len) 1467{ 1468 tcg_out_risbg(s, dest, src, 64 - len, 63, 64 - ofs, 1); 1469} 1470 1471static void tgen_gotoi(TCGContext *s, int cc, const tcg_insn_unit *dest) 1472{ 1473 ptrdiff_t off = tcg_pcrel_diff(s, dest) >> 1; 1474 if (off == (int16_t)off) { 1475 tcg_out_insn(s, RI, BRC, cc, off); 1476 } else if (off == (int32_t)off) { 1477 tcg_out_insn(s, RIL, BRCL, cc, off); 1478 } else { 1479 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)dest); 1480 tcg_out_insn(s, RR, BCR, cc, TCG_TMP0); 1481 } 1482} 1483 1484static void tgen_branch(TCGContext *s, int cc, TCGLabel *l) 1485{ 1486 if (l->has_value) { 1487 tgen_gotoi(s, cc, l->u.value_ptr); 1488 } else { 1489 tcg_out16(s, RI_BRC | (cc << 4)); 1490 tcg_out_reloc(s, s->code_ptr, R_390_PC16DBL, l, 2); 1491 s->code_ptr += 1; 1492 } 1493} 1494 1495static void tgen_compare_branch(TCGContext *s, S390Opcode opc, int cc, 1496 TCGReg r1, TCGReg r2, TCGLabel *l) 1497{ 1498 tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2); 1499 /* Format RIE-b */ 1500 tcg_out16(s, (opc & 0xff00) | (r1 << 4) | r2); 1501 tcg_out16(s, 0); 1502 tcg_out16(s, cc << 12 | (opc & 0xff)); 1503} 1504 1505static void tgen_compare_imm_branch(TCGContext *s, S390Opcode opc, int cc, 1506 TCGReg r1, int i2, TCGLabel *l) 1507{ 1508 tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2); 1509 /* Format RIE-c */ 1510 tcg_out16(s, (opc & 0xff00) | (r1 << 4) | cc); 1511 tcg_out16(s, 0); 1512 tcg_out16(s, (i2 << 8) | (opc & 0xff)); 1513} 1514 1515static void tgen_brcond(TCGContext *s, TCGType type, TCGCond c, 1516 TCGReg r1, TCGArg c2, int c2const, TCGLabel *l) 1517{ 1518 int cc; 1519 bool is_unsigned = is_unsigned_cond(c); 1520 bool in_range; 1521 S390Opcode opc; 1522 1523 cc = tcg_cond_to_s390_cond[c]; 1524 1525 if (!c2const) { 1526 opc = (type == TCG_TYPE_I32 1527 ? (is_unsigned ? RIEb_CLRJ : RIEb_CRJ) 1528 : (is_unsigned ? RIEb_CLGRJ : RIEb_CGRJ)); 1529 tgen_compare_branch(s, opc, cc, r1, c2, l); 1530 return; 1531 } 1532 1533 /* 1534 * COMPARE IMMEDIATE AND BRANCH RELATIVE has an 8-bit immediate field. 1535 * If the immediate we've been given does not fit that range, we'll 1536 * fall back to separate compare and branch instructions using the 1537 * larger comparison range afforded by COMPARE IMMEDIATE. 1538 */ 1539 if (type == TCG_TYPE_I32) { 1540 if (is_unsigned) { 1541 opc = RIEc_CLIJ; 1542 in_range = (uint32_t)c2 == (uint8_t)c2; 1543 } else { 1544 opc = RIEc_CIJ; 1545 in_range = (int32_t)c2 == (int8_t)c2; 1546 } 1547 } else { 1548 if (is_unsigned) { 1549 opc = RIEc_CLGIJ; 1550 in_range = (uint64_t)c2 == (uint8_t)c2; 1551 } else { 1552 opc = RIEc_CGIJ; 1553 in_range = (int64_t)c2 == (int8_t)c2; 1554 } 1555 } 1556 if (in_range) { 1557 tgen_compare_imm_branch(s, opc, cc, r1, c2, l); 1558 return; 1559 } 1560 1561 cc = tgen_cmp(s, type, c, r1, c2, c2const, false); 1562 tgen_branch(s, cc, l); 1563} 1564 1565static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *dest) 1566{ 1567 ptrdiff_t off = tcg_pcrel_diff(s, dest) >> 1; 1568 if (off == (int32_t)off) { 1569 tcg_out_insn(s, RIL, BRASL, TCG_REG_R14, off); 1570 } else { 1571 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)dest); 1572 tcg_out_insn(s, RR, BASR, TCG_REG_R14, TCG_TMP0); 1573 } 1574} 1575 1576static void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest, 1577 const TCGHelperInfo *info) 1578{ 1579 tcg_out_call_int(s, dest); 1580} 1581 1582typedef struct { 1583 TCGReg base; 1584 TCGReg index; 1585 int disp; 1586 TCGAtomAlign aa; 1587} HostAddress; 1588 1589bool tcg_target_has_memory_bswap(MemOp memop) 1590{ 1591 TCGAtomAlign aa; 1592 1593 if ((memop & MO_SIZE) <= MO_64) { 1594 return true; 1595 } 1596 1597 /* 1598 * Reject 16-byte memop with 16-byte atomicity, 1599 * but do allow a pair of 64-bit operations. 1600 */ 1601 aa = atom_and_align_for_opc(tcg_ctx, memop, MO_ATOM_IFALIGN, true); 1602 return aa.atom <= MO_64; 1603} 1604 1605static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg data, 1606 HostAddress h) 1607{ 1608 switch (opc & (MO_SSIZE | MO_BSWAP)) { 1609 case MO_UB: 1610 tcg_out_insn(s, RXY, LLGC, data, h.base, h.index, h.disp); 1611 break; 1612 case MO_SB: 1613 tcg_out_insn(s, RXY, LGB, data, h.base, h.index, h.disp); 1614 break; 1615 1616 case MO_UW | MO_BSWAP: 1617 /* swapped unsigned halfword load with upper bits zeroed */ 1618 tcg_out_insn(s, RXY, LRVH, data, h.base, h.index, h.disp); 1619 tcg_out_ext16u(s, data, data); 1620 break; 1621 case MO_UW: 1622 tcg_out_insn(s, RXY, LLGH, data, h.base, h.index, h.disp); 1623 break; 1624 1625 case MO_SW | MO_BSWAP: 1626 /* swapped sign-extended halfword load */ 1627 tcg_out_insn(s, RXY, LRVH, data, h.base, h.index, h.disp); 1628 tcg_out_ext16s(s, TCG_TYPE_REG, data, data); 1629 break; 1630 case MO_SW: 1631 tcg_out_insn(s, RXY, LGH, data, h.base, h.index, h.disp); 1632 break; 1633 1634 case MO_UL | MO_BSWAP: 1635 /* swapped unsigned int load with upper bits zeroed */ 1636 tcg_out_insn(s, RXY, LRV, data, h.base, h.index, h.disp); 1637 tcg_out_ext32u(s, data, data); 1638 break; 1639 case MO_UL: 1640 tcg_out_insn(s, RXY, LLGF, data, h.base, h.index, h.disp); 1641 break; 1642 1643 case MO_SL | MO_BSWAP: 1644 /* swapped sign-extended int load */ 1645 tcg_out_insn(s, RXY, LRV, data, h.base, h.index, h.disp); 1646 tcg_out_ext32s(s, data, data); 1647 break; 1648 case MO_SL: 1649 tcg_out_insn(s, RXY, LGF, data, h.base, h.index, h.disp); 1650 break; 1651 1652 case MO_UQ | MO_BSWAP: 1653 tcg_out_insn(s, RXY, LRVG, data, h.base, h.index, h.disp); 1654 break; 1655 case MO_UQ: 1656 tcg_out_insn(s, RXY, LG, data, h.base, h.index, h.disp); 1657 break; 1658 1659 default: 1660 g_assert_not_reached(); 1661 } 1662} 1663 1664static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg data, 1665 HostAddress h) 1666{ 1667 switch (opc & (MO_SIZE | MO_BSWAP)) { 1668 case MO_UB: 1669 if (h.disp >= 0 && h.disp < 0x1000) { 1670 tcg_out_insn(s, RX, STC, data, h.base, h.index, h.disp); 1671 } else { 1672 tcg_out_insn(s, RXY, STCY, data, h.base, h.index, h.disp); 1673 } 1674 break; 1675 1676 case MO_UW | MO_BSWAP: 1677 tcg_out_insn(s, RXY, STRVH, data, h.base, h.index, h.disp); 1678 break; 1679 case MO_UW: 1680 if (h.disp >= 0 && h.disp < 0x1000) { 1681 tcg_out_insn(s, RX, STH, data, h.base, h.index, h.disp); 1682 } else { 1683 tcg_out_insn(s, RXY, STHY, data, h.base, h.index, h.disp); 1684 } 1685 break; 1686 1687 case MO_UL | MO_BSWAP: 1688 tcg_out_insn(s, RXY, STRV, data, h.base, h.index, h.disp); 1689 break; 1690 case MO_UL: 1691 if (h.disp >= 0 && h.disp < 0x1000) { 1692 tcg_out_insn(s, RX, ST, data, h.base, h.index, h.disp); 1693 } else { 1694 tcg_out_insn(s, RXY, STY, data, h.base, h.index, h.disp); 1695 } 1696 break; 1697 1698 case MO_UQ | MO_BSWAP: 1699 tcg_out_insn(s, RXY, STRVG, data, h.base, h.index, h.disp); 1700 break; 1701 case MO_UQ: 1702 tcg_out_insn(s, RXY, STG, data, h.base, h.index, h.disp); 1703 break; 1704 1705 default: 1706 g_assert_not_reached(); 1707 } 1708} 1709 1710static const TCGLdstHelperParam ldst_helper_param = { 1711 .ntmp = 1, .tmp = { TCG_TMP0 } 1712}; 1713 1714static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1715{ 1716 MemOp opc = get_memop(lb->oi); 1717 1718 if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL, 1719 (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 2)) { 1720 return false; 1721 } 1722 1723 tcg_out_ld_helper_args(s, lb, &ldst_helper_param); 1724 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE]); 1725 tcg_out_ld_helper_ret(s, lb, false, &ldst_helper_param); 1726 1727 tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr); 1728 return true; 1729} 1730 1731static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1732{ 1733 MemOp opc = get_memop(lb->oi); 1734 1735 if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL, 1736 (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 2)) { 1737 return false; 1738 } 1739 1740 tcg_out_st_helper_args(s, lb, &ldst_helper_param); 1741 tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE]); 1742 1743 tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr); 1744 return true; 1745} 1746 1747/* We're expecting to use a 20-bit negative offset on the tlb memory ops. */ 1748#define MIN_TLB_MASK_TABLE_OFS -(1 << 19) 1749 1750/* 1751 * For system-mode, perform the TLB load and compare. 1752 * For user-mode, perform any required alignment tests. 1753 * In both cases, return a TCGLabelQemuLdst structure if the slow path 1754 * is required and fill in @h with the host address for the fast path. 1755 */ 1756static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 1757 TCGReg addr_reg, MemOpIdx oi, 1758 bool is_ld) 1759{ 1760 TCGType addr_type = s->addr_type; 1761 TCGLabelQemuLdst *ldst = NULL; 1762 MemOp opc = get_memop(oi); 1763 MemOp s_bits = opc & MO_SIZE; 1764 unsigned a_mask; 1765 1766 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, s_bits == MO_128); 1767 a_mask = (1 << h->aa.align) - 1; 1768 1769 if (tcg_use_softmmu) { 1770 unsigned s_mask = (1 << s_bits) - 1; 1771 int mem_index = get_mmuidx(oi); 1772 int fast_off = tlb_mask_table_ofs(s, mem_index); 1773 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); 1774 int table_off = fast_off + offsetof(CPUTLBDescFast, table); 1775 int ofs, a_off; 1776 uint64_t tlb_mask; 1777 1778 ldst = new_ldst_label(s); 1779 ldst->is_ld = is_ld; 1780 ldst->oi = oi; 1781 ldst->addrlo_reg = addr_reg; 1782 1783 tcg_out_sh64(s, RSY_SRLG, TCG_TMP0, addr_reg, TCG_REG_NONE, 1784 s->page_bits - CPU_TLB_ENTRY_BITS); 1785 1786 tcg_out_insn(s, RXY, NG, TCG_TMP0, TCG_AREG0, TCG_REG_NONE, mask_off); 1787 tcg_out_insn(s, RXY, AG, TCG_TMP0, TCG_AREG0, TCG_REG_NONE, table_off); 1788 1789 /* 1790 * For aligned accesses, we check the first byte and include the 1791 * alignment bits within the address. For unaligned access, we 1792 * check that we don't cross pages using the address of the last 1793 * byte of the access. 1794 */ 1795 a_off = (a_mask >= s_mask ? 0 : s_mask - a_mask); 1796 tlb_mask = (uint64_t)s->page_mask | a_mask; 1797 if (a_off == 0) { 1798 tgen_andi_risbg(s, TCG_REG_R0, addr_reg, tlb_mask); 1799 } else { 1800 tcg_out_insn(s, RX, LA, TCG_REG_R0, addr_reg, TCG_REG_NONE, a_off); 1801 tgen_andi(s, addr_type, TCG_REG_R0, tlb_mask); 1802 } 1803 1804 if (is_ld) { 1805 ofs = offsetof(CPUTLBEntry, addr_read); 1806 } else { 1807 ofs = offsetof(CPUTLBEntry, addr_write); 1808 } 1809 if (addr_type == TCG_TYPE_I32) { 1810 ofs += HOST_BIG_ENDIAN * 4; 1811 tcg_out_insn(s, RX, C, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs); 1812 } else { 1813 tcg_out_insn(s, RXY, CG, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs); 1814 } 1815 1816 tcg_out16(s, RI_BRC | (S390_CC_NE << 4)); 1817 ldst->label_ptr[0] = s->code_ptr++; 1818 1819 h->index = TCG_TMP0; 1820 tcg_out_insn(s, RXY, LG, h->index, TCG_TMP0, TCG_REG_NONE, 1821 offsetof(CPUTLBEntry, addend)); 1822 1823 if (addr_type == TCG_TYPE_I32) { 1824 tcg_out_insn(s, RRE, ALGFR, h->index, addr_reg); 1825 h->base = TCG_REG_NONE; 1826 } else { 1827 h->base = addr_reg; 1828 } 1829 h->disp = 0; 1830 } else { 1831 if (a_mask) { 1832 ldst = new_ldst_label(s); 1833 ldst->is_ld = is_ld; 1834 ldst->oi = oi; 1835 ldst->addrlo_reg = addr_reg; 1836 1837 /* We are expecting a_bits to max out at 7, much lower than TMLL. */ 1838 tcg_debug_assert(a_mask <= 0xffff); 1839 tcg_out_insn(s, RI, TMLL, addr_reg, a_mask); 1840 1841 tcg_out16(s, RI_BRC | (7 << 4)); /* CC in {1,2,3} */ 1842 ldst->label_ptr[0] = s->code_ptr++; 1843 } 1844 1845 h->base = addr_reg; 1846 if (addr_type == TCG_TYPE_I32) { 1847 tcg_out_ext32u(s, TCG_TMP0, addr_reg); 1848 h->base = TCG_TMP0; 1849 } 1850 if (guest_base < 0x80000) { 1851 h->index = TCG_REG_NONE; 1852 h->disp = guest_base; 1853 } else { 1854 h->index = TCG_GUEST_BASE_REG; 1855 h->disp = 0; 1856 } 1857 } 1858 1859 return ldst; 1860} 1861 1862static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_reg, 1863 MemOpIdx oi, TCGType data_type) 1864{ 1865 TCGLabelQemuLdst *ldst; 1866 HostAddress h; 1867 1868 ldst = prepare_host_addr(s, &h, addr_reg, oi, true); 1869 tcg_out_qemu_ld_direct(s, get_memop(oi), data_reg, h); 1870 1871 if (ldst) { 1872 ldst->type = data_type; 1873 ldst->datalo_reg = data_reg; 1874 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1875 } 1876} 1877 1878static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_reg, 1879 MemOpIdx oi, TCGType data_type) 1880{ 1881 TCGLabelQemuLdst *ldst; 1882 HostAddress h; 1883 1884 ldst = prepare_host_addr(s, &h, addr_reg, oi, false); 1885 tcg_out_qemu_st_direct(s, get_memop(oi), data_reg, h); 1886 1887 if (ldst) { 1888 ldst->type = data_type; 1889 ldst->datalo_reg = data_reg; 1890 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1891 } 1892} 1893 1894static void tcg_out_qemu_ldst_i128(TCGContext *s, TCGReg datalo, TCGReg datahi, 1895 TCGReg addr_reg, MemOpIdx oi, bool is_ld) 1896{ 1897 TCGLabel *l1 = NULL, *l2 = NULL; 1898 TCGLabelQemuLdst *ldst; 1899 HostAddress h; 1900 bool need_bswap; 1901 bool use_pair; 1902 S390Opcode insn; 1903 1904 ldst = prepare_host_addr(s, &h, addr_reg, oi, is_ld); 1905 1906 use_pair = h.aa.atom < MO_128; 1907 need_bswap = get_memop(oi) & MO_BSWAP; 1908 1909 if (!use_pair) { 1910 /* 1911 * Atomicity requires we use LPQ. If we've already checked for 1912 * 16-byte alignment, that's all we need. If we arrive with 1913 * lesser alignment, we have determined that less than 16-byte 1914 * alignment can be satisfied with two 8-byte loads. 1915 */ 1916 if (h.aa.align < MO_128) { 1917 use_pair = true; 1918 l1 = gen_new_label(); 1919 l2 = gen_new_label(); 1920 1921 tcg_out_insn(s, RI, TMLL, addr_reg, 15); 1922 tgen_branch(s, 7, l1); /* CC in {1,2,3} */ 1923 } 1924 1925 tcg_debug_assert(!need_bswap); 1926 tcg_debug_assert(datalo & 1); 1927 tcg_debug_assert(datahi == datalo - 1); 1928 insn = is_ld ? RXY_LPQ : RXY_STPQ; 1929 tcg_out_insn_RXY(s, insn, datahi, h.base, h.index, h.disp); 1930 1931 if (use_pair) { 1932 tgen_branch(s, S390_CC_ALWAYS, l2); 1933 tcg_out_label(s, l1); 1934 } 1935 } 1936 if (use_pair) { 1937 TCGReg d1, d2; 1938 1939 if (need_bswap) { 1940 d1 = datalo, d2 = datahi; 1941 insn = is_ld ? RXY_LRVG : RXY_STRVG; 1942 } else { 1943 d1 = datahi, d2 = datalo; 1944 insn = is_ld ? RXY_LG : RXY_STG; 1945 } 1946 1947 if (h.base == d1 || h.index == d1) { 1948 tcg_out_insn(s, RXY, LAY, TCG_TMP0, h.base, h.index, h.disp); 1949 h.base = TCG_TMP0; 1950 h.index = TCG_REG_NONE; 1951 h.disp = 0; 1952 } 1953 tcg_out_insn_RXY(s, insn, d1, h.base, h.index, h.disp); 1954 tcg_out_insn_RXY(s, insn, d2, h.base, h.index, h.disp + 8); 1955 } 1956 if (l2) { 1957 tcg_out_label(s, l2); 1958 } 1959 1960 if (ldst) { 1961 ldst->type = TCG_TYPE_I128; 1962 ldst->datalo_reg = datalo; 1963 ldst->datahi_reg = datahi; 1964 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1965 } 1966} 1967 1968static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) 1969{ 1970 /* Reuse the zeroing that exists for goto_ptr. */ 1971 if (a0 == 0) { 1972 tgen_gotoi(s, S390_CC_ALWAYS, tcg_code_gen_epilogue); 1973 } else { 1974 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, a0); 1975 tgen_gotoi(s, S390_CC_ALWAYS, tb_ret_addr); 1976 } 1977} 1978 1979static void tcg_out_goto_tb(TCGContext *s, int which) 1980{ 1981 /* 1982 * Branch displacement must be aligned for atomic patching; 1983 * see if we need to add extra nop before branch 1984 */ 1985 if (!QEMU_PTR_IS_ALIGNED(s->code_ptr + 1, 4)) { 1986 tcg_out16(s, NOP); 1987 } 1988 tcg_out16(s, RIL_BRCL | (S390_CC_ALWAYS << 4)); 1989 set_jmp_insn_offset(s, which); 1990 s->code_ptr += 2; 1991 set_jmp_reset_offset(s, which); 1992} 1993 1994void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1995 uintptr_t jmp_rx, uintptr_t jmp_rw) 1996{ 1997 if (!HAVE_FACILITY(GEN_INST_EXT)) { 1998 return; 1999 } 2000 /* patch the branch destination */ 2001 uintptr_t addr = tb->jmp_target_addr[n]; 2002 intptr_t disp = addr - (jmp_rx - 2); 2003 qatomic_set((int32_t *)jmp_rw, disp / 2); 2004 /* no need to flush icache explicitly */ 2005} 2006 2007# define OP_32_64(x) \ 2008 case glue(glue(INDEX_op_,x),_i32): \ 2009 case glue(glue(INDEX_op_,x),_i64) 2010 2011static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, 2012 const TCGArg args[TCG_MAX_OP_ARGS], 2013 const int const_args[TCG_MAX_OP_ARGS]) 2014{ 2015 S390Opcode op, op2; 2016 TCGArg a0, a1, a2; 2017 2018 switch (opc) { 2019 case INDEX_op_goto_ptr: 2020 a0 = args[0]; 2021 tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, a0); 2022 break; 2023 2024 OP_32_64(ld8u): 2025 /* ??? LLC (RXY format) is only present with the extended-immediate 2026 facility, whereas LLGC is always present. */ 2027 tcg_out_mem(s, 0, RXY_LLGC, args[0], args[1], TCG_REG_NONE, args[2]); 2028 break; 2029 2030 OP_32_64(ld8s): 2031 /* ??? LB is no smaller than LGB, so no point to using it. */ 2032 tcg_out_mem(s, 0, RXY_LGB, args[0], args[1], TCG_REG_NONE, args[2]); 2033 break; 2034 2035 OP_32_64(ld16u): 2036 /* ??? LLH (RXY format) is only present with the extended-immediate 2037 facility, whereas LLGH is always present. */ 2038 tcg_out_mem(s, 0, RXY_LLGH, args[0], args[1], TCG_REG_NONE, args[2]); 2039 break; 2040 2041 case INDEX_op_ld16s_i32: 2042 tcg_out_mem(s, RX_LH, RXY_LHY, args[0], args[1], TCG_REG_NONE, args[2]); 2043 break; 2044 2045 case INDEX_op_ld_i32: 2046 tcg_out_ld(s, TCG_TYPE_I32, args[0], args[1], args[2]); 2047 break; 2048 2049 OP_32_64(st8): 2050 tcg_out_mem(s, RX_STC, RXY_STCY, args[0], args[1], 2051 TCG_REG_NONE, args[2]); 2052 break; 2053 2054 OP_32_64(st16): 2055 tcg_out_mem(s, RX_STH, RXY_STHY, args[0], args[1], 2056 TCG_REG_NONE, args[2]); 2057 break; 2058 2059 case INDEX_op_st_i32: 2060 tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]); 2061 break; 2062 2063 case INDEX_op_add_i32: 2064 a0 = args[0], a1 = args[1], a2 = (int32_t)args[2]; 2065 if (const_args[2]) { 2066 do_addi_32: 2067 if (a0 == a1) { 2068 if (a2 == (int16_t)a2) { 2069 tcg_out_insn(s, RI, AHI, a0, a2); 2070 break; 2071 } 2072 tcg_out_insn(s, RIL, AFI, a0, a2); 2073 break; 2074 } 2075 tcg_out_mem(s, RX_LA, RXY_LAY, a0, a1, TCG_REG_NONE, a2); 2076 } else if (a0 == a1) { 2077 tcg_out_insn(s, RR, AR, a0, a2); 2078 } else { 2079 tcg_out_insn(s, RX, LA, a0, a1, a2, 0); 2080 } 2081 break; 2082 case INDEX_op_sub_i32: 2083 a0 = args[0], a1 = args[1], a2 = (int32_t)args[2]; 2084 if (const_args[2]) { 2085 a2 = -a2; 2086 goto do_addi_32; 2087 } else if (a0 == a1) { 2088 tcg_out_insn(s, RR, SR, a0, a2); 2089 } else { 2090 tcg_out_insn(s, RRFa, SRK, a0, a1, a2); 2091 } 2092 break; 2093 2094 case INDEX_op_and_i32: 2095 a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; 2096 if (const_args[2]) { 2097 tcg_out_mov(s, TCG_TYPE_I32, a0, a1); 2098 tgen_andi(s, TCG_TYPE_I32, a0, a2); 2099 } else if (a0 == a1) { 2100 tcg_out_insn(s, RR, NR, a0, a2); 2101 } else { 2102 tcg_out_insn(s, RRFa, NRK, a0, a1, a2); 2103 } 2104 break; 2105 case INDEX_op_or_i32: 2106 a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; 2107 if (const_args[2]) { 2108 tcg_out_mov(s, TCG_TYPE_I32, a0, a1); 2109 tgen_ori(s, a0, a2); 2110 } else if (a0 == a1) { 2111 tcg_out_insn(s, RR, OR, a0, a2); 2112 } else { 2113 tcg_out_insn(s, RRFa, ORK, a0, a1, a2); 2114 } 2115 break; 2116 case INDEX_op_xor_i32: 2117 a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; 2118 if (const_args[2]) { 2119 tcg_out_mov(s, TCG_TYPE_I32, a0, a1); 2120 tcg_out_insn(s, RIL, XILF, a0, a2); 2121 } else if (a0 == a1) { 2122 tcg_out_insn(s, RR, XR, args[0], args[2]); 2123 } else { 2124 tcg_out_insn(s, RRFa, XRK, a0, a1, a2); 2125 } 2126 break; 2127 2128 case INDEX_op_andc_i32: 2129 a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; 2130 if (const_args[2]) { 2131 tcg_out_mov(s, TCG_TYPE_I32, a0, a1); 2132 tgen_andi(s, TCG_TYPE_I32, a0, (uint32_t)~a2); 2133 } else { 2134 tcg_out_insn(s, RRFa, NCRK, a0, a1, a2); 2135 } 2136 break; 2137 case INDEX_op_orc_i32: 2138 a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; 2139 if (const_args[2]) { 2140 tcg_out_mov(s, TCG_TYPE_I32, a0, a1); 2141 tgen_ori(s, a0, (uint32_t)~a2); 2142 } else { 2143 tcg_out_insn(s, RRFa, OCRK, a0, a1, a2); 2144 } 2145 break; 2146 case INDEX_op_eqv_i32: 2147 a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; 2148 if (const_args[2]) { 2149 tcg_out_mov(s, TCG_TYPE_I32, a0, a1); 2150 tcg_out_insn(s, RIL, XILF, a0, ~a2); 2151 } else { 2152 tcg_out_insn(s, RRFa, NXRK, a0, a1, a2); 2153 } 2154 break; 2155 case INDEX_op_nand_i32: 2156 tcg_out_insn(s, RRFa, NNRK, args[0], args[1], args[2]); 2157 break; 2158 case INDEX_op_nor_i32: 2159 tcg_out_insn(s, RRFa, NORK, args[0], args[1], args[2]); 2160 break; 2161 2162 case INDEX_op_neg_i32: 2163 tcg_out_insn(s, RR, LCR, args[0], args[1]); 2164 break; 2165 case INDEX_op_not_i32: 2166 tcg_out_insn(s, RRFa, NORK, args[0], args[1], args[1]); 2167 break; 2168 2169 case INDEX_op_mul_i32: 2170 a0 = args[0], a1 = args[1], a2 = (int32_t)args[2]; 2171 if (const_args[2]) { 2172 tcg_out_mov(s, TCG_TYPE_I32, a0, a1); 2173 if (a2 == (int16_t)a2) { 2174 tcg_out_insn(s, RI, MHI, a0, a2); 2175 } else { 2176 tcg_out_insn(s, RIL, MSFI, a0, a2); 2177 } 2178 } else if (a0 == a1) { 2179 tcg_out_insn(s, RRE, MSR, a0, a2); 2180 } else { 2181 tcg_out_insn(s, RRFa, MSRKC, a0, a1, a2); 2182 } 2183 break; 2184 2185 case INDEX_op_div2_i32: 2186 tcg_debug_assert(args[0] == args[2]); 2187 tcg_debug_assert(args[1] == args[3]); 2188 tcg_debug_assert((args[1] & 1) == 0); 2189 tcg_debug_assert(args[0] == args[1] + 1); 2190 tcg_out_insn(s, RR, DR, args[1], args[4]); 2191 break; 2192 case INDEX_op_divu2_i32: 2193 tcg_debug_assert(args[0] == args[2]); 2194 tcg_debug_assert(args[1] == args[3]); 2195 tcg_debug_assert((args[1] & 1) == 0); 2196 tcg_debug_assert(args[0] == args[1] + 1); 2197 tcg_out_insn(s, RRE, DLR, args[1], args[4]); 2198 break; 2199 2200 case INDEX_op_shl_i32: 2201 op = RS_SLL; 2202 op2 = RSY_SLLK; 2203 do_shift32: 2204 a0 = args[0], a1 = args[1], a2 = (int32_t)args[2]; 2205 if (a0 == a1) { 2206 if (const_args[2]) { 2207 tcg_out_sh32(s, op, a0, TCG_REG_NONE, a2); 2208 } else { 2209 tcg_out_sh32(s, op, a0, a2, 0); 2210 } 2211 } else { 2212 /* Using tcg_out_sh64 here for the format; it is a 32-bit shift. */ 2213 if (const_args[2]) { 2214 tcg_out_sh64(s, op2, a0, a1, TCG_REG_NONE, a2); 2215 } else { 2216 tcg_out_sh64(s, op2, a0, a1, a2, 0); 2217 } 2218 } 2219 break; 2220 case INDEX_op_shr_i32: 2221 op = RS_SRL; 2222 op2 = RSY_SRLK; 2223 goto do_shift32; 2224 case INDEX_op_sar_i32: 2225 op = RS_SRA; 2226 op2 = RSY_SRAK; 2227 goto do_shift32; 2228 2229 case INDEX_op_rotl_i32: 2230 /* ??? Using tcg_out_sh64 here for the format; it is a 32-bit rol. */ 2231 if (const_args[2]) { 2232 tcg_out_sh64(s, RSY_RLL, args[0], args[1], TCG_REG_NONE, args[2]); 2233 } else { 2234 tcg_out_sh64(s, RSY_RLL, args[0], args[1], args[2], 0); 2235 } 2236 break; 2237 case INDEX_op_rotr_i32: 2238 if (const_args[2]) { 2239 tcg_out_sh64(s, RSY_RLL, args[0], args[1], 2240 TCG_REG_NONE, (32 - args[2]) & 31); 2241 } else { 2242 tcg_out_insn(s, RR, LCR, TCG_TMP0, args[2]); 2243 tcg_out_sh64(s, RSY_RLL, args[0], args[1], TCG_TMP0, 0); 2244 } 2245 break; 2246 2247 case INDEX_op_bswap16_i32: 2248 a0 = args[0], a1 = args[1], a2 = args[2]; 2249 tcg_out_insn(s, RRE, LRVR, a0, a1); 2250 if (a2 & TCG_BSWAP_OS) { 2251 tcg_out_sh32(s, RS_SRA, a0, TCG_REG_NONE, 16); 2252 } else { 2253 tcg_out_sh32(s, RS_SRL, a0, TCG_REG_NONE, 16); 2254 } 2255 break; 2256 case INDEX_op_bswap16_i64: 2257 a0 = args[0], a1 = args[1], a2 = args[2]; 2258 tcg_out_insn(s, RRE, LRVGR, a0, a1); 2259 if (a2 & TCG_BSWAP_OS) { 2260 tcg_out_sh64(s, RSY_SRAG, a0, a0, TCG_REG_NONE, 48); 2261 } else { 2262 tcg_out_sh64(s, RSY_SRLG, a0, a0, TCG_REG_NONE, 48); 2263 } 2264 break; 2265 2266 case INDEX_op_bswap32_i32: 2267 tcg_out_insn(s, RRE, LRVR, args[0], args[1]); 2268 break; 2269 case INDEX_op_bswap32_i64: 2270 a0 = args[0], a1 = args[1], a2 = args[2]; 2271 tcg_out_insn(s, RRE, LRVR, a0, a1); 2272 if (a2 & TCG_BSWAP_OS) { 2273 tcg_out_ext32s(s, a0, a0); 2274 } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 2275 tcg_out_ext32u(s, a0, a0); 2276 } 2277 break; 2278 2279 case INDEX_op_add2_i32: 2280 if (const_args[4]) { 2281 tcg_out_insn(s, RIL, ALFI, args[0], args[4]); 2282 } else { 2283 tcg_out_insn(s, RR, ALR, args[0], args[4]); 2284 } 2285 tcg_out_insn(s, RRE, ALCR, args[1], args[5]); 2286 break; 2287 case INDEX_op_sub2_i32: 2288 if (const_args[4]) { 2289 tcg_out_insn(s, RIL, SLFI, args[0], args[4]); 2290 } else { 2291 tcg_out_insn(s, RR, SLR, args[0], args[4]); 2292 } 2293 tcg_out_insn(s, RRE, SLBR, args[1], args[5]); 2294 break; 2295 2296 case INDEX_op_br: 2297 tgen_branch(s, S390_CC_ALWAYS, arg_label(args[0])); 2298 break; 2299 2300 case INDEX_op_brcond_i32: 2301 tgen_brcond(s, TCG_TYPE_I32, args[2], args[0], 2302 args[1], const_args[1], arg_label(args[3])); 2303 break; 2304 case INDEX_op_setcond_i32: 2305 tgen_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], 2306 args[2], const_args[2], false); 2307 break; 2308 case INDEX_op_negsetcond_i32: 2309 tgen_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], 2310 args[2], const_args[2], true); 2311 break; 2312 case INDEX_op_movcond_i32: 2313 tgen_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], 2314 args[2], const_args[2], args[3], const_args[3], args[4]); 2315 break; 2316 2317 case INDEX_op_qemu_ld_a32_i32: 2318 case INDEX_op_qemu_ld_a64_i32: 2319 tcg_out_qemu_ld(s, args[0], args[1], args[2], TCG_TYPE_I32); 2320 break; 2321 case INDEX_op_qemu_ld_a32_i64: 2322 case INDEX_op_qemu_ld_a64_i64: 2323 tcg_out_qemu_ld(s, args[0], args[1], args[2], TCG_TYPE_I64); 2324 break; 2325 case INDEX_op_qemu_st_a32_i32: 2326 case INDEX_op_qemu_st_a64_i32: 2327 tcg_out_qemu_st(s, args[0], args[1], args[2], TCG_TYPE_I32); 2328 break; 2329 case INDEX_op_qemu_st_a32_i64: 2330 case INDEX_op_qemu_st_a64_i64: 2331 tcg_out_qemu_st(s, args[0], args[1], args[2], TCG_TYPE_I64); 2332 break; 2333 case INDEX_op_qemu_ld_a32_i128: 2334 case INDEX_op_qemu_ld_a64_i128: 2335 tcg_out_qemu_ldst_i128(s, args[0], args[1], args[2], args[3], true); 2336 break; 2337 case INDEX_op_qemu_st_a32_i128: 2338 case INDEX_op_qemu_st_a64_i128: 2339 tcg_out_qemu_ldst_i128(s, args[0], args[1], args[2], args[3], false); 2340 break; 2341 2342 case INDEX_op_ld16s_i64: 2343 tcg_out_mem(s, 0, RXY_LGH, args[0], args[1], TCG_REG_NONE, args[2]); 2344 break; 2345 case INDEX_op_ld32u_i64: 2346 tcg_out_mem(s, 0, RXY_LLGF, args[0], args[1], TCG_REG_NONE, args[2]); 2347 break; 2348 case INDEX_op_ld32s_i64: 2349 tcg_out_mem(s, 0, RXY_LGF, args[0], args[1], TCG_REG_NONE, args[2]); 2350 break; 2351 case INDEX_op_ld_i64: 2352 tcg_out_ld(s, TCG_TYPE_I64, args[0], args[1], args[2]); 2353 break; 2354 2355 case INDEX_op_st32_i64: 2356 tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]); 2357 break; 2358 case INDEX_op_st_i64: 2359 tcg_out_st(s, TCG_TYPE_I64, args[0], args[1], args[2]); 2360 break; 2361 2362 case INDEX_op_add_i64: 2363 a0 = args[0], a1 = args[1], a2 = args[2]; 2364 if (const_args[2]) { 2365 do_addi_64: 2366 if (a0 == a1) { 2367 if (a2 == (int16_t)a2) { 2368 tcg_out_insn(s, RI, AGHI, a0, a2); 2369 break; 2370 } 2371 if (a2 == (int32_t)a2) { 2372 tcg_out_insn(s, RIL, AGFI, a0, a2); 2373 break; 2374 } 2375 if (a2 == (uint32_t)a2) { 2376 tcg_out_insn(s, RIL, ALGFI, a0, a2); 2377 break; 2378 } 2379 if (-a2 == (uint32_t)-a2) { 2380 tcg_out_insn(s, RIL, SLGFI, a0, -a2); 2381 break; 2382 } 2383 } 2384 tcg_out_mem(s, RX_LA, RXY_LAY, a0, a1, TCG_REG_NONE, a2); 2385 } else if (a0 == a1) { 2386 tcg_out_insn(s, RRE, AGR, a0, a2); 2387 } else { 2388 tcg_out_insn(s, RX, LA, a0, a1, a2, 0); 2389 } 2390 break; 2391 case INDEX_op_sub_i64: 2392 a0 = args[0], a1 = args[1], a2 = args[2]; 2393 if (const_args[2]) { 2394 a2 = -a2; 2395 goto do_addi_64; 2396 } else { 2397 tcg_out_insn(s, RRFa, SGRK, a0, a1, a2); 2398 } 2399 break; 2400 2401 case INDEX_op_and_i64: 2402 a0 = args[0], a1 = args[1], a2 = args[2]; 2403 if (const_args[2]) { 2404 tcg_out_mov(s, TCG_TYPE_I64, a0, a1); 2405 tgen_andi(s, TCG_TYPE_I64, args[0], args[2]); 2406 } else { 2407 tcg_out_insn(s, RRFa, NGRK, a0, a1, a2); 2408 } 2409 break; 2410 case INDEX_op_or_i64: 2411 a0 = args[0], a1 = args[1], a2 = args[2]; 2412 if (const_args[2]) { 2413 tcg_out_mov(s, TCG_TYPE_I64, a0, a1); 2414 tgen_ori(s, a0, a2); 2415 } else { 2416 tcg_out_insn(s, RRFa, OGRK, a0, a1, a2); 2417 } 2418 break; 2419 case INDEX_op_xor_i64: 2420 a0 = args[0], a1 = args[1], a2 = args[2]; 2421 if (const_args[2]) { 2422 tcg_out_mov(s, TCG_TYPE_I64, a0, a1); 2423 tgen_xori(s, a0, a2); 2424 } else { 2425 tcg_out_insn(s, RRFa, XGRK, a0, a1, a2); 2426 } 2427 break; 2428 2429 case INDEX_op_andc_i64: 2430 a0 = args[0], a1 = args[1], a2 = args[2]; 2431 if (const_args[2]) { 2432 tcg_out_mov(s, TCG_TYPE_I64, a0, a1); 2433 tgen_andi(s, TCG_TYPE_I64, a0, ~a2); 2434 } else { 2435 tcg_out_insn(s, RRFa, NCGRK, a0, a1, a2); 2436 } 2437 break; 2438 case INDEX_op_orc_i64: 2439 a0 = args[0], a1 = args[1], a2 = args[2]; 2440 if (const_args[2]) { 2441 tcg_out_mov(s, TCG_TYPE_I64, a0, a1); 2442 tgen_ori(s, a0, ~a2); 2443 } else { 2444 tcg_out_insn(s, RRFa, OCGRK, a0, a1, a2); 2445 } 2446 break; 2447 case INDEX_op_eqv_i64: 2448 a0 = args[0], a1 = args[1], a2 = args[2]; 2449 if (const_args[2]) { 2450 tcg_out_mov(s, TCG_TYPE_I64, a0, a1); 2451 tgen_xori(s, a0, ~a2); 2452 } else { 2453 tcg_out_insn(s, RRFa, NXGRK, a0, a1, a2); 2454 } 2455 break; 2456 case INDEX_op_nand_i64: 2457 tcg_out_insn(s, RRFa, NNGRK, args[0], args[1], args[2]); 2458 break; 2459 case INDEX_op_nor_i64: 2460 tcg_out_insn(s, RRFa, NOGRK, args[0], args[1], args[2]); 2461 break; 2462 2463 case INDEX_op_neg_i64: 2464 tcg_out_insn(s, RRE, LCGR, args[0], args[1]); 2465 break; 2466 case INDEX_op_not_i64: 2467 tcg_out_insn(s, RRFa, NOGRK, args[0], args[1], args[1]); 2468 break; 2469 case INDEX_op_bswap64_i64: 2470 tcg_out_insn(s, RRE, LRVGR, args[0], args[1]); 2471 break; 2472 2473 case INDEX_op_mul_i64: 2474 a0 = args[0], a1 = args[1], a2 = args[2]; 2475 if (const_args[2]) { 2476 tcg_out_mov(s, TCG_TYPE_I64, a0, a1); 2477 if (a2 == (int16_t)a2) { 2478 tcg_out_insn(s, RI, MGHI, a0, a2); 2479 } else { 2480 tcg_out_insn(s, RIL, MSGFI, a0, a2); 2481 } 2482 } else if (a0 == a1) { 2483 tcg_out_insn(s, RRE, MSGR, a0, a2); 2484 } else { 2485 tcg_out_insn(s, RRFa, MSGRKC, a0, a1, a2); 2486 } 2487 break; 2488 2489 case INDEX_op_div2_i64: 2490 /* 2491 * ??? We get an unnecessary sign-extension of the dividend 2492 * into op0 with this definition, but as we do in fact always 2493 * produce both quotient and remainder using INDEX_op_div_i64 2494 * instead requires jumping through even more hoops. 2495 */ 2496 tcg_debug_assert(args[0] == args[2]); 2497 tcg_debug_assert(args[1] == args[3]); 2498 tcg_debug_assert((args[1] & 1) == 0); 2499 tcg_debug_assert(args[0] == args[1] + 1); 2500 tcg_out_insn(s, RRE, DSGR, args[1], args[4]); 2501 break; 2502 case INDEX_op_divu2_i64: 2503 tcg_debug_assert(args[0] == args[2]); 2504 tcg_debug_assert(args[1] == args[3]); 2505 tcg_debug_assert((args[1] & 1) == 0); 2506 tcg_debug_assert(args[0] == args[1] + 1); 2507 tcg_out_insn(s, RRE, DLGR, args[1], args[4]); 2508 break; 2509 case INDEX_op_mulu2_i64: 2510 tcg_debug_assert(args[0] == args[2]); 2511 tcg_debug_assert((args[1] & 1) == 0); 2512 tcg_debug_assert(args[0] == args[1] + 1); 2513 tcg_out_insn(s, RRE, MLGR, args[1], args[3]); 2514 break; 2515 case INDEX_op_muls2_i64: 2516 tcg_debug_assert((args[1] & 1) == 0); 2517 tcg_debug_assert(args[0] == args[1] + 1); 2518 tcg_out_insn(s, RRFa, MGRK, args[1], args[2], args[3]); 2519 break; 2520 2521 case INDEX_op_shl_i64: 2522 op = RSY_SLLG; 2523 do_shift64: 2524 if (const_args[2]) { 2525 tcg_out_sh64(s, op, args[0], args[1], TCG_REG_NONE, args[2]); 2526 } else { 2527 tcg_out_sh64(s, op, args[0], args[1], args[2], 0); 2528 } 2529 break; 2530 case INDEX_op_shr_i64: 2531 op = RSY_SRLG; 2532 goto do_shift64; 2533 case INDEX_op_sar_i64: 2534 op = RSY_SRAG; 2535 goto do_shift64; 2536 2537 case INDEX_op_rotl_i64: 2538 if (const_args[2]) { 2539 tcg_out_sh64(s, RSY_RLLG, args[0], args[1], 2540 TCG_REG_NONE, args[2]); 2541 } else { 2542 tcg_out_sh64(s, RSY_RLLG, args[0], args[1], args[2], 0); 2543 } 2544 break; 2545 case INDEX_op_rotr_i64: 2546 if (const_args[2]) { 2547 tcg_out_sh64(s, RSY_RLLG, args[0], args[1], 2548 TCG_REG_NONE, (64 - args[2]) & 63); 2549 } else { 2550 /* We can use the smaller 32-bit negate because only the 2551 low 6 bits are examined for the rotate. */ 2552 tcg_out_insn(s, RR, LCR, TCG_TMP0, args[2]); 2553 tcg_out_sh64(s, RSY_RLLG, args[0], args[1], TCG_TMP0, 0); 2554 } 2555 break; 2556 2557 case INDEX_op_add2_i64: 2558 if (const_args[4]) { 2559 if ((int64_t)args[4] >= 0) { 2560 tcg_out_insn(s, RIL, ALGFI, args[0], args[4]); 2561 } else { 2562 tcg_out_insn(s, RIL, SLGFI, args[0], -args[4]); 2563 } 2564 } else { 2565 tcg_out_insn(s, RRE, ALGR, args[0], args[4]); 2566 } 2567 tcg_out_insn(s, RRE, ALCGR, args[1], args[5]); 2568 break; 2569 case INDEX_op_sub2_i64: 2570 if (const_args[4]) { 2571 if ((int64_t)args[4] >= 0) { 2572 tcg_out_insn(s, RIL, SLGFI, args[0], args[4]); 2573 } else { 2574 tcg_out_insn(s, RIL, ALGFI, args[0], -args[4]); 2575 } 2576 } else { 2577 tcg_out_insn(s, RRE, SLGR, args[0], args[4]); 2578 } 2579 tcg_out_insn(s, RRE, SLBGR, args[1], args[5]); 2580 break; 2581 2582 case INDEX_op_brcond_i64: 2583 tgen_brcond(s, TCG_TYPE_I64, args[2], args[0], 2584 args[1], const_args[1], arg_label(args[3])); 2585 break; 2586 case INDEX_op_setcond_i64: 2587 tgen_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], 2588 args[2], const_args[2], false); 2589 break; 2590 case INDEX_op_negsetcond_i64: 2591 tgen_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], 2592 args[2], const_args[2], true); 2593 break; 2594 case INDEX_op_movcond_i64: 2595 tgen_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], 2596 args[2], const_args[2], args[3], const_args[3], args[4]); 2597 break; 2598 2599 OP_32_64(deposit): 2600 a0 = args[0], a1 = args[1], a2 = args[2]; 2601 if (const_args[1]) { 2602 tgen_deposit(s, a0, a2, args[3], args[4], 1); 2603 } else { 2604 /* Since we can't support "0Z" as a constraint, we allow a1 in 2605 any register. Fix things up as if a matching constraint. */ 2606 if (a0 != a1) { 2607 TCGType type = (opc == INDEX_op_deposit_i64); 2608 if (a0 == a2) { 2609 tcg_out_mov(s, type, TCG_TMP0, a2); 2610 a2 = TCG_TMP0; 2611 } 2612 tcg_out_mov(s, type, a0, a1); 2613 } 2614 tgen_deposit(s, a0, a2, args[3], args[4], 0); 2615 } 2616 break; 2617 2618 OP_32_64(extract): 2619 tgen_extract(s, args[0], args[1], args[2], args[3]); 2620 break; 2621 2622 case INDEX_op_clz_i64: 2623 tgen_clz(s, args[0], args[1], args[2], const_args[2]); 2624 break; 2625 2626 case INDEX_op_ctpop_i32: 2627 tgen_ctpop(s, TCG_TYPE_I32, args[0], args[1]); 2628 break; 2629 case INDEX_op_ctpop_i64: 2630 tgen_ctpop(s, TCG_TYPE_I64, args[0], args[1]); 2631 break; 2632 2633 case INDEX_op_mb: 2634 /* The host memory model is quite strong, we simply need to 2635 serialize the instruction stream. */ 2636 if (args[0] & TCG_MO_ST_LD) { 2637 /* fast-bcr-serialization facility (45) is present */ 2638 tcg_out_insn(s, RR, BCR, 14, 0); 2639 } 2640 break; 2641 2642 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ 2643 case INDEX_op_mov_i64: 2644 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2645 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 2646 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 2647 case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ 2648 case INDEX_op_ext8s_i64: 2649 case INDEX_op_ext8u_i32: 2650 case INDEX_op_ext8u_i64: 2651 case INDEX_op_ext16s_i32: 2652 case INDEX_op_ext16s_i64: 2653 case INDEX_op_ext16u_i32: 2654 case INDEX_op_ext16u_i64: 2655 case INDEX_op_ext32s_i64: 2656 case INDEX_op_ext32u_i64: 2657 case INDEX_op_ext_i32_i64: 2658 case INDEX_op_extu_i32_i64: 2659 case INDEX_op_extrl_i64_i32: 2660 default: 2661 g_assert_not_reached(); 2662 } 2663} 2664 2665static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 2666 TCGReg dst, TCGReg src) 2667{ 2668 if (is_general_reg(src)) { 2669 /* Replicate general register into two MO_64. */ 2670 tcg_out_insn(s, VRRf, VLVGP, dst, src, src); 2671 if (vece == MO_64) { 2672 return true; 2673 } 2674 src = dst; 2675 } 2676 2677 /* 2678 * Recall that the "standard" integer, within a vector, is the 2679 * rightmost element of the leftmost doubleword, a-la VLLEZ. 2680 */ 2681 tcg_out_insn(s, VRIc, VREP, dst, (8 >> vece) - 1, src, vece); 2682 return true; 2683} 2684 2685static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 2686 TCGReg dst, TCGReg base, intptr_t offset) 2687{ 2688 tcg_out_vrx_mem(s, VRX_VLREP, dst, base, TCG_REG_NONE, offset, vece); 2689 return true; 2690} 2691 2692static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 2693 TCGReg dst, int64_t val) 2694{ 2695 int i, mask, msb, lsb; 2696 2697 /* Look for int16_t elements. */ 2698 if (vece <= MO_16 || 2699 (vece == MO_32 ? (int32_t)val : val) == (int16_t)val) { 2700 tcg_out_insn(s, VRIa, VREPI, dst, val, vece); 2701 return; 2702 } 2703 2704 /* Look for bit masks. */ 2705 if (vece == MO_32) { 2706 if (risbg_mask((int32_t)val)) { 2707 /* Handle wraparound by swapping msb and lsb. */ 2708 if ((val & 0x80000001u) == 0x80000001u) { 2709 msb = 32 - ctz32(~val); 2710 lsb = clz32(~val) - 1; 2711 } else { 2712 msb = clz32(val); 2713 lsb = 31 - ctz32(val); 2714 } 2715 tcg_out_insn(s, VRIb, VGM, dst, msb, lsb, MO_32); 2716 return; 2717 } 2718 } else { 2719 if (risbg_mask(val)) { 2720 /* Handle wraparound by swapping msb and lsb. */ 2721 if ((val & 0x8000000000000001ull) == 0x8000000000000001ull) { 2722 /* Handle wraparound by swapping msb and lsb. */ 2723 msb = 64 - ctz64(~val); 2724 lsb = clz64(~val) - 1; 2725 } else { 2726 msb = clz64(val); 2727 lsb = 63 - ctz64(val); 2728 } 2729 tcg_out_insn(s, VRIb, VGM, dst, msb, lsb, MO_64); 2730 return; 2731 } 2732 } 2733 2734 /* Look for all bytes 0x00 or 0xff. */ 2735 for (i = mask = 0; i < 8; i++) { 2736 uint8_t byte = val >> (i * 8); 2737 if (byte == 0xff) { 2738 mask |= 1 << i; 2739 } else if (byte != 0) { 2740 break; 2741 } 2742 } 2743 if (i == 8) { 2744 tcg_out_insn(s, VRIa, VGBM, dst, mask * 0x0101, 0); 2745 return; 2746 } 2747 2748 /* Otherwise, stuff it in the constant pool. */ 2749 tcg_out_insn(s, RIL, LARL, TCG_TMP0, 0); 2750 new_pool_label(s, val, R_390_PC32DBL, s->code_ptr - 2, 2); 2751 tcg_out_insn(s, VRX, VLREP, dst, TCG_TMP0, TCG_REG_NONE, 0, MO_64); 2752} 2753 2754static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 2755 unsigned vecl, unsigned vece, 2756 const TCGArg args[TCG_MAX_OP_ARGS], 2757 const int const_args[TCG_MAX_OP_ARGS]) 2758{ 2759 TCGType type = vecl + TCG_TYPE_V64; 2760 TCGArg a0 = args[0], a1 = args[1], a2 = args[2]; 2761 2762 switch (opc) { 2763 case INDEX_op_ld_vec: 2764 tcg_out_ld(s, type, a0, a1, a2); 2765 break; 2766 case INDEX_op_st_vec: 2767 tcg_out_st(s, type, a0, a1, a2); 2768 break; 2769 case INDEX_op_dupm_vec: 2770 tcg_out_dupm_vec(s, type, vece, a0, a1, a2); 2771 break; 2772 2773 case INDEX_op_abs_vec: 2774 tcg_out_insn(s, VRRa, VLP, a0, a1, vece); 2775 break; 2776 case INDEX_op_neg_vec: 2777 tcg_out_insn(s, VRRa, VLC, a0, a1, vece); 2778 break; 2779 case INDEX_op_not_vec: 2780 tcg_out_insn(s, VRRc, VNO, a0, a1, a1, 0); 2781 break; 2782 2783 case INDEX_op_add_vec: 2784 tcg_out_insn(s, VRRc, VA, a0, a1, a2, vece); 2785 break; 2786 case INDEX_op_sub_vec: 2787 tcg_out_insn(s, VRRc, VS, a0, a1, a2, vece); 2788 break; 2789 case INDEX_op_and_vec: 2790 tcg_out_insn(s, VRRc, VN, a0, a1, a2, 0); 2791 break; 2792 case INDEX_op_andc_vec: 2793 tcg_out_insn(s, VRRc, VNC, a0, a1, a2, 0); 2794 break; 2795 case INDEX_op_mul_vec: 2796 tcg_out_insn(s, VRRc, VML, a0, a1, a2, vece); 2797 break; 2798 case INDEX_op_or_vec: 2799 tcg_out_insn(s, VRRc, VO, a0, a1, a2, 0); 2800 break; 2801 case INDEX_op_orc_vec: 2802 tcg_out_insn(s, VRRc, VOC, a0, a1, a2, 0); 2803 break; 2804 case INDEX_op_xor_vec: 2805 tcg_out_insn(s, VRRc, VX, a0, a1, a2, 0); 2806 break; 2807 case INDEX_op_nand_vec: 2808 tcg_out_insn(s, VRRc, VNN, a0, a1, a2, 0); 2809 break; 2810 case INDEX_op_nor_vec: 2811 tcg_out_insn(s, VRRc, VNO, a0, a1, a2, 0); 2812 break; 2813 case INDEX_op_eqv_vec: 2814 tcg_out_insn(s, VRRc, VNX, a0, a1, a2, 0); 2815 break; 2816 2817 case INDEX_op_shli_vec: 2818 tcg_out_insn(s, VRSa, VESL, a0, a2, TCG_REG_NONE, a1, vece); 2819 break; 2820 case INDEX_op_shri_vec: 2821 tcg_out_insn(s, VRSa, VESRL, a0, a2, TCG_REG_NONE, a1, vece); 2822 break; 2823 case INDEX_op_sari_vec: 2824 tcg_out_insn(s, VRSa, VESRA, a0, a2, TCG_REG_NONE, a1, vece); 2825 break; 2826 case INDEX_op_rotli_vec: 2827 tcg_out_insn(s, VRSa, VERLL, a0, a2, TCG_REG_NONE, a1, vece); 2828 break; 2829 case INDEX_op_shls_vec: 2830 tcg_out_insn(s, VRSa, VESL, a0, 0, a2, a1, vece); 2831 break; 2832 case INDEX_op_shrs_vec: 2833 tcg_out_insn(s, VRSa, VESRL, a0, 0, a2, a1, vece); 2834 break; 2835 case INDEX_op_sars_vec: 2836 tcg_out_insn(s, VRSa, VESRA, a0, 0, a2, a1, vece); 2837 break; 2838 case INDEX_op_rotls_vec: 2839 tcg_out_insn(s, VRSa, VERLL, a0, 0, a2, a1, vece); 2840 break; 2841 case INDEX_op_shlv_vec: 2842 tcg_out_insn(s, VRRc, VESLV, a0, a1, a2, vece); 2843 break; 2844 case INDEX_op_shrv_vec: 2845 tcg_out_insn(s, VRRc, VESRLV, a0, a1, a2, vece); 2846 break; 2847 case INDEX_op_sarv_vec: 2848 tcg_out_insn(s, VRRc, VESRAV, a0, a1, a2, vece); 2849 break; 2850 case INDEX_op_rotlv_vec: 2851 tcg_out_insn(s, VRRc, VERLLV, a0, a1, a2, vece); 2852 break; 2853 2854 case INDEX_op_smin_vec: 2855 tcg_out_insn(s, VRRc, VMN, a0, a1, a2, vece); 2856 break; 2857 case INDEX_op_smax_vec: 2858 tcg_out_insn(s, VRRc, VMX, a0, a1, a2, vece); 2859 break; 2860 case INDEX_op_umin_vec: 2861 tcg_out_insn(s, VRRc, VMNL, a0, a1, a2, vece); 2862 break; 2863 case INDEX_op_umax_vec: 2864 tcg_out_insn(s, VRRc, VMXL, a0, a1, a2, vece); 2865 break; 2866 2867 case INDEX_op_bitsel_vec: 2868 tcg_out_insn(s, VRRe, VSEL, a0, a2, args[3], a1); 2869 break; 2870 2871 case INDEX_op_cmp_vec: 2872 switch ((TCGCond)args[3]) { 2873 case TCG_COND_EQ: 2874 tcg_out_insn(s, VRRc, VCEQ, a0, a1, a2, vece); 2875 break; 2876 case TCG_COND_GT: 2877 tcg_out_insn(s, VRRc, VCH, a0, a1, a2, vece); 2878 break; 2879 case TCG_COND_GTU: 2880 tcg_out_insn(s, VRRc, VCHL, a0, a1, a2, vece); 2881 break; 2882 default: 2883 g_assert_not_reached(); 2884 } 2885 break; 2886 2887 case INDEX_op_s390_vuph_vec: 2888 tcg_out_insn(s, VRRa, VUPH, a0, a1, vece); 2889 break; 2890 case INDEX_op_s390_vupl_vec: 2891 tcg_out_insn(s, VRRa, VUPL, a0, a1, vece); 2892 break; 2893 case INDEX_op_s390_vpks_vec: 2894 tcg_out_insn(s, VRRc, VPKS, a0, a1, a2, vece); 2895 break; 2896 2897 case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ 2898 case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ 2899 default: 2900 g_assert_not_reached(); 2901 } 2902} 2903 2904int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) 2905{ 2906 switch (opc) { 2907 case INDEX_op_abs_vec: 2908 case INDEX_op_add_vec: 2909 case INDEX_op_and_vec: 2910 case INDEX_op_andc_vec: 2911 case INDEX_op_bitsel_vec: 2912 case INDEX_op_eqv_vec: 2913 case INDEX_op_nand_vec: 2914 case INDEX_op_neg_vec: 2915 case INDEX_op_nor_vec: 2916 case INDEX_op_not_vec: 2917 case INDEX_op_or_vec: 2918 case INDEX_op_orc_vec: 2919 case INDEX_op_rotli_vec: 2920 case INDEX_op_rotls_vec: 2921 case INDEX_op_rotlv_vec: 2922 case INDEX_op_sari_vec: 2923 case INDEX_op_sars_vec: 2924 case INDEX_op_sarv_vec: 2925 case INDEX_op_shli_vec: 2926 case INDEX_op_shls_vec: 2927 case INDEX_op_shlv_vec: 2928 case INDEX_op_shri_vec: 2929 case INDEX_op_shrs_vec: 2930 case INDEX_op_shrv_vec: 2931 case INDEX_op_smax_vec: 2932 case INDEX_op_smin_vec: 2933 case INDEX_op_sub_vec: 2934 case INDEX_op_umax_vec: 2935 case INDEX_op_umin_vec: 2936 case INDEX_op_xor_vec: 2937 return 1; 2938 case INDEX_op_cmp_vec: 2939 case INDEX_op_cmpsel_vec: 2940 case INDEX_op_rotrv_vec: 2941 return -1; 2942 case INDEX_op_mul_vec: 2943 return vece < MO_64; 2944 case INDEX_op_ssadd_vec: 2945 case INDEX_op_sssub_vec: 2946 return vece < MO_64 ? -1 : 0; 2947 default: 2948 return 0; 2949 } 2950} 2951 2952static bool expand_vec_cmp_noinv(TCGType type, unsigned vece, TCGv_vec v0, 2953 TCGv_vec v1, TCGv_vec v2, TCGCond cond) 2954{ 2955 bool need_swap = false, need_inv = false; 2956 2957 switch (cond) { 2958 case TCG_COND_EQ: 2959 case TCG_COND_GT: 2960 case TCG_COND_GTU: 2961 break; 2962 case TCG_COND_NE: 2963 case TCG_COND_LE: 2964 case TCG_COND_LEU: 2965 need_inv = true; 2966 break; 2967 case TCG_COND_LT: 2968 case TCG_COND_LTU: 2969 need_swap = true; 2970 break; 2971 case TCG_COND_GE: 2972 case TCG_COND_GEU: 2973 need_swap = need_inv = true; 2974 break; 2975 default: 2976 g_assert_not_reached(); 2977 } 2978 2979 if (need_inv) { 2980 cond = tcg_invert_cond(cond); 2981 } 2982 if (need_swap) { 2983 TCGv_vec t1; 2984 t1 = v1, v1 = v2, v2 = t1; 2985 cond = tcg_swap_cond(cond); 2986 } 2987 2988 vec_gen_4(INDEX_op_cmp_vec, type, vece, tcgv_vec_arg(v0), 2989 tcgv_vec_arg(v1), tcgv_vec_arg(v2), cond); 2990 2991 return need_inv; 2992} 2993 2994static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0, 2995 TCGv_vec v1, TCGv_vec v2, TCGCond cond) 2996{ 2997 if (expand_vec_cmp_noinv(type, vece, v0, v1, v2, cond)) { 2998 tcg_gen_not_vec(vece, v0, v0); 2999 } 3000} 3001 3002static void expand_vec_cmpsel(TCGType type, unsigned vece, TCGv_vec v0, 3003 TCGv_vec c1, TCGv_vec c2, 3004 TCGv_vec v3, TCGv_vec v4, TCGCond cond) 3005{ 3006 TCGv_vec t = tcg_temp_new_vec(type); 3007 3008 if (expand_vec_cmp_noinv(type, vece, t, c1, c2, cond)) { 3009 /* Invert the sense of the compare by swapping arguments. */ 3010 tcg_gen_bitsel_vec(vece, v0, t, v4, v3); 3011 } else { 3012 tcg_gen_bitsel_vec(vece, v0, t, v3, v4); 3013 } 3014 tcg_temp_free_vec(t); 3015} 3016 3017static void expand_vec_sat(TCGType type, unsigned vece, TCGv_vec v0, 3018 TCGv_vec v1, TCGv_vec v2, TCGOpcode add_sub_opc) 3019{ 3020 TCGv_vec h1 = tcg_temp_new_vec(type); 3021 TCGv_vec h2 = tcg_temp_new_vec(type); 3022 TCGv_vec l1 = tcg_temp_new_vec(type); 3023 TCGv_vec l2 = tcg_temp_new_vec(type); 3024 3025 tcg_debug_assert (vece < MO_64); 3026 3027 /* Unpack with sign-extension. */ 3028 vec_gen_2(INDEX_op_s390_vuph_vec, type, vece, 3029 tcgv_vec_arg(h1), tcgv_vec_arg(v1)); 3030 vec_gen_2(INDEX_op_s390_vuph_vec, type, vece, 3031 tcgv_vec_arg(h2), tcgv_vec_arg(v2)); 3032 3033 vec_gen_2(INDEX_op_s390_vupl_vec, type, vece, 3034 tcgv_vec_arg(l1), tcgv_vec_arg(v1)); 3035 vec_gen_2(INDEX_op_s390_vupl_vec, type, vece, 3036 tcgv_vec_arg(l2), tcgv_vec_arg(v2)); 3037 3038 /* Arithmetic on a wider element size. */ 3039 vec_gen_3(add_sub_opc, type, vece + 1, tcgv_vec_arg(h1), 3040 tcgv_vec_arg(h1), tcgv_vec_arg(h2)); 3041 vec_gen_3(add_sub_opc, type, vece + 1, tcgv_vec_arg(l1), 3042 tcgv_vec_arg(l1), tcgv_vec_arg(l2)); 3043 3044 /* Pack with saturation. */ 3045 vec_gen_3(INDEX_op_s390_vpks_vec, type, vece + 1, 3046 tcgv_vec_arg(v0), tcgv_vec_arg(h1), tcgv_vec_arg(l1)); 3047 3048 tcg_temp_free_vec(h1); 3049 tcg_temp_free_vec(h2); 3050 tcg_temp_free_vec(l1); 3051 tcg_temp_free_vec(l2); 3052} 3053 3054void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, 3055 TCGArg a0, ...) 3056{ 3057 va_list va; 3058 TCGv_vec v0, v1, v2, v3, v4, t0; 3059 3060 va_start(va, a0); 3061 v0 = temp_tcgv_vec(arg_temp(a0)); 3062 v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); 3063 v2 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); 3064 3065 switch (opc) { 3066 case INDEX_op_cmp_vec: 3067 expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg)); 3068 break; 3069 3070 case INDEX_op_cmpsel_vec: 3071 v3 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); 3072 v4 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); 3073 expand_vec_cmpsel(type, vece, v0, v1, v2, v3, v4, va_arg(va, TCGArg)); 3074 break; 3075 3076 case INDEX_op_rotrv_vec: 3077 t0 = tcg_temp_new_vec(type); 3078 tcg_gen_neg_vec(vece, t0, v2); 3079 tcg_gen_rotlv_vec(vece, v0, v1, t0); 3080 tcg_temp_free_vec(t0); 3081 break; 3082 3083 case INDEX_op_ssadd_vec: 3084 expand_vec_sat(type, vece, v0, v1, v2, INDEX_op_add_vec); 3085 break; 3086 case INDEX_op_sssub_vec: 3087 expand_vec_sat(type, vece, v0, v1, v2, INDEX_op_sub_vec); 3088 break; 3089 3090 default: 3091 g_assert_not_reached(); 3092 } 3093 va_end(va); 3094} 3095 3096static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) 3097{ 3098 switch (op) { 3099 case INDEX_op_goto_ptr: 3100 return C_O0_I1(r); 3101 3102 case INDEX_op_ld8u_i32: 3103 case INDEX_op_ld8u_i64: 3104 case INDEX_op_ld8s_i32: 3105 case INDEX_op_ld8s_i64: 3106 case INDEX_op_ld16u_i32: 3107 case INDEX_op_ld16u_i64: 3108 case INDEX_op_ld16s_i32: 3109 case INDEX_op_ld16s_i64: 3110 case INDEX_op_ld_i32: 3111 case INDEX_op_ld32u_i64: 3112 case INDEX_op_ld32s_i64: 3113 case INDEX_op_ld_i64: 3114 return C_O1_I1(r, r); 3115 3116 case INDEX_op_st8_i32: 3117 case INDEX_op_st8_i64: 3118 case INDEX_op_st16_i32: 3119 case INDEX_op_st16_i64: 3120 case INDEX_op_st_i32: 3121 case INDEX_op_st32_i64: 3122 case INDEX_op_st_i64: 3123 return C_O0_I2(r, r); 3124 3125 case INDEX_op_add_i32: 3126 case INDEX_op_add_i64: 3127 case INDEX_op_shl_i64: 3128 case INDEX_op_shr_i64: 3129 case INDEX_op_sar_i64: 3130 case INDEX_op_rotl_i32: 3131 case INDEX_op_rotl_i64: 3132 case INDEX_op_rotr_i32: 3133 case INDEX_op_rotr_i64: 3134 case INDEX_op_setcond_i32: 3135 case INDEX_op_negsetcond_i32: 3136 return C_O1_I2(r, r, ri); 3137 case INDEX_op_setcond_i64: 3138 case INDEX_op_negsetcond_i64: 3139 return C_O1_I2(r, r, rA); 3140 3141 case INDEX_op_clz_i64: 3142 return C_O1_I2(r, r, rI); 3143 3144 case INDEX_op_sub_i32: 3145 case INDEX_op_sub_i64: 3146 case INDEX_op_and_i32: 3147 case INDEX_op_or_i32: 3148 case INDEX_op_xor_i32: 3149 return C_O1_I2(r, r, ri); 3150 case INDEX_op_and_i64: 3151 return C_O1_I2(r, r, rNKR); 3152 case INDEX_op_or_i64: 3153 case INDEX_op_xor_i64: 3154 return C_O1_I2(r, r, rK); 3155 3156 case INDEX_op_andc_i32: 3157 case INDEX_op_orc_i32: 3158 case INDEX_op_eqv_i32: 3159 return C_O1_I2(r, r, ri); 3160 case INDEX_op_andc_i64: 3161 return C_O1_I2(r, r, rKR); 3162 case INDEX_op_orc_i64: 3163 case INDEX_op_eqv_i64: 3164 return C_O1_I2(r, r, rNK); 3165 3166 case INDEX_op_nand_i32: 3167 case INDEX_op_nand_i64: 3168 case INDEX_op_nor_i32: 3169 case INDEX_op_nor_i64: 3170 return C_O1_I2(r, r, r); 3171 3172 case INDEX_op_mul_i32: 3173 return (HAVE_FACILITY(MISC_INSN_EXT2) 3174 ? C_O1_I2(r, r, ri) 3175 : C_O1_I2(r, 0, ri)); 3176 case INDEX_op_mul_i64: 3177 return (HAVE_FACILITY(MISC_INSN_EXT2) 3178 ? C_O1_I2(r, r, rJ) 3179 : C_O1_I2(r, 0, rJ)); 3180 3181 case INDEX_op_shl_i32: 3182 case INDEX_op_shr_i32: 3183 case INDEX_op_sar_i32: 3184 return C_O1_I2(r, r, ri); 3185 3186 case INDEX_op_brcond_i32: 3187 return C_O0_I2(r, ri); 3188 case INDEX_op_brcond_i64: 3189 return C_O0_I2(r, rA); 3190 3191 case INDEX_op_bswap16_i32: 3192 case INDEX_op_bswap16_i64: 3193 case INDEX_op_bswap32_i32: 3194 case INDEX_op_bswap32_i64: 3195 case INDEX_op_bswap64_i64: 3196 case INDEX_op_neg_i32: 3197 case INDEX_op_neg_i64: 3198 case INDEX_op_not_i32: 3199 case INDEX_op_not_i64: 3200 case INDEX_op_ext8s_i32: 3201 case INDEX_op_ext8s_i64: 3202 case INDEX_op_ext8u_i32: 3203 case INDEX_op_ext8u_i64: 3204 case INDEX_op_ext16s_i32: 3205 case INDEX_op_ext16s_i64: 3206 case INDEX_op_ext16u_i32: 3207 case INDEX_op_ext16u_i64: 3208 case INDEX_op_ext32s_i64: 3209 case INDEX_op_ext32u_i64: 3210 case INDEX_op_ext_i32_i64: 3211 case INDEX_op_extu_i32_i64: 3212 case INDEX_op_extract_i32: 3213 case INDEX_op_extract_i64: 3214 case INDEX_op_ctpop_i32: 3215 case INDEX_op_ctpop_i64: 3216 return C_O1_I1(r, r); 3217 3218 case INDEX_op_qemu_ld_a32_i32: 3219 case INDEX_op_qemu_ld_a64_i32: 3220 case INDEX_op_qemu_ld_a32_i64: 3221 case INDEX_op_qemu_ld_a64_i64: 3222 return C_O1_I1(r, r); 3223 case INDEX_op_qemu_st_a32_i64: 3224 case INDEX_op_qemu_st_a64_i64: 3225 case INDEX_op_qemu_st_a32_i32: 3226 case INDEX_op_qemu_st_a64_i32: 3227 return C_O0_I2(r, r); 3228 case INDEX_op_qemu_ld_a32_i128: 3229 case INDEX_op_qemu_ld_a64_i128: 3230 return C_O2_I1(o, m, r); 3231 case INDEX_op_qemu_st_a32_i128: 3232 case INDEX_op_qemu_st_a64_i128: 3233 return C_O0_I3(o, m, r); 3234 3235 case INDEX_op_deposit_i32: 3236 case INDEX_op_deposit_i64: 3237 return C_O1_I2(r, rZ, r); 3238 3239 case INDEX_op_movcond_i32: 3240 return C_O1_I4(r, r, ri, rI, r); 3241 case INDEX_op_movcond_i64: 3242 return C_O1_I4(r, r, rA, rI, r); 3243 3244 case INDEX_op_div2_i32: 3245 case INDEX_op_div2_i64: 3246 case INDEX_op_divu2_i32: 3247 case INDEX_op_divu2_i64: 3248 return C_O2_I3(o, m, 0, 1, r); 3249 3250 case INDEX_op_mulu2_i64: 3251 return C_O2_I2(o, m, 0, r); 3252 case INDEX_op_muls2_i64: 3253 return C_O2_I2(o, m, r, r); 3254 3255 case INDEX_op_add2_i32: 3256 case INDEX_op_sub2_i32: 3257 return C_N1_O1_I4(r, r, 0, 1, ri, r); 3258 3259 case INDEX_op_add2_i64: 3260 case INDEX_op_sub2_i64: 3261 return C_N1_O1_I4(r, r, 0, 1, rA, r); 3262 3263 case INDEX_op_st_vec: 3264 return C_O0_I2(v, r); 3265 case INDEX_op_ld_vec: 3266 case INDEX_op_dupm_vec: 3267 return C_O1_I1(v, r); 3268 case INDEX_op_dup_vec: 3269 return C_O1_I1(v, vr); 3270 case INDEX_op_abs_vec: 3271 case INDEX_op_neg_vec: 3272 case INDEX_op_not_vec: 3273 case INDEX_op_rotli_vec: 3274 case INDEX_op_sari_vec: 3275 case INDEX_op_shli_vec: 3276 case INDEX_op_shri_vec: 3277 case INDEX_op_s390_vuph_vec: 3278 case INDEX_op_s390_vupl_vec: 3279 return C_O1_I1(v, v); 3280 case INDEX_op_add_vec: 3281 case INDEX_op_sub_vec: 3282 case INDEX_op_and_vec: 3283 case INDEX_op_andc_vec: 3284 case INDEX_op_or_vec: 3285 case INDEX_op_orc_vec: 3286 case INDEX_op_xor_vec: 3287 case INDEX_op_nand_vec: 3288 case INDEX_op_nor_vec: 3289 case INDEX_op_eqv_vec: 3290 case INDEX_op_cmp_vec: 3291 case INDEX_op_mul_vec: 3292 case INDEX_op_rotlv_vec: 3293 case INDEX_op_rotrv_vec: 3294 case INDEX_op_shlv_vec: 3295 case INDEX_op_shrv_vec: 3296 case INDEX_op_sarv_vec: 3297 case INDEX_op_smax_vec: 3298 case INDEX_op_smin_vec: 3299 case INDEX_op_umax_vec: 3300 case INDEX_op_umin_vec: 3301 case INDEX_op_s390_vpks_vec: 3302 return C_O1_I2(v, v, v); 3303 case INDEX_op_rotls_vec: 3304 case INDEX_op_shls_vec: 3305 case INDEX_op_shrs_vec: 3306 case INDEX_op_sars_vec: 3307 return C_O1_I2(v, v, r); 3308 case INDEX_op_bitsel_vec: 3309 return C_O1_I3(v, v, v, v); 3310 3311 default: 3312 g_assert_not_reached(); 3313 } 3314} 3315 3316/* 3317 * Mainline glibc added HWCAP_S390_VX before it was kernel abi. 3318 * Some distros have fixed this up locally, others have not. 3319 */ 3320#ifndef HWCAP_S390_VXRS 3321#define HWCAP_S390_VXRS 2048 3322#endif 3323 3324static void query_s390_facilities(void) 3325{ 3326 unsigned long hwcap = qemu_getauxval(AT_HWCAP); 3327 const char *which; 3328 3329 /* Is STORE FACILITY LIST EXTENDED available? Honestly, I believe this 3330 is present on all 64-bit systems, but let's check for it anyway. */ 3331 if (hwcap & HWCAP_S390_STFLE) { 3332 register int r0 __asm__("0") = ARRAY_SIZE(s390_facilities) - 1; 3333 register void *r1 __asm__("1") = s390_facilities; 3334 3335 /* stfle 0(%r1) */ 3336 asm volatile(".word 0xb2b0,0x1000" 3337 : "=r"(r0) : "r"(r0), "r"(r1) : "memory", "cc"); 3338 } 3339 3340 /* 3341 * Use of vector registers requires os support beyond the facility bit. 3342 * If the kernel does not advertise support, disable the facility bits. 3343 * There is nothing else we currently care about in the 3rd word, so 3344 * disable VECTOR with one store. 3345 */ 3346 if (!(hwcap & HWCAP_S390_VXRS)) { 3347 s390_facilities[2] = 0; 3348 } 3349 3350 /* 3351 * Minimum supported cpu revision is z196. 3352 * Check for all required facilities. 3353 * ZARCH_ACTIVE is done via preprocessor check for 64-bit. 3354 */ 3355 if (!HAVE_FACILITY(LONG_DISP)) { 3356 which = "long-displacement"; 3357 goto fail; 3358 } 3359 if (!HAVE_FACILITY(EXT_IMM)) { 3360 which = "extended-immediate"; 3361 goto fail; 3362 } 3363 if (!HAVE_FACILITY(GEN_INST_EXT)) { 3364 which = "general-instructions-extension"; 3365 goto fail; 3366 } 3367 /* 3368 * Facility 45 is a big bin that contains: distinct-operands, 3369 * fast-BCR-serialization, high-word, population-count, 3370 * interlocked-access-1, and load/store-on-condition-1 3371 */ 3372 if (!HAVE_FACILITY(45)) { 3373 which = "45"; 3374 goto fail; 3375 } 3376 return; 3377 3378 fail: 3379 error_report("%s: missing required facility %s", __func__, which); 3380 exit(EXIT_FAILURE); 3381} 3382 3383static void tcg_target_init(TCGContext *s) 3384{ 3385 query_s390_facilities(); 3386 3387 tcg_target_available_regs[TCG_TYPE_I32] = 0xffff; 3388 tcg_target_available_regs[TCG_TYPE_I64] = 0xffff; 3389 if (HAVE_FACILITY(VECTOR)) { 3390 tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull; 3391 tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull; 3392 } 3393 3394 tcg_target_call_clobber_regs = 0; 3395 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0); 3396 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1); 3397 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2); 3398 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3); 3399 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R4); 3400 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R5); 3401 /* The r6 register is technically call-saved, but it's also a parameter 3402 register, so it can get killed by setup for the qemu_st helper. */ 3403 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R6); 3404 /* The return register can be considered call-clobbered. */ 3405 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14); 3406 3407 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); 3408 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); 3409 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V2); 3410 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V3); 3411 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V4); 3412 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V5); 3413 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V6); 3414 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V7); 3415 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V16); 3416 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V17); 3417 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V18); 3418 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V19); 3419 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V20); 3420 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V21); 3421 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V22); 3422 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V23); 3423 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V24); 3424 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V25); 3425 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V26); 3426 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V27); 3427 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V28); 3428 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V29); 3429 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V30); 3430 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V31); 3431 3432 s->reserved_regs = 0; 3433 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); 3434 /* XXX many insns can't be used with R0, so we better avoid it for now */ 3435 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); 3436 tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); 3437} 3438 3439#define FRAME_SIZE ((int)(TCG_TARGET_CALL_STACK_OFFSET \ 3440 + TCG_STATIC_CALL_ARGS_SIZE \ 3441 + CPU_TEMP_BUF_NLONGS * sizeof(long))) 3442 3443static void tcg_target_qemu_prologue(TCGContext *s) 3444{ 3445 /* stmg %r6,%r15,48(%r15) (save registers) */ 3446 tcg_out_insn(s, RXY, STMG, TCG_REG_R6, TCG_REG_R15, TCG_REG_R15, 48); 3447 3448 /* aghi %r15,-frame_size */ 3449 tcg_out_insn(s, RI, AGHI, TCG_REG_R15, -FRAME_SIZE); 3450 3451 tcg_set_frame(s, TCG_REG_CALL_STACK, 3452 TCG_STATIC_CALL_ARGS_SIZE + TCG_TARGET_CALL_STACK_OFFSET, 3453 CPU_TEMP_BUF_NLONGS * sizeof(long)); 3454 3455 if (!tcg_use_softmmu && guest_base >= 0x80000) { 3456 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); 3457 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 3458 } 3459 3460 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 3461 3462 /* br %r3 (go to TB) */ 3463 tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, tcg_target_call_iarg_regs[1]); 3464 3465 /* 3466 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 3467 * and fall through to the rest of the epilogue. 3468 */ 3469 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 3470 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, 0); 3471 3472 /* TB epilogue */ 3473 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 3474 3475 /* lmg %r6,%r15,fs+48(%r15) (restore registers) */ 3476 tcg_out_insn(s, RXY, LMG, TCG_REG_R6, TCG_REG_R15, TCG_REG_R15, 3477 FRAME_SIZE + 48); 3478 3479 /* br %r14 (return) */ 3480 tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_R14); 3481} 3482 3483static void tcg_out_tb_start(TCGContext *s) 3484{ 3485 /* nothing to do */ 3486} 3487 3488static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 3489{ 3490 memset(p, 0x07, count * sizeof(tcg_insn_unit)); 3491} 3492 3493typedef struct { 3494 DebugFrameHeader h; 3495 uint8_t fde_def_cfa[4]; 3496 uint8_t fde_reg_ofs[18]; 3497} DebugFrame; 3498 3499/* We're expecting a 2 byte uleb128 encoded value. */ 3500QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14)); 3501 3502#define ELF_HOST_MACHINE EM_S390 3503 3504static const DebugFrame debug_frame = { 3505 .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ 3506 .h.cie.id = -1, 3507 .h.cie.version = 1, 3508 .h.cie.code_align = 1, 3509 .h.cie.data_align = 8, /* sleb128 8 */ 3510 .h.cie.return_column = TCG_REG_R14, 3511 3512 /* Total FDE size does not include the "len" member. */ 3513 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 3514 3515 .fde_def_cfa = { 3516 12, TCG_REG_CALL_STACK, /* DW_CFA_def_cfa %r15, ... */ 3517 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 3518 (FRAME_SIZE >> 7) 3519 }, 3520 .fde_reg_ofs = { 3521 0x86, 6, /* DW_CFA_offset, %r6, 48 */ 3522 0x87, 7, /* DW_CFA_offset, %r7, 56 */ 3523 0x88, 8, /* DW_CFA_offset, %r8, 64 */ 3524 0x89, 9, /* DW_CFA_offset, %r92, 72 */ 3525 0x8a, 10, /* DW_CFA_offset, %r10, 80 */ 3526 0x8b, 11, /* DW_CFA_offset, %r11, 88 */ 3527 0x8c, 12, /* DW_CFA_offset, %r12, 96 */ 3528 0x8d, 13, /* DW_CFA_offset, %r13, 104 */ 3529 0x8e, 14, /* DW_CFA_offset, %r14, 112 */ 3530 } 3531}; 3532 3533void tcg_register_jit(const void *buf, size_t buf_size) 3534{ 3535 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 3536} 3537