1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2009 Ulrich Hecht <uli@suse.de> 5 * Copyright (c) 2009 Alexander Graf <agraf@suse.de> 6 * Copyright (c) 2010 Richard Henderson <rth@twiddle.net> 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27#include "../tcg-ldst.c.inc" 28#include "../tcg-pool.c.inc" 29#include "elf.h" 30 31/* Used for function call generation. */ 32#define TCG_TARGET_STACK_ALIGN 8 33#define TCG_TARGET_CALL_STACK_OFFSET 160 34#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EXTEND 35#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL 36#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_BY_REF 37#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF 38 39#define TCG_CT_CONST_S16 (1 << 8) 40#define TCG_CT_CONST_S32 (1 << 9) 41#define TCG_CT_CONST_U32 (1 << 10) 42#define TCG_CT_CONST_ZERO (1 << 11) 43#define TCG_CT_CONST_P32 (1 << 12) 44#define TCG_CT_CONST_INV (1 << 13) 45#define TCG_CT_CONST_INVRISBG (1 << 14) 46#define TCG_CT_CONST_CMP (1 << 15) 47#define TCG_CT_CONST_M1 (1 << 16) 48 49#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 16) 50#define ALL_VECTOR_REGS MAKE_64BIT_MASK(32, 32) 51 52/* Several places within the instruction set 0 means "no register" 53 rather than TCG_REG_R0. */ 54#define TCG_REG_NONE 0 55 56/* A scratch register that may be be used throughout the backend. */ 57#define TCG_TMP0 TCG_REG_R1 58#define TCG_VEC_TMP0 TCG_REG_V31 59 60#define TCG_GUEST_BASE_REG TCG_REG_R13 61 62/* All of the following instructions are prefixed with their instruction 63 format, and are defined as 8- or 16-bit quantities, even when the two 64 halves of the 16-bit quantity may appear 32 bits apart in the insn. 65 This makes it easy to copy the values from the tables in Appendix B. */ 66typedef enum S390Opcode { 67 RIL_AFI = 0xc209, 68 RIL_AGFI = 0xc208, 69 RIL_ALFI = 0xc20b, 70 RIL_ALGFI = 0xc20a, 71 RIL_BRASL = 0xc005, 72 RIL_BRCL = 0xc004, 73 RIL_CFI = 0xc20d, 74 RIL_CGFI = 0xc20c, 75 RIL_CLFI = 0xc20f, 76 RIL_CLGFI = 0xc20e, 77 RIL_CLRL = 0xc60f, 78 RIL_CLGRL = 0xc60a, 79 RIL_CRL = 0xc60d, 80 RIL_CGRL = 0xc608, 81 RIL_IIHF = 0xc008, 82 RIL_IILF = 0xc009, 83 RIL_LARL = 0xc000, 84 RIL_LGFI = 0xc001, 85 RIL_LGRL = 0xc408, 86 RIL_LLIHF = 0xc00e, 87 RIL_LLILF = 0xc00f, 88 RIL_LRL = 0xc40d, 89 RIL_MSFI = 0xc201, 90 RIL_MSGFI = 0xc200, 91 RIL_NIHF = 0xc00a, 92 RIL_NILF = 0xc00b, 93 RIL_OIHF = 0xc00c, 94 RIL_OILF = 0xc00d, 95 RIL_SLFI = 0xc205, 96 RIL_SLGFI = 0xc204, 97 RIL_XIHF = 0xc006, 98 RIL_XILF = 0xc007, 99 100 RI_AGHI = 0xa70b, 101 RI_AHI = 0xa70a, 102 RI_BRC = 0xa704, 103 RI_CHI = 0xa70e, 104 RI_CGHI = 0xa70f, 105 RI_IIHH = 0xa500, 106 RI_IIHL = 0xa501, 107 RI_IILH = 0xa502, 108 RI_IILL = 0xa503, 109 RI_LGHI = 0xa709, 110 RI_LLIHH = 0xa50c, 111 RI_LLIHL = 0xa50d, 112 RI_LLILH = 0xa50e, 113 RI_LLILL = 0xa50f, 114 RI_MGHI = 0xa70d, 115 RI_MHI = 0xa70c, 116 RI_NIHH = 0xa504, 117 RI_NIHL = 0xa505, 118 RI_NILH = 0xa506, 119 RI_NILL = 0xa507, 120 RI_OIHH = 0xa508, 121 RI_OIHL = 0xa509, 122 RI_OILH = 0xa50a, 123 RI_OILL = 0xa50b, 124 RI_TMLL = 0xa701, 125 RI_TMLH = 0xa700, 126 RI_TMHL = 0xa703, 127 RI_TMHH = 0xa702, 128 129 RIEb_CGRJ = 0xec64, 130 RIEb_CLGRJ = 0xec65, 131 RIEb_CLRJ = 0xec77, 132 RIEb_CRJ = 0xec76, 133 134 RIEc_CGIJ = 0xec7c, 135 RIEc_CIJ = 0xec7e, 136 RIEc_CLGIJ = 0xec7d, 137 RIEc_CLIJ = 0xec7f, 138 139 RIEf_RISBG = 0xec55, 140 141 RIEg_LOCGHI = 0xec46, 142 143 RRE_AGR = 0xb908, 144 RRE_ALGR = 0xb90a, 145 RRE_ALCR = 0xb998, 146 RRE_ALCGR = 0xb988, 147 RRE_ALGFR = 0xb91a, 148 RRE_CGR = 0xb920, 149 RRE_CLGR = 0xb921, 150 RRE_DLGR = 0xb987, 151 RRE_DLR = 0xb997, 152 RRE_DSGFR = 0xb91d, 153 RRE_DSGR = 0xb90d, 154 RRE_FLOGR = 0xb983, 155 RRE_LGBR = 0xb906, 156 RRE_LCGR = 0xb903, 157 RRE_LGFR = 0xb914, 158 RRE_LGHR = 0xb907, 159 RRE_LGR = 0xb904, 160 RRE_LLGCR = 0xb984, 161 RRE_LLGFR = 0xb916, 162 RRE_LLGHR = 0xb985, 163 RRE_LRVR = 0xb91f, 164 RRE_LRVGR = 0xb90f, 165 RRE_LTGR = 0xb902, 166 RRE_MLGR = 0xb986, 167 RRE_MSGR = 0xb90c, 168 RRE_MSR = 0xb252, 169 RRE_NGR = 0xb980, 170 RRE_OGR = 0xb981, 171 RRE_SGR = 0xb909, 172 RRE_SLGR = 0xb90b, 173 RRE_SLBR = 0xb999, 174 RRE_SLBGR = 0xb989, 175 RRE_XGR = 0xb982, 176 177 RRFa_MGRK = 0xb9ec, 178 RRFa_MSRKC = 0xb9fd, 179 RRFa_MSGRKC = 0xb9ed, 180 RRFa_NCRK = 0xb9f5, 181 RRFa_NCGRK = 0xb9e5, 182 RRFa_NNRK = 0xb974, 183 RRFa_NNGRK = 0xb964, 184 RRFa_NORK = 0xb976, 185 RRFa_NOGRK = 0xb966, 186 RRFa_NRK = 0xb9f4, 187 RRFa_NGRK = 0xb9e4, 188 RRFa_NXRK = 0xb977, 189 RRFa_NXGRK = 0xb967, 190 RRFa_OCRK = 0xb975, 191 RRFa_OCGRK = 0xb965, 192 RRFa_ORK = 0xb9f6, 193 RRFa_OGRK = 0xb9e6, 194 RRFa_SRK = 0xb9f9, 195 RRFa_SGRK = 0xb9e9, 196 RRFa_SLRK = 0xb9fb, 197 RRFa_SLGRK = 0xb9eb, 198 RRFa_XRK = 0xb9f7, 199 RRFa_XGRK = 0xb9e7, 200 201 RRFam_SELGR = 0xb9e3, 202 203 RRFc_LOCR = 0xb9f2, 204 RRFc_LOCGR = 0xb9e2, 205 RRFc_POPCNT = 0xb9e1, 206 207 RR_AR = 0x1a, 208 RR_ALR = 0x1e, 209 RR_BASR = 0x0d, 210 RR_BCR = 0x07, 211 RR_CLR = 0x15, 212 RR_CR = 0x19, 213 RR_DR = 0x1d, 214 RR_LCR = 0x13, 215 RR_LR = 0x18, 216 RR_LTR = 0x12, 217 RR_NR = 0x14, 218 RR_OR = 0x16, 219 RR_SR = 0x1b, 220 RR_SLR = 0x1f, 221 RR_XR = 0x17, 222 223 RSY_RLL = 0xeb1d, 224 RSY_RLLG = 0xeb1c, 225 RSY_SLLG = 0xeb0d, 226 RSY_SLLK = 0xebdf, 227 RSY_SRAG = 0xeb0a, 228 RSY_SRAK = 0xebdc, 229 RSY_SRLG = 0xeb0c, 230 RSY_SRLK = 0xebde, 231 232 RS_SLL = 0x89, 233 RS_SRA = 0x8a, 234 RS_SRL = 0x88, 235 236 RXY_AG = 0xe308, 237 RXY_AY = 0xe35a, 238 RXY_CG = 0xe320, 239 RXY_CLG = 0xe321, 240 RXY_CLY = 0xe355, 241 RXY_CY = 0xe359, 242 RXY_LAY = 0xe371, 243 RXY_LB = 0xe376, 244 RXY_LG = 0xe304, 245 RXY_LGB = 0xe377, 246 RXY_LGF = 0xe314, 247 RXY_LGH = 0xe315, 248 RXY_LHY = 0xe378, 249 RXY_LLGC = 0xe390, 250 RXY_LLGF = 0xe316, 251 RXY_LLGH = 0xe391, 252 RXY_LMG = 0xeb04, 253 RXY_LPQ = 0xe38f, 254 RXY_LRV = 0xe31e, 255 RXY_LRVG = 0xe30f, 256 RXY_LRVH = 0xe31f, 257 RXY_LY = 0xe358, 258 RXY_NG = 0xe380, 259 RXY_OG = 0xe381, 260 RXY_STCY = 0xe372, 261 RXY_STG = 0xe324, 262 RXY_STHY = 0xe370, 263 RXY_STMG = 0xeb24, 264 RXY_STPQ = 0xe38e, 265 RXY_STRV = 0xe33e, 266 RXY_STRVG = 0xe32f, 267 RXY_STRVH = 0xe33f, 268 RXY_STY = 0xe350, 269 RXY_XG = 0xe382, 270 271 RX_A = 0x5a, 272 RX_C = 0x59, 273 RX_L = 0x58, 274 RX_LA = 0x41, 275 RX_LH = 0x48, 276 RX_ST = 0x50, 277 RX_STC = 0x42, 278 RX_STH = 0x40, 279 280 VRIa_VGBM = 0xe744, 281 VRIa_VREPI = 0xe745, 282 VRIb_VGM = 0xe746, 283 VRIc_VREP = 0xe74d, 284 285 VRRa_VLC = 0xe7de, 286 VRRa_VLP = 0xe7df, 287 VRRa_VLR = 0xe756, 288 VRRc_VA = 0xe7f3, 289 VRRc_VCEQ = 0xe7f8, /* we leave the m5 cs field 0 */ 290 VRRc_VCH = 0xe7fb, /* " */ 291 VRRc_VCHL = 0xe7f9, /* " */ 292 VRRc_VERLLV = 0xe773, 293 VRRc_VESLV = 0xe770, 294 VRRc_VESRAV = 0xe77a, 295 VRRc_VESRLV = 0xe778, 296 VRRc_VML = 0xe7a2, 297 VRRc_VMN = 0xe7fe, 298 VRRc_VMNL = 0xe7fc, 299 VRRc_VMX = 0xe7ff, 300 VRRc_VMXL = 0xe7fd, 301 VRRc_VN = 0xe768, 302 VRRc_VNC = 0xe769, 303 VRRc_VNN = 0xe76e, 304 VRRc_VNO = 0xe76b, 305 VRRc_VNX = 0xe76c, 306 VRRc_VO = 0xe76a, 307 VRRc_VOC = 0xe76f, 308 VRRc_VPKS = 0xe797, /* we leave the m5 cs field 0 */ 309 VRRc_VS = 0xe7f7, 310 VRRa_VUPH = 0xe7d7, 311 VRRa_VUPL = 0xe7d6, 312 VRRc_VX = 0xe76d, 313 VRRe_VSEL = 0xe78d, 314 VRRf_VLVGP = 0xe762, 315 316 VRSa_VERLL = 0xe733, 317 VRSa_VESL = 0xe730, 318 VRSa_VESRA = 0xe73a, 319 VRSa_VESRL = 0xe738, 320 VRSb_VLVG = 0xe722, 321 VRSc_VLGV = 0xe721, 322 323 VRX_VL = 0xe706, 324 VRX_VLLEZ = 0xe704, 325 VRX_VLREP = 0xe705, 326 VRX_VST = 0xe70e, 327 VRX_VSTEF = 0xe70b, 328 VRX_VSTEG = 0xe70a, 329 330 NOP = 0x0707, 331} S390Opcode; 332 333#ifdef CONFIG_DEBUG_TCG 334static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 335 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", 336 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", 337 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 338 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7", 339 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15", 340 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23", 341 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31", 342}; 343#endif 344 345/* Since R6 is a potential argument register, choose it last of the 346 call-saved registers. Likewise prefer the call-clobbered registers 347 in reverse order to maximize the chance of avoiding the arguments. */ 348static const int tcg_target_reg_alloc_order[] = { 349 /* Call saved registers. */ 350 TCG_REG_R13, 351 TCG_REG_R12, 352 TCG_REG_R11, 353 TCG_REG_R10, 354 TCG_REG_R9, 355 TCG_REG_R8, 356 TCG_REG_R7, 357 TCG_REG_R6, 358 /* Call clobbered registers. */ 359 TCG_REG_R14, 360 TCG_REG_R0, 361 TCG_REG_R1, 362 /* Argument registers, in reverse order of allocation. */ 363 TCG_REG_R5, 364 TCG_REG_R4, 365 TCG_REG_R3, 366 TCG_REG_R2, 367 368 /* V8-V15 are call saved, and omitted. */ 369 TCG_REG_V0, 370 TCG_REG_V1, 371 TCG_REG_V2, 372 TCG_REG_V3, 373 TCG_REG_V4, 374 TCG_REG_V5, 375 TCG_REG_V6, 376 TCG_REG_V7, 377 TCG_REG_V16, 378 TCG_REG_V17, 379 TCG_REG_V18, 380 TCG_REG_V19, 381 TCG_REG_V20, 382 TCG_REG_V21, 383 TCG_REG_V22, 384 TCG_REG_V23, 385 TCG_REG_V24, 386 TCG_REG_V25, 387 TCG_REG_V26, 388 TCG_REG_V27, 389 TCG_REG_V28, 390 TCG_REG_V29, 391 TCG_REG_V30, 392 TCG_REG_V31, 393}; 394 395static const int tcg_target_call_iarg_regs[] = { 396 TCG_REG_R2, 397 TCG_REG_R3, 398 TCG_REG_R4, 399 TCG_REG_R5, 400 TCG_REG_R6, 401}; 402 403static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 404{ 405 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 406 tcg_debug_assert(slot == 0); 407 return TCG_REG_R2; 408} 409 410#define S390_CC_EQ 8 411#define S390_CC_LT 4 412#define S390_CC_GT 2 413#define S390_CC_OV 1 414#define S390_CC_NE (S390_CC_LT | S390_CC_GT) 415#define S390_CC_LE (S390_CC_LT | S390_CC_EQ) 416#define S390_CC_GE (S390_CC_GT | S390_CC_EQ) 417#define S390_CC_NEVER 0 418#define S390_CC_ALWAYS 15 419 420#define S390_TM_EQ 8 /* CC == 0 */ 421#define S390_TM_NE 7 /* CC in {1,2,3} */ 422 423/* Condition codes that result from a COMPARE and COMPARE LOGICAL. */ 424static const uint8_t tcg_cond_to_s390_cond[16] = { 425 [TCG_COND_EQ] = S390_CC_EQ, 426 [TCG_COND_NE] = S390_CC_NE, 427 [TCG_COND_TSTEQ] = S390_CC_EQ, 428 [TCG_COND_TSTNE] = S390_CC_NE, 429 [TCG_COND_LT] = S390_CC_LT, 430 [TCG_COND_LE] = S390_CC_LE, 431 [TCG_COND_GT] = S390_CC_GT, 432 [TCG_COND_GE] = S390_CC_GE, 433 [TCG_COND_LTU] = S390_CC_LT, 434 [TCG_COND_LEU] = S390_CC_LE, 435 [TCG_COND_GTU] = S390_CC_GT, 436 [TCG_COND_GEU] = S390_CC_GE, 437}; 438 439/* Condition codes that result from a LOAD AND TEST. Here, we have no 440 unsigned instruction variation, however since the test is vs zero we 441 can re-map the outcomes appropriately. */ 442static const uint8_t tcg_cond_to_ltr_cond[16] = { 443 [TCG_COND_EQ] = S390_CC_EQ, 444 [TCG_COND_NE] = S390_CC_NE, 445 [TCG_COND_TSTEQ] = S390_CC_ALWAYS, 446 [TCG_COND_TSTNE] = S390_CC_NEVER, 447 [TCG_COND_LT] = S390_CC_LT, 448 [TCG_COND_LE] = S390_CC_LE, 449 [TCG_COND_GT] = S390_CC_GT, 450 [TCG_COND_GE] = S390_CC_GE, 451 [TCG_COND_LTU] = S390_CC_NEVER, 452 [TCG_COND_LEU] = S390_CC_EQ, 453 [TCG_COND_GTU] = S390_CC_NE, 454 [TCG_COND_GEU] = S390_CC_ALWAYS, 455}; 456 457static const tcg_insn_unit *tb_ret_addr; 458uint64_t s390_facilities[3]; 459 460static inline bool is_general_reg(TCGReg r) 461{ 462 return r <= TCG_REG_R15; 463} 464 465static inline bool is_vector_reg(TCGReg r) 466{ 467 return r >= TCG_REG_V0 && r <= TCG_REG_V31; 468} 469 470static bool patch_reloc(tcg_insn_unit *src_rw, int type, 471 intptr_t value, intptr_t addend) 472{ 473 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 474 intptr_t pcrel2; 475 uint32_t old; 476 477 value += addend; 478 pcrel2 = (tcg_insn_unit *)value - src_rx; 479 480 switch (type) { 481 case R_390_PC16DBL: 482 if (pcrel2 == (int16_t)pcrel2) { 483 tcg_patch16(src_rw, pcrel2); 484 return true; 485 } 486 break; 487 case R_390_PC32DBL: 488 if (pcrel2 == (int32_t)pcrel2) { 489 tcg_patch32(src_rw, pcrel2); 490 return true; 491 } 492 break; 493 case R_390_20: 494 if (value == sextract64(value, 0, 20)) { 495 old = *(uint32_t *)src_rw & 0xf00000ff; 496 old |= ((value & 0xfff) << 16) | ((value & 0xff000) >> 4); 497 tcg_patch32(src_rw, old); 498 return true; 499 } 500 break; 501 default: 502 g_assert_not_reached(); 503 } 504 return false; 505} 506 507static int is_const_p16(uint64_t val) 508{ 509 for (int i = 0; i < 4; ++i) { 510 uint64_t mask = 0xffffull << (i * 16); 511 if ((val & ~mask) == 0) { 512 return i; 513 } 514 } 515 return -1; 516} 517 518static int is_const_p32(uint64_t val) 519{ 520 if ((val & 0xffffffff00000000ull) == 0) { 521 return 0; 522 } 523 if ((val & 0x00000000ffffffffull) == 0) { 524 return 1; 525 } 526 return -1; 527} 528 529/* 530 * Accept bit patterns like these: 531 * 0....01....1 532 * 1....10....0 533 * 1..10..01..1 534 * 0..01..10..0 535 * Copied from gcc sources. 536 */ 537static bool risbg_mask(uint64_t c) 538{ 539 uint64_t lsb; 540 /* We don't change the number of transitions by inverting, 541 so make sure we start with the LSB zero. */ 542 if (c & 1) { 543 c = ~c; 544 } 545 /* Reject all zeros or all ones. */ 546 if (c == 0) { 547 return false; 548 } 549 /* Find the first transition. */ 550 lsb = c & -c; 551 /* Invert to look for a second transition. */ 552 c = ~c; 553 /* Erase the first transition. */ 554 c &= -lsb; 555 /* Find the second transition, if any. */ 556 lsb = c & -c; 557 /* Match if all the bits are 1's, or if c is zero. */ 558 return c == -lsb; 559} 560 561/* Test if a constant matches the constraint. */ 562static bool tcg_target_const_match(int64_t val, int ct, 563 TCGType type, TCGCond cond, int vece) 564{ 565 uint64_t uval = val; 566 567 if (ct & TCG_CT_CONST) { 568 return true; 569 } 570 if (type == TCG_TYPE_I32) { 571 uval = (uint32_t)val; 572 val = (int32_t)val; 573 } 574 575 if (ct & TCG_CT_CONST_CMP) { 576 if (is_tst_cond(cond)) { 577 if (is_const_p16(uval) >= 0) { 578 return true; /* TMxx */ 579 } 580 if (risbg_mask(uval)) { 581 return true; /* RISBG */ 582 } 583 return false; 584 } 585 586 if (type == TCG_TYPE_I32) { 587 return true; 588 } 589 590 switch (cond) { 591 case TCG_COND_EQ: 592 case TCG_COND_NE: 593 ct |= TCG_CT_CONST_S32 | TCG_CT_CONST_U32; /* CGFI or CLGFI */ 594 break; 595 case TCG_COND_LT: 596 case TCG_COND_GE: 597 case TCG_COND_LE: 598 case TCG_COND_GT: 599 ct |= TCG_CT_CONST_S32; /* CGFI */ 600 break; 601 case TCG_COND_LTU: 602 case TCG_COND_GEU: 603 case TCG_COND_LEU: 604 case TCG_COND_GTU: 605 ct |= TCG_CT_CONST_U32; /* CLGFI */ 606 break; 607 case TCG_COND_TSTNE: 608 case TCG_COND_TSTEQ: 609 /* checked above, fallthru */ 610 default: 611 g_assert_not_reached(); 612 } 613 } 614 615 if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) { 616 return true; 617 } 618 if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) { 619 return true; 620 } 621 if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) { 622 return true; 623 } 624 if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 625 return true; 626 } 627 if ((ct & TCG_CT_CONST_M1) && val == -1) { 628 return true; 629 } 630 631 if (ct & TCG_CT_CONST_INV) { 632 val = ~val; 633 } 634 if ((ct & TCG_CT_CONST_P32) && is_const_p32(val) >= 0) { 635 return true; 636 } 637 if ((ct & TCG_CT_CONST_INVRISBG) && risbg_mask(~val)) { 638 return true; 639 } 640 return false; 641} 642 643/* Emit instructions according to the given instruction format. */ 644 645static void tcg_out_insn_RR(TCGContext *s, S390Opcode op, TCGReg r1, TCGReg r2) 646{ 647 tcg_out16(s, (op << 8) | (r1 << 4) | r2); 648} 649 650static void tcg_out_insn_RRE(TCGContext *s, S390Opcode op, 651 TCGReg r1, TCGReg r2) 652{ 653 tcg_out32(s, (op << 16) | (r1 << 4) | r2); 654} 655 656/* RRF-a without the m4 field */ 657static void tcg_out_insn_RRFa(TCGContext *s, S390Opcode op, 658 TCGReg r1, TCGReg r2, TCGReg r3) 659{ 660 tcg_out32(s, (op << 16) | (r3 << 12) | (r1 << 4) | r2); 661} 662 663/* RRF-a with the m4 field */ 664static void tcg_out_insn_RRFam(TCGContext *s, S390Opcode op, 665 TCGReg r1, TCGReg r2, TCGReg r3, int m4) 666{ 667 tcg_out32(s, (op << 16) | (r3 << 12) | (m4 << 8) | (r1 << 4) | r2); 668} 669 670static void tcg_out_insn_RRFc(TCGContext *s, S390Opcode op, 671 TCGReg r1, TCGReg r2, int m3) 672{ 673 tcg_out32(s, (op << 16) | (m3 << 12) | (r1 << 4) | r2); 674} 675 676static void tcg_out_insn_RI(TCGContext *s, S390Opcode op, TCGReg r1, int i2) 677{ 678 tcg_out32(s, (op << 16) | (r1 << 20) | (i2 & 0xffff)); 679} 680 681static void tcg_out_insn_RIEg(TCGContext *s, S390Opcode op, TCGReg r1, 682 int i2, int m3) 683{ 684 tcg_out16(s, (op & 0xff00) | (r1 << 4) | m3); 685 tcg_out32(s, (i2 << 16) | (op & 0xff)); 686} 687 688static void tcg_out_insn_RIL(TCGContext *s, S390Opcode op, TCGReg r1, int i2) 689{ 690 tcg_out16(s, op | (r1 << 4)); 691 tcg_out32(s, i2); 692} 693 694static void tcg_out_insn_RS(TCGContext *s, S390Opcode op, TCGReg r1, 695 TCGReg b2, TCGReg r3, int disp) 696{ 697 tcg_out32(s, (op << 24) | (r1 << 20) | (r3 << 16) | (b2 << 12) 698 | (disp & 0xfff)); 699} 700 701static void tcg_out_insn_RSY(TCGContext *s, S390Opcode op, TCGReg r1, 702 TCGReg b2, TCGReg r3, int disp) 703{ 704 tcg_out16(s, (op & 0xff00) | (r1 << 4) | r3); 705 tcg_out32(s, (op & 0xff) | (b2 << 28) 706 | ((disp & 0xfff) << 16) | ((disp & 0xff000) >> 4)); 707} 708 709#define tcg_out_insn_RX tcg_out_insn_RS 710#define tcg_out_insn_RXY tcg_out_insn_RSY 711 712static int RXB(TCGReg v1, TCGReg v2, TCGReg v3, TCGReg v4) 713{ 714 /* 715 * Shift bit 4 of each regno to its corresponding bit of RXB. 716 * RXB itself begins at bit 8 of the instruction so 8 - 4 = 4 717 * is the left-shift of the 4th operand. 718 */ 719 return ((v1 & 0x10) << (4 + 3)) 720 | ((v2 & 0x10) << (4 + 2)) 721 | ((v3 & 0x10) << (4 + 1)) 722 | ((v4 & 0x10) << (4 + 0)); 723} 724 725static void tcg_out_insn_VRIa(TCGContext *s, S390Opcode op, 726 TCGReg v1, uint16_t i2, int m3) 727{ 728 tcg_debug_assert(is_vector_reg(v1)); 729 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4)); 730 tcg_out16(s, i2); 731 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m3 << 12)); 732} 733 734static void tcg_out_insn_VRIb(TCGContext *s, S390Opcode op, 735 TCGReg v1, uint8_t i2, uint8_t i3, int m4) 736{ 737 tcg_debug_assert(is_vector_reg(v1)); 738 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4)); 739 tcg_out16(s, (i2 << 8) | (i3 & 0xff)); 740 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m4 << 12)); 741} 742 743static void tcg_out_insn_VRIc(TCGContext *s, S390Opcode op, 744 TCGReg v1, uint16_t i2, TCGReg v3, int m4) 745{ 746 tcg_debug_assert(is_vector_reg(v1)); 747 tcg_debug_assert(is_vector_reg(v3)); 748 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v3 & 0xf)); 749 tcg_out16(s, i2); 750 tcg_out16(s, (op & 0x00ff) | RXB(v1, v3, 0, 0) | (m4 << 12)); 751} 752 753static void tcg_out_insn_VRRa(TCGContext *s, S390Opcode op, 754 TCGReg v1, TCGReg v2, int m3) 755{ 756 tcg_debug_assert(is_vector_reg(v1)); 757 tcg_debug_assert(is_vector_reg(v2)); 758 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v2 & 0xf)); 759 tcg_out32(s, (op & 0x00ff) | RXB(v1, v2, 0, 0) | (m3 << 12)); 760} 761 762static void tcg_out_insn_VRRc(TCGContext *s, S390Opcode op, 763 TCGReg v1, TCGReg v2, TCGReg v3, int m4) 764{ 765 tcg_debug_assert(is_vector_reg(v1)); 766 tcg_debug_assert(is_vector_reg(v2)); 767 tcg_debug_assert(is_vector_reg(v3)); 768 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v2 & 0xf)); 769 tcg_out16(s, v3 << 12); 770 tcg_out16(s, (op & 0x00ff) | RXB(v1, v2, v3, 0) | (m4 << 12)); 771} 772 773static void tcg_out_insn_VRRe(TCGContext *s, S390Opcode op, 774 TCGReg v1, TCGReg v2, TCGReg v3, TCGReg v4) 775{ 776 tcg_debug_assert(is_vector_reg(v1)); 777 tcg_debug_assert(is_vector_reg(v2)); 778 tcg_debug_assert(is_vector_reg(v3)); 779 tcg_debug_assert(is_vector_reg(v4)); 780 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v2 & 0xf)); 781 tcg_out16(s, v3 << 12); 782 tcg_out16(s, (op & 0x00ff) | RXB(v1, v2, v3, v4) | (v4 << 12)); 783} 784 785static void tcg_out_insn_VRRf(TCGContext *s, S390Opcode op, 786 TCGReg v1, TCGReg r2, TCGReg r3) 787{ 788 tcg_debug_assert(is_vector_reg(v1)); 789 tcg_debug_assert(is_general_reg(r2)); 790 tcg_debug_assert(is_general_reg(r3)); 791 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | r2); 792 tcg_out16(s, r3 << 12); 793 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0)); 794} 795 796static void tcg_out_insn_VRSa(TCGContext *s, S390Opcode op, TCGReg v1, 797 intptr_t d2, TCGReg b2, TCGReg v3, int m4) 798{ 799 tcg_debug_assert(is_vector_reg(v1)); 800 tcg_debug_assert(d2 >= 0 && d2 <= 0xfff); 801 tcg_debug_assert(is_general_reg(b2)); 802 tcg_debug_assert(is_vector_reg(v3)); 803 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v3 & 0xf)); 804 tcg_out16(s, b2 << 12 | d2); 805 tcg_out16(s, (op & 0x00ff) | RXB(v1, v3, 0, 0) | (m4 << 12)); 806} 807 808static void tcg_out_insn_VRSb(TCGContext *s, S390Opcode op, TCGReg v1, 809 intptr_t d2, TCGReg b2, TCGReg r3, int m4) 810{ 811 tcg_debug_assert(is_vector_reg(v1)); 812 tcg_debug_assert(d2 >= 0 && d2 <= 0xfff); 813 tcg_debug_assert(is_general_reg(b2)); 814 tcg_debug_assert(is_general_reg(r3)); 815 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | r3); 816 tcg_out16(s, b2 << 12 | d2); 817 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m4 << 12)); 818} 819 820static void tcg_out_insn_VRSc(TCGContext *s, S390Opcode op, TCGReg r1, 821 intptr_t d2, TCGReg b2, TCGReg v3, int m4) 822{ 823 tcg_debug_assert(is_general_reg(r1)); 824 tcg_debug_assert(d2 >= 0 && d2 <= 0xfff); 825 tcg_debug_assert(is_general_reg(b2)); 826 tcg_debug_assert(is_vector_reg(v3)); 827 tcg_out16(s, (op & 0xff00) | (r1 << 4) | (v3 & 0xf)); 828 tcg_out16(s, b2 << 12 | d2); 829 tcg_out16(s, (op & 0x00ff) | RXB(0, v3, 0, 0) | (m4 << 12)); 830} 831 832static void tcg_out_insn_VRX(TCGContext *s, S390Opcode op, TCGReg v1, 833 TCGReg b2, TCGReg x2, intptr_t d2, int m3) 834{ 835 tcg_debug_assert(is_vector_reg(v1)); 836 tcg_debug_assert(d2 >= 0 && d2 <= 0xfff); 837 tcg_debug_assert(is_general_reg(x2)); 838 tcg_debug_assert(is_general_reg(b2)); 839 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | x2); 840 tcg_out16(s, (b2 << 12) | d2); 841 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m3 << 12)); 842} 843 844/* Emit an opcode with "type-checking" of the format. */ 845#define tcg_out_insn(S, FMT, OP, ...) \ 846 glue(tcg_out_insn_,FMT)(S, glue(glue(FMT,_),OP), ## __VA_ARGS__) 847 848 849/* emit 64-bit shifts */ 850static void tcg_out_sh64(TCGContext* s, S390Opcode op, TCGReg dest, 851 TCGReg src, TCGReg sh_reg, int sh_imm) 852{ 853 tcg_out_insn_RSY(s, op, dest, sh_reg, src, sh_imm); 854} 855 856/* emit 32-bit shifts */ 857static void tcg_out_sh32(TCGContext* s, S390Opcode op, TCGReg dest, 858 TCGReg sh_reg, int sh_imm) 859{ 860 tcg_out_insn_RS(s, op, dest, sh_reg, 0, sh_imm); 861} 862 863static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg dst, TCGReg src) 864{ 865 if (src == dst) { 866 return true; 867 } 868 switch (type) { 869 case TCG_TYPE_I32: 870 if (likely(is_general_reg(dst) && is_general_reg(src))) { 871 tcg_out_insn(s, RR, LR, dst, src); 872 break; 873 } 874 /* fallthru */ 875 876 case TCG_TYPE_I64: 877 if (likely(is_general_reg(dst))) { 878 if (likely(is_general_reg(src))) { 879 tcg_out_insn(s, RRE, LGR, dst, src); 880 } else { 881 tcg_out_insn(s, VRSc, VLGV, dst, 0, 0, src, 3); 882 } 883 break; 884 } else if (is_general_reg(src)) { 885 tcg_out_insn(s, VRSb, VLVG, dst, 0, 0, src, 3); 886 break; 887 } 888 /* fallthru */ 889 890 case TCG_TYPE_V64: 891 case TCG_TYPE_V128: 892 tcg_out_insn(s, VRRa, VLR, dst, src, 0); 893 break; 894 895 default: 896 g_assert_not_reached(); 897 } 898 return true; 899} 900 901static const S390Opcode li_insns[4] = { 902 RI_LLILL, RI_LLILH, RI_LLIHL, RI_LLIHH 903}; 904static const S390Opcode oi_insns[4] = { 905 RI_OILL, RI_OILH, RI_OIHL, RI_OIHH 906}; 907static const S390Opcode lif_insns[2] = { 908 RIL_LLILF, RIL_LLIHF, 909}; 910static const S390Opcode tm_insns[4] = { 911 RI_TMLL, RI_TMLH, RI_TMHL, RI_TMHH 912}; 913 914/* load a register with an immediate value */ 915static void tcg_out_movi(TCGContext *s, TCGType type, 916 TCGReg ret, tcg_target_long sval) 917{ 918 tcg_target_ulong uval = sval; 919 ptrdiff_t pc_off; 920 int i; 921 922 if (type == TCG_TYPE_I32) { 923 uval = (uint32_t)sval; 924 sval = (int32_t)sval; 925 } 926 927 /* Try all 32-bit insns that can load it in one go. */ 928 if (sval >= -0x8000 && sval < 0x8000) { 929 tcg_out_insn(s, RI, LGHI, ret, sval); 930 return; 931 } 932 933 i = is_const_p16(uval); 934 if (i >= 0) { 935 tcg_out_insn_RI(s, li_insns[i], ret, uval >> (i * 16)); 936 return; 937 } 938 939 /* Try all 48-bit insns that can load it in one go. */ 940 if (sval == (int32_t)sval) { 941 tcg_out_insn(s, RIL, LGFI, ret, sval); 942 return; 943 } 944 945 i = is_const_p32(uval); 946 if (i >= 0) { 947 tcg_out_insn_RIL(s, lif_insns[i], ret, uval >> (i * 32)); 948 return; 949 } 950 951 /* Try for PC-relative address load. For odd addresses, add one. */ 952 pc_off = tcg_pcrel_diff(s, (void *)sval) >> 1; 953 if (pc_off == (int32_t)pc_off) { 954 tcg_out_insn(s, RIL, LARL, ret, pc_off); 955 if (sval & 1) { 956 tcg_out_insn(s, RI, AGHI, ret, 1); 957 } 958 return; 959 } 960 961 /* Otherwise, load it by parts. */ 962 i = is_const_p16((uint32_t)uval); 963 if (i >= 0) { 964 tcg_out_insn_RI(s, li_insns[i], ret, uval >> (i * 16)); 965 } else { 966 tcg_out_insn(s, RIL, LLILF, ret, uval); 967 } 968 uval >>= 32; 969 i = is_const_p16(uval); 970 if (i >= 0) { 971 tcg_out_insn_RI(s, oi_insns[i + 2], ret, uval >> (i * 16)); 972 } else { 973 tcg_out_insn(s, RIL, OIHF, ret, uval); 974 } 975} 976 977/* Emit a load/store type instruction. Inputs are: 978 DATA: The register to be loaded or stored. 979 BASE+OFS: The effective address. 980 OPC_RX: If the operation has an RX format opcode (e.g. STC), otherwise 0. 981 OPC_RXY: The RXY format opcode for the operation (e.g. STCY). */ 982 983static void tcg_out_mem(TCGContext *s, S390Opcode opc_rx, S390Opcode opc_rxy, 984 TCGReg data, TCGReg base, TCGReg index, 985 tcg_target_long ofs) 986{ 987 if (ofs < -0x80000 || ofs >= 0x80000) { 988 /* Combine the low 20 bits of the offset with the actual load insn; 989 the high 44 bits must come from an immediate load. */ 990 tcg_target_long low = ((ofs & 0xfffff) ^ 0x80000) - 0x80000; 991 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - low); 992 ofs = low; 993 994 /* If we were already given an index register, add it in. */ 995 if (index != TCG_REG_NONE) { 996 tcg_out_insn(s, RRE, AGR, TCG_TMP0, index); 997 } 998 index = TCG_TMP0; 999 } 1000 1001 if (opc_rx && ofs >= 0 && ofs < 0x1000) { 1002 tcg_out_insn_RX(s, opc_rx, data, base, index, ofs); 1003 } else { 1004 tcg_out_insn_RXY(s, opc_rxy, data, base, index, ofs); 1005 } 1006} 1007 1008static void tcg_out_vrx_mem(TCGContext *s, S390Opcode opc_vrx, 1009 TCGReg data, TCGReg base, TCGReg index, 1010 tcg_target_long ofs, int m3) 1011{ 1012 if (ofs < 0 || ofs >= 0x1000) { 1013 if (ofs >= -0x80000 && ofs < 0x80000) { 1014 tcg_out_insn(s, RXY, LAY, TCG_TMP0, base, index, ofs); 1015 base = TCG_TMP0; 1016 index = TCG_REG_NONE; 1017 ofs = 0; 1018 } else { 1019 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs); 1020 if (index != TCG_REG_NONE) { 1021 tcg_out_insn(s, RRE, AGR, TCG_TMP0, index); 1022 } 1023 index = TCG_TMP0; 1024 ofs = 0; 1025 } 1026 } 1027 tcg_out_insn_VRX(s, opc_vrx, data, base, index, ofs, m3); 1028} 1029 1030/* load data without address translation or endianness conversion */ 1031static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg data, 1032 TCGReg base, intptr_t ofs) 1033{ 1034 switch (type) { 1035 case TCG_TYPE_I32: 1036 if (likely(is_general_reg(data))) { 1037 tcg_out_mem(s, RX_L, RXY_LY, data, base, TCG_REG_NONE, ofs); 1038 break; 1039 } 1040 tcg_out_vrx_mem(s, VRX_VLLEZ, data, base, TCG_REG_NONE, ofs, MO_32); 1041 break; 1042 1043 case TCG_TYPE_I64: 1044 if (likely(is_general_reg(data))) { 1045 tcg_out_mem(s, 0, RXY_LG, data, base, TCG_REG_NONE, ofs); 1046 break; 1047 } 1048 /* fallthru */ 1049 1050 case TCG_TYPE_V64: 1051 tcg_out_vrx_mem(s, VRX_VLLEZ, data, base, TCG_REG_NONE, ofs, MO_64); 1052 break; 1053 1054 case TCG_TYPE_V128: 1055 /* Hint quadword aligned. */ 1056 tcg_out_vrx_mem(s, VRX_VL, data, base, TCG_REG_NONE, ofs, 4); 1057 break; 1058 1059 default: 1060 g_assert_not_reached(); 1061 } 1062} 1063 1064static void tcg_out_st(TCGContext *s, TCGType type, TCGReg data, 1065 TCGReg base, intptr_t ofs) 1066{ 1067 switch (type) { 1068 case TCG_TYPE_I32: 1069 if (likely(is_general_reg(data))) { 1070 tcg_out_mem(s, RX_ST, RXY_STY, data, base, TCG_REG_NONE, ofs); 1071 } else { 1072 tcg_out_vrx_mem(s, VRX_VSTEF, data, base, TCG_REG_NONE, ofs, 1); 1073 } 1074 break; 1075 1076 case TCG_TYPE_I64: 1077 if (likely(is_general_reg(data))) { 1078 tcg_out_mem(s, 0, RXY_STG, data, base, TCG_REG_NONE, ofs); 1079 break; 1080 } 1081 /* fallthru */ 1082 1083 case TCG_TYPE_V64: 1084 tcg_out_vrx_mem(s, VRX_VSTEG, data, base, TCG_REG_NONE, ofs, 0); 1085 break; 1086 1087 case TCG_TYPE_V128: 1088 /* Hint quadword aligned. */ 1089 tcg_out_vrx_mem(s, VRX_VST, data, base, TCG_REG_NONE, ofs, 4); 1090 break; 1091 1092 default: 1093 g_assert_not_reached(); 1094 } 1095} 1096 1097static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 1098 TCGReg base, intptr_t ofs) 1099{ 1100 return false; 1101} 1102 1103static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 1104{ 1105 return false; 1106} 1107 1108static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 1109 tcg_target_long imm) 1110{ 1111 /* This function is only used for passing structs by reference. */ 1112 tcg_out_mem(s, RX_LA, RXY_LAY, rd, rs, TCG_REG_NONE, imm); 1113} 1114 1115static inline void tcg_out_risbg(TCGContext *s, TCGReg dest, TCGReg src, 1116 int msb, int lsb, int ofs, int z) 1117{ 1118 /* Format RIE-f */ 1119 tcg_out16(s, (RIEf_RISBG & 0xff00) | (dest << 4) | src); 1120 tcg_out16(s, (msb << 8) | (z << 7) | lsb); 1121 tcg_out16(s, (ofs << 8) | (RIEf_RISBG & 0xff)); 1122} 1123 1124static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) 1125{ 1126 tcg_out_insn(s, RRE, LGBR, dest, src); 1127} 1128 1129static void tcg_out_ext8u(TCGContext *s, TCGReg dest, TCGReg src) 1130{ 1131 tcg_out_insn(s, RRE, LLGCR, dest, src); 1132} 1133 1134static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) 1135{ 1136 tcg_out_insn(s, RRE, LGHR, dest, src); 1137} 1138 1139static void tcg_out_ext16u(TCGContext *s, TCGReg dest, TCGReg src) 1140{ 1141 tcg_out_insn(s, RRE, LLGHR, dest, src); 1142} 1143 1144static void tcg_out_ext32s(TCGContext *s, TCGReg dest, TCGReg src) 1145{ 1146 tcg_out_insn(s, RRE, LGFR, dest, src); 1147} 1148 1149static void tcg_out_ext32u(TCGContext *s, TCGReg dest, TCGReg src) 1150{ 1151 tcg_out_insn(s, RRE, LLGFR, dest, src); 1152} 1153 1154static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg dest, TCGReg src) 1155{ 1156 tcg_out_ext32s(s, dest, src); 1157} 1158 1159static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg dest, TCGReg src) 1160{ 1161 tcg_out_ext32u(s, dest, src); 1162} 1163 1164static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg dest, TCGReg src) 1165{ 1166 tcg_out_mov(s, TCG_TYPE_I32, dest, src); 1167} 1168 1169static void tgen_andi_risbg(TCGContext *s, TCGReg out, TCGReg in, uint64_t val) 1170{ 1171 int msb, lsb; 1172 if ((val & 0x8000000000000001ull) == 0x8000000000000001ull) { 1173 /* Achieve wraparound by swapping msb and lsb. */ 1174 msb = 64 - ctz64(~val); 1175 lsb = clz64(~val) - 1; 1176 } else { 1177 msb = clz64(val); 1178 lsb = 63 - ctz64(val); 1179 } 1180 tcg_out_risbg(s, out, in, msb, lsb, 0, 1); 1181} 1182 1183static void tgen_andi(TCGContext *s, TCGType type, TCGReg dest, uint64_t val) 1184{ 1185 static const S390Opcode ni_insns[4] = { 1186 RI_NILL, RI_NILH, RI_NIHL, RI_NIHH 1187 }; 1188 static const S390Opcode nif_insns[2] = { 1189 RIL_NILF, RIL_NIHF 1190 }; 1191 uint64_t valid = (type == TCG_TYPE_I32 ? 0xffffffffull : -1ull); 1192 int i; 1193 1194 /* Look for the zero-extensions. */ 1195 if ((val & valid) == 0xffffffff) { 1196 tcg_out_ext32u(s, dest, dest); 1197 return; 1198 } 1199 if ((val & valid) == 0xff) { 1200 tcg_out_ext8u(s, dest, dest); 1201 return; 1202 } 1203 if ((val & valid) == 0xffff) { 1204 tcg_out_ext16u(s, dest, dest); 1205 return; 1206 } 1207 1208 i = is_const_p16(~val & valid); 1209 if (i >= 0) { 1210 tcg_out_insn_RI(s, ni_insns[i], dest, val >> (i * 16)); 1211 return; 1212 } 1213 1214 i = is_const_p32(~val & valid); 1215 tcg_debug_assert(i == 0 || type != TCG_TYPE_I32); 1216 if (i >= 0) { 1217 tcg_out_insn_RIL(s, nif_insns[i], dest, val >> (i * 32)); 1218 return; 1219 } 1220 1221 if (risbg_mask(val)) { 1222 tgen_andi_risbg(s, dest, dest, val); 1223 return; 1224 } 1225 1226 g_assert_not_reached(); 1227} 1228 1229static void tgen_ori(TCGContext *s, TCGReg dest, uint64_t val) 1230{ 1231 static const S390Opcode oif_insns[2] = { 1232 RIL_OILF, RIL_OIHF 1233 }; 1234 1235 int i; 1236 1237 i = is_const_p16(val); 1238 if (i >= 0) { 1239 tcg_out_insn_RI(s, oi_insns[i], dest, val >> (i * 16)); 1240 return; 1241 } 1242 1243 i = is_const_p32(val); 1244 if (i >= 0) { 1245 tcg_out_insn_RIL(s, oif_insns[i], dest, val >> (i * 32)); 1246 return; 1247 } 1248 1249 g_assert_not_reached(); 1250} 1251 1252static void tgen_xori(TCGContext *s, TCGReg dest, uint64_t val) 1253{ 1254 switch (is_const_p32(val)) { 1255 case 0: 1256 tcg_out_insn(s, RIL, XILF, dest, val); 1257 break; 1258 case 1: 1259 tcg_out_insn(s, RIL, XIHF, dest, val >> 32); 1260 break; 1261 default: 1262 g_assert_not_reached(); 1263 } 1264} 1265 1266static int tgen_cmp2(TCGContext *s, TCGType type, TCGCond c, TCGReg r1, 1267 TCGArg c2, bool c2const, bool need_carry, int *inv_cc) 1268{ 1269 bool is_unsigned = is_unsigned_cond(c); 1270 TCGCond inv_c = tcg_invert_cond(c); 1271 S390Opcode op; 1272 1273 if (is_tst_cond(c)) { 1274 tcg_debug_assert(!need_carry); 1275 1276 if (!c2const) { 1277 if (type == TCG_TYPE_I32) { 1278 tcg_out_insn(s, RRFa, NRK, TCG_REG_R0, r1, c2); 1279 } else { 1280 tcg_out_insn(s, RRFa, NGRK, TCG_REG_R0, r1, c2); 1281 } 1282 goto exit; 1283 } 1284 1285 if (type == TCG_TYPE_I32) { 1286 c2 = (uint32_t)c2; 1287 } 1288 1289 int i = is_const_p16(c2); 1290 if (i >= 0) { 1291 tcg_out_insn_RI(s, tm_insns[i], r1, c2 >> (i * 16)); 1292 *inv_cc = c == TCG_COND_TSTEQ ? S390_TM_NE : S390_TM_EQ; 1293 return *inv_cc ^ 15; 1294 } 1295 1296 if (risbg_mask(c2)) { 1297 tgen_andi_risbg(s, TCG_REG_R0, r1, c2); 1298 goto exit; 1299 } 1300 g_assert_not_reached(); 1301 } 1302 1303 if (c2const) { 1304 if (c2 == 0) { 1305 if (!(is_unsigned && need_carry)) { 1306 if (type == TCG_TYPE_I32) { 1307 tcg_out_insn(s, RR, LTR, r1, r1); 1308 } else { 1309 tcg_out_insn(s, RRE, LTGR, r1, r1); 1310 } 1311 *inv_cc = tcg_cond_to_ltr_cond[inv_c]; 1312 return tcg_cond_to_ltr_cond[c]; 1313 } 1314 } 1315 1316 if (!is_unsigned && c2 == (int16_t)c2) { 1317 op = (type == TCG_TYPE_I32 ? RI_CHI : RI_CGHI); 1318 tcg_out_insn_RI(s, op, r1, c2); 1319 goto exit; 1320 } 1321 1322 if (type == TCG_TYPE_I32) { 1323 op = (is_unsigned ? RIL_CLFI : RIL_CFI); 1324 tcg_out_insn_RIL(s, op, r1, c2); 1325 goto exit; 1326 } 1327 1328 /* Should match TCG_CT_CONST_CMP. */ 1329 switch (c) { 1330 case TCG_COND_LT: 1331 case TCG_COND_GE: 1332 case TCG_COND_LE: 1333 case TCG_COND_GT: 1334 tcg_debug_assert(c2 == (int32_t)c2); 1335 op = RIL_CGFI; 1336 break; 1337 case TCG_COND_EQ: 1338 case TCG_COND_NE: 1339 if (c2 == (int32_t)c2) { 1340 op = RIL_CGFI; 1341 break; 1342 } 1343 /* fall through */ 1344 case TCG_COND_LTU: 1345 case TCG_COND_GEU: 1346 case TCG_COND_LEU: 1347 case TCG_COND_GTU: 1348 tcg_debug_assert(c2 == (uint32_t)c2); 1349 op = RIL_CLGFI; 1350 break; 1351 default: 1352 g_assert_not_reached(); 1353 } 1354 tcg_out_insn_RIL(s, op, r1, c2); 1355 } else if (type == TCG_TYPE_I32) { 1356 op = (is_unsigned ? RR_CLR : RR_CR); 1357 tcg_out_insn_RR(s, op, r1, c2); 1358 } else { 1359 op = (is_unsigned ? RRE_CLGR : RRE_CGR); 1360 tcg_out_insn_RRE(s, op, r1, c2); 1361 } 1362 1363 exit: 1364 *inv_cc = tcg_cond_to_s390_cond[inv_c]; 1365 return tcg_cond_to_s390_cond[c]; 1366} 1367 1368static int tgen_cmp(TCGContext *s, TCGType type, TCGCond c, TCGReg r1, 1369 TCGArg c2, bool c2const, bool need_carry) 1370{ 1371 int inv_cc; 1372 return tgen_cmp2(s, type, c, r1, c2, c2const, need_carry, &inv_cc); 1373} 1374 1375static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, 1376 TCGReg dest, TCGReg c1, TCGArg c2, 1377 bool c2const, bool neg) 1378{ 1379 int cc; 1380 1381 /* With LOC2, we can always emit the minimum 3 insns. */ 1382 if (HAVE_FACILITY(LOAD_ON_COND2)) { 1383 /* Emit: d = 0, d = (cc ? 1 : d). */ 1384 cc = tgen_cmp(s, type, cond, c1, c2, c2const, false); 1385 tcg_out_movi(s, TCG_TYPE_I64, dest, 0); 1386 tcg_out_insn(s, RIEg, LOCGHI, dest, neg ? -1 : 1, cc); 1387 return; 1388 } 1389 1390 switch (cond) { 1391 case TCG_COND_GEU: 1392 case TCG_COND_LTU: 1393 case TCG_COND_LT: 1394 case TCG_COND_GE: 1395 /* Swap operands so that we can use LEU/GTU/GT/LE. */ 1396 if (!c2const) { 1397 TCGReg t = c1; 1398 c1 = c2; 1399 c2 = t; 1400 cond = tcg_swap_cond(cond); 1401 } 1402 break; 1403 default: 1404 break; 1405 } 1406 1407 switch (cond) { 1408 case TCG_COND_NE: 1409 /* X != 0 is X > 0. */ 1410 if (c2const && c2 == 0) { 1411 cond = TCG_COND_GTU; 1412 } else { 1413 break; 1414 } 1415 /* fallthru */ 1416 1417 case TCG_COND_GTU: 1418 case TCG_COND_GT: 1419 /* 1420 * The result of a compare has CC=2 for GT and CC=3 unused. 1421 * ADD LOGICAL WITH CARRY considers (CC & 2) the carry bit. 1422 */ 1423 tgen_cmp(s, type, cond, c1, c2, c2const, true); 1424 tcg_out_movi(s, type, dest, 0); 1425 tcg_out_insn(s, RRE, ALCGR, dest, dest); 1426 if (neg) { 1427 if (type == TCG_TYPE_I32) { 1428 tcg_out_insn(s, RR, LCR, dest, dest); 1429 } else { 1430 tcg_out_insn(s, RRE, LCGR, dest, dest); 1431 } 1432 } 1433 return; 1434 1435 case TCG_COND_EQ: 1436 /* X == 0 is X <= 0. */ 1437 if (c2const && c2 == 0) { 1438 cond = TCG_COND_LEU; 1439 } else { 1440 break; 1441 } 1442 /* fallthru */ 1443 1444 case TCG_COND_LEU: 1445 case TCG_COND_LE: 1446 /* 1447 * As above, but we're looking for borrow, or !carry. 1448 * The second insn computes d - d - borrow, or -1 for true 1449 * and 0 for false. So we must mask to 1 bit afterward. 1450 */ 1451 tgen_cmp(s, type, cond, c1, c2, c2const, true); 1452 tcg_out_insn(s, RRE, SLBGR, dest, dest); 1453 if (!neg) { 1454 tgen_andi(s, type, dest, 1); 1455 } 1456 return; 1457 1458 default: 1459 g_assert_not_reached(); 1460 } 1461 1462 cc = tgen_cmp(s, type, cond, c1, c2, c2const, false); 1463 /* Emit: d = 0, t = 1, d = (cc ? t : d). */ 1464 tcg_out_movi(s, TCG_TYPE_I64, dest, 0); 1465 tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, neg ? -1 : 1); 1466 tcg_out_insn(s, RRFc, LOCGR, dest, TCG_TMP0, cc); 1467} 1468 1469static void tgen_movcond_int(TCGContext *s, TCGType type, TCGReg dest, 1470 TCGArg v3, int v3const, TCGReg v4, 1471 int cc, int inv_cc) 1472{ 1473 TCGReg src; 1474 1475 if (v3const) { 1476 if (dest == v4) { 1477 if (HAVE_FACILITY(LOAD_ON_COND2)) { 1478 /* Emit: if (cc) dest = v3. */ 1479 tcg_out_insn(s, RIEg, LOCGHI, dest, v3, cc); 1480 return; 1481 } 1482 tcg_out_insn(s, RI, LGHI, TCG_TMP0, v3); 1483 src = TCG_TMP0; 1484 } else { 1485 /* LGR+LOCGHI is larger than LGHI+LOCGR. */ 1486 tcg_out_insn(s, RI, LGHI, dest, v3); 1487 cc = inv_cc; 1488 src = v4; 1489 } 1490 } else { 1491 if (HAVE_FACILITY(MISC_INSN_EXT3)) { 1492 /* Emit: dest = cc ? v3 : v4. */ 1493 tcg_out_insn(s, RRFam, SELGR, dest, v3, v4, cc); 1494 return; 1495 } 1496 if (dest == v4) { 1497 src = v3; 1498 } else { 1499 tcg_out_mov(s, type, dest, v3); 1500 cc = inv_cc; 1501 src = v4; 1502 } 1503 } 1504 1505 /* Emit: if (cc) dest = src. */ 1506 tcg_out_insn(s, RRFc, LOCGR, dest, src, cc); 1507} 1508 1509static void tgen_movcond(TCGContext *s, TCGType type, TCGCond c, TCGReg dest, 1510 TCGReg c1, TCGArg c2, int c2const, 1511 TCGArg v3, int v3const, TCGReg v4) 1512{ 1513 int cc, inv_cc; 1514 1515 cc = tgen_cmp2(s, type, c, c1, c2, c2const, false, &inv_cc); 1516 tgen_movcond_int(s, type, dest, v3, v3const, v4, cc, inv_cc); 1517} 1518 1519static void tgen_clz(TCGContext *s, TCGReg dest, TCGReg a1, 1520 TCGArg a2, int a2const) 1521{ 1522 /* Since this sets both R and R+1, we have no choice but to store the 1523 result into R0, allowing R1 == TCG_TMP0 to be clobbered as well. */ 1524 QEMU_BUILD_BUG_ON(TCG_TMP0 != TCG_REG_R1); 1525 tcg_out_insn(s, RRE, FLOGR, TCG_REG_R0, a1); 1526 1527 if (a2const && a2 == 64) { 1528 tcg_out_mov(s, TCG_TYPE_I64, dest, TCG_REG_R0); 1529 return; 1530 } 1531 1532 /* 1533 * Conditions from FLOGR are: 1534 * 2 -> one bit found 1535 * 8 -> no one bit found 1536 */ 1537 tgen_movcond_int(s, TCG_TYPE_I64, dest, a2, a2const, TCG_REG_R0, 8, 2); 1538} 1539 1540static void tgen_ctpop(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) 1541{ 1542 /* With MIE3, and bit 0 of m4 set, we get the complete result. */ 1543 if (HAVE_FACILITY(MISC_INSN_EXT3)) { 1544 if (type == TCG_TYPE_I32) { 1545 tcg_out_ext32u(s, dest, src); 1546 src = dest; 1547 } 1548 tcg_out_insn(s, RRFc, POPCNT, dest, src, 8); 1549 return; 1550 } 1551 1552 /* Without MIE3, each byte gets the count of bits for the byte. */ 1553 tcg_out_insn(s, RRFc, POPCNT, dest, src, 0); 1554 1555 /* Multiply to sum each byte at the top of the word. */ 1556 if (type == TCG_TYPE_I32) { 1557 tcg_out_insn(s, RIL, MSFI, dest, 0x01010101); 1558 tcg_out_sh32(s, RS_SRL, dest, TCG_REG_NONE, 24); 1559 } else { 1560 tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 0x0101010101010101ull); 1561 tcg_out_insn(s, RRE, MSGR, dest, TCG_TMP0); 1562 tcg_out_sh64(s, RSY_SRLG, dest, dest, TCG_REG_NONE, 56); 1563 } 1564} 1565 1566static void tgen_deposit(TCGContext *s, TCGReg dest, TCGReg src, 1567 int ofs, int len, int z) 1568{ 1569 int lsb = (63 - ofs); 1570 int msb = lsb - (len - 1); 1571 tcg_out_risbg(s, dest, src, msb, lsb, ofs, z); 1572} 1573 1574static void tgen_extract(TCGContext *s, TCGReg dest, TCGReg src, 1575 int ofs, int len) 1576{ 1577 tcg_out_risbg(s, dest, src, 64 - len, 63, 64 - ofs, 1); 1578} 1579 1580static void tgen_gotoi(TCGContext *s, int cc, const tcg_insn_unit *dest) 1581{ 1582 ptrdiff_t off = tcg_pcrel_diff(s, dest) >> 1; 1583 if (off == (int16_t)off) { 1584 tcg_out_insn(s, RI, BRC, cc, off); 1585 } else if (off == (int32_t)off) { 1586 tcg_out_insn(s, RIL, BRCL, cc, off); 1587 } else { 1588 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)dest); 1589 tcg_out_insn(s, RR, BCR, cc, TCG_TMP0); 1590 } 1591} 1592 1593static void tgen_branch(TCGContext *s, int cc, TCGLabel *l) 1594{ 1595 if (l->has_value) { 1596 tgen_gotoi(s, cc, l->u.value_ptr); 1597 } else { 1598 tcg_out16(s, RI_BRC | (cc << 4)); 1599 tcg_out_reloc(s, s->code_ptr, R_390_PC16DBL, l, 2); 1600 s->code_ptr += 1; 1601 } 1602} 1603 1604static void tgen_compare_branch(TCGContext *s, S390Opcode opc, int cc, 1605 TCGReg r1, TCGReg r2, TCGLabel *l) 1606{ 1607 tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2); 1608 /* Format RIE-b */ 1609 tcg_out16(s, (opc & 0xff00) | (r1 << 4) | r2); 1610 tcg_out16(s, 0); 1611 tcg_out16(s, cc << 12 | (opc & 0xff)); 1612} 1613 1614static void tgen_compare_imm_branch(TCGContext *s, S390Opcode opc, int cc, 1615 TCGReg r1, int i2, TCGLabel *l) 1616{ 1617 tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2); 1618 /* Format RIE-c */ 1619 tcg_out16(s, (opc & 0xff00) | (r1 << 4) | cc); 1620 tcg_out16(s, 0); 1621 tcg_out16(s, (i2 << 8) | (opc & 0xff)); 1622} 1623 1624static void tgen_brcond(TCGContext *s, TCGType type, TCGCond c, 1625 TCGReg r1, TCGArg c2, int c2const, TCGLabel *l) 1626{ 1627 int cc; 1628 1629 if (!is_tst_cond(c)) { 1630 bool is_unsigned = is_unsigned_cond(c); 1631 bool in_range; 1632 S390Opcode opc; 1633 1634 cc = tcg_cond_to_s390_cond[c]; 1635 1636 if (!c2const) { 1637 opc = (type == TCG_TYPE_I32 1638 ? (is_unsigned ? RIEb_CLRJ : RIEb_CRJ) 1639 : (is_unsigned ? RIEb_CLGRJ : RIEb_CGRJ)); 1640 tgen_compare_branch(s, opc, cc, r1, c2, l); 1641 return; 1642 } 1643 1644 /* 1645 * COMPARE IMMEDIATE AND BRANCH RELATIVE has an 8-bit immediate field. 1646 * If the immediate we've been given does not fit that range, we'll 1647 * fall back to separate compare and branch instructions using the 1648 * larger comparison range afforded by COMPARE IMMEDIATE. 1649 */ 1650 if (type == TCG_TYPE_I32) { 1651 if (is_unsigned) { 1652 opc = RIEc_CLIJ; 1653 in_range = (uint32_t)c2 == (uint8_t)c2; 1654 } else { 1655 opc = RIEc_CIJ; 1656 in_range = (int32_t)c2 == (int8_t)c2; 1657 } 1658 } else { 1659 if (is_unsigned) { 1660 opc = RIEc_CLGIJ; 1661 in_range = (uint64_t)c2 == (uint8_t)c2; 1662 } else { 1663 opc = RIEc_CGIJ; 1664 in_range = (int64_t)c2 == (int8_t)c2; 1665 } 1666 } 1667 if (in_range) { 1668 tgen_compare_imm_branch(s, opc, cc, r1, c2, l); 1669 return; 1670 } 1671 } 1672 1673 cc = tgen_cmp(s, type, c, r1, c2, c2const, false); 1674 tgen_branch(s, cc, l); 1675} 1676 1677static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *dest) 1678{ 1679 ptrdiff_t off = tcg_pcrel_diff(s, dest) >> 1; 1680 if (off == (int32_t)off) { 1681 tcg_out_insn(s, RIL, BRASL, TCG_REG_R14, off); 1682 } else { 1683 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)dest); 1684 tcg_out_insn(s, RR, BASR, TCG_REG_R14, TCG_TMP0); 1685 } 1686} 1687 1688static void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest, 1689 const TCGHelperInfo *info) 1690{ 1691 tcg_out_call_int(s, dest); 1692} 1693 1694typedef struct { 1695 TCGReg base; 1696 TCGReg index; 1697 int disp; 1698 TCGAtomAlign aa; 1699} HostAddress; 1700 1701bool tcg_target_has_memory_bswap(MemOp memop) 1702{ 1703 TCGAtomAlign aa; 1704 1705 if ((memop & MO_SIZE) <= MO_64) { 1706 return true; 1707 } 1708 1709 /* 1710 * Reject 16-byte memop with 16-byte atomicity, 1711 * but do allow a pair of 64-bit operations. 1712 */ 1713 aa = atom_and_align_for_opc(tcg_ctx, memop, MO_ATOM_IFALIGN, true); 1714 return aa.atom <= MO_64; 1715} 1716 1717static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg data, 1718 HostAddress h) 1719{ 1720 switch (opc & (MO_SSIZE | MO_BSWAP)) { 1721 case MO_UB: 1722 tcg_out_insn(s, RXY, LLGC, data, h.base, h.index, h.disp); 1723 break; 1724 case MO_SB: 1725 tcg_out_insn(s, RXY, LGB, data, h.base, h.index, h.disp); 1726 break; 1727 1728 case MO_UW | MO_BSWAP: 1729 /* swapped unsigned halfword load with upper bits zeroed */ 1730 tcg_out_insn(s, RXY, LRVH, data, h.base, h.index, h.disp); 1731 tcg_out_ext16u(s, data, data); 1732 break; 1733 case MO_UW: 1734 tcg_out_insn(s, RXY, LLGH, data, h.base, h.index, h.disp); 1735 break; 1736 1737 case MO_SW | MO_BSWAP: 1738 /* swapped sign-extended halfword load */ 1739 tcg_out_insn(s, RXY, LRVH, data, h.base, h.index, h.disp); 1740 tcg_out_ext16s(s, TCG_TYPE_REG, data, data); 1741 break; 1742 case MO_SW: 1743 tcg_out_insn(s, RXY, LGH, data, h.base, h.index, h.disp); 1744 break; 1745 1746 case MO_UL | MO_BSWAP: 1747 /* swapped unsigned int load with upper bits zeroed */ 1748 tcg_out_insn(s, RXY, LRV, data, h.base, h.index, h.disp); 1749 tcg_out_ext32u(s, data, data); 1750 break; 1751 case MO_UL: 1752 tcg_out_insn(s, RXY, LLGF, data, h.base, h.index, h.disp); 1753 break; 1754 1755 case MO_SL | MO_BSWAP: 1756 /* swapped sign-extended int load */ 1757 tcg_out_insn(s, RXY, LRV, data, h.base, h.index, h.disp); 1758 tcg_out_ext32s(s, data, data); 1759 break; 1760 case MO_SL: 1761 tcg_out_insn(s, RXY, LGF, data, h.base, h.index, h.disp); 1762 break; 1763 1764 case MO_UQ | MO_BSWAP: 1765 tcg_out_insn(s, RXY, LRVG, data, h.base, h.index, h.disp); 1766 break; 1767 case MO_UQ: 1768 tcg_out_insn(s, RXY, LG, data, h.base, h.index, h.disp); 1769 break; 1770 1771 default: 1772 g_assert_not_reached(); 1773 } 1774} 1775 1776static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg data, 1777 HostAddress h) 1778{ 1779 switch (opc & (MO_SIZE | MO_BSWAP)) { 1780 case MO_UB: 1781 if (h.disp >= 0 && h.disp < 0x1000) { 1782 tcg_out_insn(s, RX, STC, data, h.base, h.index, h.disp); 1783 } else { 1784 tcg_out_insn(s, RXY, STCY, data, h.base, h.index, h.disp); 1785 } 1786 break; 1787 1788 case MO_UW | MO_BSWAP: 1789 tcg_out_insn(s, RXY, STRVH, data, h.base, h.index, h.disp); 1790 break; 1791 case MO_UW: 1792 if (h.disp >= 0 && h.disp < 0x1000) { 1793 tcg_out_insn(s, RX, STH, data, h.base, h.index, h.disp); 1794 } else { 1795 tcg_out_insn(s, RXY, STHY, data, h.base, h.index, h.disp); 1796 } 1797 break; 1798 1799 case MO_UL | MO_BSWAP: 1800 tcg_out_insn(s, RXY, STRV, data, h.base, h.index, h.disp); 1801 break; 1802 case MO_UL: 1803 if (h.disp >= 0 && h.disp < 0x1000) { 1804 tcg_out_insn(s, RX, ST, data, h.base, h.index, h.disp); 1805 } else { 1806 tcg_out_insn(s, RXY, STY, data, h.base, h.index, h.disp); 1807 } 1808 break; 1809 1810 case MO_UQ | MO_BSWAP: 1811 tcg_out_insn(s, RXY, STRVG, data, h.base, h.index, h.disp); 1812 break; 1813 case MO_UQ: 1814 tcg_out_insn(s, RXY, STG, data, h.base, h.index, h.disp); 1815 break; 1816 1817 default: 1818 g_assert_not_reached(); 1819 } 1820} 1821 1822static const TCGLdstHelperParam ldst_helper_param = { 1823 .ntmp = 1, .tmp = { TCG_TMP0 } 1824}; 1825 1826static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1827{ 1828 MemOp opc = get_memop(lb->oi); 1829 1830 if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL, 1831 (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 2)) { 1832 return false; 1833 } 1834 1835 tcg_out_ld_helper_args(s, lb, &ldst_helper_param); 1836 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE]); 1837 tcg_out_ld_helper_ret(s, lb, false, &ldst_helper_param); 1838 1839 tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr); 1840 return true; 1841} 1842 1843static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1844{ 1845 MemOp opc = get_memop(lb->oi); 1846 1847 if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL, 1848 (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 2)) { 1849 return false; 1850 } 1851 1852 tcg_out_st_helper_args(s, lb, &ldst_helper_param); 1853 tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE]); 1854 1855 tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr); 1856 return true; 1857} 1858 1859/* We're expecting to use a 20-bit negative offset on the tlb memory ops. */ 1860#define MIN_TLB_MASK_TABLE_OFS -(1 << 19) 1861 1862/* 1863 * For system-mode, perform the TLB load and compare. 1864 * For user-mode, perform any required alignment tests. 1865 * In both cases, return a TCGLabelQemuLdst structure if the slow path 1866 * is required and fill in @h with the host address for the fast path. 1867 */ 1868static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 1869 TCGReg addr_reg, MemOpIdx oi, 1870 bool is_ld) 1871{ 1872 TCGType addr_type = s->addr_type; 1873 TCGLabelQemuLdst *ldst = NULL; 1874 MemOp opc = get_memop(oi); 1875 MemOp s_bits = opc & MO_SIZE; 1876 unsigned a_mask; 1877 1878 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, s_bits == MO_128); 1879 a_mask = (1 << h->aa.align) - 1; 1880 1881 if (tcg_use_softmmu) { 1882 unsigned s_mask = (1 << s_bits) - 1; 1883 int mem_index = get_mmuidx(oi); 1884 int fast_off = tlb_mask_table_ofs(s, mem_index); 1885 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); 1886 int table_off = fast_off + offsetof(CPUTLBDescFast, table); 1887 int ofs, a_off; 1888 uint64_t tlb_mask; 1889 1890 ldst = new_ldst_label(s); 1891 ldst->is_ld = is_ld; 1892 ldst->oi = oi; 1893 ldst->addrlo_reg = addr_reg; 1894 1895 tcg_out_sh64(s, RSY_SRLG, TCG_TMP0, addr_reg, TCG_REG_NONE, 1896 s->page_bits - CPU_TLB_ENTRY_BITS); 1897 1898 tcg_out_insn(s, RXY, NG, TCG_TMP0, TCG_AREG0, TCG_REG_NONE, mask_off); 1899 tcg_out_insn(s, RXY, AG, TCG_TMP0, TCG_AREG0, TCG_REG_NONE, table_off); 1900 1901 /* 1902 * For aligned accesses, we check the first byte and include the 1903 * alignment bits within the address. For unaligned access, we 1904 * check that we don't cross pages using the address of the last 1905 * byte of the access. 1906 */ 1907 a_off = (a_mask >= s_mask ? 0 : s_mask - a_mask); 1908 tlb_mask = (uint64_t)s->page_mask | a_mask; 1909 if (a_off == 0) { 1910 tgen_andi_risbg(s, TCG_REG_R0, addr_reg, tlb_mask); 1911 } else { 1912 tcg_out_insn(s, RX, LA, TCG_REG_R0, addr_reg, TCG_REG_NONE, a_off); 1913 tgen_andi(s, addr_type, TCG_REG_R0, tlb_mask); 1914 } 1915 1916 if (is_ld) { 1917 ofs = offsetof(CPUTLBEntry, addr_read); 1918 } else { 1919 ofs = offsetof(CPUTLBEntry, addr_write); 1920 } 1921 if (addr_type == TCG_TYPE_I32) { 1922 ofs += HOST_BIG_ENDIAN * 4; 1923 tcg_out_insn(s, RX, C, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs); 1924 } else { 1925 tcg_out_insn(s, RXY, CG, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs); 1926 } 1927 1928 tcg_out16(s, RI_BRC | (S390_CC_NE << 4)); 1929 ldst->label_ptr[0] = s->code_ptr++; 1930 1931 h->index = TCG_TMP0; 1932 tcg_out_insn(s, RXY, LG, h->index, TCG_TMP0, TCG_REG_NONE, 1933 offsetof(CPUTLBEntry, addend)); 1934 1935 if (addr_type == TCG_TYPE_I32) { 1936 tcg_out_insn(s, RRE, ALGFR, h->index, addr_reg); 1937 h->base = TCG_REG_NONE; 1938 } else { 1939 h->base = addr_reg; 1940 } 1941 h->disp = 0; 1942 } else { 1943 if (a_mask) { 1944 ldst = new_ldst_label(s); 1945 ldst->is_ld = is_ld; 1946 ldst->oi = oi; 1947 ldst->addrlo_reg = addr_reg; 1948 1949 tcg_debug_assert(a_mask <= 0xffff); 1950 tcg_out_insn(s, RI, TMLL, addr_reg, a_mask); 1951 1952 tcg_out16(s, RI_BRC | (S390_TM_NE << 4)); 1953 ldst->label_ptr[0] = s->code_ptr++; 1954 } 1955 1956 h->base = addr_reg; 1957 if (addr_type == TCG_TYPE_I32) { 1958 tcg_out_ext32u(s, TCG_TMP0, addr_reg); 1959 h->base = TCG_TMP0; 1960 } 1961 if (guest_base < 0x80000) { 1962 h->index = TCG_REG_NONE; 1963 h->disp = guest_base; 1964 } else { 1965 h->index = TCG_GUEST_BASE_REG; 1966 h->disp = 0; 1967 } 1968 } 1969 1970 return ldst; 1971} 1972 1973static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_reg, 1974 MemOpIdx oi, TCGType data_type) 1975{ 1976 TCGLabelQemuLdst *ldst; 1977 HostAddress h; 1978 1979 ldst = prepare_host_addr(s, &h, addr_reg, oi, true); 1980 tcg_out_qemu_ld_direct(s, get_memop(oi), data_reg, h); 1981 1982 if (ldst) { 1983 ldst->type = data_type; 1984 ldst->datalo_reg = data_reg; 1985 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1986 } 1987} 1988 1989static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_reg, 1990 MemOpIdx oi, TCGType data_type) 1991{ 1992 TCGLabelQemuLdst *ldst; 1993 HostAddress h; 1994 1995 ldst = prepare_host_addr(s, &h, addr_reg, oi, false); 1996 tcg_out_qemu_st_direct(s, get_memop(oi), data_reg, h); 1997 1998 if (ldst) { 1999 ldst->type = data_type; 2000 ldst->datalo_reg = data_reg; 2001 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 2002 } 2003} 2004 2005static void tcg_out_qemu_ldst_i128(TCGContext *s, TCGReg datalo, TCGReg datahi, 2006 TCGReg addr_reg, MemOpIdx oi, bool is_ld) 2007{ 2008 TCGLabel *l1 = NULL, *l2 = NULL; 2009 TCGLabelQemuLdst *ldst; 2010 HostAddress h; 2011 bool need_bswap; 2012 bool use_pair; 2013 S390Opcode insn; 2014 2015 ldst = prepare_host_addr(s, &h, addr_reg, oi, is_ld); 2016 2017 use_pair = h.aa.atom < MO_128; 2018 need_bswap = get_memop(oi) & MO_BSWAP; 2019 2020 if (!use_pair) { 2021 /* 2022 * Atomicity requires we use LPQ. If we've already checked for 2023 * 16-byte alignment, that's all we need. If we arrive with 2024 * lesser alignment, we have determined that less than 16-byte 2025 * alignment can be satisfied with two 8-byte loads. 2026 */ 2027 if (h.aa.align < MO_128) { 2028 use_pair = true; 2029 l1 = gen_new_label(); 2030 l2 = gen_new_label(); 2031 2032 tcg_out_insn(s, RI, TMLL, addr_reg, 15); 2033 tgen_branch(s, S390_TM_NE, l1); 2034 } 2035 2036 tcg_debug_assert(!need_bswap); 2037 tcg_debug_assert(datalo & 1); 2038 tcg_debug_assert(datahi == datalo - 1); 2039 insn = is_ld ? RXY_LPQ : RXY_STPQ; 2040 tcg_out_insn_RXY(s, insn, datahi, h.base, h.index, h.disp); 2041 2042 if (use_pair) { 2043 tgen_branch(s, S390_CC_ALWAYS, l2); 2044 tcg_out_label(s, l1); 2045 } 2046 } 2047 if (use_pair) { 2048 TCGReg d1, d2; 2049 2050 if (need_bswap) { 2051 d1 = datalo, d2 = datahi; 2052 insn = is_ld ? RXY_LRVG : RXY_STRVG; 2053 } else { 2054 d1 = datahi, d2 = datalo; 2055 insn = is_ld ? RXY_LG : RXY_STG; 2056 } 2057 2058 if (h.base == d1 || h.index == d1) { 2059 tcg_out_insn(s, RXY, LAY, TCG_TMP0, h.base, h.index, h.disp); 2060 h.base = TCG_TMP0; 2061 h.index = TCG_REG_NONE; 2062 h.disp = 0; 2063 } 2064 tcg_out_insn_RXY(s, insn, d1, h.base, h.index, h.disp); 2065 tcg_out_insn_RXY(s, insn, d2, h.base, h.index, h.disp + 8); 2066 } 2067 if (l2) { 2068 tcg_out_label(s, l2); 2069 } 2070 2071 if (ldst) { 2072 ldst->type = TCG_TYPE_I128; 2073 ldst->datalo_reg = datalo; 2074 ldst->datahi_reg = datahi; 2075 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 2076 } 2077} 2078 2079static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) 2080{ 2081 /* Reuse the zeroing that exists for goto_ptr. */ 2082 if (a0 == 0) { 2083 tgen_gotoi(s, S390_CC_ALWAYS, tcg_code_gen_epilogue); 2084 } else { 2085 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, a0); 2086 tgen_gotoi(s, S390_CC_ALWAYS, tb_ret_addr); 2087 } 2088} 2089 2090static void tcg_out_goto_tb(TCGContext *s, int which) 2091{ 2092 /* 2093 * Branch displacement must be aligned for atomic patching; 2094 * see if we need to add extra nop before branch 2095 */ 2096 if (!QEMU_PTR_IS_ALIGNED(s->code_ptr + 1, 4)) { 2097 tcg_out16(s, NOP); 2098 } 2099 tcg_out16(s, RIL_BRCL | (S390_CC_ALWAYS << 4)); 2100 set_jmp_insn_offset(s, which); 2101 s->code_ptr += 2; 2102 set_jmp_reset_offset(s, which); 2103} 2104 2105void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 2106 uintptr_t jmp_rx, uintptr_t jmp_rw) 2107{ 2108 if (!HAVE_FACILITY(GEN_INST_EXT)) { 2109 return; 2110 } 2111 /* patch the branch destination */ 2112 uintptr_t addr = tb->jmp_target_addr[n]; 2113 intptr_t disp = addr - (jmp_rx - 2); 2114 qatomic_set((int32_t *)jmp_rw, disp / 2); 2115 /* no need to flush icache explicitly */ 2116} 2117 2118# define OP_32_64(x) \ 2119 case glue(glue(INDEX_op_,x),_i32): \ 2120 case glue(glue(INDEX_op_,x),_i64) 2121 2122static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, 2123 const TCGArg args[TCG_MAX_OP_ARGS], 2124 const int const_args[TCG_MAX_OP_ARGS]) 2125{ 2126 S390Opcode op, op2; 2127 TCGArg a0, a1, a2; 2128 2129 switch (opc) { 2130 case INDEX_op_goto_ptr: 2131 a0 = args[0]; 2132 tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, a0); 2133 break; 2134 2135 OP_32_64(ld8u): 2136 /* ??? LLC (RXY format) is only present with the extended-immediate 2137 facility, whereas LLGC is always present. */ 2138 tcg_out_mem(s, 0, RXY_LLGC, args[0], args[1], TCG_REG_NONE, args[2]); 2139 break; 2140 2141 OP_32_64(ld8s): 2142 /* ??? LB is no smaller than LGB, so no point to using it. */ 2143 tcg_out_mem(s, 0, RXY_LGB, args[0], args[1], TCG_REG_NONE, args[2]); 2144 break; 2145 2146 OP_32_64(ld16u): 2147 /* ??? LLH (RXY format) is only present with the extended-immediate 2148 facility, whereas LLGH is always present. */ 2149 tcg_out_mem(s, 0, RXY_LLGH, args[0], args[1], TCG_REG_NONE, args[2]); 2150 break; 2151 2152 case INDEX_op_ld16s_i32: 2153 tcg_out_mem(s, RX_LH, RXY_LHY, args[0], args[1], TCG_REG_NONE, args[2]); 2154 break; 2155 2156 case INDEX_op_ld_i32: 2157 tcg_out_ld(s, TCG_TYPE_I32, args[0], args[1], args[2]); 2158 break; 2159 2160 OP_32_64(st8): 2161 tcg_out_mem(s, RX_STC, RXY_STCY, args[0], args[1], 2162 TCG_REG_NONE, args[2]); 2163 break; 2164 2165 OP_32_64(st16): 2166 tcg_out_mem(s, RX_STH, RXY_STHY, args[0], args[1], 2167 TCG_REG_NONE, args[2]); 2168 break; 2169 2170 case INDEX_op_st_i32: 2171 tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]); 2172 break; 2173 2174 case INDEX_op_add_i32: 2175 a0 = args[0], a1 = args[1], a2 = (int32_t)args[2]; 2176 if (const_args[2]) { 2177 do_addi_32: 2178 if (a0 == a1) { 2179 if (a2 == (int16_t)a2) { 2180 tcg_out_insn(s, RI, AHI, a0, a2); 2181 break; 2182 } 2183 tcg_out_insn(s, RIL, AFI, a0, a2); 2184 break; 2185 } 2186 tcg_out_mem(s, RX_LA, RXY_LAY, a0, a1, TCG_REG_NONE, a2); 2187 } else if (a0 == a1) { 2188 tcg_out_insn(s, RR, AR, a0, a2); 2189 } else { 2190 tcg_out_insn(s, RX, LA, a0, a1, a2, 0); 2191 } 2192 break; 2193 case INDEX_op_sub_i32: 2194 a0 = args[0], a1 = args[1], a2 = (int32_t)args[2]; 2195 if (const_args[2]) { 2196 a2 = -a2; 2197 goto do_addi_32; 2198 } else if (a0 == a1) { 2199 tcg_out_insn(s, RR, SR, a0, a2); 2200 } else { 2201 tcg_out_insn(s, RRFa, SRK, a0, a1, a2); 2202 } 2203 break; 2204 2205 case INDEX_op_and_i32: 2206 a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; 2207 if (const_args[2]) { 2208 tcg_out_mov(s, TCG_TYPE_I32, a0, a1); 2209 tgen_andi(s, TCG_TYPE_I32, a0, a2); 2210 } else if (a0 == a1) { 2211 tcg_out_insn(s, RR, NR, a0, a2); 2212 } else { 2213 tcg_out_insn(s, RRFa, NRK, a0, a1, a2); 2214 } 2215 break; 2216 case INDEX_op_or_i32: 2217 a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; 2218 if (const_args[2]) { 2219 tcg_out_mov(s, TCG_TYPE_I32, a0, a1); 2220 tgen_ori(s, a0, a2); 2221 } else if (a0 == a1) { 2222 tcg_out_insn(s, RR, OR, a0, a2); 2223 } else { 2224 tcg_out_insn(s, RRFa, ORK, a0, a1, a2); 2225 } 2226 break; 2227 case INDEX_op_xor_i32: 2228 a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; 2229 if (const_args[2]) { 2230 tcg_out_mov(s, TCG_TYPE_I32, a0, a1); 2231 tcg_out_insn(s, RIL, XILF, a0, a2); 2232 } else if (a0 == a1) { 2233 tcg_out_insn(s, RR, XR, args[0], args[2]); 2234 } else { 2235 tcg_out_insn(s, RRFa, XRK, a0, a1, a2); 2236 } 2237 break; 2238 2239 case INDEX_op_andc_i32: 2240 a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; 2241 if (const_args[2]) { 2242 tcg_out_mov(s, TCG_TYPE_I32, a0, a1); 2243 tgen_andi(s, TCG_TYPE_I32, a0, (uint32_t)~a2); 2244 } else { 2245 tcg_out_insn(s, RRFa, NCRK, a0, a1, a2); 2246 } 2247 break; 2248 case INDEX_op_orc_i32: 2249 a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; 2250 if (const_args[2]) { 2251 tcg_out_mov(s, TCG_TYPE_I32, a0, a1); 2252 tgen_ori(s, a0, (uint32_t)~a2); 2253 } else { 2254 tcg_out_insn(s, RRFa, OCRK, a0, a1, a2); 2255 } 2256 break; 2257 case INDEX_op_eqv_i32: 2258 a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; 2259 if (const_args[2]) { 2260 tcg_out_mov(s, TCG_TYPE_I32, a0, a1); 2261 tcg_out_insn(s, RIL, XILF, a0, ~a2); 2262 } else { 2263 tcg_out_insn(s, RRFa, NXRK, a0, a1, a2); 2264 } 2265 break; 2266 case INDEX_op_nand_i32: 2267 tcg_out_insn(s, RRFa, NNRK, args[0], args[1], args[2]); 2268 break; 2269 case INDEX_op_nor_i32: 2270 tcg_out_insn(s, RRFa, NORK, args[0], args[1], args[2]); 2271 break; 2272 2273 case INDEX_op_neg_i32: 2274 tcg_out_insn(s, RR, LCR, args[0], args[1]); 2275 break; 2276 case INDEX_op_not_i32: 2277 tcg_out_insn(s, RRFa, NORK, args[0], args[1], args[1]); 2278 break; 2279 2280 case INDEX_op_mul_i32: 2281 a0 = args[0], a1 = args[1], a2 = (int32_t)args[2]; 2282 if (const_args[2]) { 2283 tcg_out_mov(s, TCG_TYPE_I32, a0, a1); 2284 if (a2 == (int16_t)a2) { 2285 tcg_out_insn(s, RI, MHI, a0, a2); 2286 } else { 2287 tcg_out_insn(s, RIL, MSFI, a0, a2); 2288 } 2289 } else if (a0 == a1) { 2290 tcg_out_insn(s, RRE, MSR, a0, a2); 2291 } else { 2292 tcg_out_insn(s, RRFa, MSRKC, a0, a1, a2); 2293 } 2294 break; 2295 2296 case INDEX_op_div2_i32: 2297 tcg_debug_assert(args[0] == args[2]); 2298 tcg_debug_assert(args[1] == args[3]); 2299 tcg_debug_assert((args[1] & 1) == 0); 2300 tcg_debug_assert(args[0] == args[1] + 1); 2301 tcg_out_insn(s, RR, DR, args[1], args[4]); 2302 break; 2303 case INDEX_op_divu2_i32: 2304 tcg_debug_assert(args[0] == args[2]); 2305 tcg_debug_assert(args[1] == args[3]); 2306 tcg_debug_assert((args[1] & 1) == 0); 2307 tcg_debug_assert(args[0] == args[1] + 1); 2308 tcg_out_insn(s, RRE, DLR, args[1], args[4]); 2309 break; 2310 2311 case INDEX_op_shl_i32: 2312 op = RS_SLL; 2313 op2 = RSY_SLLK; 2314 do_shift32: 2315 a0 = args[0], a1 = args[1], a2 = (int32_t)args[2]; 2316 if (a0 == a1) { 2317 if (const_args[2]) { 2318 tcg_out_sh32(s, op, a0, TCG_REG_NONE, a2); 2319 } else { 2320 tcg_out_sh32(s, op, a0, a2, 0); 2321 } 2322 } else { 2323 /* Using tcg_out_sh64 here for the format; it is a 32-bit shift. */ 2324 if (const_args[2]) { 2325 tcg_out_sh64(s, op2, a0, a1, TCG_REG_NONE, a2); 2326 } else { 2327 tcg_out_sh64(s, op2, a0, a1, a2, 0); 2328 } 2329 } 2330 break; 2331 case INDEX_op_shr_i32: 2332 op = RS_SRL; 2333 op2 = RSY_SRLK; 2334 goto do_shift32; 2335 case INDEX_op_sar_i32: 2336 op = RS_SRA; 2337 op2 = RSY_SRAK; 2338 goto do_shift32; 2339 2340 case INDEX_op_rotl_i32: 2341 /* ??? Using tcg_out_sh64 here for the format; it is a 32-bit rol. */ 2342 if (const_args[2]) { 2343 tcg_out_sh64(s, RSY_RLL, args[0], args[1], TCG_REG_NONE, args[2]); 2344 } else { 2345 tcg_out_sh64(s, RSY_RLL, args[0], args[1], args[2], 0); 2346 } 2347 break; 2348 case INDEX_op_rotr_i32: 2349 if (const_args[2]) { 2350 tcg_out_sh64(s, RSY_RLL, args[0], args[1], 2351 TCG_REG_NONE, (32 - args[2]) & 31); 2352 } else { 2353 tcg_out_insn(s, RR, LCR, TCG_TMP0, args[2]); 2354 tcg_out_sh64(s, RSY_RLL, args[0], args[1], TCG_TMP0, 0); 2355 } 2356 break; 2357 2358 case INDEX_op_bswap16_i32: 2359 a0 = args[0], a1 = args[1], a2 = args[2]; 2360 tcg_out_insn(s, RRE, LRVR, a0, a1); 2361 if (a2 & TCG_BSWAP_OS) { 2362 tcg_out_sh32(s, RS_SRA, a0, TCG_REG_NONE, 16); 2363 } else { 2364 tcg_out_sh32(s, RS_SRL, a0, TCG_REG_NONE, 16); 2365 } 2366 break; 2367 case INDEX_op_bswap16_i64: 2368 a0 = args[0], a1 = args[1], a2 = args[2]; 2369 tcg_out_insn(s, RRE, LRVGR, a0, a1); 2370 if (a2 & TCG_BSWAP_OS) { 2371 tcg_out_sh64(s, RSY_SRAG, a0, a0, TCG_REG_NONE, 48); 2372 } else { 2373 tcg_out_sh64(s, RSY_SRLG, a0, a0, TCG_REG_NONE, 48); 2374 } 2375 break; 2376 2377 case INDEX_op_bswap32_i32: 2378 tcg_out_insn(s, RRE, LRVR, args[0], args[1]); 2379 break; 2380 case INDEX_op_bswap32_i64: 2381 a0 = args[0], a1 = args[1], a2 = args[2]; 2382 tcg_out_insn(s, RRE, LRVR, a0, a1); 2383 if (a2 & TCG_BSWAP_OS) { 2384 tcg_out_ext32s(s, a0, a0); 2385 } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 2386 tcg_out_ext32u(s, a0, a0); 2387 } 2388 break; 2389 2390 case INDEX_op_add2_i32: 2391 if (const_args[4]) { 2392 tcg_out_insn(s, RIL, ALFI, args[0], args[4]); 2393 } else { 2394 tcg_out_insn(s, RR, ALR, args[0], args[4]); 2395 } 2396 tcg_out_insn(s, RRE, ALCR, args[1], args[5]); 2397 break; 2398 case INDEX_op_sub2_i32: 2399 if (const_args[4]) { 2400 tcg_out_insn(s, RIL, SLFI, args[0], args[4]); 2401 } else { 2402 tcg_out_insn(s, RR, SLR, args[0], args[4]); 2403 } 2404 tcg_out_insn(s, RRE, SLBR, args[1], args[5]); 2405 break; 2406 2407 case INDEX_op_br: 2408 tgen_branch(s, S390_CC_ALWAYS, arg_label(args[0])); 2409 break; 2410 2411 case INDEX_op_brcond_i32: 2412 tgen_brcond(s, TCG_TYPE_I32, args[2], args[0], 2413 args[1], const_args[1], arg_label(args[3])); 2414 break; 2415 case INDEX_op_setcond_i32: 2416 tgen_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], 2417 args[2], const_args[2], false); 2418 break; 2419 case INDEX_op_negsetcond_i32: 2420 tgen_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], 2421 args[2], const_args[2], true); 2422 break; 2423 case INDEX_op_movcond_i32: 2424 tgen_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], 2425 args[2], const_args[2], args[3], const_args[3], args[4]); 2426 break; 2427 2428 case INDEX_op_qemu_ld_a32_i32: 2429 case INDEX_op_qemu_ld_a64_i32: 2430 tcg_out_qemu_ld(s, args[0], args[1], args[2], TCG_TYPE_I32); 2431 break; 2432 case INDEX_op_qemu_ld_a32_i64: 2433 case INDEX_op_qemu_ld_a64_i64: 2434 tcg_out_qemu_ld(s, args[0], args[1], args[2], TCG_TYPE_I64); 2435 break; 2436 case INDEX_op_qemu_st_a32_i32: 2437 case INDEX_op_qemu_st_a64_i32: 2438 tcg_out_qemu_st(s, args[0], args[1], args[2], TCG_TYPE_I32); 2439 break; 2440 case INDEX_op_qemu_st_a32_i64: 2441 case INDEX_op_qemu_st_a64_i64: 2442 tcg_out_qemu_st(s, args[0], args[1], args[2], TCG_TYPE_I64); 2443 break; 2444 case INDEX_op_qemu_ld_a32_i128: 2445 case INDEX_op_qemu_ld_a64_i128: 2446 tcg_out_qemu_ldst_i128(s, args[0], args[1], args[2], args[3], true); 2447 break; 2448 case INDEX_op_qemu_st_a32_i128: 2449 case INDEX_op_qemu_st_a64_i128: 2450 tcg_out_qemu_ldst_i128(s, args[0], args[1], args[2], args[3], false); 2451 break; 2452 2453 case INDEX_op_ld16s_i64: 2454 tcg_out_mem(s, 0, RXY_LGH, args[0], args[1], TCG_REG_NONE, args[2]); 2455 break; 2456 case INDEX_op_ld32u_i64: 2457 tcg_out_mem(s, 0, RXY_LLGF, args[0], args[1], TCG_REG_NONE, args[2]); 2458 break; 2459 case INDEX_op_ld32s_i64: 2460 tcg_out_mem(s, 0, RXY_LGF, args[0], args[1], TCG_REG_NONE, args[2]); 2461 break; 2462 case INDEX_op_ld_i64: 2463 tcg_out_ld(s, TCG_TYPE_I64, args[0], args[1], args[2]); 2464 break; 2465 2466 case INDEX_op_st32_i64: 2467 tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]); 2468 break; 2469 case INDEX_op_st_i64: 2470 tcg_out_st(s, TCG_TYPE_I64, args[0], args[1], args[2]); 2471 break; 2472 2473 case INDEX_op_add_i64: 2474 a0 = args[0], a1 = args[1], a2 = args[2]; 2475 if (const_args[2]) { 2476 do_addi_64: 2477 if (a0 == a1) { 2478 if (a2 == (int16_t)a2) { 2479 tcg_out_insn(s, RI, AGHI, a0, a2); 2480 break; 2481 } 2482 if (a2 == (int32_t)a2) { 2483 tcg_out_insn(s, RIL, AGFI, a0, a2); 2484 break; 2485 } 2486 if (a2 == (uint32_t)a2) { 2487 tcg_out_insn(s, RIL, ALGFI, a0, a2); 2488 break; 2489 } 2490 if (-a2 == (uint32_t)-a2) { 2491 tcg_out_insn(s, RIL, SLGFI, a0, -a2); 2492 break; 2493 } 2494 } 2495 tcg_out_mem(s, RX_LA, RXY_LAY, a0, a1, TCG_REG_NONE, a2); 2496 } else if (a0 == a1) { 2497 tcg_out_insn(s, RRE, AGR, a0, a2); 2498 } else { 2499 tcg_out_insn(s, RX, LA, a0, a1, a2, 0); 2500 } 2501 break; 2502 case INDEX_op_sub_i64: 2503 a0 = args[0], a1 = args[1], a2 = args[2]; 2504 if (const_args[2]) { 2505 a2 = -a2; 2506 goto do_addi_64; 2507 } else { 2508 tcg_out_insn(s, RRFa, SGRK, a0, a1, a2); 2509 } 2510 break; 2511 2512 case INDEX_op_and_i64: 2513 a0 = args[0], a1 = args[1], a2 = args[2]; 2514 if (const_args[2]) { 2515 tcg_out_mov(s, TCG_TYPE_I64, a0, a1); 2516 tgen_andi(s, TCG_TYPE_I64, args[0], args[2]); 2517 } else { 2518 tcg_out_insn(s, RRFa, NGRK, a0, a1, a2); 2519 } 2520 break; 2521 case INDEX_op_or_i64: 2522 a0 = args[0], a1 = args[1], a2 = args[2]; 2523 if (const_args[2]) { 2524 tcg_out_mov(s, TCG_TYPE_I64, a0, a1); 2525 tgen_ori(s, a0, a2); 2526 } else { 2527 tcg_out_insn(s, RRFa, OGRK, a0, a1, a2); 2528 } 2529 break; 2530 case INDEX_op_xor_i64: 2531 a0 = args[0], a1 = args[1], a2 = args[2]; 2532 if (const_args[2]) { 2533 tcg_out_mov(s, TCG_TYPE_I64, a0, a1); 2534 tgen_xori(s, a0, a2); 2535 } else { 2536 tcg_out_insn(s, RRFa, XGRK, a0, a1, a2); 2537 } 2538 break; 2539 2540 case INDEX_op_andc_i64: 2541 a0 = args[0], a1 = args[1], a2 = args[2]; 2542 if (const_args[2]) { 2543 tcg_out_mov(s, TCG_TYPE_I64, a0, a1); 2544 tgen_andi(s, TCG_TYPE_I64, a0, ~a2); 2545 } else { 2546 tcg_out_insn(s, RRFa, NCGRK, a0, a1, a2); 2547 } 2548 break; 2549 case INDEX_op_orc_i64: 2550 a0 = args[0], a1 = args[1], a2 = args[2]; 2551 if (const_args[2]) { 2552 tcg_out_mov(s, TCG_TYPE_I64, a0, a1); 2553 tgen_ori(s, a0, ~a2); 2554 } else { 2555 tcg_out_insn(s, RRFa, OCGRK, a0, a1, a2); 2556 } 2557 break; 2558 case INDEX_op_eqv_i64: 2559 a0 = args[0], a1 = args[1], a2 = args[2]; 2560 if (const_args[2]) { 2561 tcg_out_mov(s, TCG_TYPE_I64, a0, a1); 2562 tgen_xori(s, a0, ~a2); 2563 } else { 2564 tcg_out_insn(s, RRFa, NXGRK, a0, a1, a2); 2565 } 2566 break; 2567 case INDEX_op_nand_i64: 2568 tcg_out_insn(s, RRFa, NNGRK, args[0], args[1], args[2]); 2569 break; 2570 case INDEX_op_nor_i64: 2571 tcg_out_insn(s, RRFa, NOGRK, args[0], args[1], args[2]); 2572 break; 2573 2574 case INDEX_op_neg_i64: 2575 tcg_out_insn(s, RRE, LCGR, args[0], args[1]); 2576 break; 2577 case INDEX_op_not_i64: 2578 tcg_out_insn(s, RRFa, NOGRK, args[0], args[1], args[1]); 2579 break; 2580 case INDEX_op_bswap64_i64: 2581 tcg_out_insn(s, RRE, LRVGR, args[0], args[1]); 2582 break; 2583 2584 case INDEX_op_mul_i64: 2585 a0 = args[0], a1 = args[1], a2 = args[2]; 2586 if (const_args[2]) { 2587 tcg_out_mov(s, TCG_TYPE_I64, a0, a1); 2588 if (a2 == (int16_t)a2) { 2589 tcg_out_insn(s, RI, MGHI, a0, a2); 2590 } else { 2591 tcg_out_insn(s, RIL, MSGFI, a0, a2); 2592 } 2593 } else if (a0 == a1) { 2594 tcg_out_insn(s, RRE, MSGR, a0, a2); 2595 } else { 2596 tcg_out_insn(s, RRFa, MSGRKC, a0, a1, a2); 2597 } 2598 break; 2599 2600 case INDEX_op_div2_i64: 2601 /* 2602 * ??? We get an unnecessary sign-extension of the dividend 2603 * into op0 with this definition, but as we do in fact always 2604 * produce both quotient and remainder using INDEX_op_div_i64 2605 * instead requires jumping through even more hoops. 2606 */ 2607 tcg_debug_assert(args[0] == args[2]); 2608 tcg_debug_assert(args[1] == args[3]); 2609 tcg_debug_assert((args[1] & 1) == 0); 2610 tcg_debug_assert(args[0] == args[1] + 1); 2611 tcg_out_insn(s, RRE, DSGR, args[1], args[4]); 2612 break; 2613 case INDEX_op_divu2_i64: 2614 tcg_debug_assert(args[0] == args[2]); 2615 tcg_debug_assert(args[1] == args[3]); 2616 tcg_debug_assert((args[1] & 1) == 0); 2617 tcg_debug_assert(args[0] == args[1] + 1); 2618 tcg_out_insn(s, RRE, DLGR, args[1], args[4]); 2619 break; 2620 case INDEX_op_mulu2_i64: 2621 tcg_debug_assert(args[0] == args[2]); 2622 tcg_debug_assert((args[1] & 1) == 0); 2623 tcg_debug_assert(args[0] == args[1] + 1); 2624 tcg_out_insn(s, RRE, MLGR, args[1], args[3]); 2625 break; 2626 case INDEX_op_muls2_i64: 2627 tcg_debug_assert((args[1] & 1) == 0); 2628 tcg_debug_assert(args[0] == args[1] + 1); 2629 tcg_out_insn(s, RRFa, MGRK, args[1], args[2], args[3]); 2630 break; 2631 2632 case INDEX_op_shl_i64: 2633 op = RSY_SLLG; 2634 do_shift64: 2635 if (const_args[2]) { 2636 tcg_out_sh64(s, op, args[0], args[1], TCG_REG_NONE, args[2]); 2637 } else { 2638 tcg_out_sh64(s, op, args[0], args[1], args[2], 0); 2639 } 2640 break; 2641 case INDEX_op_shr_i64: 2642 op = RSY_SRLG; 2643 goto do_shift64; 2644 case INDEX_op_sar_i64: 2645 op = RSY_SRAG; 2646 goto do_shift64; 2647 2648 case INDEX_op_rotl_i64: 2649 if (const_args[2]) { 2650 tcg_out_sh64(s, RSY_RLLG, args[0], args[1], 2651 TCG_REG_NONE, args[2]); 2652 } else { 2653 tcg_out_sh64(s, RSY_RLLG, args[0], args[1], args[2], 0); 2654 } 2655 break; 2656 case INDEX_op_rotr_i64: 2657 if (const_args[2]) { 2658 tcg_out_sh64(s, RSY_RLLG, args[0], args[1], 2659 TCG_REG_NONE, (64 - args[2]) & 63); 2660 } else { 2661 /* We can use the smaller 32-bit negate because only the 2662 low 6 bits are examined for the rotate. */ 2663 tcg_out_insn(s, RR, LCR, TCG_TMP0, args[2]); 2664 tcg_out_sh64(s, RSY_RLLG, args[0], args[1], TCG_TMP0, 0); 2665 } 2666 break; 2667 2668 case INDEX_op_add2_i64: 2669 if (const_args[4]) { 2670 if ((int64_t)args[4] >= 0) { 2671 tcg_out_insn(s, RIL, ALGFI, args[0], args[4]); 2672 } else { 2673 tcg_out_insn(s, RIL, SLGFI, args[0], -args[4]); 2674 } 2675 } else { 2676 tcg_out_insn(s, RRE, ALGR, args[0], args[4]); 2677 } 2678 tcg_out_insn(s, RRE, ALCGR, args[1], args[5]); 2679 break; 2680 case INDEX_op_sub2_i64: 2681 if (const_args[4]) { 2682 if ((int64_t)args[4] >= 0) { 2683 tcg_out_insn(s, RIL, SLGFI, args[0], args[4]); 2684 } else { 2685 tcg_out_insn(s, RIL, ALGFI, args[0], -args[4]); 2686 } 2687 } else { 2688 tcg_out_insn(s, RRE, SLGR, args[0], args[4]); 2689 } 2690 tcg_out_insn(s, RRE, SLBGR, args[1], args[5]); 2691 break; 2692 2693 case INDEX_op_brcond_i64: 2694 tgen_brcond(s, TCG_TYPE_I64, args[2], args[0], 2695 args[1], const_args[1], arg_label(args[3])); 2696 break; 2697 case INDEX_op_setcond_i64: 2698 tgen_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], 2699 args[2], const_args[2], false); 2700 break; 2701 case INDEX_op_negsetcond_i64: 2702 tgen_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], 2703 args[2], const_args[2], true); 2704 break; 2705 case INDEX_op_movcond_i64: 2706 tgen_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], 2707 args[2], const_args[2], args[3], const_args[3], args[4]); 2708 break; 2709 2710 OP_32_64(deposit): 2711 a0 = args[0], a1 = args[1], a2 = args[2]; 2712 if (const_args[1]) { 2713 tgen_deposit(s, a0, a2, args[3], args[4], 1); 2714 } else { 2715 /* Since we can't support "0Z" as a constraint, we allow a1 in 2716 any register. Fix things up as if a matching constraint. */ 2717 if (a0 != a1) { 2718 TCGType type = (opc == INDEX_op_deposit_i64); 2719 if (a0 == a2) { 2720 tcg_out_mov(s, type, TCG_TMP0, a2); 2721 a2 = TCG_TMP0; 2722 } 2723 tcg_out_mov(s, type, a0, a1); 2724 } 2725 tgen_deposit(s, a0, a2, args[3], args[4], 0); 2726 } 2727 break; 2728 2729 OP_32_64(extract): 2730 tgen_extract(s, args[0], args[1], args[2], args[3]); 2731 break; 2732 2733 case INDEX_op_clz_i64: 2734 tgen_clz(s, args[0], args[1], args[2], const_args[2]); 2735 break; 2736 2737 case INDEX_op_ctpop_i32: 2738 tgen_ctpop(s, TCG_TYPE_I32, args[0], args[1]); 2739 break; 2740 case INDEX_op_ctpop_i64: 2741 tgen_ctpop(s, TCG_TYPE_I64, args[0], args[1]); 2742 break; 2743 2744 case INDEX_op_mb: 2745 /* The host memory model is quite strong, we simply need to 2746 serialize the instruction stream. */ 2747 if (args[0] & TCG_MO_ST_LD) { 2748 /* fast-bcr-serialization facility (45) is present */ 2749 tcg_out_insn(s, RR, BCR, 14, 0); 2750 } 2751 break; 2752 2753 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ 2754 case INDEX_op_mov_i64: 2755 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2756 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 2757 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 2758 case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ 2759 case INDEX_op_ext8s_i64: 2760 case INDEX_op_ext8u_i32: 2761 case INDEX_op_ext8u_i64: 2762 case INDEX_op_ext16s_i32: 2763 case INDEX_op_ext16s_i64: 2764 case INDEX_op_ext16u_i32: 2765 case INDEX_op_ext16u_i64: 2766 case INDEX_op_ext32s_i64: 2767 case INDEX_op_ext32u_i64: 2768 case INDEX_op_ext_i32_i64: 2769 case INDEX_op_extu_i32_i64: 2770 case INDEX_op_extrl_i64_i32: 2771 default: 2772 g_assert_not_reached(); 2773 } 2774} 2775 2776static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 2777 TCGReg dst, TCGReg src) 2778{ 2779 if (is_general_reg(src)) { 2780 /* Replicate general register into two MO_64. */ 2781 tcg_out_insn(s, VRRf, VLVGP, dst, src, src); 2782 if (vece == MO_64) { 2783 return true; 2784 } 2785 src = dst; 2786 } 2787 2788 /* 2789 * Recall that the "standard" integer, within a vector, is the 2790 * rightmost element of the leftmost doubleword, a-la VLLEZ. 2791 */ 2792 tcg_out_insn(s, VRIc, VREP, dst, (8 >> vece) - 1, src, vece); 2793 return true; 2794} 2795 2796static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 2797 TCGReg dst, TCGReg base, intptr_t offset) 2798{ 2799 tcg_out_vrx_mem(s, VRX_VLREP, dst, base, TCG_REG_NONE, offset, vece); 2800 return true; 2801} 2802 2803static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 2804 TCGReg dst, int64_t val) 2805{ 2806 int i, mask, msb, lsb; 2807 2808 /* Look for int16_t elements. */ 2809 if (vece <= MO_16 || 2810 (vece == MO_32 ? (int32_t)val : val) == (int16_t)val) { 2811 tcg_out_insn(s, VRIa, VREPI, dst, val, vece); 2812 return; 2813 } 2814 2815 /* Look for bit masks. */ 2816 if (vece == MO_32) { 2817 if (risbg_mask((int32_t)val)) { 2818 /* Handle wraparound by swapping msb and lsb. */ 2819 if ((val & 0x80000001u) == 0x80000001u) { 2820 msb = 32 - ctz32(~val); 2821 lsb = clz32(~val) - 1; 2822 } else { 2823 msb = clz32(val); 2824 lsb = 31 - ctz32(val); 2825 } 2826 tcg_out_insn(s, VRIb, VGM, dst, msb, lsb, MO_32); 2827 return; 2828 } 2829 } else { 2830 if (risbg_mask(val)) { 2831 /* Handle wraparound by swapping msb and lsb. */ 2832 if ((val & 0x8000000000000001ull) == 0x8000000000000001ull) { 2833 /* Handle wraparound by swapping msb and lsb. */ 2834 msb = 64 - ctz64(~val); 2835 lsb = clz64(~val) - 1; 2836 } else { 2837 msb = clz64(val); 2838 lsb = 63 - ctz64(val); 2839 } 2840 tcg_out_insn(s, VRIb, VGM, dst, msb, lsb, MO_64); 2841 return; 2842 } 2843 } 2844 2845 /* Look for all bytes 0x00 or 0xff. */ 2846 for (i = mask = 0; i < 8; i++) { 2847 uint8_t byte = val >> (i * 8); 2848 if (byte == 0xff) { 2849 mask |= 1 << i; 2850 } else if (byte != 0) { 2851 break; 2852 } 2853 } 2854 if (i == 8) { 2855 tcg_out_insn(s, VRIa, VGBM, dst, mask * 0x0101, 0); 2856 return; 2857 } 2858 2859 /* Otherwise, stuff it in the constant pool. */ 2860 tcg_out_insn(s, RIL, LARL, TCG_TMP0, 0); 2861 new_pool_label(s, val, R_390_PC32DBL, s->code_ptr - 2, 2); 2862 tcg_out_insn(s, VRX, VLREP, dst, TCG_TMP0, TCG_REG_NONE, 0, MO_64); 2863} 2864 2865static bool tcg_out_cmp_vec_noinv(TCGContext *s, unsigned vece, TCGReg a0, 2866 TCGReg a1, TCGReg a2, TCGCond cond) 2867{ 2868 bool need_swap = false, need_inv = false; 2869 2870 switch (cond) { 2871 case TCG_COND_EQ: 2872 case TCG_COND_GT: 2873 case TCG_COND_GTU: 2874 break; 2875 case TCG_COND_NE: 2876 case TCG_COND_LE: 2877 case TCG_COND_LEU: 2878 need_inv = true; 2879 break; 2880 case TCG_COND_LT: 2881 case TCG_COND_LTU: 2882 need_swap = true; 2883 break; 2884 case TCG_COND_GE: 2885 case TCG_COND_GEU: 2886 need_swap = need_inv = true; 2887 break; 2888 default: 2889 g_assert_not_reached(); 2890 } 2891 2892 if (need_inv) { 2893 cond = tcg_invert_cond(cond); 2894 } 2895 if (need_swap) { 2896 TCGReg swap = a1; 2897 a1 = a2; 2898 a2 = swap; 2899 cond = tcg_swap_cond(cond); 2900 } 2901 2902 switch (cond) { 2903 case TCG_COND_EQ: 2904 tcg_out_insn(s, VRRc, VCEQ, a0, a1, a2, vece); 2905 break; 2906 case TCG_COND_GT: 2907 tcg_out_insn(s, VRRc, VCH, a0, a1, a2, vece); 2908 break; 2909 case TCG_COND_GTU: 2910 tcg_out_insn(s, VRRc, VCHL, a0, a1, a2, vece); 2911 break; 2912 default: 2913 g_assert_not_reached(); 2914 } 2915 return need_inv; 2916} 2917 2918static void tcg_out_cmp_vec(TCGContext *s, unsigned vece, TCGReg a0, 2919 TCGReg a1, TCGReg a2, TCGCond cond) 2920{ 2921 if (tcg_out_cmp_vec_noinv(s, vece, a0, a1, a2, cond)) { 2922 tcg_out_insn(s, VRRc, VNO, a0, a0, a0, 0); 2923 } 2924} 2925 2926static void tcg_out_cmpsel_vec(TCGContext *s, unsigned vece, TCGReg a0, 2927 TCGReg c1, TCGReg c2, TCGArg v3, 2928 int const_v3, TCGReg v4, TCGCond cond) 2929{ 2930 bool inv = tcg_out_cmp_vec_noinv(s, vece, TCG_VEC_TMP0, c1, c2, cond); 2931 2932 if (!const_v3) { 2933 if (inv) { 2934 tcg_out_insn(s, VRRe, VSEL, a0, v4, v3, TCG_VEC_TMP0); 2935 } else { 2936 tcg_out_insn(s, VRRe, VSEL, a0, v3, v4, TCG_VEC_TMP0); 2937 } 2938 } else if (v3) { 2939 if (inv) { 2940 tcg_out_insn(s, VRRc, VOC, a0, v4, TCG_VEC_TMP0, 0); 2941 } else { 2942 tcg_out_insn(s, VRRc, VO, a0, v4, TCG_VEC_TMP0, 0); 2943 } 2944 } else { 2945 if (inv) { 2946 tcg_out_insn(s, VRRc, VN, a0, v4, TCG_VEC_TMP0, 0); 2947 } else { 2948 tcg_out_insn(s, VRRc, VNC, a0, v4, TCG_VEC_TMP0, 0); 2949 } 2950 } 2951} 2952 2953static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 2954 unsigned vecl, unsigned vece, 2955 const TCGArg args[TCG_MAX_OP_ARGS], 2956 const int const_args[TCG_MAX_OP_ARGS]) 2957{ 2958 TCGType type = vecl + TCG_TYPE_V64; 2959 TCGArg a0 = args[0], a1 = args[1], a2 = args[2]; 2960 2961 switch (opc) { 2962 case INDEX_op_ld_vec: 2963 tcg_out_ld(s, type, a0, a1, a2); 2964 break; 2965 case INDEX_op_st_vec: 2966 tcg_out_st(s, type, a0, a1, a2); 2967 break; 2968 case INDEX_op_dupm_vec: 2969 tcg_out_dupm_vec(s, type, vece, a0, a1, a2); 2970 break; 2971 2972 case INDEX_op_abs_vec: 2973 tcg_out_insn(s, VRRa, VLP, a0, a1, vece); 2974 break; 2975 case INDEX_op_neg_vec: 2976 tcg_out_insn(s, VRRa, VLC, a0, a1, vece); 2977 break; 2978 case INDEX_op_not_vec: 2979 tcg_out_insn(s, VRRc, VNO, a0, a1, a1, 0); 2980 break; 2981 2982 case INDEX_op_add_vec: 2983 tcg_out_insn(s, VRRc, VA, a0, a1, a2, vece); 2984 break; 2985 case INDEX_op_sub_vec: 2986 tcg_out_insn(s, VRRc, VS, a0, a1, a2, vece); 2987 break; 2988 case INDEX_op_and_vec: 2989 tcg_out_insn(s, VRRc, VN, a0, a1, a2, 0); 2990 break; 2991 case INDEX_op_andc_vec: 2992 tcg_out_insn(s, VRRc, VNC, a0, a1, a2, 0); 2993 break; 2994 case INDEX_op_mul_vec: 2995 tcg_out_insn(s, VRRc, VML, a0, a1, a2, vece); 2996 break; 2997 case INDEX_op_or_vec: 2998 tcg_out_insn(s, VRRc, VO, a0, a1, a2, 0); 2999 break; 3000 case INDEX_op_orc_vec: 3001 tcg_out_insn(s, VRRc, VOC, a0, a1, a2, 0); 3002 break; 3003 case INDEX_op_xor_vec: 3004 tcg_out_insn(s, VRRc, VX, a0, a1, a2, 0); 3005 break; 3006 case INDEX_op_nand_vec: 3007 tcg_out_insn(s, VRRc, VNN, a0, a1, a2, 0); 3008 break; 3009 case INDEX_op_nor_vec: 3010 tcg_out_insn(s, VRRc, VNO, a0, a1, a2, 0); 3011 break; 3012 case INDEX_op_eqv_vec: 3013 tcg_out_insn(s, VRRc, VNX, a0, a1, a2, 0); 3014 break; 3015 3016 case INDEX_op_shli_vec: 3017 tcg_out_insn(s, VRSa, VESL, a0, a2, TCG_REG_NONE, a1, vece); 3018 break; 3019 case INDEX_op_shri_vec: 3020 tcg_out_insn(s, VRSa, VESRL, a0, a2, TCG_REG_NONE, a1, vece); 3021 break; 3022 case INDEX_op_sari_vec: 3023 tcg_out_insn(s, VRSa, VESRA, a0, a2, TCG_REG_NONE, a1, vece); 3024 break; 3025 case INDEX_op_rotli_vec: 3026 tcg_out_insn(s, VRSa, VERLL, a0, a2, TCG_REG_NONE, a1, vece); 3027 break; 3028 case INDEX_op_shls_vec: 3029 tcg_out_insn(s, VRSa, VESL, a0, 0, a2, a1, vece); 3030 break; 3031 case INDEX_op_shrs_vec: 3032 tcg_out_insn(s, VRSa, VESRL, a0, 0, a2, a1, vece); 3033 break; 3034 case INDEX_op_sars_vec: 3035 tcg_out_insn(s, VRSa, VESRA, a0, 0, a2, a1, vece); 3036 break; 3037 case INDEX_op_rotls_vec: 3038 tcg_out_insn(s, VRSa, VERLL, a0, 0, a2, a1, vece); 3039 break; 3040 case INDEX_op_shlv_vec: 3041 tcg_out_insn(s, VRRc, VESLV, a0, a1, a2, vece); 3042 break; 3043 case INDEX_op_shrv_vec: 3044 tcg_out_insn(s, VRRc, VESRLV, a0, a1, a2, vece); 3045 break; 3046 case INDEX_op_sarv_vec: 3047 tcg_out_insn(s, VRRc, VESRAV, a0, a1, a2, vece); 3048 break; 3049 case INDEX_op_rotlv_vec: 3050 tcg_out_insn(s, VRRc, VERLLV, a0, a1, a2, vece); 3051 break; 3052 3053 case INDEX_op_smin_vec: 3054 tcg_out_insn(s, VRRc, VMN, a0, a1, a2, vece); 3055 break; 3056 case INDEX_op_smax_vec: 3057 tcg_out_insn(s, VRRc, VMX, a0, a1, a2, vece); 3058 break; 3059 case INDEX_op_umin_vec: 3060 tcg_out_insn(s, VRRc, VMNL, a0, a1, a2, vece); 3061 break; 3062 case INDEX_op_umax_vec: 3063 tcg_out_insn(s, VRRc, VMXL, a0, a1, a2, vece); 3064 break; 3065 3066 case INDEX_op_bitsel_vec: 3067 tcg_out_insn(s, VRRe, VSEL, a0, a2, args[3], a1); 3068 break; 3069 3070 case INDEX_op_cmp_vec: 3071 tcg_out_cmp_vec(s, vece, a0, a1, a2, args[3]); 3072 break; 3073 case INDEX_op_cmpsel_vec: 3074 tcg_out_cmpsel_vec(s, vece, a0, a1, a2, args[3], const_args[3], 3075 args[4], args[5]); 3076 break; 3077 3078 case INDEX_op_s390_vuph_vec: 3079 tcg_out_insn(s, VRRa, VUPH, a0, a1, vece); 3080 break; 3081 case INDEX_op_s390_vupl_vec: 3082 tcg_out_insn(s, VRRa, VUPL, a0, a1, vece); 3083 break; 3084 case INDEX_op_s390_vpks_vec: 3085 tcg_out_insn(s, VRRc, VPKS, a0, a1, a2, vece); 3086 break; 3087 3088 case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ 3089 case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ 3090 default: 3091 g_assert_not_reached(); 3092 } 3093} 3094 3095int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) 3096{ 3097 switch (opc) { 3098 case INDEX_op_abs_vec: 3099 case INDEX_op_add_vec: 3100 case INDEX_op_and_vec: 3101 case INDEX_op_andc_vec: 3102 case INDEX_op_bitsel_vec: 3103 case INDEX_op_eqv_vec: 3104 case INDEX_op_nand_vec: 3105 case INDEX_op_neg_vec: 3106 case INDEX_op_nor_vec: 3107 case INDEX_op_not_vec: 3108 case INDEX_op_or_vec: 3109 case INDEX_op_orc_vec: 3110 case INDEX_op_rotli_vec: 3111 case INDEX_op_rotls_vec: 3112 case INDEX_op_rotlv_vec: 3113 case INDEX_op_sari_vec: 3114 case INDEX_op_sars_vec: 3115 case INDEX_op_sarv_vec: 3116 case INDEX_op_shli_vec: 3117 case INDEX_op_shls_vec: 3118 case INDEX_op_shlv_vec: 3119 case INDEX_op_shri_vec: 3120 case INDEX_op_shrs_vec: 3121 case INDEX_op_shrv_vec: 3122 case INDEX_op_smax_vec: 3123 case INDEX_op_smin_vec: 3124 case INDEX_op_sub_vec: 3125 case INDEX_op_umax_vec: 3126 case INDEX_op_umin_vec: 3127 case INDEX_op_xor_vec: 3128 case INDEX_op_cmp_vec: 3129 case INDEX_op_cmpsel_vec: 3130 return 1; 3131 case INDEX_op_rotrv_vec: 3132 return -1; 3133 case INDEX_op_mul_vec: 3134 return vece < MO_64; 3135 case INDEX_op_ssadd_vec: 3136 case INDEX_op_sssub_vec: 3137 return vece < MO_64 ? -1 : 0; 3138 default: 3139 return 0; 3140 } 3141} 3142 3143static void expand_vec_sat(TCGType type, unsigned vece, TCGv_vec v0, 3144 TCGv_vec v1, TCGv_vec v2, TCGOpcode add_sub_opc) 3145{ 3146 TCGv_vec h1 = tcg_temp_new_vec(type); 3147 TCGv_vec h2 = tcg_temp_new_vec(type); 3148 TCGv_vec l1 = tcg_temp_new_vec(type); 3149 TCGv_vec l2 = tcg_temp_new_vec(type); 3150 3151 tcg_debug_assert (vece < MO_64); 3152 3153 /* Unpack with sign-extension. */ 3154 vec_gen_2(INDEX_op_s390_vuph_vec, type, vece, 3155 tcgv_vec_arg(h1), tcgv_vec_arg(v1)); 3156 vec_gen_2(INDEX_op_s390_vuph_vec, type, vece, 3157 tcgv_vec_arg(h2), tcgv_vec_arg(v2)); 3158 3159 vec_gen_2(INDEX_op_s390_vupl_vec, type, vece, 3160 tcgv_vec_arg(l1), tcgv_vec_arg(v1)); 3161 vec_gen_2(INDEX_op_s390_vupl_vec, type, vece, 3162 tcgv_vec_arg(l2), tcgv_vec_arg(v2)); 3163 3164 /* Arithmetic on a wider element size. */ 3165 vec_gen_3(add_sub_opc, type, vece + 1, tcgv_vec_arg(h1), 3166 tcgv_vec_arg(h1), tcgv_vec_arg(h2)); 3167 vec_gen_3(add_sub_opc, type, vece + 1, tcgv_vec_arg(l1), 3168 tcgv_vec_arg(l1), tcgv_vec_arg(l2)); 3169 3170 /* Pack with saturation. */ 3171 vec_gen_3(INDEX_op_s390_vpks_vec, type, vece + 1, 3172 tcgv_vec_arg(v0), tcgv_vec_arg(h1), tcgv_vec_arg(l1)); 3173 3174 tcg_temp_free_vec(h1); 3175 tcg_temp_free_vec(h2); 3176 tcg_temp_free_vec(l1); 3177 tcg_temp_free_vec(l2); 3178} 3179 3180void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, 3181 TCGArg a0, ...) 3182{ 3183 va_list va; 3184 TCGv_vec v0, v1, v2, t0; 3185 3186 va_start(va, a0); 3187 v0 = temp_tcgv_vec(arg_temp(a0)); 3188 v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); 3189 v2 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); 3190 3191 switch (opc) { 3192 case INDEX_op_rotrv_vec: 3193 t0 = tcg_temp_new_vec(type); 3194 tcg_gen_neg_vec(vece, t0, v2); 3195 tcg_gen_rotlv_vec(vece, v0, v1, t0); 3196 tcg_temp_free_vec(t0); 3197 break; 3198 3199 case INDEX_op_ssadd_vec: 3200 expand_vec_sat(type, vece, v0, v1, v2, INDEX_op_add_vec); 3201 break; 3202 case INDEX_op_sssub_vec: 3203 expand_vec_sat(type, vece, v0, v1, v2, INDEX_op_sub_vec); 3204 break; 3205 3206 default: 3207 g_assert_not_reached(); 3208 } 3209 va_end(va); 3210} 3211 3212static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) 3213{ 3214 switch (op) { 3215 case INDEX_op_goto_ptr: 3216 return C_O0_I1(r); 3217 3218 case INDEX_op_ld8u_i32: 3219 case INDEX_op_ld8u_i64: 3220 case INDEX_op_ld8s_i32: 3221 case INDEX_op_ld8s_i64: 3222 case INDEX_op_ld16u_i32: 3223 case INDEX_op_ld16u_i64: 3224 case INDEX_op_ld16s_i32: 3225 case INDEX_op_ld16s_i64: 3226 case INDEX_op_ld_i32: 3227 case INDEX_op_ld32u_i64: 3228 case INDEX_op_ld32s_i64: 3229 case INDEX_op_ld_i64: 3230 return C_O1_I1(r, r); 3231 3232 case INDEX_op_st8_i32: 3233 case INDEX_op_st8_i64: 3234 case INDEX_op_st16_i32: 3235 case INDEX_op_st16_i64: 3236 case INDEX_op_st_i32: 3237 case INDEX_op_st32_i64: 3238 case INDEX_op_st_i64: 3239 return C_O0_I2(r, r); 3240 3241 case INDEX_op_add_i32: 3242 case INDEX_op_add_i64: 3243 case INDEX_op_shl_i64: 3244 case INDEX_op_shr_i64: 3245 case INDEX_op_sar_i64: 3246 case INDEX_op_rotl_i32: 3247 case INDEX_op_rotl_i64: 3248 case INDEX_op_rotr_i32: 3249 case INDEX_op_rotr_i64: 3250 return C_O1_I2(r, r, ri); 3251 case INDEX_op_setcond_i32: 3252 case INDEX_op_negsetcond_i32: 3253 case INDEX_op_setcond_i64: 3254 case INDEX_op_negsetcond_i64: 3255 return C_O1_I2(r, r, rC); 3256 3257 case INDEX_op_clz_i64: 3258 return C_O1_I2(r, r, rI); 3259 3260 case INDEX_op_sub_i32: 3261 case INDEX_op_sub_i64: 3262 case INDEX_op_and_i32: 3263 case INDEX_op_or_i32: 3264 case INDEX_op_xor_i32: 3265 return C_O1_I2(r, r, ri); 3266 case INDEX_op_and_i64: 3267 return C_O1_I2(r, r, rNKR); 3268 case INDEX_op_or_i64: 3269 case INDEX_op_xor_i64: 3270 return C_O1_I2(r, r, rK); 3271 3272 case INDEX_op_andc_i32: 3273 case INDEX_op_orc_i32: 3274 case INDEX_op_eqv_i32: 3275 return C_O1_I2(r, r, ri); 3276 case INDEX_op_andc_i64: 3277 return C_O1_I2(r, r, rKR); 3278 case INDEX_op_orc_i64: 3279 case INDEX_op_eqv_i64: 3280 return C_O1_I2(r, r, rNK); 3281 3282 case INDEX_op_nand_i32: 3283 case INDEX_op_nand_i64: 3284 case INDEX_op_nor_i32: 3285 case INDEX_op_nor_i64: 3286 return C_O1_I2(r, r, r); 3287 3288 case INDEX_op_mul_i32: 3289 return (HAVE_FACILITY(MISC_INSN_EXT2) 3290 ? C_O1_I2(r, r, ri) 3291 : C_O1_I2(r, 0, ri)); 3292 case INDEX_op_mul_i64: 3293 return (HAVE_FACILITY(MISC_INSN_EXT2) 3294 ? C_O1_I2(r, r, rJ) 3295 : C_O1_I2(r, 0, rJ)); 3296 3297 case INDEX_op_shl_i32: 3298 case INDEX_op_shr_i32: 3299 case INDEX_op_sar_i32: 3300 return C_O1_I2(r, r, ri); 3301 3302 case INDEX_op_brcond_i32: 3303 return C_O0_I2(r, ri); 3304 case INDEX_op_brcond_i64: 3305 return C_O0_I2(r, rC); 3306 3307 case INDEX_op_bswap16_i32: 3308 case INDEX_op_bswap16_i64: 3309 case INDEX_op_bswap32_i32: 3310 case INDEX_op_bswap32_i64: 3311 case INDEX_op_bswap64_i64: 3312 case INDEX_op_neg_i32: 3313 case INDEX_op_neg_i64: 3314 case INDEX_op_not_i32: 3315 case INDEX_op_not_i64: 3316 case INDEX_op_ext8s_i32: 3317 case INDEX_op_ext8s_i64: 3318 case INDEX_op_ext8u_i32: 3319 case INDEX_op_ext8u_i64: 3320 case INDEX_op_ext16s_i32: 3321 case INDEX_op_ext16s_i64: 3322 case INDEX_op_ext16u_i32: 3323 case INDEX_op_ext16u_i64: 3324 case INDEX_op_ext32s_i64: 3325 case INDEX_op_ext32u_i64: 3326 case INDEX_op_ext_i32_i64: 3327 case INDEX_op_extu_i32_i64: 3328 case INDEX_op_extract_i32: 3329 case INDEX_op_extract_i64: 3330 case INDEX_op_ctpop_i32: 3331 case INDEX_op_ctpop_i64: 3332 return C_O1_I1(r, r); 3333 3334 case INDEX_op_qemu_ld_a32_i32: 3335 case INDEX_op_qemu_ld_a64_i32: 3336 case INDEX_op_qemu_ld_a32_i64: 3337 case INDEX_op_qemu_ld_a64_i64: 3338 return C_O1_I1(r, r); 3339 case INDEX_op_qemu_st_a32_i64: 3340 case INDEX_op_qemu_st_a64_i64: 3341 case INDEX_op_qemu_st_a32_i32: 3342 case INDEX_op_qemu_st_a64_i32: 3343 return C_O0_I2(r, r); 3344 case INDEX_op_qemu_ld_a32_i128: 3345 case INDEX_op_qemu_ld_a64_i128: 3346 return C_O2_I1(o, m, r); 3347 case INDEX_op_qemu_st_a32_i128: 3348 case INDEX_op_qemu_st_a64_i128: 3349 return C_O0_I3(o, m, r); 3350 3351 case INDEX_op_deposit_i32: 3352 case INDEX_op_deposit_i64: 3353 return C_O1_I2(r, rZ, r); 3354 3355 case INDEX_op_movcond_i32: 3356 return C_O1_I4(r, r, ri, rI, r); 3357 case INDEX_op_movcond_i64: 3358 return C_O1_I4(r, r, rC, rI, r); 3359 3360 case INDEX_op_div2_i32: 3361 case INDEX_op_div2_i64: 3362 case INDEX_op_divu2_i32: 3363 case INDEX_op_divu2_i64: 3364 return C_O2_I3(o, m, 0, 1, r); 3365 3366 case INDEX_op_mulu2_i64: 3367 return C_O2_I2(o, m, 0, r); 3368 case INDEX_op_muls2_i64: 3369 return C_O2_I2(o, m, r, r); 3370 3371 case INDEX_op_add2_i32: 3372 case INDEX_op_sub2_i32: 3373 return C_N1_O1_I4(r, r, 0, 1, ri, r); 3374 3375 case INDEX_op_add2_i64: 3376 case INDEX_op_sub2_i64: 3377 return C_N1_O1_I4(r, r, 0, 1, rJU, r); 3378 3379 case INDEX_op_st_vec: 3380 return C_O0_I2(v, r); 3381 case INDEX_op_ld_vec: 3382 case INDEX_op_dupm_vec: 3383 return C_O1_I1(v, r); 3384 case INDEX_op_dup_vec: 3385 return C_O1_I1(v, vr); 3386 case INDEX_op_abs_vec: 3387 case INDEX_op_neg_vec: 3388 case INDEX_op_not_vec: 3389 case INDEX_op_rotli_vec: 3390 case INDEX_op_sari_vec: 3391 case INDEX_op_shli_vec: 3392 case INDEX_op_shri_vec: 3393 case INDEX_op_s390_vuph_vec: 3394 case INDEX_op_s390_vupl_vec: 3395 return C_O1_I1(v, v); 3396 case INDEX_op_add_vec: 3397 case INDEX_op_sub_vec: 3398 case INDEX_op_and_vec: 3399 case INDEX_op_andc_vec: 3400 case INDEX_op_or_vec: 3401 case INDEX_op_orc_vec: 3402 case INDEX_op_xor_vec: 3403 case INDEX_op_nand_vec: 3404 case INDEX_op_nor_vec: 3405 case INDEX_op_eqv_vec: 3406 case INDEX_op_cmp_vec: 3407 case INDEX_op_mul_vec: 3408 case INDEX_op_rotlv_vec: 3409 case INDEX_op_rotrv_vec: 3410 case INDEX_op_shlv_vec: 3411 case INDEX_op_shrv_vec: 3412 case INDEX_op_sarv_vec: 3413 case INDEX_op_smax_vec: 3414 case INDEX_op_smin_vec: 3415 case INDEX_op_umax_vec: 3416 case INDEX_op_umin_vec: 3417 case INDEX_op_s390_vpks_vec: 3418 return C_O1_I2(v, v, v); 3419 case INDEX_op_rotls_vec: 3420 case INDEX_op_shls_vec: 3421 case INDEX_op_shrs_vec: 3422 case INDEX_op_sars_vec: 3423 return C_O1_I2(v, v, r); 3424 case INDEX_op_bitsel_vec: 3425 return C_O1_I3(v, v, v, v); 3426 case INDEX_op_cmpsel_vec: 3427 return (TCG_TARGET_HAS_orc_vec 3428 ? C_O1_I4(v, v, v, vZM, v) 3429 : C_O1_I4(v, v, v, vZ, v)); 3430 3431 default: 3432 g_assert_not_reached(); 3433 } 3434} 3435 3436/* 3437 * Mainline glibc added HWCAP_S390_VX before it was kernel abi. 3438 * Some distros have fixed this up locally, others have not. 3439 */ 3440#ifndef HWCAP_S390_VXRS 3441#define HWCAP_S390_VXRS 2048 3442#endif 3443 3444static void query_s390_facilities(void) 3445{ 3446 unsigned long hwcap = qemu_getauxval(AT_HWCAP); 3447 const char *which; 3448 3449 /* Is STORE FACILITY LIST EXTENDED available? Honestly, I believe this 3450 is present on all 64-bit systems, but let's check for it anyway. */ 3451 if (hwcap & HWCAP_S390_STFLE) { 3452 register int r0 __asm__("0") = ARRAY_SIZE(s390_facilities) - 1; 3453 register void *r1 __asm__("1") = s390_facilities; 3454 3455 /* stfle 0(%r1) */ 3456 asm volatile(".word 0xb2b0,0x1000" 3457 : "=r"(r0) : "r"(r0), "r"(r1) : "memory", "cc"); 3458 } 3459 3460 /* 3461 * Use of vector registers requires os support beyond the facility bit. 3462 * If the kernel does not advertise support, disable the facility bits. 3463 * There is nothing else we currently care about in the 3rd word, so 3464 * disable VECTOR with one store. 3465 */ 3466 if (!(hwcap & HWCAP_S390_VXRS)) { 3467 s390_facilities[2] = 0; 3468 } 3469 3470 /* 3471 * Minimum supported cpu revision is z196. 3472 * Check for all required facilities. 3473 * ZARCH_ACTIVE is done via preprocessor check for 64-bit. 3474 */ 3475 if (!HAVE_FACILITY(LONG_DISP)) { 3476 which = "long-displacement"; 3477 goto fail; 3478 } 3479 if (!HAVE_FACILITY(EXT_IMM)) { 3480 which = "extended-immediate"; 3481 goto fail; 3482 } 3483 if (!HAVE_FACILITY(GEN_INST_EXT)) { 3484 which = "general-instructions-extension"; 3485 goto fail; 3486 } 3487 /* 3488 * Facility 45 is a big bin that contains: distinct-operands, 3489 * fast-BCR-serialization, high-word, population-count, 3490 * interlocked-access-1, and load/store-on-condition-1 3491 */ 3492 if (!HAVE_FACILITY(45)) { 3493 which = "45"; 3494 goto fail; 3495 } 3496 return; 3497 3498 fail: 3499 error_report("%s: missing required facility %s", __func__, which); 3500 exit(EXIT_FAILURE); 3501} 3502 3503static void tcg_target_init(TCGContext *s) 3504{ 3505 query_s390_facilities(); 3506 3507 tcg_target_available_regs[TCG_TYPE_I32] = 0xffff; 3508 tcg_target_available_regs[TCG_TYPE_I64] = 0xffff; 3509 if (HAVE_FACILITY(VECTOR)) { 3510 tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull; 3511 tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull; 3512 } 3513 3514 tcg_target_call_clobber_regs = 0; 3515 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0); 3516 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1); 3517 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2); 3518 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3); 3519 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R4); 3520 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R5); 3521 /* The r6 register is technically call-saved, but it's also a parameter 3522 register, so it can get killed by setup for the qemu_st helper. */ 3523 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R6); 3524 /* The return register can be considered call-clobbered. */ 3525 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14); 3526 3527 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); 3528 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); 3529 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V2); 3530 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V3); 3531 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V4); 3532 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V5); 3533 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V6); 3534 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V7); 3535 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V16); 3536 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V17); 3537 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V18); 3538 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V19); 3539 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V20); 3540 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V21); 3541 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V22); 3542 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V23); 3543 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V24); 3544 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V25); 3545 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V26); 3546 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V27); 3547 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V28); 3548 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V29); 3549 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V30); 3550 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V31); 3551 3552 s->reserved_regs = 0; 3553 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); 3554 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP0); 3555 /* XXX many insns can't be used with R0, so we better avoid it for now */ 3556 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); 3557 tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); 3558} 3559 3560#define FRAME_SIZE ((int)(TCG_TARGET_CALL_STACK_OFFSET \ 3561 + TCG_STATIC_CALL_ARGS_SIZE \ 3562 + CPU_TEMP_BUF_NLONGS * sizeof(long))) 3563 3564static void tcg_target_qemu_prologue(TCGContext *s) 3565{ 3566 /* stmg %r6,%r15,48(%r15) (save registers) */ 3567 tcg_out_insn(s, RXY, STMG, TCG_REG_R6, TCG_REG_R15, TCG_REG_R15, 48); 3568 3569 /* aghi %r15,-frame_size */ 3570 tcg_out_insn(s, RI, AGHI, TCG_REG_R15, -FRAME_SIZE); 3571 3572 tcg_set_frame(s, TCG_REG_CALL_STACK, 3573 TCG_STATIC_CALL_ARGS_SIZE + TCG_TARGET_CALL_STACK_OFFSET, 3574 CPU_TEMP_BUF_NLONGS * sizeof(long)); 3575 3576 if (!tcg_use_softmmu && guest_base >= 0x80000) { 3577 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); 3578 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 3579 } 3580 3581 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 3582 3583 /* br %r3 (go to TB) */ 3584 tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, tcg_target_call_iarg_regs[1]); 3585 3586 /* 3587 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 3588 * and fall through to the rest of the epilogue. 3589 */ 3590 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 3591 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, 0); 3592 3593 /* TB epilogue */ 3594 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 3595 3596 /* lmg %r6,%r15,fs+48(%r15) (restore registers) */ 3597 tcg_out_insn(s, RXY, LMG, TCG_REG_R6, TCG_REG_R15, TCG_REG_R15, 3598 FRAME_SIZE + 48); 3599 3600 /* br %r14 (return) */ 3601 tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_R14); 3602} 3603 3604static void tcg_out_tb_start(TCGContext *s) 3605{ 3606 /* nothing to do */ 3607} 3608 3609static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 3610{ 3611 memset(p, 0x07, count * sizeof(tcg_insn_unit)); 3612} 3613 3614typedef struct { 3615 DebugFrameHeader h; 3616 uint8_t fde_def_cfa[4]; 3617 uint8_t fde_reg_ofs[18]; 3618} DebugFrame; 3619 3620/* We're expecting a 2 byte uleb128 encoded value. */ 3621QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14)); 3622 3623#define ELF_HOST_MACHINE EM_S390 3624 3625static const DebugFrame debug_frame = { 3626 .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ 3627 .h.cie.id = -1, 3628 .h.cie.version = 1, 3629 .h.cie.code_align = 1, 3630 .h.cie.data_align = 8, /* sleb128 8 */ 3631 .h.cie.return_column = TCG_REG_R14, 3632 3633 /* Total FDE size does not include the "len" member. */ 3634 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 3635 3636 .fde_def_cfa = { 3637 12, TCG_REG_CALL_STACK, /* DW_CFA_def_cfa %r15, ... */ 3638 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 3639 (FRAME_SIZE >> 7) 3640 }, 3641 .fde_reg_ofs = { 3642 0x86, 6, /* DW_CFA_offset, %r6, 48 */ 3643 0x87, 7, /* DW_CFA_offset, %r7, 56 */ 3644 0x88, 8, /* DW_CFA_offset, %r8, 64 */ 3645 0x89, 9, /* DW_CFA_offset, %r92, 72 */ 3646 0x8a, 10, /* DW_CFA_offset, %r10, 80 */ 3647 0x8b, 11, /* DW_CFA_offset, %r11, 88 */ 3648 0x8c, 12, /* DW_CFA_offset, %r12, 96 */ 3649 0x8d, 13, /* DW_CFA_offset, %r13, 104 */ 3650 0x8e, 14, /* DW_CFA_offset, %r14, 112 */ 3651 } 3652}; 3653 3654void tcg_register_jit(const void *buf, size_t buf_size) 3655{ 3656 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 3657} 3658