1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2009 Ulrich Hecht <uli@suse.de> 5 * Copyright (c) 2009 Alexander Graf <agraf@suse.de> 6 * Copyright (c) 2010 Richard Henderson <rth@twiddle.net> 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27#include "elf.h" 28 29/* Used for function call generation. */ 30#define TCG_TARGET_STACK_ALIGN 8 31#define TCG_TARGET_CALL_STACK_OFFSET 160 32#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EXTEND 33#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL 34#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_BY_REF 35#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF 36 37#define TCG_CT_CONST_S16 (1 << 8) 38#define TCG_CT_CONST_S32 (1 << 9) 39#define TCG_CT_CONST_U32 (1 << 10) 40#define TCG_CT_CONST_ZERO (1 << 11) 41#define TCG_CT_CONST_P32 (1 << 12) 42#define TCG_CT_CONST_INV (1 << 13) 43#define TCG_CT_CONST_INVRISBG (1 << 14) 44#define TCG_CT_CONST_CMP (1 << 15) 45#define TCG_CT_CONST_M1 (1 << 16) 46 47#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 16) 48#define ALL_VECTOR_REGS MAKE_64BIT_MASK(32, 32) 49 50/* Several places within the instruction set 0 means "no register" 51 rather than TCG_REG_R0. */ 52#define TCG_REG_NONE 0 53 54/* A scratch register that may be be used throughout the backend. */ 55#define TCG_TMP0 TCG_REG_R1 56#define TCG_VEC_TMP0 TCG_REG_V31 57 58#define TCG_GUEST_BASE_REG TCG_REG_R13 59 60/* All of the following instructions are prefixed with their instruction 61 format, and are defined as 8- or 16-bit quantities, even when the two 62 halves of the 16-bit quantity may appear 32 bits apart in the insn. 63 This makes it easy to copy the values from the tables in Appendix B. */ 64typedef enum S390Opcode { 65 RIL_AFI = 0xc209, 66 RIL_AGFI = 0xc208, 67 RIL_ALFI = 0xc20b, 68 RIL_ALGFI = 0xc20a, 69 RIL_BRASL = 0xc005, 70 RIL_BRCL = 0xc004, 71 RIL_CFI = 0xc20d, 72 RIL_CGFI = 0xc20c, 73 RIL_CLFI = 0xc20f, 74 RIL_CLGFI = 0xc20e, 75 RIL_CLRL = 0xc60f, 76 RIL_CLGRL = 0xc60a, 77 RIL_CRL = 0xc60d, 78 RIL_CGRL = 0xc608, 79 RIL_IIHF = 0xc008, 80 RIL_IILF = 0xc009, 81 RIL_LARL = 0xc000, 82 RIL_LGFI = 0xc001, 83 RIL_LGRL = 0xc408, 84 RIL_LLIHF = 0xc00e, 85 RIL_LLILF = 0xc00f, 86 RIL_LRL = 0xc40d, 87 RIL_MSFI = 0xc201, 88 RIL_MSGFI = 0xc200, 89 RIL_NIHF = 0xc00a, 90 RIL_NILF = 0xc00b, 91 RIL_OIHF = 0xc00c, 92 RIL_OILF = 0xc00d, 93 RIL_SLFI = 0xc205, 94 RIL_SLGFI = 0xc204, 95 RIL_XIHF = 0xc006, 96 RIL_XILF = 0xc007, 97 98 RI_AGHI = 0xa70b, 99 RI_AHI = 0xa70a, 100 RI_BRC = 0xa704, 101 RI_CHI = 0xa70e, 102 RI_CGHI = 0xa70f, 103 RI_IIHH = 0xa500, 104 RI_IIHL = 0xa501, 105 RI_IILH = 0xa502, 106 RI_IILL = 0xa503, 107 RI_LGHI = 0xa709, 108 RI_LLIHH = 0xa50c, 109 RI_LLIHL = 0xa50d, 110 RI_LLILH = 0xa50e, 111 RI_LLILL = 0xa50f, 112 RI_MGHI = 0xa70d, 113 RI_MHI = 0xa70c, 114 RI_NIHH = 0xa504, 115 RI_NIHL = 0xa505, 116 RI_NILH = 0xa506, 117 RI_NILL = 0xa507, 118 RI_OIHH = 0xa508, 119 RI_OIHL = 0xa509, 120 RI_OILH = 0xa50a, 121 RI_OILL = 0xa50b, 122 RI_TMLL = 0xa701, 123 RI_TMLH = 0xa700, 124 RI_TMHL = 0xa703, 125 RI_TMHH = 0xa702, 126 127 RIEb_CGRJ = 0xec64, 128 RIEb_CLGRJ = 0xec65, 129 RIEb_CLRJ = 0xec77, 130 RIEb_CRJ = 0xec76, 131 132 RIEc_CGIJ = 0xec7c, 133 RIEc_CIJ = 0xec7e, 134 RIEc_CLGIJ = 0xec7d, 135 RIEc_CLIJ = 0xec7f, 136 137 RIEf_RISBG = 0xec55, 138 139 RIEg_LOCGHI = 0xec46, 140 141 RRE_AGR = 0xb908, 142 RRE_ALGR = 0xb90a, 143 RRE_ALCR = 0xb998, 144 RRE_ALCGR = 0xb988, 145 RRE_ALGFR = 0xb91a, 146 RRE_CGR = 0xb920, 147 RRE_CLGR = 0xb921, 148 RRE_DLGR = 0xb987, 149 RRE_DLR = 0xb997, 150 RRE_DSGFR = 0xb91d, 151 RRE_DSGR = 0xb90d, 152 RRE_FLOGR = 0xb983, 153 RRE_LGBR = 0xb906, 154 RRE_LCGR = 0xb903, 155 RRE_LGFR = 0xb914, 156 RRE_LGHR = 0xb907, 157 RRE_LGR = 0xb904, 158 RRE_LLGCR = 0xb984, 159 RRE_LLGFR = 0xb916, 160 RRE_LLGHR = 0xb985, 161 RRE_LRVR = 0xb91f, 162 RRE_LRVGR = 0xb90f, 163 RRE_LTGR = 0xb902, 164 RRE_MLGR = 0xb986, 165 RRE_MSGR = 0xb90c, 166 RRE_MSR = 0xb252, 167 RRE_NGR = 0xb980, 168 RRE_OGR = 0xb981, 169 RRE_SGR = 0xb909, 170 RRE_SLGR = 0xb90b, 171 RRE_SLBR = 0xb999, 172 RRE_SLBGR = 0xb989, 173 RRE_XGR = 0xb982, 174 175 RRFa_MGRK = 0xb9ec, 176 RRFa_MSRKC = 0xb9fd, 177 RRFa_MSGRKC = 0xb9ed, 178 RRFa_NCRK = 0xb9f5, 179 RRFa_NCGRK = 0xb9e5, 180 RRFa_NNRK = 0xb974, 181 RRFa_NNGRK = 0xb964, 182 RRFa_NORK = 0xb976, 183 RRFa_NOGRK = 0xb966, 184 RRFa_NRK = 0xb9f4, 185 RRFa_NGRK = 0xb9e4, 186 RRFa_NXRK = 0xb977, 187 RRFa_NXGRK = 0xb967, 188 RRFa_OCRK = 0xb975, 189 RRFa_OCGRK = 0xb965, 190 RRFa_ORK = 0xb9f6, 191 RRFa_OGRK = 0xb9e6, 192 RRFa_SRK = 0xb9f9, 193 RRFa_SGRK = 0xb9e9, 194 RRFa_SLRK = 0xb9fb, 195 RRFa_SLGRK = 0xb9eb, 196 RRFa_XRK = 0xb9f7, 197 RRFa_XGRK = 0xb9e7, 198 199 RRFam_SELGR = 0xb9e3, 200 201 RRFc_LOCR = 0xb9f2, 202 RRFc_LOCGR = 0xb9e2, 203 RRFc_POPCNT = 0xb9e1, 204 205 RR_AR = 0x1a, 206 RR_ALR = 0x1e, 207 RR_BASR = 0x0d, 208 RR_BCR = 0x07, 209 RR_CLR = 0x15, 210 RR_CR = 0x19, 211 RR_DR = 0x1d, 212 RR_LCR = 0x13, 213 RR_LR = 0x18, 214 RR_LTR = 0x12, 215 RR_NR = 0x14, 216 RR_OR = 0x16, 217 RR_SR = 0x1b, 218 RR_SLR = 0x1f, 219 RR_XR = 0x17, 220 221 RSY_RLL = 0xeb1d, 222 RSY_RLLG = 0xeb1c, 223 RSY_SLLG = 0xeb0d, 224 RSY_SLLK = 0xebdf, 225 RSY_SRAG = 0xeb0a, 226 RSY_SRAK = 0xebdc, 227 RSY_SRLG = 0xeb0c, 228 RSY_SRLK = 0xebde, 229 230 RS_SLL = 0x89, 231 RS_SRA = 0x8a, 232 RS_SRL = 0x88, 233 234 RXY_AG = 0xe308, 235 RXY_AY = 0xe35a, 236 RXY_CG = 0xe320, 237 RXY_CLG = 0xe321, 238 RXY_CLY = 0xe355, 239 RXY_CY = 0xe359, 240 RXY_LAY = 0xe371, 241 RXY_LB = 0xe376, 242 RXY_LG = 0xe304, 243 RXY_LGB = 0xe377, 244 RXY_LGF = 0xe314, 245 RXY_LGH = 0xe315, 246 RXY_LHY = 0xe378, 247 RXY_LLGC = 0xe390, 248 RXY_LLGF = 0xe316, 249 RXY_LLGH = 0xe391, 250 RXY_LMG = 0xeb04, 251 RXY_LPQ = 0xe38f, 252 RXY_LRV = 0xe31e, 253 RXY_LRVG = 0xe30f, 254 RXY_LRVH = 0xe31f, 255 RXY_LY = 0xe358, 256 RXY_NG = 0xe380, 257 RXY_OG = 0xe381, 258 RXY_STCY = 0xe372, 259 RXY_STG = 0xe324, 260 RXY_STHY = 0xe370, 261 RXY_STMG = 0xeb24, 262 RXY_STPQ = 0xe38e, 263 RXY_STRV = 0xe33e, 264 RXY_STRVG = 0xe32f, 265 RXY_STRVH = 0xe33f, 266 RXY_STY = 0xe350, 267 RXY_XG = 0xe382, 268 269 RX_A = 0x5a, 270 RX_C = 0x59, 271 RX_L = 0x58, 272 RX_LA = 0x41, 273 RX_LH = 0x48, 274 RX_ST = 0x50, 275 RX_STC = 0x42, 276 RX_STH = 0x40, 277 278 VRIa_VGBM = 0xe744, 279 VRIa_VREPI = 0xe745, 280 VRIb_VGM = 0xe746, 281 VRIc_VREP = 0xe74d, 282 283 VRRa_VLC = 0xe7de, 284 VRRa_VLP = 0xe7df, 285 VRRa_VLR = 0xe756, 286 VRRc_VA = 0xe7f3, 287 VRRc_VCEQ = 0xe7f8, /* we leave the m5 cs field 0 */ 288 VRRc_VCH = 0xe7fb, /* " */ 289 VRRc_VCHL = 0xe7f9, /* " */ 290 VRRc_VERLLV = 0xe773, 291 VRRc_VESLV = 0xe770, 292 VRRc_VESRAV = 0xe77a, 293 VRRc_VESRLV = 0xe778, 294 VRRc_VML = 0xe7a2, 295 VRRc_VMN = 0xe7fe, 296 VRRc_VMNL = 0xe7fc, 297 VRRc_VMX = 0xe7ff, 298 VRRc_VMXL = 0xe7fd, 299 VRRc_VN = 0xe768, 300 VRRc_VNC = 0xe769, 301 VRRc_VNN = 0xe76e, 302 VRRc_VNO = 0xe76b, 303 VRRc_VNX = 0xe76c, 304 VRRc_VO = 0xe76a, 305 VRRc_VOC = 0xe76f, 306 VRRc_VPKS = 0xe797, /* we leave the m5 cs field 0 */ 307 VRRc_VS = 0xe7f7, 308 VRRa_VUPH = 0xe7d7, 309 VRRa_VUPL = 0xe7d6, 310 VRRc_VX = 0xe76d, 311 VRRe_VSEL = 0xe78d, 312 VRRf_VLVGP = 0xe762, 313 314 VRSa_VERLL = 0xe733, 315 VRSa_VESL = 0xe730, 316 VRSa_VESRA = 0xe73a, 317 VRSa_VESRL = 0xe738, 318 VRSb_VLVG = 0xe722, 319 VRSc_VLGV = 0xe721, 320 321 VRX_VL = 0xe706, 322 VRX_VLLEZ = 0xe704, 323 VRX_VLREP = 0xe705, 324 VRX_VST = 0xe70e, 325 VRX_VSTEF = 0xe70b, 326 VRX_VSTEG = 0xe70a, 327 328 NOP = 0x0707, 329} S390Opcode; 330 331#ifdef CONFIG_DEBUG_TCG 332static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 333 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", 334 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", 335 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 336 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7", 337 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15", 338 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23", 339 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31", 340}; 341#endif 342 343/* Since R6 is a potential argument register, choose it last of the 344 call-saved registers. Likewise prefer the call-clobbered registers 345 in reverse order to maximize the chance of avoiding the arguments. */ 346static const int tcg_target_reg_alloc_order[] = { 347 /* Call saved registers. */ 348 TCG_REG_R13, 349 TCG_REG_R12, 350 TCG_REG_R11, 351 TCG_REG_R10, 352 TCG_REG_R9, 353 TCG_REG_R8, 354 TCG_REG_R7, 355 TCG_REG_R6, 356 /* Call clobbered registers. */ 357 TCG_REG_R14, 358 TCG_REG_R0, 359 TCG_REG_R1, 360 /* Argument registers, in reverse order of allocation. */ 361 TCG_REG_R5, 362 TCG_REG_R4, 363 TCG_REG_R3, 364 TCG_REG_R2, 365 366 /* V8-V15 are call saved, and omitted. */ 367 TCG_REG_V0, 368 TCG_REG_V1, 369 TCG_REG_V2, 370 TCG_REG_V3, 371 TCG_REG_V4, 372 TCG_REG_V5, 373 TCG_REG_V6, 374 TCG_REG_V7, 375 TCG_REG_V16, 376 TCG_REG_V17, 377 TCG_REG_V18, 378 TCG_REG_V19, 379 TCG_REG_V20, 380 TCG_REG_V21, 381 TCG_REG_V22, 382 TCG_REG_V23, 383 TCG_REG_V24, 384 TCG_REG_V25, 385 TCG_REG_V26, 386 TCG_REG_V27, 387 TCG_REG_V28, 388 TCG_REG_V29, 389 TCG_REG_V30, 390 TCG_REG_V31, 391}; 392 393static const int tcg_target_call_iarg_regs[] = { 394 TCG_REG_R2, 395 TCG_REG_R3, 396 TCG_REG_R4, 397 TCG_REG_R5, 398 TCG_REG_R6, 399}; 400 401static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 402{ 403 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 404 tcg_debug_assert(slot == 0); 405 return TCG_REG_R2; 406} 407 408#define S390_CC_EQ 8 409#define S390_CC_LT 4 410#define S390_CC_GT 2 411#define S390_CC_OV 1 412#define S390_CC_NE (S390_CC_LT | S390_CC_GT) 413#define S390_CC_LE (S390_CC_LT | S390_CC_EQ) 414#define S390_CC_GE (S390_CC_GT | S390_CC_EQ) 415#define S390_CC_NEVER 0 416#define S390_CC_ALWAYS 15 417 418#define S390_TM_EQ 8 /* CC == 0 */ 419#define S390_TM_NE 7 /* CC in {1,2,3} */ 420 421/* Condition codes that result from a COMPARE and COMPARE LOGICAL. */ 422static const uint8_t tcg_cond_to_s390_cond[16] = { 423 [TCG_COND_EQ] = S390_CC_EQ, 424 [TCG_COND_NE] = S390_CC_NE, 425 [TCG_COND_TSTEQ] = S390_CC_EQ, 426 [TCG_COND_TSTNE] = S390_CC_NE, 427 [TCG_COND_LT] = S390_CC_LT, 428 [TCG_COND_LE] = S390_CC_LE, 429 [TCG_COND_GT] = S390_CC_GT, 430 [TCG_COND_GE] = S390_CC_GE, 431 [TCG_COND_LTU] = S390_CC_LT, 432 [TCG_COND_LEU] = S390_CC_LE, 433 [TCG_COND_GTU] = S390_CC_GT, 434 [TCG_COND_GEU] = S390_CC_GE, 435}; 436 437/* Condition codes that result from a LOAD AND TEST. Here, we have no 438 unsigned instruction variation, however since the test is vs zero we 439 can re-map the outcomes appropriately. */ 440static const uint8_t tcg_cond_to_ltr_cond[16] = { 441 [TCG_COND_EQ] = S390_CC_EQ, 442 [TCG_COND_NE] = S390_CC_NE, 443 [TCG_COND_TSTEQ] = S390_CC_ALWAYS, 444 [TCG_COND_TSTNE] = S390_CC_NEVER, 445 [TCG_COND_LT] = S390_CC_LT, 446 [TCG_COND_LE] = S390_CC_LE, 447 [TCG_COND_GT] = S390_CC_GT, 448 [TCG_COND_GE] = S390_CC_GE, 449 [TCG_COND_LTU] = S390_CC_NEVER, 450 [TCG_COND_LEU] = S390_CC_EQ, 451 [TCG_COND_GTU] = S390_CC_NE, 452 [TCG_COND_GEU] = S390_CC_ALWAYS, 453}; 454 455static const tcg_insn_unit *tb_ret_addr; 456uint64_t s390_facilities[3]; 457 458static inline bool is_general_reg(TCGReg r) 459{ 460 return r <= TCG_REG_R15; 461} 462 463static inline bool is_vector_reg(TCGReg r) 464{ 465 return r >= TCG_REG_V0 && r <= TCG_REG_V31; 466} 467 468static bool patch_reloc(tcg_insn_unit *src_rw, int type, 469 intptr_t value, intptr_t addend) 470{ 471 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 472 intptr_t pcrel2; 473 uint32_t old; 474 475 value += addend; 476 pcrel2 = (tcg_insn_unit *)value - src_rx; 477 478 switch (type) { 479 case R_390_PC16DBL: 480 if (pcrel2 == (int16_t)pcrel2) { 481 tcg_patch16(src_rw, pcrel2); 482 return true; 483 } 484 break; 485 case R_390_PC32DBL: 486 if (pcrel2 == (int32_t)pcrel2) { 487 tcg_patch32(src_rw, pcrel2); 488 return true; 489 } 490 break; 491 case R_390_20: 492 if (value == sextract64(value, 0, 20)) { 493 old = *(uint32_t *)src_rw & 0xf00000ff; 494 old |= ((value & 0xfff) << 16) | ((value & 0xff000) >> 4); 495 tcg_patch32(src_rw, old); 496 return true; 497 } 498 break; 499 default: 500 g_assert_not_reached(); 501 } 502 return false; 503} 504 505static int is_const_p16(uint64_t val) 506{ 507 for (int i = 0; i < 4; ++i) { 508 uint64_t mask = 0xffffull << (i * 16); 509 if ((val & ~mask) == 0) { 510 return i; 511 } 512 } 513 return -1; 514} 515 516static int is_const_p32(uint64_t val) 517{ 518 if ((val & 0xffffffff00000000ull) == 0) { 519 return 0; 520 } 521 if ((val & 0x00000000ffffffffull) == 0) { 522 return 1; 523 } 524 return -1; 525} 526 527/* 528 * Accept bit patterns like these: 529 * 0....01....1 530 * 1....10....0 531 * 1..10..01..1 532 * 0..01..10..0 533 * Copied from gcc sources. 534 */ 535static bool risbg_mask(uint64_t c) 536{ 537 uint64_t lsb; 538 /* We don't change the number of transitions by inverting, 539 so make sure we start with the LSB zero. */ 540 if (c & 1) { 541 c = ~c; 542 } 543 /* Reject all zeros or all ones. */ 544 if (c == 0) { 545 return false; 546 } 547 /* Find the first transition. */ 548 lsb = c & -c; 549 /* Invert to look for a second transition. */ 550 c = ~c; 551 /* Erase the first transition. */ 552 c &= -lsb; 553 /* Find the second transition, if any. */ 554 lsb = c & -c; 555 /* Match if all the bits are 1's, or if c is zero. */ 556 return c == -lsb; 557} 558 559/* Test if a constant matches the constraint. */ 560static bool tcg_target_const_match(int64_t val, int ct, 561 TCGType type, TCGCond cond, int vece) 562{ 563 uint64_t uval = val; 564 565 if (ct & TCG_CT_CONST) { 566 return true; 567 } 568 if (type == TCG_TYPE_I32) { 569 uval = (uint32_t)val; 570 val = (int32_t)val; 571 } 572 573 if (ct & TCG_CT_CONST_CMP) { 574 if (is_tst_cond(cond)) { 575 if (is_const_p16(uval) >= 0) { 576 return true; /* TMxx */ 577 } 578 if (risbg_mask(uval)) { 579 return true; /* RISBG */ 580 } 581 return false; 582 } 583 584 if (type == TCG_TYPE_I32) { 585 return true; 586 } 587 588 switch (cond) { 589 case TCG_COND_EQ: 590 case TCG_COND_NE: 591 ct |= TCG_CT_CONST_S32 | TCG_CT_CONST_U32; /* CGFI or CLGFI */ 592 break; 593 case TCG_COND_LT: 594 case TCG_COND_GE: 595 case TCG_COND_LE: 596 case TCG_COND_GT: 597 ct |= TCG_CT_CONST_S32; /* CGFI */ 598 break; 599 case TCG_COND_LTU: 600 case TCG_COND_GEU: 601 case TCG_COND_LEU: 602 case TCG_COND_GTU: 603 ct |= TCG_CT_CONST_U32; /* CLGFI */ 604 break; 605 case TCG_COND_TSTNE: 606 case TCG_COND_TSTEQ: 607 /* checked above, fallthru */ 608 default: 609 g_assert_not_reached(); 610 } 611 } 612 613 if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) { 614 return true; 615 } 616 if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) { 617 return true; 618 } 619 if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) { 620 return true; 621 } 622 if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 623 return true; 624 } 625 if ((ct & TCG_CT_CONST_M1) && val == -1) { 626 return true; 627 } 628 629 if (ct & TCG_CT_CONST_INV) { 630 val = ~val; 631 } 632 if ((ct & TCG_CT_CONST_P32) && is_const_p32(val) >= 0) { 633 return true; 634 } 635 if ((ct & TCG_CT_CONST_INVRISBG) && risbg_mask(~val)) { 636 return true; 637 } 638 return false; 639} 640 641/* Emit instructions according to the given instruction format. */ 642 643static void tcg_out_insn_RR(TCGContext *s, S390Opcode op, TCGReg r1, TCGReg r2) 644{ 645 tcg_out16(s, (op << 8) | (r1 << 4) | r2); 646} 647 648static void tcg_out_insn_RRE(TCGContext *s, S390Opcode op, 649 TCGReg r1, TCGReg r2) 650{ 651 tcg_out32(s, (op << 16) | (r1 << 4) | r2); 652} 653 654/* RRF-a without the m4 field */ 655static void tcg_out_insn_RRFa(TCGContext *s, S390Opcode op, 656 TCGReg r1, TCGReg r2, TCGReg r3) 657{ 658 tcg_out32(s, (op << 16) | (r3 << 12) | (r1 << 4) | r2); 659} 660 661/* RRF-a with the m4 field */ 662static void tcg_out_insn_RRFam(TCGContext *s, S390Opcode op, 663 TCGReg r1, TCGReg r2, TCGReg r3, int m4) 664{ 665 tcg_out32(s, (op << 16) | (r3 << 12) | (m4 << 8) | (r1 << 4) | r2); 666} 667 668static void tcg_out_insn_RRFc(TCGContext *s, S390Opcode op, 669 TCGReg r1, TCGReg r2, int m3) 670{ 671 tcg_out32(s, (op << 16) | (m3 << 12) | (r1 << 4) | r2); 672} 673 674static void tcg_out_insn_RI(TCGContext *s, S390Opcode op, TCGReg r1, int i2) 675{ 676 tcg_out32(s, (op << 16) | (r1 << 20) | (i2 & 0xffff)); 677} 678 679static void tcg_out_insn_RIEg(TCGContext *s, S390Opcode op, TCGReg r1, 680 int i2, int m3) 681{ 682 tcg_out16(s, (op & 0xff00) | (r1 << 4) | m3); 683 tcg_out32(s, (i2 << 16) | (op & 0xff)); 684} 685 686static void tcg_out_insn_RIL(TCGContext *s, S390Opcode op, TCGReg r1, int i2) 687{ 688 tcg_out16(s, op | (r1 << 4)); 689 tcg_out32(s, i2); 690} 691 692static void tcg_out_insn_RS(TCGContext *s, S390Opcode op, TCGReg r1, 693 TCGReg b2, TCGReg r3, int disp) 694{ 695 tcg_out32(s, (op << 24) | (r1 << 20) | (r3 << 16) | (b2 << 12) 696 | (disp & 0xfff)); 697} 698 699static void tcg_out_insn_RSY(TCGContext *s, S390Opcode op, TCGReg r1, 700 TCGReg b2, TCGReg r3, int disp) 701{ 702 tcg_out16(s, (op & 0xff00) | (r1 << 4) | r3); 703 tcg_out32(s, (op & 0xff) | (b2 << 28) 704 | ((disp & 0xfff) << 16) | ((disp & 0xff000) >> 4)); 705} 706 707#define tcg_out_insn_RX tcg_out_insn_RS 708#define tcg_out_insn_RXY tcg_out_insn_RSY 709 710static int RXB(TCGReg v1, TCGReg v2, TCGReg v3, TCGReg v4) 711{ 712 /* 713 * Shift bit 4 of each regno to its corresponding bit of RXB. 714 * RXB itself begins at bit 8 of the instruction so 8 - 4 = 4 715 * is the left-shift of the 4th operand. 716 */ 717 return ((v1 & 0x10) << (4 + 3)) 718 | ((v2 & 0x10) << (4 + 2)) 719 | ((v3 & 0x10) << (4 + 1)) 720 | ((v4 & 0x10) << (4 + 0)); 721} 722 723static void tcg_out_insn_VRIa(TCGContext *s, S390Opcode op, 724 TCGReg v1, uint16_t i2, int m3) 725{ 726 tcg_debug_assert(is_vector_reg(v1)); 727 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4)); 728 tcg_out16(s, i2); 729 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m3 << 12)); 730} 731 732static void tcg_out_insn_VRIb(TCGContext *s, S390Opcode op, 733 TCGReg v1, uint8_t i2, uint8_t i3, int m4) 734{ 735 tcg_debug_assert(is_vector_reg(v1)); 736 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4)); 737 tcg_out16(s, (i2 << 8) | (i3 & 0xff)); 738 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m4 << 12)); 739} 740 741static void tcg_out_insn_VRIc(TCGContext *s, S390Opcode op, 742 TCGReg v1, uint16_t i2, TCGReg v3, int m4) 743{ 744 tcg_debug_assert(is_vector_reg(v1)); 745 tcg_debug_assert(is_vector_reg(v3)); 746 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v3 & 0xf)); 747 tcg_out16(s, i2); 748 tcg_out16(s, (op & 0x00ff) | RXB(v1, v3, 0, 0) | (m4 << 12)); 749} 750 751static void tcg_out_insn_VRRa(TCGContext *s, S390Opcode op, 752 TCGReg v1, TCGReg v2, int m3) 753{ 754 tcg_debug_assert(is_vector_reg(v1)); 755 tcg_debug_assert(is_vector_reg(v2)); 756 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v2 & 0xf)); 757 tcg_out32(s, (op & 0x00ff) | RXB(v1, v2, 0, 0) | (m3 << 12)); 758} 759 760static void tcg_out_insn_VRRc(TCGContext *s, S390Opcode op, 761 TCGReg v1, TCGReg v2, TCGReg v3, int m4) 762{ 763 tcg_debug_assert(is_vector_reg(v1)); 764 tcg_debug_assert(is_vector_reg(v2)); 765 tcg_debug_assert(is_vector_reg(v3)); 766 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v2 & 0xf)); 767 tcg_out16(s, v3 << 12); 768 tcg_out16(s, (op & 0x00ff) | RXB(v1, v2, v3, 0) | (m4 << 12)); 769} 770 771static void tcg_out_insn_VRRe(TCGContext *s, S390Opcode op, 772 TCGReg v1, TCGReg v2, TCGReg v3, TCGReg v4) 773{ 774 tcg_debug_assert(is_vector_reg(v1)); 775 tcg_debug_assert(is_vector_reg(v2)); 776 tcg_debug_assert(is_vector_reg(v3)); 777 tcg_debug_assert(is_vector_reg(v4)); 778 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v2 & 0xf)); 779 tcg_out16(s, v3 << 12); 780 tcg_out16(s, (op & 0x00ff) | RXB(v1, v2, v3, v4) | (v4 << 12)); 781} 782 783static void tcg_out_insn_VRRf(TCGContext *s, S390Opcode op, 784 TCGReg v1, TCGReg r2, TCGReg r3) 785{ 786 tcg_debug_assert(is_vector_reg(v1)); 787 tcg_debug_assert(is_general_reg(r2)); 788 tcg_debug_assert(is_general_reg(r3)); 789 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | r2); 790 tcg_out16(s, r3 << 12); 791 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0)); 792} 793 794static void tcg_out_insn_VRSa(TCGContext *s, S390Opcode op, TCGReg v1, 795 intptr_t d2, TCGReg b2, TCGReg v3, int m4) 796{ 797 tcg_debug_assert(is_vector_reg(v1)); 798 tcg_debug_assert(d2 >= 0 && d2 <= 0xfff); 799 tcg_debug_assert(is_general_reg(b2)); 800 tcg_debug_assert(is_vector_reg(v3)); 801 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v3 & 0xf)); 802 tcg_out16(s, b2 << 12 | d2); 803 tcg_out16(s, (op & 0x00ff) | RXB(v1, v3, 0, 0) | (m4 << 12)); 804} 805 806static void tcg_out_insn_VRSb(TCGContext *s, S390Opcode op, TCGReg v1, 807 intptr_t d2, TCGReg b2, TCGReg r3, int m4) 808{ 809 tcg_debug_assert(is_vector_reg(v1)); 810 tcg_debug_assert(d2 >= 0 && d2 <= 0xfff); 811 tcg_debug_assert(is_general_reg(b2)); 812 tcg_debug_assert(is_general_reg(r3)); 813 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | r3); 814 tcg_out16(s, b2 << 12 | d2); 815 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m4 << 12)); 816} 817 818static void tcg_out_insn_VRSc(TCGContext *s, S390Opcode op, TCGReg r1, 819 intptr_t d2, TCGReg b2, TCGReg v3, int m4) 820{ 821 tcg_debug_assert(is_general_reg(r1)); 822 tcg_debug_assert(d2 >= 0 && d2 <= 0xfff); 823 tcg_debug_assert(is_general_reg(b2)); 824 tcg_debug_assert(is_vector_reg(v3)); 825 tcg_out16(s, (op & 0xff00) | (r1 << 4) | (v3 & 0xf)); 826 tcg_out16(s, b2 << 12 | d2); 827 tcg_out16(s, (op & 0x00ff) | RXB(0, v3, 0, 0) | (m4 << 12)); 828} 829 830static void tcg_out_insn_VRX(TCGContext *s, S390Opcode op, TCGReg v1, 831 TCGReg b2, TCGReg x2, intptr_t d2, int m3) 832{ 833 tcg_debug_assert(is_vector_reg(v1)); 834 tcg_debug_assert(d2 >= 0 && d2 <= 0xfff); 835 tcg_debug_assert(is_general_reg(x2)); 836 tcg_debug_assert(is_general_reg(b2)); 837 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | x2); 838 tcg_out16(s, (b2 << 12) | d2); 839 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m3 << 12)); 840} 841 842/* Emit an opcode with "type-checking" of the format. */ 843#define tcg_out_insn(S, FMT, OP, ...) \ 844 glue(tcg_out_insn_,FMT)(S, glue(glue(FMT,_),OP), ## __VA_ARGS__) 845 846 847/* emit 64-bit shifts */ 848static void tcg_out_sh64(TCGContext* s, S390Opcode op, TCGReg dest, 849 TCGReg src, TCGReg sh_reg, int sh_imm) 850{ 851 tcg_out_insn_RSY(s, op, dest, sh_reg, src, sh_imm); 852} 853 854/* emit 32-bit shifts */ 855static void tcg_out_sh32(TCGContext* s, S390Opcode op, TCGReg dest, 856 TCGReg sh_reg, int sh_imm) 857{ 858 tcg_out_insn_RS(s, op, dest, sh_reg, 0, sh_imm); 859} 860 861static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg dst, TCGReg src) 862{ 863 if (src == dst) { 864 return true; 865 } 866 switch (type) { 867 case TCG_TYPE_I32: 868 if (likely(is_general_reg(dst) && is_general_reg(src))) { 869 tcg_out_insn(s, RR, LR, dst, src); 870 break; 871 } 872 /* fallthru */ 873 874 case TCG_TYPE_I64: 875 if (likely(is_general_reg(dst))) { 876 if (likely(is_general_reg(src))) { 877 tcg_out_insn(s, RRE, LGR, dst, src); 878 } else { 879 tcg_out_insn(s, VRSc, VLGV, dst, 0, 0, src, 3); 880 } 881 break; 882 } else if (is_general_reg(src)) { 883 tcg_out_insn(s, VRSb, VLVG, dst, 0, 0, src, 3); 884 break; 885 } 886 /* fallthru */ 887 888 case TCG_TYPE_V64: 889 case TCG_TYPE_V128: 890 tcg_out_insn(s, VRRa, VLR, dst, src, 0); 891 break; 892 893 default: 894 g_assert_not_reached(); 895 } 896 return true; 897} 898 899static const S390Opcode li_insns[4] = { 900 RI_LLILL, RI_LLILH, RI_LLIHL, RI_LLIHH 901}; 902static const S390Opcode oi_insns[4] = { 903 RI_OILL, RI_OILH, RI_OIHL, RI_OIHH 904}; 905static const S390Opcode lif_insns[2] = { 906 RIL_LLILF, RIL_LLIHF, 907}; 908static const S390Opcode tm_insns[4] = { 909 RI_TMLL, RI_TMLH, RI_TMHL, RI_TMHH 910}; 911 912/* load a register with an immediate value */ 913static void tcg_out_movi(TCGContext *s, TCGType type, 914 TCGReg ret, tcg_target_long sval) 915{ 916 tcg_target_ulong uval = sval; 917 ptrdiff_t pc_off; 918 int i; 919 920 if (type == TCG_TYPE_I32) { 921 uval = (uint32_t)sval; 922 sval = (int32_t)sval; 923 } 924 925 /* Try all 32-bit insns that can load it in one go. */ 926 if (sval >= -0x8000 && sval < 0x8000) { 927 tcg_out_insn(s, RI, LGHI, ret, sval); 928 return; 929 } 930 931 i = is_const_p16(uval); 932 if (i >= 0) { 933 tcg_out_insn_RI(s, li_insns[i], ret, uval >> (i * 16)); 934 return; 935 } 936 937 /* Try all 48-bit insns that can load it in one go. */ 938 if (sval == (int32_t)sval) { 939 tcg_out_insn(s, RIL, LGFI, ret, sval); 940 return; 941 } 942 943 i = is_const_p32(uval); 944 if (i >= 0) { 945 tcg_out_insn_RIL(s, lif_insns[i], ret, uval >> (i * 32)); 946 return; 947 } 948 949 /* Try for PC-relative address load. For odd addresses, add one. */ 950 pc_off = tcg_pcrel_diff(s, (void *)sval) >> 1; 951 if (pc_off == (int32_t)pc_off) { 952 tcg_out_insn(s, RIL, LARL, ret, pc_off); 953 if (sval & 1) { 954 tcg_out_insn(s, RI, AGHI, ret, 1); 955 } 956 return; 957 } 958 959 /* Otherwise, load it by parts. */ 960 i = is_const_p16((uint32_t)uval); 961 if (i >= 0) { 962 tcg_out_insn_RI(s, li_insns[i], ret, uval >> (i * 16)); 963 } else { 964 tcg_out_insn(s, RIL, LLILF, ret, uval); 965 } 966 uval >>= 32; 967 i = is_const_p16(uval); 968 if (i >= 0) { 969 tcg_out_insn_RI(s, oi_insns[i + 2], ret, uval >> (i * 16)); 970 } else { 971 tcg_out_insn(s, RIL, OIHF, ret, uval); 972 } 973} 974 975/* Emit a load/store type instruction. Inputs are: 976 DATA: The register to be loaded or stored. 977 BASE+OFS: The effective address. 978 OPC_RX: If the operation has an RX format opcode (e.g. STC), otherwise 0. 979 OPC_RXY: The RXY format opcode for the operation (e.g. STCY). */ 980 981static void tcg_out_mem(TCGContext *s, S390Opcode opc_rx, S390Opcode opc_rxy, 982 TCGReg data, TCGReg base, TCGReg index, 983 tcg_target_long ofs) 984{ 985 if (ofs < -0x80000 || ofs >= 0x80000) { 986 /* Combine the low 20 bits of the offset with the actual load insn; 987 the high 44 bits must come from an immediate load. */ 988 tcg_target_long low = ((ofs & 0xfffff) ^ 0x80000) - 0x80000; 989 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - low); 990 ofs = low; 991 992 /* If we were already given an index register, add it in. */ 993 if (index != TCG_REG_NONE) { 994 tcg_out_insn(s, RRE, AGR, TCG_TMP0, index); 995 } 996 index = TCG_TMP0; 997 } 998 999 if (opc_rx && ofs >= 0 && ofs < 0x1000) { 1000 tcg_out_insn_RX(s, opc_rx, data, base, index, ofs); 1001 } else { 1002 tcg_out_insn_RXY(s, opc_rxy, data, base, index, ofs); 1003 } 1004} 1005 1006static void tcg_out_vrx_mem(TCGContext *s, S390Opcode opc_vrx, 1007 TCGReg data, TCGReg base, TCGReg index, 1008 tcg_target_long ofs, int m3) 1009{ 1010 if (ofs < 0 || ofs >= 0x1000) { 1011 if (ofs >= -0x80000 && ofs < 0x80000) { 1012 tcg_out_insn(s, RXY, LAY, TCG_TMP0, base, index, ofs); 1013 base = TCG_TMP0; 1014 index = TCG_REG_NONE; 1015 ofs = 0; 1016 } else { 1017 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs); 1018 if (index != TCG_REG_NONE) { 1019 tcg_out_insn(s, RRE, AGR, TCG_TMP0, index); 1020 } 1021 index = TCG_TMP0; 1022 ofs = 0; 1023 } 1024 } 1025 tcg_out_insn_VRX(s, opc_vrx, data, base, index, ofs, m3); 1026} 1027 1028/* load data without address translation or endianness conversion */ 1029static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg data, 1030 TCGReg base, intptr_t ofs) 1031{ 1032 switch (type) { 1033 case TCG_TYPE_I32: 1034 if (likely(is_general_reg(data))) { 1035 tcg_out_mem(s, RX_L, RXY_LY, data, base, TCG_REG_NONE, ofs); 1036 break; 1037 } 1038 tcg_out_vrx_mem(s, VRX_VLLEZ, data, base, TCG_REG_NONE, ofs, MO_32); 1039 break; 1040 1041 case TCG_TYPE_I64: 1042 if (likely(is_general_reg(data))) { 1043 tcg_out_mem(s, 0, RXY_LG, data, base, TCG_REG_NONE, ofs); 1044 break; 1045 } 1046 /* fallthru */ 1047 1048 case TCG_TYPE_V64: 1049 tcg_out_vrx_mem(s, VRX_VLLEZ, data, base, TCG_REG_NONE, ofs, MO_64); 1050 break; 1051 1052 case TCG_TYPE_V128: 1053 /* Hint quadword aligned. */ 1054 tcg_out_vrx_mem(s, VRX_VL, data, base, TCG_REG_NONE, ofs, 4); 1055 break; 1056 1057 default: 1058 g_assert_not_reached(); 1059 } 1060} 1061 1062static void tcg_out_st(TCGContext *s, TCGType type, TCGReg data, 1063 TCGReg base, intptr_t ofs) 1064{ 1065 switch (type) { 1066 case TCG_TYPE_I32: 1067 if (likely(is_general_reg(data))) { 1068 tcg_out_mem(s, RX_ST, RXY_STY, data, base, TCG_REG_NONE, ofs); 1069 } else { 1070 tcg_out_vrx_mem(s, VRX_VSTEF, data, base, TCG_REG_NONE, ofs, 1); 1071 } 1072 break; 1073 1074 case TCG_TYPE_I64: 1075 if (likely(is_general_reg(data))) { 1076 tcg_out_mem(s, 0, RXY_STG, data, base, TCG_REG_NONE, ofs); 1077 break; 1078 } 1079 /* fallthru */ 1080 1081 case TCG_TYPE_V64: 1082 tcg_out_vrx_mem(s, VRX_VSTEG, data, base, TCG_REG_NONE, ofs, 0); 1083 break; 1084 1085 case TCG_TYPE_V128: 1086 /* Hint quadword aligned. */ 1087 tcg_out_vrx_mem(s, VRX_VST, data, base, TCG_REG_NONE, ofs, 4); 1088 break; 1089 1090 default: 1091 g_assert_not_reached(); 1092 } 1093} 1094 1095static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 1096 TCGReg base, intptr_t ofs) 1097{ 1098 return false; 1099} 1100 1101static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 1102{ 1103 return false; 1104} 1105 1106static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 1107 tcg_target_long imm) 1108{ 1109 /* This function is only used for passing structs by reference. */ 1110 tcg_out_mem(s, RX_LA, RXY_LAY, rd, rs, TCG_REG_NONE, imm); 1111} 1112 1113static inline void tcg_out_risbg(TCGContext *s, TCGReg dest, TCGReg src, 1114 int msb, int lsb, int ofs, int z) 1115{ 1116 /* Format RIE-f */ 1117 tcg_out16(s, (RIEf_RISBG & 0xff00) | (dest << 4) | src); 1118 tcg_out16(s, (msb << 8) | (z << 7) | lsb); 1119 tcg_out16(s, (ofs << 8) | (RIEf_RISBG & 0xff)); 1120} 1121 1122static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) 1123{ 1124 tcg_out_insn(s, RRE, LGBR, dest, src); 1125} 1126 1127static void tcg_out_ext8u(TCGContext *s, TCGReg dest, TCGReg src) 1128{ 1129 tcg_out_insn(s, RRE, LLGCR, dest, src); 1130} 1131 1132static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) 1133{ 1134 tcg_out_insn(s, RRE, LGHR, dest, src); 1135} 1136 1137static void tcg_out_ext16u(TCGContext *s, TCGReg dest, TCGReg src) 1138{ 1139 tcg_out_insn(s, RRE, LLGHR, dest, src); 1140} 1141 1142static void tcg_out_ext32s(TCGContext *s, TCGReg dest, TCGReg src) 1143{ 1144 tcg_out_insn(s, RRE, LGFR, dest, src); 1145} 1146 1147static void tcg_out_ext32u(TCGContext *s, TCGReg dest, TCGReg src) 1148{ 1149 tcg_out_insn(s, RRE, LLGFR, dest, src); 1150} 1151 1152static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg dest, TCGReg src) 1153{ 1154 tcg_out_ext32s(s, dest, src); 1155} 1156 1157static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg dest, TCGReg src) 1158{ 1159 tcg_out_ext32u(s, dest, src); 1160} 1161 1162static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg dest, TCGReg src) 1163{ 1164 tcg_out_mov(s, TCG_TYPE_I32, dest, src); 1165} 1166 1167static void tgen_andi_risbg(TCGContext *s, TCGReg out, TCGReg in, uint64_t val) 1168{ 1169 int msb, lsb; 1170 if ((val & 0x8000000000000001ull) == 0x8000000000000001ull) { 1171 /* Achieve wraparound by swapping msb and lsb. */ 1172 msb = 64 - ctz64(~val); 1173 lsb = clz64(~val) - 1; 1174 } else { 1175 msb = clz64(val); 1176 lsb = 63 - ctz64(val); 1177 } 1178 tcg_out_risbg(s, out, in, msb, lsb, 0, 1); 1179} 1180 1181static void tgen_andi(TCGContext *s, TCGType type, TCGReg dest, uint64_t val) 1182{ 1183 static const S390Opcode ni_insns[4] = { 1184 RI_NILL, RI_NILH, RI_NIHL, RI_NIHH 1185 }; 1186 static const S390Opcode nif_insns[2] = { 1187 RIL_NILF, RIL_NIHF 1188 }; 1189 uint64_t valid = (type == TCG_TYPE_I32 ? 0xffffffffull : -1ull); 1190 int i; 1191 1192 /* Look for the zero-extensions. */ 1193 if ((val & valid) == 0xffffffff) { 1194 tcg_out_ext32u(s, dest, dest); 1195 return; 1196 } 1197 if ((val & valid) == 0xff) { 1198 tcg_out_ext8u(s, dest, dest); 1199 return; 1200 } 1201 if ((val & valid) == 0xffff) { 1202 tcg_out_ext16u(s, dest, dest); 1203 return; 1204 } 1205 1206 i = is_const_p16(~val & valid); 1207 if (i >= 0) { 1208 tcg_out_insn_RI(s, ni_insns[i], dest, val >> (i * 16)); 1209 return; 1210 } 1211 1212 i = is_const_p32(~val & valid); 1213 tcg_debug_assert(i == 0 || type != TCG_TYPE_I32); 1214 if (i >= 0) { 1215 tcg_out_insn_RIL(s, nif_insns[i], dest, val >> (i * 32)); 1216 return; 1217 } 1218 1219 if (risbg_mask(val)) { 1220 tgen_andi_risbg(s, dest, dest, val); 1221 return; 1222 } 1223 1224 g_assert_not_reached(); 1225} 1226 1227static void tgen_ori(TCGContext *s, TCGReg dest, uint64_t val) 1228{ 1229 static const S390Opcode oif_insns[2] = { 1230 RIL_OILF, RIL_OIHF 1231 }; 1232 1233 int i; 1234 1235 i = is_const_p16(val); 1236 if (i >= 0) { 1237 tcg_out_insn_RI(s, oi_insns[i], dest, val >> (i * 16)); 1238 return; 1239 } 1240 1241 i = is_const_p32(val); 1242 if (i >= 0) { 1243 tcg_out_insn_RIL(s, oif_insns[i], dest, val >> (i * 32)); 1244 return; 1245 } 1246 1247 g_assert_not_reached(); 1248} 1249 1250static void tgen_xori(TCGContext *s, TCGReg dest, uint64_t val) 1251{ 1252 switch (is_const_p32(val)) { 1253 case 0: 1254 tcg_out_insn(s, RIL, XILF, dest, val); 1255 break; 1256 case 1: 1257 tcg_out_insn(s, RIL, XIHF, dest, val >> 32); 1258 break; 1259 default: 1260 g_assert_not_reached(); 1261 } 1262} 1263 1264static int tgen_cmp2(TCGContext *s, TCGType type, TCGCond c, TCGReg r1, 1265 TCGArg c2, bool c2const, bool need_carry, int *inv_cc) 1266{ 1267 bool is_unsigned = is_unsigned_cond(c); 1268 TCGCond inv_c = tcg_invert_cond(c); 1269 S390Opcode op; 1270 1271 if (is_tst_cond(c)) { 1272 tcg_debug_assert(!need_carry); 1273 1274 if (!c2const) { 1275 if (type == TCG_TYPE_I32) { 1276 tcg_out_insn(s, RRFa, NRK, TCG_REG_R0, r1, c2); 1277 } else { 1278 tcg_out_insn(s, RRFa, NGRK, TCG_REG_R0, r1, c2); 1279 } 1280 goto exit; 1281 } 1282 1283 if (type == TCG_TYPE_I32) { 1284 c2 = (uint32_t)c2; 1285 } 1286 1287 int i = is_const_p16(c2); 1288 if (i >= 0) { 1289 tcg_out_insn_RI(s, tm_insns[i], r1, c2 >> (i * 16)); 1290 *inv_cc = c == TCG_COND_TSTEQ ? S390_TM_NE : S390_TM_EQ; 1291 return *inv_cc ^ 15; 1292 } 1293 1294 if (risbg_mask(c2)) { 1295 tgen_andi_risbg(s, TCG_REG_R0, r1, c2); 1296 goto exit; 1297 } 1298 g_assert_not_reached(); 1299 } 1300 1301 if (c2const) { 1302 if (c2 == 0) { 1303 if (!(is_unsigned && need_carry)) { 1304 if (type == TCG_TYPE_I32) { 1305 tcg_out_insn(s, RR, LTR, r1, r1); 1306 } else { 1307 tcg_out_insn(s, RRE, LTGR, r1, r1); 1308 } 1309 *inv_cc = tcg_cond_to_ltr_cond[inv_c]; 1310 return tcg_cond_to_ltr_cond[c]; 1311 } 1312 } 1313 1314 if (!is_unsigned && c2 == (int16_t)c2) { 1315 op = (type == TCG_TYPE_I32 ? RI_CHI : RI_CGHI); 1316 tcg_out_insn_RI(s, op, r1, c2); 1317 goto exit; 1318 } 1319 1320 if (type == TCG_TYPE_I32) { 1321 op = (is_unsigned ? RIL_CLFI : RIL_CFI); 1322 tcg_out_insn_RIL(s, op, r1, c2); 1323 goto exit; 1324 } 1325 1326 /* Should match TCG_CT_CONST_CMP. */ 1327 switch (c) { 1328 case TCG_COND_LT: 1329 case TCG_COND_GE: 1330 case TCG_COND_LE: 1331 case TCG_COND_GT: 1332 tcg_debug_assert(c2 == (int32_t)c2); 1333 op = RIL_CGFI; 1334 break; 1335 case TCG_COND_EQ: 1336 case TCG_COND_NE: 1337 if (c2 == (int32_t)c2) { 1338 op = RIL_CGFI; 1339 break; 1340 } 1341 /* fall through */ 1342 case TCG_COND_LTU: 1343 case TCG_COND_GEU: 1344 case TCG_COND_LEU: 1345 case TCG_COND_GTU: 1346 tcg_debug_assert(c2 == (uint32_t)c2); 1347 op = RIL_CLGFI; 1348 break; 1349 default: 1350 g_assert_not_reached(); 1351 } 1352 tcg_out_insn_RIL(s, op, r1, c2); 1353 } else if (type == TCG_TYPE_I32) { 1354 op = (is_unsigned ? RR_CLR : RR_CR); 1355 tcg_out_insn_RR(s, op, r1, c2); 1356 } else { 1357 op = (is_unsigned ? RRE_CLGR : RRE_CGR); 1358 tcg_out_insn_RRE(s, op, r1, c2); 1359 } 1360 1361 exit: 1362 *inv_cc = tcg_cond_to_s390_cond[inv_c]; 1363 return tcg_cond_to_s390_cond[c]; 1364} 1365 1366static int tgen_cmp(TCGContext *s, TCGType type, TCGCond c, TCGReg r1, 1367 TCGArg c2, bool c2const, bool need_carry) 1368{ 1369 int inv_cc; 1370 return tgen_cmp2(s, type, c, r1, c2, c2const, need_carry, &inv_cc); 1371} 1372 1373static void tgen_setcond_int(TCGContext *s, TCGType type, TCGCond cond, 1374 TCGReg dest, TCGReg c1, TCGArg c2, 1375 bool c2const, bool neg) 1376{ 1377 int cc; 1378 1379 /* With LOC2, we can always emit the minimum 3 insns. */ 1380 if (HAVE_FACILITY(LOAD_ON_COND2)) { 1381 /* Emit: d = 0, d = (cc ? 1 : d). */ 1382 cc = tgen_cmp(s, type, cond, c1, c2, c2const, false); 1383 tcg_out_movi(s, TCG_TYPE_I64, dest, 0); 1384 tcg_out_insn(s, RIEg, LOCGHI, dest, neg ? -1 : 1, cc); 1385 return; 1386 } 1387 1388 switch (cond) { 1389 case TCG_COND_GEU: 1390 case TCG_COND_LTU: 1391 case TCG_COND_LT: 1392 case TCG_COND_GE: 1393 /* Swap operands so that we can use LEU/GTU/GT/LE. */ 1394 if (!c2const) { 1395 TCGReg t = c1; 1396 c1 = c2; 1397 c2 = t; 1398 cond = tcg_swap_cond(cond); 1399 } 1400 break; 1401 default: 1402 break; 1403 } 1404 1405 switch (cond) { 1406 case TCG_COND_NE: 1407 /* X != 0 is X > 0. */ 1408 if (c2const && c2 == 0) { 1409 cond = TCG_COND_GTU; 1410 } else { 1411 break; 1412 } 1413 /* fallthru */ 1414 1415 case TCG_COND_GTU: 1416 case TCG_COND_GT: 1417 /* 1418 * The result of a compare has CC=2 for GT and CC=3 unused. 1419 * ADD LOGICAL WITH CARRY considers (CC & 2) the carry bit. 1420 */ 1421 tgen_cmp(s, type, cond, c1, c2, c2const, true); 1422 tcg_out_movi(s, type, dest, 0); 1423 tcg_out_insn(s, RRE, ALCGR, dest, dest); 1424 if (neg) { 1425 if (type == TCG_TYPE_I32) { 1426 tcg_out_insn(s, RR, LCR, dest, dest); 1427 } else { 1428 tcg_out_insn(s, RRE, LCGR, dest, dest); 1429 } 1430 } 1431 return; 1432 1433 case TCG_COND_EQ: 1434 /* X == 0 is X <= 0. */ 1435 if (c2const && c2 == 0) { 1436 cond = TCG_COND_LEU; 1437 } else { 1438 break; 1439 } 1440 /* fallthru */ 1441 1442 case TCG_COND_LEU: 1443 case TCG_COND_LE: 1444 /* 1445 * As above, but we're looking for borrow, or !carry. 1446 * The second insn computes d - d - borrow, or -1 for true 1447 * and 0 for false. So we must mask to 1 bit afterward. 1448 */ 1449 tgen_cmp(s, type, cond, c1, c2, c2const, true); 1450 tcg_out_insn(s, RRE, SLBGR, dest, dest); 1451 if (!neg) { 1452 tgen_andi(s, type, dest, 1); 1453 } 1454 return; 1455 1456 default: 1457 g_assert_not_reached(); 1458 } 1459 1460 cc = tgen_cmp(s, type, cond, c1, c2, c2const, false); 1461 /* Emit: d = 0, t = 1, d = (cc ? t : d). */ 1462 tcg_out_movi(s, TCG_TYPE_I64, dest, 0); 1463 tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, neg ? -1 : 1); 1464 tcg_out_insn(s, RRFc, LOCGR, dest, TCG_TMP0, cc); 1465} 1466 1467static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, 1468 TCGReg dest, TCGReg arg1, TCGReg arg2) 1469{ 1470 tgen_setcond_int(s, type, cond, dest, arg1, arg2, false, false); 1471} 1472 1473static void tgen_setcondi(TCGContext *s, TCGType type, TCGCond cond, 1474 TCGReg dest, TCGReg arg1, tcg_target_long arg2) 1475{ 1476 tgen_setcond_int(s, type, cond, dest, arg1, arg2, true, false); 1477} 1478 1479static const TCGOutOpSetcond outop_setcond = { 1480 .base.static_constraint = C_O1_I2(r, r, rC), 1481 .out_rrr = tgen_setcond, 1482 .out_rri = tgen_setcondi, 1483}; 1484 1485static void tgen_negsetcond(TCGContext *s, TCGType type, TCGCond cond, 1486 TCGReg dest, TCGReg arg1, TCGReg arg2) 1487{ 1488 tgen_setcond_int(s, type, cond, dest, arg1, arg2, false, true); 1489} 1490 1491static void tgen_negsetcondi(TCGContext *s, TCGType type, TCGCond cond, 1492 TCGReg dest, TCGReg arg1, tcg_target_long arg2) 1493{ 1494 tgen_setcond_int(s, type, cond, dest, arg1, arg2, true, true); 1495} 1496 1497static const TCGOutOpSetcond outop_negsetcond = { 1498 .base.static_constraint = C_O1_I2(r, r, rC), 1499 .out_rrr = tgen_negsetcond, 1500 .out_rri = tgen_negsetcondi, 1501}; 1502 1503static void tgen_movcond_int(TCGContext *s, TCGType type, TCGReg dest, 1504 TCGArg v3, int v3const, TCGReg v4, 1505 int cc, int inv_cc) 1506{ 1507 TCGReg src; 1508 1509 if (v3const) { 1510 if (dest == v4) { 1511 if (HAVE_FACILITY(LOAD_ON_COND2)) { 1512 /* Emit: if (cc) dest = v3. */ 1513 tcg_out_insn(s, RIEg, LOCGHI, dest, v3, cc); 1514 return; 1515 } 1516 tcg_out_insn(s, RI, LGHI, TCG_TMP0, v3); 1517 src = TCG_TMP0; 1518 } else { 1519 /* LGR+LOCGHI is larger than LGHI+LOCGR. */ 1520 tcg_out_insn(s, RI, LGHI, dest, v3); 1521 cc = inv_cc; 1522 src = v4; 1523 } 1524 } else { 1525 if (HAVE_FACILITY(MISC_INSN_EXT3)) { 1526 /* Emit: dest = cc ? v3 : v4. */ 1527 tcg_out_insn(s, RRFam, SELGR, dest, v3, v4, cc); 1528 return; 1529 } 1530 if (dest == v4) { 1531 src = v3; 1532 } else { 1533 tcg_out_mov(s, type, dest, v3); 1534 cc = inv_cc; 1535 src = v4; 1536 } 1537 } 1538 1539 /* Emit: if (cc) dest = src. */ 1540 tcg_out_insn(s, RRFc, LOCGR, dest, src, cc); 1541} 1542 1543static void tgen_movcond(TCGContext *s, TCGType type, TCGCond c, 1544 TCGReg dest, TCGReg c1, TCGArg c2, bool c2const, 1545 TCGArg v3, bool v3const, TCGArg v4, bool v4const) 1546{ 1547 int cc, inv_cc; 1548 1549 cc = tgen_cmp2(s, type, c, c1, c2, c2const, false, &inv_cc); 1550 tgen_movcond_int(s, type, dest, v3, v3const, v4, cc, inv_cc); 1551} 1552 1553static const TCGOutOpMovcond outop_movcond = { 1554 .base.static_constraint = C_O1_I4(r, r, rC, rI, r), 1555 .out = tgen_movcond, 1556}; 1557 1558static void tgen_deposit(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, 1559 TCGReg a2, unsigned ofs, unsigned len) 1560{ 1561 unsigned lsb = (63 - ofs); 1562 unsigned msb = lsb - (len - 1); 1563 1564 /* 1565 * Since we can't support "0Z" as a constraint, we allow a1 in 1566 * any register. Fix things up as if a matching constraint. 1567 */ 1568 if (a0 != a1) { 1569 if (a0 == a2) { 1570 tcg_out_mov(s, type, TCG_TMP0, a2); 1571 a2 = TCG_TMP0; 1572 } 1573 tcg_out_mov(s, type, a0, a1); 1574 } 1575 tcg_out_risbg(s, a0, a2, msb, lsb, ofs, false); 1576} 1577 1578static void tgen_depositz(TCGContext *s, TCGType type, TCGReg a0, TCGReg a2, 1579 unsigned ofs, unsigned len) 1580{ 1581 unsigned lsb = (63 - ofs); 1582 unsigned msb = lsb - (len - 1); 1583 tcg_out_risbg(s, a0, a2, msb, lsb, ofs, true); 1584} 1585 1586static const TCGOutOpDeposit outop_deposit = { 1587 .base.static_constraint = C_O1_I2(r, rZ, r), 1588 .out_rrr = tgen_deposit, 1589 .out_rzr = tgen_depositz, 1590}; 1591 1592static void tgen_extract(TCGContext *s, TCGType type, TCGReg dest, 1593 TCGReg src, unsigned ofs, unsigned len) 1594{ 1595 if (ofs == 0) { 1596 switch (len) { 1597 case 8: 1598 tcg_out_ext8u(s, dest, src); 1599 return; 1600 case 16: 1601 tcg_out_ext16u(s, dest, src); 1602 return; 1603 case 32: 1604 tcg_out_ext32u(s, dest, src); 1605 return; 1606 } 1607 } 1608 tcg_out_risbg(s, dest, src, 64 - len, 63, 64 - ofs, 1); 1609} 1610 1611static const TCGOutOpExtract outop_extract = { 1612 .base.static_constraint = C_O1_I1(r, r), 1613 .out_rr = tgen_extract, 1614}; 1615 1616static void tgen_sextract(TCGContext *s, TCGType type, TCGReg dest, 1617 TCGReg src, unsigned ofs, unsigned len) 1618{ 1619 if (ofs == 0) { 1620 switch (len) { 1621 case 8: 1622 tcg_out_ext8s(s, TCG_TYPE_REG, dest, src); 1623 return; 1624 case 16: 1625 tcg_out_ext16s(s, TCG_TYPE_REG, dest, src); 1626 return; 1627 case 32: 1628 tcg_out_ext32s(s, dest, src); 1629 return; 1630 } 1631 } 1632 g_assert_not_reached(); 1633} 1634 1635static const TCGOutOpExtract outop_sextract = { 1636 .base.static_constraint = C_O1_I1(r, r), 1637 .out_rr = tgen_sextract, 1638}; 1639 1640static void tgen_gotoi(TCGContext *s, int cc, const tcg_insn_unit *dest) 1641{ 1642 ptrdiff_t off = tcg_pcrel_diff(s, dest) >> 1; 1643 if (off == (int16_t)off) { 1644 tcg_out_insn(s, RI, BRC, cc, off); 1645 } else if (off == (int32_t)off) { 1646 tcg_out_insn(s, RIL, BRCL, cc, off); 1647 } else { 1648 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)dest); 1649 tcg_out_insn(s, RR, BCR, cc, TCG_TMP0); 1650 } 1651} 1652 1653static void tgen_branch(TCGContext *s, int cc, TCGLabel *l) 1654{ 1655 if (l->has_value) { 1656 tgen_gotoi(s, cc, l->u.value_ptr); 1657 } else { 1658 tcg_out16(s, RI_BRC | (cc << 4)); 1659 tcg_out_reloc(s, s->code_ptr, R_390_PC16DBL, l, 2); 1660 s->code_ptr += 1; 1661 } 1662} 1663 1664static void tgen_compare_branch(TCGContext *s, S390Opcode opc, int cc, 1665 TCGReg r1, TCGReg r2, TCGLabel *l) 1666{ 1667 tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2); 1668 /* Format RIE-b */ 1669 tcg_out16(s, (opc & 0xff00) | (r1 << 4) | r2); 1670 tcg_out16(s, 0); 1671 tcg_out16(s, cc << 12 | (opc & 0xff)); 1672} 1673 1674static void tgen_compare_imm_branch(TCGContext *s, S390Opcode opc, int cc, 1675 TCGReg r1, int i2, TCGLabel *l) 1676{ 1677 tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2); 1678 /* Format RIE-c */ 1679 tcg_out16(s, (opc & 0xff00) | (r1 << 4) | cc); 1680 tcg_out16(s, 0); 1681 tcg_out16(s, (i2 << 8) | (opc & 0xff)); 1682} 1683 1684static void tgen_brcond(TCGContext *s, TCGType type, TCGCond c, 1685 TCGReg r1, TCGArg c2, int c2const, TCGLabel *l) 1686{ 1687 int cc; 1688 1689 if (!is_tst_cond(c)) { 1690 bool is_unsigned = is_unsigned_cond(c); 1691 bool in_range; 1692 S390Opcode opc; 1693 1694 cc = tcg_cond_to_s390_cond[c]; 1695 1696 if (!c2const) { 1697 opc = (type == TCG_TYPE_I32 1698 ? (is_unsigned ? RIEb_CLRJ : RIEb_CRJ) 1699 : (is_unsigned ? RIEb_CLGRJ : RIEb_CGRJ)); 1700 tgen_compare_branch(s, opc, cc, r1, c2, l); 1701 return; 1702 } 1703 1704 /* 1705 * COMPARE IMMEDIATE AND BRANCH RELATIVE has an 8-bit immediate field. 1706 * If the immediate we've been given does not fit that range, we'll 1707 * fall back to separate compare and branch instructions using the 1708 * larger comparison range afforded by COMPARE IMMEDIATE. 1709 */ 1710 if (type == TCG_TYPE_I32) { 1711 if (is_unsigned) { 1712 opc = RIEc_CLIJ; 1713 in_range = (uint32_t)c2 == (uint8_t)c2; 1714 } else { 1715 opc = RIEc_CIJ; 1716 in_range = (int32_t)c2 == (int8_t)c2; 1717 } 1718 } else { 1719 if (is_unsigned) { 1720 opc = RIEc_CLGIJ; 1721 in_range = (uint64_t)c2 == (uint8_t)c2; 1722 } else { 1723 opc = RIEc_CGIJ; 1724 in_range = (int64_t)c2 == (int8_t)c2; 1725 } 1726 } 1727 if (in_range) { 1728 tgen_compare_imm_branch(s, opc, cc, r1, c2, l); 1729 return; 1730 } 1731 } 1732 1733 cc = tgen_cmp(s, type, c, r1, c2, c2const, false); 1734 tgen_branch(s, cc, l); 1735} 1736 1737static void tgen_brcondr(TCGContext *s, TCGType type, TCGCond c, 1738 TCGReg a0, TCGReg a1, TCGLabel *l) 1739{ 1740 tgen_brcond(s, type, c, a0, a1, false, l); 1741} 1742 1743static void tgen_brcondi(TCGContext *s, TCGType type, TCGCond c, 1744 TCGReg a0, tcg_target_long a1, TCGLabel *l) 1745{ 1746 tgen_brcond(s, type, c, a0, a1, true, l); 1747} 1748 1749static const TCGOutOpBrcond outop_brcond = { 1750 .base.static_constraint = C_O0_I2(r, rC), 1751 .out_rr = tgen_brcondr, 1752 .out_ri = tgen_brcondi, 1753}; 1754 1755static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *dest) 1756{ 1757 ptrdiff_t off = tcg_pcrel_diff(s, dest) >> 1; 1758 if (off == (int32_t)off) { 1759 tcg_out_insn(s, RIL, BRASL, TCG_REG_R14, off); 1760 } else { 1761 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)dest); 1762 tcg_out_insn(s, RR, BASR, TCG_REG_R14, TCG_TMP0); 1763 } 1764} 1765 1766static void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest, 1767 const TCGHelperInfo *info) 1768{ 1769 tcg_out_call_int(s, dest); 1770} 1771 1772typedef struct { 1773 TCGReg base; 1774 TCGReg index; 1775 int disp; 1776 TCGAtomAlign aa; 1777} HostAddress; 1778 1779bool tcg_target_has_memory_bswap(MemOp memop) 1780{ 1781 TCGAtomAlign aa; 1782 1783 if ((memop & MO_SIZE) <= MO_64) { 1784 return true; 1785 } 1786 1787 /* 1788 * Reject 16-byte memop with 16-byte atomicity, 1789 * but do allow a pair of 64-bit operations. 1790 */ 1791 aa = atom_and_align_for_opc(tcg_ctx, memop, MO_ATOM_IFALIGN, true); 1792 return aa.atom <= MO_64; 1793} 1794 1795static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg data, 1796 HostAddress h) 1797{ 1798 switch (opc & (MO_SSIZE | MO_BSWAP)) { 1799 case MO_UB: 1800 tcg_out_insn(s, RXY, LLGC, data, h.base, h.index, h.disp); 1801 break; 1802 case MO_SB: 1803 tcg_out_insn(s, RXY, LGB, data, h.base, h.index, h.disp); 1804 break; 1805 1806 case MO_UW | MO_BSWAP: 1807 /* swapped unsigned halfword load with upper bits zeroed */ 1808 tcg_out_insn(s, RXY, LRVH, data, h.base, h.index, h.disp); 1809 tcg_out_ext16u(s, data, data); 1810 break; 1811 case MO_UW: 1812 tcg_out_insn(s, RXY, LLGH, data, h.base, h.index, h.disp); 1813 break; 1814 1815 case MO_SW | MO_BSWAP: 1816 /* swapped sign-extended halfword load */ 1817 tcg_out_insn(s, RXY, LRVH, data, h.base, h.index, h.disp); 1818 tcg_out_ext16s(s, TCG_TYPE_REG, data, data); 1819 break; 1820 case MO_SW: 1821 tcg_out_insn(s, RXY, LGH, data, h.base, h.index, h.disp); 1822 break; 1823 1824 case MO_UL | MO_BSWAP: 1825 /* swapped unsigned int load with upper bits zeroed */ 1826 tcg_out_insn(s, RXY, LRV, data, h.base, h.index, h.disp); 1827 tcg_out_ext32u(s, data, data); 1828 break; 1829 case MO_UL: 1830 tcg_out_insn(s, RXY, LLGF, data, h.base, h.index, h.disp); 1831 break; 1832 1833 case MO_SL | MO_BSWAP: 1834 /* swapped sign-extended int load */ 1835 tcg_out_insn(s, RXY, LRV, data, h.base, h.index, h.disp); 1836 tcg_out_ext32s(s, data, data); 1837 break; 1838 case MO_SL: 1839 tcg_out_insn(s, RXY, LGF, data, h.base, h.index, h.disp); 1840 break; 1841 1842 case MO_UQ | MO_BSWAP: 1843 tcg_out_insn(s, RXY, LRVG, data, h.base, h.index, h.disp); 1844 break; 1845 case MO_UQ: 1846 tcg_out_insn(s, RXY, LG, data, h.base, h.index, h.disp); 1847 break; 1848 1849 default: 1850 g_assert_not_reached(); 1851 } 1852} 1853 1854static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg data, 1855 HostAddress h) 1856{ 1857 switch (opc & (MO_SIZE | MO_BSWAP)) { 1858 case MO_UB: 1859 if (h.disp >= 0 && h.disp < 0x1000) { 1860 tcg_out_insn(s, RX, STC, data, h.base, h.index, h.disp); 1861 } else { 1862 tcg_out_insn(s, RXY, STCY, data, h.base, h.index, h.disp); 1863 } 1864 break; 1865 1866 case MO_UW | MO_BSWAP: 1867 tcg_out_insn(s, RXY, STRVH, data, h.base, h.index, h.disp); 1868 break; 1869 case MO_UW: 1870 if (h.disp >= 0 && h.disp < 0x1000) { 1871 tcg_out_insn(s, RX, STH, data, h.base, h.index, h.disp); 1872 } else { 1873 tcg_out_insn(s, RXY, STHY, data, h.base, h.index, h.disp); 1874 } 1875 break; 1876 1877 case MO_UL | MO_BSWAP: 1878 tcg_out_insn(s, RXY, STRV, data, h.base, h.index, h.disp); 1879 break; 1880 case MO_UL: 1881 if (h.disp >= 0 && h.disp < 0x1000) { 1882 tcg_out_insn(s, RX, ST, data, h.base, h.index, h.disp); 1883 } else { 1884 tcg_out_insn(s, RXY, STY, data, h.base, h.index, h.disp); 1885 } 1886 break; 1887 1888 case MO_UQ | MO_BSWAP: 1889 tcg_out_insn(s, RXY, STRVG, data, h.base, h.index, h.disp); 1890 break; 1891 case MO_UQ: 1892 tcg_out_insn(s, RXY, STG, data, h.base, h.index, h.disp); 1893 break; 1894 1895 default: 1896 g_assert_not_reached(); 1897 } 1898} 1899 1900static const TCGLdstHelperParam ldst_helper_param = { 1901 .ntmp = 1, .tmp = { TCG_TMP0 } 1902}; 1903 1904static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1905{ 1906 MemOp opc = get_memop(lb->oi); 1907 1908 if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL, 1909 (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 2)) { 1910 return false; 1911 } 1912 1913 tcg_out_ld_helper_args(s, lb, &ldst_helper_param); 1914 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE]); 1915 tcg_out_ld_helper_ret(s, lb, false, &ldst_helper_param); 1916 1917 tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr); 1918 return true; 1919} 1920 1921static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1922{ 1923 MemOp opc = get_memop(lb->oi); 1924 1925 if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL, 1926 (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 2)) { 1927 return false; 1928 } 1929 1930 tcg_out_st_helper_args(s, lb, &ldst_helper_param); 1931 tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE]); 1932 1933 tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr); 1934 return true; 1935} 1936 1937/* We're expecting to use a 20-bit negative offset on the tlb memory ops. */ 1938#define MIN_TLB_MASK_TABLE_OFS -(1 << 19) 1939 1940/* 1941 * For system-mode, perform the TLB load and compare. 1942 * For user-mode, perform any required alignment tests. 1943 * In both cases, return a TCGLabelQemuLdst structure if the slow path 1944 * is required and fill in @h with the host address for the fast path. 1945 */ 1946static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 1947 TCGReg addr_reg, MemOpIdx oi, 1948 bool is_ld) 1949{ 1950 TCGType addr_type = s->addr_type; 1951 TCGLabelQemuLdst *ldst = NULL; 1952 MemOp opc = get_memop(oi); 1953 MemOp s_bits = opc & MO_SIZE; 1954 unsigned a_mask; 1955 1956 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, s_bits == MO_128); 1957 a_mask = (1 << h->aa.align) - 1; 1958 1959 if (tcg_use_softmmu) { 1960 unsigned s_mask = (1 << s_bits) - 1; 1961 int mem_index = get_mmuidx(oi); 1962 int fast_off = tlb_mask_table_ofs(s, mem_index); 1963 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); 1964 int table_off = fast_off + offsetof(CPUTLBDescFast, table); 1965 int ofs, a_off; 1966 uint64_t tlb_mask; 1967 1968 ldst = new_ldst_label(s); 1969 ldst->is_ld = is_ld; 1970 ldst->oi = oi; 1971 ldst->addr_reg = addr_reg; 1972 1973 tcg_out_sh64(s, RSY_SRLG, TCG_TMP0, addr_reg, TCG_REG_NONE, 1974 s->page_bits - CPU_TLB_ENTRY_BITS); 1975 1976 tcg_out_insn(s, RXY, NG, TCG_TMP0, TCG_AREG0, TCG_REG_NONE, mask_off); 1977 tcg_out_insn(s, RXY, AG, TCG_TMP0, TCG_AREG0, TCG_REG_NONE, table_off); 1978 1979 /* 1980 * For aligned accesses, we check the first byte and include the 1981 * alignment bits within the address. For unaligned access, we 1982 * check that we don't cross pages using the address of the last 1983 * byte of the access. 1984 */ 1985 a_off = (a_mask >= s_mask ? 0 : s_mask - a_mask); 1986 tlb_mask = (uint64_t)s->page_mask | a_mask; 1987 if (a_off == 0) { 1988 tgen_andi_risbg(s, TCG_REG_R0, addr_reg, tlb_mask); 1989 } else { 1990 tcg_out_insn(s, RX, LA, TCG_REG_R0, addr_reg, TCG_REG_NONE, a_off); 1991 tgen_andi(s, addr_type, TCG_REG_R0, tlb_mask); 1992 } 1993 1994 if (is_ld) { 1995 ofs = offsetof(CPUTLBEntry, addr_read); 1996 } else { 1997 ofs = offsetof(CPUTLBEntry, addr_write); 1998 } 1999 if (addr_type == TCG_TYPE_I32) { 2000 ofs += HOST_BIG_ENDIAN * 4; 2001 tcg_out_insn(s, RX, C, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs); 2002 } else { 2003 tcg_out_insn(s, RXY, CG, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs); 2004 } 2005 2006 tcg_out16(s, RI_BRC | (S390_CC_NE << 4)); 2007 ldst->label_ptr[0] = s->code_ptr++; 2008 2009 h->index = TCG_TMP0; 2010 tcg_out_insn(s, RXY, LG, h->index, TCG_TMP0, TCG_REG_NONE, 2011 offsetof(CPUTLBEntry, addend)); 2012 2013 if (addr_type == TCG_TYPE_I32) { 2014 tcg_out_insn(s, RRE, ALGFR, h->index, addr_reg); 2015 h->base = TCG_REG_NONE; 2016 } else { 2017 h->base = addr_reg; 2018 } 2019 h->disp = 0; 2020 } else { 2021 if (a_mask) { 2022 ldst = new_ldst_label(s); 2023 ldst->is_ld = is_ld; 2024 ldst->oi = oi; 2025 ldst->addr_reg = addr_reg; 2026 2027 tcg_debug_assert(a_mask <= 0xffff); 2028 tcg_out_insn(s, RI, TMLL, addr_reg, a_mask); 2029 2030 tcg_out16(s, RI_BRC | (S390_TM_NE << 4)); 2031 ldst->label_ptr[0] = s->code_ptr++; 2032 } 2033 2034 h->base = addr_reg; 2035 if (addr_type == TCG_TYPE_I32) { 2036 tcg_out_ext32u(s, TCG_TMP0, addr_reg); 2037 h->base = TCG_TMP0; 2038 } 2039 if (guest_base < 0x80000) { 2040 h->index = TCG_REG_NONE; 2041 h->disp = guest_base; 2042 } else { 2043 h->index = TCG_GUEST_BASE_REG; 2044 h->disp = 0; 2045 } 2046 } 2047 2048 return ldst; 2049} 2050 2051static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_reg, 2052 MemOpIdx oi, TCGType data_type) 2053{ 2054 TCGLabelQemuLdst *ldst; 2055 HostAddress h; 2056 2057 ldst = prepare_host_addr(s, &h, addr_reg, oi, true); 2058 tcg_out_qemu_ld_direct(s, get_memop(oi), data_reg, h); 2059 2060 if (ldst) { 2061 ldst->type = data_type; 2062 ldst->datalo_reg = data_reg; 2063 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 2064 } 2065} 2066 2067static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_reg, 2068 MemOpIdx oi, TCGType data_type) 2069{ 2070 TCGLabelQemuLdst *ldst; 2071 HostAddress h; 2072 2073 ldst = prepare_host_addr(s, &h, addr_reg, oi, false); 2074 tcg_out_qemu_st_direct(s, get_memop(oi), data_reg, h); 2075 2076 if (ldst) { 2077 ldst->type = data_type; 2078 ldst->datalo_reg = data_reg; 2079 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 2080 } 2081} 2082 2083static void tcg_out_qemu_ldst_i128(TCGContext *s, TCGReg datalo, TCGReg datahi, 2084 TCGReg addr_reg, MemOpIdx oi, bool is_ld) 2085{ 2086 TCGLabel *l1 = NULL, *l2 = NULL; 2087 TCGLabelQemuLdst *ldst; 2088 HostAddress h; 2089 bool need_bswap; 2090 bool use_pair; 2091 S390Opcode insn; 2092 2093 ldst = prepare_host_addr(s, &h, addr_reg, oi, is_ld); 2094 2095 use_pair = h.aa.atom < MO_128; 2096 need_bswap = get_memop(oi) & MO_BSWAP; 2097 2098 if (!use_pair) { 2099 /* 2100 * Atomicity requires we use LPQ. If we've already checked for 2101 * 16-byte alignment, that's all we need. If we arrive with 2102 * lesser alignment, we have determined that less than 16-byte 2103 * alignment can be satisfied with two 8-byte loads. 2104 */ 2105 if (h.aa.align < MO_128) { 2106 use_pair = true; 2107 l1 = gen_new_label(); 2108 l2 = gen_new_label(); 2109 2110 tcg_out_insn(s, RI, TMLL, addr_reg, 15); 2111 tgen_branch(s, S390_TM_NE, l1); 2112 } 2113 2114 tcg_debug_assert(!need_bswap); 2115 tcg_debug_assert(datalo & 1); 2116 tcg_debug_assert(datahi == datalo - 1); 2117 insn = is_ld ? RXY_LPQ : RXY_STPQ; 2118 tcg_out_insn_RXY(s, insn, datahi, h.base, h.index, h.disp); 2119 2120 if (use_pair) { 2121 tgen_branch(s, S390_CC_ALWAYS, l2); 2122 tcg_out_label(s, l1); 2123 } 2124 } 2125 if (use_pair) { 2126 TCGReg d1, d2; 2127 2128 if (need_bswap) { 2129 d1 = datalo, d2 = datahi; 2130 insn = is_ld ? RXY_LRVG : RXY_STRVG; 2131 } else { 2132 d1 = datahi, d2 = datalo; 2133 insn = is_ld ? RXY_LG : RXY_STG; 2134 } 2135 2136 if (h.base == d1 || h.index == d1) { 2137 tcg_out_insn(s, RXY, LAY, TCG_TMP0, h.base, h.index, h.disp); 2138 h.base = TCG_TMP0; 2139 h.index = TCG_REG_NONE; 2140 h.disp = 0; 2141 } 2142 tcg_out_insn_RXY(s, insn, d1, h.base, h.index, h.disp); 2143 tcg_out_insn_RXY(s, insn, d2, h.base, h.index, h.disp + 8); 2144 } 2145 if (l2) { 2146 tcg_out_label(s, l2); 2147 } 2148 2149 if (ldst) { 2150 ldst->type = TCG_TYPE_I128; 2151 ldst->datalo_reg = datalo; 2152 ldst->datahi_reg = datahi; 2153 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 2154 } 2155} 2156 2157static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) 2158{ 2159 /* Reuse the zeroing that exists for goto_ptr. */ 2160 if (a0 == 0) { 2161 tgen_gotoi(s, S390_CC_ALWAYS, tcg_code_gen_epilogue); 2162 } else { 2163 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, a0); 2164 tgen_gotoi(s, S390_CC_ALWAYS, tb_ret_addr); 2165 } 2166} 2167 2168static void tcg_out_goto_tb(TCGContext *s, int which) 2169{ 2170 /* 2171 * Branch displacement must be aligned for atomic patching; 2172 * see if we need to add extra nop before branch 2173 */ 2174 if (!QEMU_PTR_IS_ALIGNED(s->code_ptr + 1, 4)) { 2175 tcg_out16(s, NOP); 2176 } 2177 tcg_out16(s, RIL_BRCL | (S390_CC_ALWAYS << 4)); 2178 set_jmp_insn_offset(s, which); 2179 s->code_ptr += 2; 2180 set_jmp_reset_offset(s, which); 2181} 2182 2183void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 2184 uintptr_t jmp_rx, uintptr_t jmp_rw) 2185{ 2186 if (!HAVE_FACILITY(GEN_INST_EXT)) { 2187 return; 2188 } 2189 /* patch the branch destination */ 2190 uintptr_t addr = tb->jmp_target_addr[n]; 2191 intptr_t disp = addr - (jmp_rx - 2); 2192 qatomic_set((int32_t *)jmp_rw, disp / 2); 2193 /* no need to flush icache explicitly */ 2194} 2195 2196 2197static void tgen_add(TCGContext *s, TCGType type, 2198 TCGReg a0, TCGReg a1, TCGReg a2) 2199{ 2200 if (a0 != a1) { 2201 tcg_out_insn(s, RX, LA, a0, a1, a2, 0); 2202 } else if (type == TCG_TYPE_I32) { 2203 tcg_out_insn(s, RR, AR, a0, a2); 2204 } else { 2205 tcg_out_insn(s, RRE, AGR, a0, a2); 2206 } 2207} 2208 2209static void tgen_addi(TCGContext *s, TCGType type, 2210 TCGReg a0, TCGReg a1, tcg_target_long a2) 2211{ 2212 if (a0 == a1) { 2213 if (type == TCG_TYPE_I32) { 2214 if (a2 == (int16_t)a2) { 2215 tcg_out_insn(s, RI, AHI, a0, a2); 2216 } else { 2217 tcg_out_insn(s, RIL, AFI, a0, a2); 2218 } 2219 return; 2220 } 2221 if (a2 == (int16_t)a2) { 2222 tcg_out_insn(s, RI, AGHI, a0, a2); 2223 return; 2224 } 2225 if (a2 == (int32_t)a2) { 2226 tcg_out_insn(s, RIL, AGFI, a0, a2); 2227 return; 2228 } 2229 if (a2 == (uint32_t)a2) { 2230 tcg_out_insn(s, RIL, ALGFI, a0, a2); 2231 return; 2232 } 2233 if (-a2 == (uint32_t)-a2) { 2234 tcg_out_insn(s, RIL, SLGFI, a0, -a2); 2235 return; 2236 } 2237 } 2238 tcg_out_mem(s, RX_LA, RXY_LAY, a0, a1, TCG_REG_NONE, a2); 2239} 2240 2241static const TCGOutOpBinary outop_add = { 2242 .base.static_constraint = C_O1_I2(r, r, ri), 2243 .out_rrr = tgen_add, 2244 .out_rri = tgen_addi, 2245}; 2246 2247static void tgen_and(TCGContext *s, TCGType type, 2248 TCGReg a0, TCGReg a1, TCGReg a2) 2249{ 2250 if (type != TCG_TYPE_I32) { 2251 tcg_out_insn(s, RRFa, NGRK, a0, a1, a2); 2252 } else if (a0 == a1) { 2253 tcg_out_insn(s, RR, NR, a0, a2); 2254 } else { 2255 tcg_out_insn(s, RRFa, NRK, a0, a1, a2); 2256 } 2257} 2258 2259static void tgen_andi_3(TCGContext *s, TCGType type, 2260 TCGReg a0, TCGReg a1, tcg_target_long a2) 2261{ 2262 tcg_out_mov(s, type, a0, a1); 2263 tgen_andi(s, type, a0, a2); 2264} 2265 2266static const TCGOutOpBinary outop_and = { 2267 .base.static_constraint = C_O1_I2(r, r, rNKR), 2268 .out_rrr = tgen_and, 2269 .out_rri = tgen_andi_3, 2270}; 2271 2272static void tgen_andc(TCGContext *s, TCGType type, 2273 TCGReg a0, TCGReg a1, TCGReg a2) 2274{ 2275 if (type == TCG_TYPE_I32) { 2276 tcg_out_insn(s, RRFa, NCRK, a0, a1, a2); 2277 } else { 2278 tcg_out_insn(s, RRFa, NCGRK, a0, a1, a2); 2279 } 2280} 2281 2282static TCGConstraintSetIndex cset_misc3_rrr(TCGType type, unsigned flags) 2283{ 2284 return HAVE_FACILITY(MISC_INSN_EXT3) ? C_O1_I2(r, r, r) : C_NotImplemented; 2285} 2286 2287static const TCGOutOpBinary outop_andc = { 2288 .base.static_constraint = C_Dynamic, 2289 .base.dynamic_constraint = cset_misc3_rrr, 2290 .out_rrr = tgen_andc, 2291}; 2292 2293static void tgen_clz_int(TCGContext *s, TCGReg dest, TCGReg a1, 2294 TCGArg a2, int a2const) 2295{ 2296 /* 2297 * Since this sets both R and R+1, we have no choice but to store the 2298 * result into R0, allowing R1 == TCG_TMP0 to be clobbered as well. 2299 */ 2300 QEMU_BUILD_BUG_ON(TCG_TMP0 != TCG_REG_R1); 2301 tcg_out_insn(s, RRE, FLOGR, TCG_REG_R0, a1); 2302 2303 if (a2const && a2 == 64) { 2304 tcg_out_mov(s, TCG_TYPE_I64, dest, TCG_REG_R0); 2305 return; 2306 } 2307 2308 /* 2309 * Conditions from FLOGR are: 2310 * 2 -> one bit found 2311 * 8 -> no one bit found 2312 */ 2313 tgen_movcond_int(s, TCG_TYPE_I64, dest, a2, a2const, TCG_REG_R0, 8, 2); 2314} 2315 2316static void tgen_clz(TCGContext *s, TCGType type, 2317 TCGReg a0, TCGReg a1, TCGReg a2) 2318{ 2319 tgen_clz_int(s, a0, a1, a2, false); 2320} 2321 2322static void tgen_clzi(TCGContext *s, TCGType type, 2323 TCGReg a0, TCGReg a1, tcg_target_long a2) 2324{ 2325 tgen_clz_int(s, a0, a1, a2, true); 2326} 2327 2328static TCGConstraintSetIndex cset_clz(TCGType type, unsigned flags) 2329{ 2330 return type == TCG_TYPE_I64 ? C_O1_I2(r, r, rI) : C_NotImplemented; 2331} 2332 2333static const TCGOutOpBinary outop_clz = { 2334 .base.static_constraint = C_Dynamic, 2335 .base.dynamic_constraint = cset_clz, 2336 .out_rrr = tgen_clz, 2337 .out_rri = tgen_clzi, 2338}; 2339 2340static void tgen_ctpop(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) 2341{ 2342 /* With MIE3, and bit 0 of m4 set, we get the complete result. */ 2343 if (HAVE_FACILITY(MISC_INSN_EXT3)) { 2344 if (type == TCG_TYPE_I32) { 2345 tcg_out_ext32u(s, dest, src); 2346 src = dest; 2347 } 2348 tcg_out_insn(s, RRFc, POPCNT, dest, src, 8); 2349 return; 2350 } 2351 2352 /* Without MIE3, each byte gets the count of bits for the byte. */ 2353 tcg_out_insn(s, RRFc, POPCNT, dest, src, 0); 2354 2355 /* Multiply to sum each byte at the top of the word. */ 2356 if (type == TCG_TYPE_I32) { 2357 tcg_out_insn(s, RIL, MSFI, dest, 0x01010101); 2358 tcg_out_sh32(s, RS_SRL, dest, TCG_REG_NONE, 24); 2359 } else { 2360 tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 0x0101010101010101ull); 2361 tcg_out_insn(s, RRE, MSGR, dest, TCG_TMP0); 2362 tcg_out_sh64(s, RSY_SRLG, dest, dest, TCG_REG_NONE, 56); 2363 } 2364} 2365 2366static const TCGOutOpUnary outop_ctpop = { 2367 .base.static_constraint = C_O1_I1(r, r), 2368 .out_rr = tgen_ctpop, 2369}; 2370 2371static const TCGOutOpBinary outop_ctz = { 2372 .base.static_constraint = C_NotImplemented, 2373}; 2374 2375static const TCGOutOpBinary outop_divs = { 2376 .base.static_constraint = C_NotImplemented, 2377}; 2378 2379static void tgen_divs2(TCGContext *s, TCGType type, 2380 TCGReg a0, TCGReg a1, TCGReg a4) 2381{ 2382 tcg_debug_assert((a1 & 1) == 0); 2383 tcg_debug_assert(a0 == a1 + 1); 2384 if (type == TCG_TYPE_I32) { 2385 tcg_out_insn(s, RR, DR, a1, a4); 2386 } else { 2387 /* 2388 * TODO: Move the sign-extend of the numerator from a2 into a3 2389 * into the tcg backend, instead of in early expansion. It is 2390 * required for 32-bit DR, but not 64-bit DSGR. 2391 */ 2392 tcg_out_insn(s, RRE, DSGR, a1, a4); 2393 } 2394} 2395 2396static const TCGOutOpDivRem outop_divs2 = { 2397 .base.static_constraint = C_O2_I3(o, m, 0, 1, r), 2398 .out_rr01r = tgen_divs2, 2399}; 2400 2401static const TCGOutOpBinary outop_divu = { 2402 .base.static_constraint = C_NotImplemented, 2403}; 2404 2405static void tgen_divu2(TCGContext *s, TCGType type, 2406 TCGReg a0, TCGReg a1, TCGReg a4) 2407{ 2408 tcg_debug_assert((a1 & 1) == 0); 2409 tcg_debug_assert(a0 == a1 + 1); 2410 if (type == TCG_TYPE_I32) { 2411 tcg_out_insn(s, RRE, DLR, a1, a4); 2412 } else { 2413 tcg_out_insn(s, RRE, DLGR, a1, a4); 2414 } 2415} 2416 2417static const TCGOutOpDivRem outop_divu2 = { 2418 .base.static_constraint = C_O2_I3(o, m, 0, 1, r), 2419 .out_rr01r = tgen_divu2, 2420}; 2421 2422static void tgen_eqv(TCGContext *s, TCGType type, 2423 TCGReg a0, TCGReg a1, TCGReg a2) 2424{ 2425 if (type == TCG_TYPE_I32) { 2426 tcg_out_insn(s, RRFa, NXRK, a0, a1, a2); 2427 } else { 2428 tcg_out_insn(s, RRFa, NXGRK, a0, a1, a2); 2429 } 2430} 2431 2432static const TCGOutOpBinary outop_eqv = { 2433 .base.static_constraint = C_Dynamic, 2434 .base.dynamic_constraint = cset_misc3_rrr, 2435 .out_rrr = tgen_eqv, 2436}; 2437 2438static void tgen_extrh_i64_i32(TCGContext *s, TCGType t, TCGReg a0, TCGReg a1) 2439{ 2440 tcg_out_sh64(s, RSY_SRLG, a0, a1, TCG_REG_NONE, 32); 2441} 2442 2443static const TCGOutOpUnary outop_extrh_i64_i32 = { 2444 .base.static_constraint = C_O1_I1(r, r), 2445 .out_rr = tgen_extrh_i64_i32, 2446}; 2447 2448static void tgen_mul(TCGContext *s, TCGType type, 2449 TCGReg a0, TCGReg a1, TCGReg a2) 2450{ 2451 if (type == TCG_TYPE_I32) { 2452 if (a0 == a1) { 2453 tcg_out_insn(s, RRE, MSR, a0, a2); 2454 } else { 2455 tcg_out_insn(s, RRFa, MSRKC, a0, a1, a2); 2456 } 2457 } else { 2458 if (a0 == a1) { 2459 tcg_out_insn(s, RRE, MSGR, a0, a2); 2460 } else { 2461 tcg_out_insn(s, RRFa, MSGRKC, a0, a1, a2); 2462 } 2463 } 2464} 2465 2466static void tgen_muli(TCGContext *s, TCGType type, 2467 TCGReg a0, TCGReg a1, tcg_target_long a2) 2468{ 2469 tcg_out_mov(s, type, a0, a1); 2470 if (type == TCG_TYPE_I32) { 2471 if (a2 == (int16_t)a2) { 2472 tcg_out_insn(s, RI, MHI, a0, a2); 2473 } else { 2474 tcg_out_insn(s, RIL, MSFI, a0, a2); 2475 } 2476 } else { 2477 if (a2 == (int16_t)a2) { 2478 tcg_out_insn(s, RI, MGHI, a0, a2); 2479 } else { 2480 tcg_out_insn(s, RIL, MSGFI, a0, a2); 2481 } 2482 } 2483} 2484 2485static TCGConstraintSetIndex cset_mul(TCGType type, unsigned flags) 2486{ 2487 return (HAVE_FACILITY(MISC_INSN_EXT2) 2488 ? C_O1_I2(r, r, rJ) 2489 : C_O1_I2(r, 0, rJ)); 2490} 2491 2492static const TCGOutOpBinary outop_mul = { 2493 .base.static_constraint = C_Dynamic, 2494 .base.dynamic_constraint = cset_mul, 2495 .out_rrr = tgen_mul, 2496 .out_rri = tgen_muli, 2497}; 2498 2499static void tgen_muls2(TCGContext *s, TCGType type, 2500 TCGReg a0, TCGReg a1, TCGReg a2, TCGReg a3) 2501{ 2502 tcg_debug_assert((a1 & 1) == 0); 2503 tcg_debug_assert(a0 == a1 + 1); 2504 tcg_out_insn(s, RRFa, MGRK, a1, a2, a3); 2505} 2506 2507static TCGConstraintSetIndex cset_muls2(TCGType type, unsigned flags) 2508{ 2509 return (type == TCG_TYPE_I64 && HAVE_FACILITY(MISC_INSN_EXT2) 2510 ? C_O2_I2(o, m, r, r) : C_NotImplemented); 2511} 2512 2513static const TCGOutOpMul2 outop_muls2 = { 2514 .base.static_constraint = C_Dynamic, 2515 .base.dynamic_constraint = cset_muls2, 2516 .out_rrrr = tgen_muls2, 2517}; 2518 2519static const TCGOutOpBinary outop_mulsh = { 2520 .base.static_constraint = C_NotImplemented, 2521}; 2522 2523static void tgen_mulu2(TCGContext *s, TCGType type, 2524 TCGReg a0, TCGReg a1, TCGReg a2, TCGReg a3) 2525{ 2526 tcg_debug_assert(a0 == a2); 2527 tcg_debug_assert((a1 & 1) == 0); 2528 tcg_debug_assert(a0 == a1 + 1); 2529 tcg_out_insn(s, RRE, MLGR, a1, a3); 2530} 2531 2532static TCGConstraintSetIndex cset_mulu2(TCGType type, unsigned flags) 2533{ 2534 return (type == TCG_TYPE_I64 && HAVE_FACILITY(MISC_INSN_EXT2) 2535 ? C_O2_I2(o, m, 0, r) : C_NotImplemented); 2536} 2537 2538static const TCGOutOpMul2 outop_mulu2 = { 2539 .base.static_constraint = C_Dynamic, 2540 .base.dynamic_constraint = cset_mulu2, 2541 .out_rrrr = tgen_mulu2, 2542}; 2543 2544static const TCGOutOpBinary outop_muluh = { 2545 .base.static_constraint = C_NotImplemented, 2546}; 2547 2548static void tgen_nand(TCGContext *s, TCGType type, 2549 TCGReg a0, TCGReg a1, TCGReg a2) 2550{ 2551 if (type == TCG_TYPE_I32) { 2552 tcg_out_insn(s, RRFa, NNRK, a0, a1, a2); 2553 } else { 2554 tcg_out_insn(s, RRFa, NNGRK, a0, a1, a2); 2555 } 2556} 2557 2558static const TCGOutOpBinary outop_nand = { 2559 .base.static_constraint = C_Dynamic, 2560 .base.dynamic_constraint = cset_misc3_rrr, 2561 .out_rrr = tgen_nand, 2562}; 2563 2564static void tgen_nor(TCGContext *s, TCGType type, 2565 TCGReg a0, TCGReg a1, TCGReg a2) 2566{ 2567 if (type == TCG_TYPE_I32) { 2568 tcg_out_insn(s, RRFa, NORK, a0, a1, a2); 2569 } else { 2570 tcg_out_insn(s, RRFa, NOGRK, a0, a1, a2); 2571 } 2572} 2573 2574static const TCGOutOpBinary outop_nor = { 2575 .base.static_constraint = C_Dynamic, 2576 .base.dynamic_constraint = cset_misc3_rrr, 2577 .out_rrr = tgen_nor, 2578}; 2579 2580static void tgen_or(TCGContext *s, TCGType type, 2581 TCGReg a0, TCGReg a1, TCGReg a2) 2582{ 2583 if (type != TCG_TYPE_I32) { 2584 tcg_out_insn(s, RRFa, OGRK, a0, a1, a2); 2585 } else if (a0 == a1) { 2586 tcg_out_insn(s, RR, OR, a0, a2); 2587 } else { 2588 tcg_out_insn(s, RRFa, ORK, a0, a1, a2); 2589 } 2590} 2591 2592static void tgen_ori_3(TCGContext *s, TCGType type, 2593 TCGReg a0, TCGReg a1, tcg_target_long a2) 2594{ 2595 tcg_out_mov(s, type, a0, a1); 2596 tgen_ori(s, a0, type == TCG_TYPE_I32 ? (uint32_t)a2 : a2); 2597} 2598 2599static const TCGOutOpBinary outop_or = { 2600 .base.static_constraint = C_O1_I2(r, r, rK), 2601 .out_rrr = tgen_or, 2602 .out_rri = tgen_ori_3, 2603}; 2604 2605static void tgen_orc(TCGContext *s, TCGType type, 2606 TCGReg a0, TCGReg a1, TCGReg a2) 2607{ 2608 if (type == TCG_TYPE_I32) { 2609 tcg_out_insn(s, RRFa, OCRK, a0, a1, a2); 2610 } else { 2611 tcg_out_insn(s, RRFa, OCGRK, a0, a1, a2); 2612 } 2613} 2614 2615static const TCGOutOpBinary outop_orc = { 2616 .base.static_constraint = C_Dynamic, 2617 .base.dynamic_constraint = cset_misc3_rrr, 2618 .out_rrr = tgen_orc, 2619}; 2620 2621static const TCGOutOpBinary outop_rems = { 2622 .base.static_constraint = C_NotImplemented, 2623}; 2624 2625static const TCGOutOpBinary outop_remu = { 2626 .base.static_constraint = C_NotImplemented, 2627}; 2628 2629static void tgen_rotl_int(TCGContext *s, TCGType type, TCGReg dst, 2630 TCGReg src, TCGReg v, tcg_target_long i) 2631{ 2632 S390Opcode insn = type == TCG_TYPE_I32 ? RSY_RLL : RSY_RLLG; 2633 tcg_out_sh64(s, insn, dst, src, v, i); 2634} 2635 2636static void tgen_rotl(TCGContext *s, TCGType type, 2637 TCGReg a0, TCGReg a1, TCGReg a2) 2638{ 2639 tgen_rotl_int(s, type, a0, a1, a2, 0); 2640} 2641 2642static void tgen_rotli(TCGContext *s, TCGType type, 2643 TCGReg a0, TCGReg a1, tcg_target_long a2) 2644{ 2645 tgen_rotl_int(s, type, a0, a1, TCG_REG_NONE, a2); 2646} 2647 2648static const TCGOutOpBinary outop_rotl = { 2649 .base.static_constraint = C_O1_I2(r, r, ri), 2650 .out_rrr = tgen_rotl, 2651 .out_rri = tgen_rotli, 2652}; 2653 2654static const TCGOutOpBinary outop_rotr = { 2655 .base.static_constraint = C_NotImplemented, 2656}; 2657 2658static void tgen_sar_int(TCGContext *s, TCGType type, TCGReg dst, 2659 TCGReg src, TCGReg v, tcg_target_long i) 2660{ 2661 if (type != TCG_TYPE_I32) { 2662 tcg_out_sh64(s, RSY_SRAG, dst, src, v, i); 2663 } else if (dst == src) { 2664 tcg_out_sh32(s, RS_SRA, dst, v, i); 2665 } else { 2666 tcg_out_sh64(s, RSY_SRAK, dst, src, v, i); 2667 } 2668} 2669 2670static void tgen_sar(TCGContext *s, TCGType type, 2671 TCGReg a0, TCGReg a1, TCGReg a2) 2672{ 2673 tgen_sar_int(s, type, a0, a1, a2, 0); 2674} 2675 2676static void tgen_sari(TCGContext *s, TCGType type, 2677 TCGReg a0, TCGReg a1, tcg_target_long a2) 2678{ 2679 tgen_sar_int(s, type, a0, a1, TCG_REG_NONE, a2); 2680} 2681 2682static const TCGOutOpBinary outop_sar = { 2683 .base.static_constraint = C_O1_I2(r, r, ri), 2684 .out_rrr = tgen_sar, 2685 .out_rri = tgen_sari, 2686}; 2687 2688static void tgen_shl_int(TCGContext *s, TCGType type, TCGReg dst, 2689 TCGReg src, TCGReg v, tcg_target_long i) 2690{ 2691 if (type != TCG_TYPE_I32) { 2692 tcg_out_sh64(s, RSY_SLLG, dst, src, v, i); 2693 } else if (dst == src) { 2694 tcg_out_sh32(s, RS_SLL, dst, v, i); 2695 } else { 2696 tcg_out_sh64(s, RSY_SLLK, dst, src, v, i); 2697 } 2698} 2699 2700static void tgen_shl(TCGContext *s, TCGType type, 2701 TCGReg a0, TCGReg a1, TCGReg a2) 2702{ 2703 tgen_shl_int(s, type, a0, a1, a2, 0); 2704} 2705 2706static void tgen_shli(TCGContext *s, TCGType type, 2707 TCGReg a0, TCGReg a1, tcg_target_long a2) 2708{ 2709 tgen_shl_int(s, type, a0, a1, TCG_REG_NONE, a2); 2710} 2711 2712static const TCGOutOpBinary outop_shl = { 2713 .base.static_constraint = C_O1_I2(r, r, ri), 2714 .out_rrr = tgen_shl, 2715 .out_rri = tgen_shli, 2716}; 2717 2718static void tgen_shr_int(TCGContext *s, TCGType type, TCGReg dst, 2719 TCGReg src, TCGReg v, tcg_target_long i) 2720{ 2721 if (type != TCG_TYPE_I32) { 2722 tcg_out_sh64(s, RSY_SRLG, dst, src, v, i); 2723 } else if (dst == src) { 2724 tcg_out_sh32(s, RS_SRL, dst, v, i); 2725 } else { 2726 tcg_out_sh64(s, RSY_SRLK, dst, src, v, i); 2727 } 2728} 2729 2730static void tgen_shr(TCGContext *s, TCGType type, 2731 TCGReg a0, TCGReg a1, TCGReg a2) 2732{ 2733 tgen_shr_int(s, type, a0, a1, a2, 0); 2734} 2735 2736static void tgen_shri(TCGContext *s, TCGType type, 2737 TCGReg a0, TCGReg a1, tcg_target_long a2) 2738{ 2739 tgen_shr_int(s, type, a0, a1, TCG_REG_NONE, a2); 2740} 2741 2742static const TCGOutOpBinary outop_shr = { 2743 .base.static_constraint = C_O1_I2(r, r, ri), 2744 .out_rrr = tgen_shr, 2745 .out_rri = tgen_shri, 2746}; 2747 2748static void tgen_sub(TCGContext *s, TCGType type, 2749 TCGReg a0, TCGReg a1, TCGReg a2) 2750{ 2751 if (type != TCG_TYPE_I32) { 2752 tcg_out_insn(s, RRFa, SGRK, a0, a1, a2); 2753 } else if (a0 == a1) { 2754 tcg_out_insn(s, RR, SR, a0, a2); 2755 } else { 2756 tcg_out_insn(s, RRFa, SRK, a0, a1, a2); 2757 } 2758} 2759 2760static const TCGOutOpSubtract outop_sub = { 2761 .base.static_constraint = C_O1_I2(r, r, r), 2762 .out_rrr = tgen_sub, 2763}; 2764 2765static void tgen_xor(TCGContext *s, TCGType type, 2766 TCGReg a0, TCGReg a1, TCGReg a2) 2767{ 2768 if (type != TCG_TYPE_I32) { 2769 tcg_out_insn(s, RRFa, XGRK, a0, a1, a2); 2770 } else if (a0 == a1) { 2771 tcg_out_insn(s, RR, XR, a0, a2); 2772 } else { 2773 tcg_out_insn(s, RRFa, XRK, a0, a1, a2); 2774 } 2775} 2776 2777static void tgen_xori_3(TCGContext *s, TCGType type, 2778 TCGReg a0, TCGReg a1, tcg_target_long a2) 2779{ 2780 tcg_out_mov(s, type, a0, a1); 2781 tgen_xori(s, a0, type == TCG_TYPE_I32 ? (uint32_t)a2 : a2); 2782} 2783 2784static const TCGOutOpBinary outop_xor = { 2785 .base.static_constraint = C_O1_I2(r, r, rK), 2786 .out_rrr = tgen_xor, 2787 .out_rri = tgen_xori_3, 2788}; 2789 2790static void tgen_bswap16(TCGContext *s, TCGType type, 2791 TCGReg a0, TCGReg a1, unsigned flags) 2792{ 2793 if (type == TCG_TYPE_I32) { 2794 tcg_out_insn(s, RRE, LRVR, a0, a1); 2795 tcg_out_sh32(s, (flags & TCG_BSWAP_OS ? RS_SRA : RS_SRL), 2796 a0, TCG_REG_NONE, 16); 2797 } else { 2798 tcg_out_insn(s, RRE, LRVGR, a0, a1); 2799 tcg_out_sh64(s, (flags & TCG_BSWAP_OS ? RSY_SRAG : RSY_SRLG), 2800 a0, a0, TCG_REG_NONE, 48); 2801 } 2802} 2803 2804static const TCGOutOpBswap outop_bswap16 = { 2805 .base.static_constraint = C_O1_I1(r, r), 2806 .out_rr = tgen_bswap16, 2807}; 2808 2809static void tgen_bswap32(TCGContext *s, TCGType type, 2810 TCGReg a0, TCGReg a1, unsigned flags) 2811{ 2812 tcg_out_insn(s, RRE, LRVR, a0, a1); 2813 if (flags & TCG_BSWAP_OS) { 2814 tcg_out_ext32s(s, a0, a0); 2815 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 2816 tcg_out_ext32u(s, a0, a0); 2817 } 2818} 2819 2820static const TCGOutOpBswap outop_bswap32 = { 2821 .base.static_constraint = C_O1_I1(r, r), 2822 .out_rr = tgen_bswap32, 2823}; 2824 2825static void tgen_bswap64(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2826{ 2827 tcg_out_insn(s, RRE, LRVGR, a0, a1); 2828} 2829 2830static const TCGOutOpUnary outop_bswap64 = { 2831 .base.static_constraint = C_O1_I1(r, r), 2832 .out_rr = tgen_bswap64, 2833}; 2834 2835static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2836{ 2837 if (type == TCG_TYPE_I32) { 2838 tcg_out_insn(s, RR, LCR, a0, a1); 2839 } else { 2840 tcg_out_insn(s, RRE, LCGR, a0, a1); 2841 } 2842} 2843 2844static const TCGOutOpUnary outop_neg = { 2845 .base.static_constraint = C_O1_I1(r, r), 2846 .out_rr = tgen_neg, 2847}; 2848 2849static void tgen_not(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2850{ 2851 tgen_nor(s, type, a0, a1, a1); 2852} 2853 2854static TCGConstraintSetIndex cset_not(TCGType type, unsigned flags) 2855{ 2856 return HAVE_FACILITY(MISC_INSN_EXT3) ? C_O1_I1(r, r) : C_NotImplemented; 2857} 2858 2859static const TCGOutOpUnary outop_not = { 2860 .base.static_constraint = C_Dynamic, 2861 .base.dynamic_constraint = cset_not, 2862 .out_rr = tgen_not, 2863}; 2864 2865 2866# define OP_32_64(x) \ 2867 case glue(glue(INDEX_op_,x),_i32): \ 2868 case glue(glue(INDEX_op_,x),_i64) 2869 2870static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, 2871 const TCGArg args[TCG_MAX_OP_ARGS], 2872 const int const_args[TCG_MAX_OP_ARGS]) 2873{ 2874 TCGArg a0; 2875 2876 switch (opc) { 2877 case INDEX_op_goto_ptr: 2878 a0 = args[0]; 2879 tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, a0); 2880 break; 2881 2882 OP_32_64(ld8u): 2883 /* ??? LLC (RXY format) is only present with the extended-immediate 2884 facility, whereas LLGC is always present. */ 2885 tcg_out_mem(s, 0, RXY_LLGC, args[0], args[1], TCG_REG_NONE, args[2]); 2886 break; 2887 2888 OP_32_64(ld8s): 2889 /* ??? LB is no smaller than LGB, so no point to using it. */ 2890 tcg_out_mem(s, 0, RXY_LGB, args[0], args[1], TCG_REG_NONE, args[2]); 2891 break; 2892 2893 OP_32_64(ld16u): 2894 /* ??? LLH (RXY format) is only present with the extended-immediate 2895 facility, whereas LLGH is always present. */ 2896 tcg_out_mem(s, 0, RXY_LLGH, args[0], args[1], TCG_REG_NONE, args[2]); 2897 break; 2898 2899 case INDEX_op_ld16s_i32: 2900 tcg_out_mem(s, RX_LH, RXY_LHY, args[0], args[1], TCG_REG_NONE, args[2]); 2901 break; 2902 2903 case INDEX_op_ld_i32: 2904 tcg_out_ld(s, TCG_TYPE_I32, args[0], args[1], args[2]); 2905 break; 2906 2907 OP_32_64(st8): 2908 tcg_out_mem(s, RX_STC, RXY_STCY, args[0], args[1], 2909 TCG_REG_NONE, args[2]); 2910 break; 2911 2912 OP_32_64(st16): 2913 tcg_out_mem(s, RX_STH, RXY_STHY, args[0], args[1], 2914 TCG_REG_NONE, args[2]); 2915 break; 2916 2917 case INDEX_op_st_i32: 2918 tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]); 2919 break; 2920 2921 case INDEX_op_add2_i32: 2922 if (const_args[4]) { 2923 tcg_out_insn(s, RIL, ALFI, args[0], args[4]); 2924 } else { 2925 tcg_out_insn(s, RR, ALR, args[0], args[4]); 2926 } 2927 tcg_out_insn(s, RRE, ALCR, args[1], args[5]); 2928 break; 2929 case INDEX_op_sub2_i32: 2930 if (const_args[4]) { 2931 tcg_out_insn(s, RIL, SLFI, args[0], args[4]); 2932 } else { 2933 tcg_out_insn(s, RR, SLR, args[0], args[4]); 2934 } 2935 tcg_out_insn(s, RRE, SLBR, args[1], args[5]); 2936 break; 2937 2938 case INDEX_op_br: 2939 tgen_branch(s, S390_CC_ALWAYS, arg_label(args[0])); 2940 break; 2941 2942 case INDEX_op_qemu_ld_i32: 2943 tcg_out_qemu_ld(s, args[0], args[1], args[2], TCG_TYPE_I32); 2944 break; 2945 case INDEX_op_qemu_ld_i64: 2946 tcg_out_qemu_ld(s, args[0], args[1], args[2], TCG_TYPE_I64); 2947 break; 2948 case INDEX_op_qemu_st_i32: 2949 tcg_out_qemu_st(s, args[0], args[1], args[2], TCG_TYPE_I32); 2950 break; 2951 case INDEX_op_qemu_st_i64: 2952 tcg_out_qemu_st(s, args[0], args[1], args[2], TCG_TYPE_I64); 2953 break; 2954 case INDEX_op_qemu_ld_i128: 2955 tcg_out_qemu_ldst_i128(s, args[0], args[1], args[2], args[3], true); 2956 break; 2957 case INDEX_op_qemu_st_i128: 2958 tcg_out_qemu_ldst_i128(s, args[0], args[1], args[2], args[3], false); 2959 break; 2960 2961 case INDEX_op_ld16s_i64: 2962 tcg_out_mem(s, 0, RXY_LGH, args[0], args[1], TCG_REG_NONE, args[2]); 2963 break; 2964 case INDEX_op_ld32u_i64: 2965 tcg_out_mem(s, 0, RXY_LLGF, args[0], args[1], TCG_REG_NONE, args[2]); 2966 break; 2967 case INDEX_op_ld32s_i64: 2968 tcg_out_mem(s, 0, RXY_LGF, args[0], args[1], TCG_REG_NONE, args[2]); 2969 break; 2970 case INDEX_op_ld_i64: 2971 tcg_out_ld(s, TCG_TYPE_I64, args[0], args[1], args[2]); 2972 break; 2973 2974 case INDEX_op_st32_i64: 2975 tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]); 2976 break; 2977 case INDEX_op_st_i64: 2978 tcg_out_st(s, TCG_TYPE_I64, args[0], args[1], args[2]); 2979 break; 2980 2981 case INDEX_op_add2_i64: 2982 if (const_args[4]) { 2983 if ((int64_t)args[4] >= 0) { 2984 tcg_out_insn(s, RIL, ALGFI, args[0], args[4]); 2985 } else { 2986 tcg_out_insn(s, RIL, SLGFI, args[0], -args[4]); 2987 } 2988 } else { 2989 tcg_out_insn(s, RRE, ALGR, args[0], args[4]); 2990 } 2991 tcg_out_insn(s, RRE, ALCGR, args[1], args[5]); 2992 break; 2993 case INDEX_op_sub2_i64: 2994 if (const_args[4]) { 2995 if ((int64_t)args[4] >= 0) { 2996 tcg_out_insn(s, RIL, SLGFI, args[0], args[4]); 2997 } else { 2998 tcg_out_insn(s, RIL, ALGFI, args[0], -args[4]); 2999 } 3000 } else { 3001 tcg_out_insn(s, RRE, SLGR, args[0], args[4]); 3002 } 3003 tcg_out_insn(s, RRE, SLBGR, args[1], args[5]); 3004 break; 3005 3006 case INDEX_op_mb: 3007 /* The host memory model is quite strong, we simply need to 3008 serialize the instruction stream. */ 3009 if (args[0] & TCG_MO_ST_LD) { 3010 /* fast-bcr-serialization facility (45) is present */ 3011 tcg_out_insn(s, RR, BCR, 14, 0); 3012 } 3013 break; 3014 3015 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 3016 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 3017 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 3018 default: 3019 g_assert_not_reached(); 3020 } 3021} 3022 3023static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 3024 TCGReg dst, TCGReg src) 3025{ 3026 if (is_general_reg(src)) { 3027 /* Replicate general register into two MO_64. */ 3028 tcg_out_insn(s, VRRf, VLVGP, dst, src, src); 3029 if (vece == MO_64) { 3030 return true; 3031 } 3032 src = dst; 3033 } 3034 3035 /* 3036 * Recall that the "standard" integer, within a vector, is the 3037 * rightmost element of the leftmost doubleword, a-la VLLEZ. 3038 */ 3039 tcg_out_insn(s, VRIc, VREP, dst, (8 >> vece) - 1, src, vece); 3040 return true; 3041} 3042 3043static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 3044 TCGReg dst, TCGReg base, intptr_t offset) 3045{ 3046 tcg_out_vrx_mem(s, VRX_VLREP, dst, base, TCG_REG_NONE, offset, vece); 3047 return true; 3048} 3049 3050static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 3051 TCGReg dst, int64_t val) 3052{ 3053 int i, mask, msb, lsb; 3054 3055 /* Look for int16_t elements. */ 3056 if (vece <= MO_16 || 3057 (vece == MO_32 ? (int32_t)val : val) == (int16_t)val) { 3058 tcg_out_insn(s, VRIa, VREPI, dst, val, vece); 3059 return; 3060 } 3061 3062 /* Look for bit masks. */ 3063 if (vece == MO_32) { 3064 if (risbg_mask((int32_t)val)) { 3065 /* Handle wraparound by swapping msb and lsb. */ 3066 if ((val & 0x80000001u) == 0x80000001u) { 3067 msb = 32 - ctz32(~val); 3068 lsb = clz32(~val) - 1; 3069 } else { 3070 msb = clz32(val); 3071 lsb = 31 - ctz32(val); 3072 } 3073 tcg_out_insn(s, VRIb, VGM, dst, msb, lsb, MO_32); 3074 return; 3075 } 3076 } else { 3077 if (risbg_mask(val)) { 3078 /* Handle wraparound by swapping msb and lsb. */ 3079 if ((val & 0x8000000000000001ull) == 0x8000000000000001ull) { 3080 /* Handle wraparound by swapping msb and lsb. */ 3081 msb = 64 - ctz64(~val); 3082 lsb = clz64(~val) - 1; 3083 } else { 3084 msb = clz64(val); 3085 lsb = 63 - ctz64(val); 3086 } 3087 tcg_out_insn(s, VRIb, VGM, dst, msb, lsb, MO_64); 3088 return; 3089 } 3090 } 3091 3092 /* Look for all bytes 0x00 or 0xff. */ 3093 for (i = mask = 0; i < 8; i++) { 3094 uint8_t byte = val >> (i * 8); 3095 if (byte == 0xff) { 3096 mask |= 1 << i; 3097 } else if (byte != 0) { 3098 break; 3099 } 3100 } 3101 if (i == 8) { 3102 tcg_out_insn(s, VRIa, VGBM, dst, mask * 0x0101, 0); 3103 return; 3104 } 3105 3106 /* Otherwise, stuff it in the constant pool. */ 3107 tcg_out_insn(s, RIL, LARL, TCG_TMP0, 0); 3108 new_pool_label(s, val, R_390_PC32DBL, s->code_ptr - 2, 2); 3109 tcg_out_insn(s, VRX, VLREP, dst, TCG_TMP0, TCG_REG_NONE, 0, MO_64); 3110} 3111 3112static bool tcg_out_cmp_vec_noinv(TCGContext *s, unsigned vece, TCGReg a0, 3113 TCGReg a1, TCGReg a2, TCGCond cond) 3114{ 3115 bool need_swap = false, need_inv = false; 3116 3117 switch (cond) { 3118 case TCG_COND_EQ: 3119 case TCG_COND_GT: 3120 case TCG_COND_GTU: 3121 break; 3122 case TCG_COND_NE: 3123 case TCG_COND_LE: 3124 case TCG_COND_LEU: 3125 need_inv = true; 3126 break; 3127 case TCG_COND_LT: 3128 case TCG_COND_LTU: 3129 need_swap = true; 3130 break; 3131 case TCG_COND_GE: 3132 case TCG_COND_GEU: 3133 need_swap = need_inv = true; 3134 break; 3135 default: 3136 g_assert_not_reached(); 3137 } 3138 3139 if (need_inv) { 3140 cond = tcg_invert_cond(cond); 3141 } 3142 if (need_swap) { 3143 TCGReg swap = a1; 3144 a1 = a2; 3145 a2 = swap; 3146 cond = tcg_swap_cond(cond); 3147 } 3148 3149 switch (cond) { 3150 case TCG_COND_EQ: 3151 tcg_out_insn(s, VRRc, VCEQ, a0, a1, a2, vece); 3152 break; 3153 case TCG_COND_GT: 3154 tcg_out_insn(s, VRRc, VCH, a0, a1, a2, vece); 3155 break; 3156 case TCG_COND_GTU: 3157 tcg_out_insn(s, VRRc, VCHL, a0, a1, a2, vece); 3158 break; 3159 default: 3160 g_assert_not_reached(); 3161 } 3162 return need_inv; 3163} 3164 3165static void tcg_out_cmp_vec(TCGContext *s, unsigned vece, TCGReg a0, 3166 TCGReg a1, TCGReg a2, TCGCond cond) 3167{ 3168 if (tcg_out_cmp_vec_noinv(s, vece, a0, a1, a2, cond)) { 3169 tcg_out_insn(s, VRRc, VNO, a0, a0, a0, 0); 3170 } 3171} 3172 3173static void tcg_out_cmpsel_vec(TCGContext *s, unsigned vece, TCGReg a0, 3174 TCGReg c1, TCGReg c2, TCGArg v3, 3175 int const_v3, TCGReg v4, TCGCond cond) 3176{ 3177 bool inv = tcg_out_cmp_vec_noinv(s, vece, TCG_VEC_TMP0, c1, c2, cond); 3178 3179 if (!const_v3) { 3180 if (inv) { 3181 tcg_out_insn(s, VRRe, VSEL, a0, v4, v3, TCG_VEC_TMP0); 3182 } else { 3183 tcg_out_insn(s, VRRe, VSEL, a0, v3, v4, TCG_VEC_TMP0); 3184 } 3185 } else if (v3) { 3186 if (inv) { 3187 tcg_out_insn(s, VRRc, VOC, a0, v4, TCG_VEC_TMP0, 0); 3188 } else { 3189 tcg_out_insn(s, VRRc, VO, a0, v4, TCG_VEC_TMP0, 0); 3190 } 3191 } else { 3192 if (inv) { 3193 tcg_out_insn(s, VRRc, VN, a0, v4, TCG_VEC_TMP0, 0); 3194 } else { 3195 tcg_out_insn(s, VRRc, VNC, a0, v4, TCG_VEC_TMP0, 0); 3196 } 3197 } 3198} 3199 3200static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 3201 unsigned vecl, unsigned vece, 3202 const TCGArg args[TCG_MAX_OP_ARGS], 3203 const int const_args[TCG_MAX_OP_ARGS]) 3204{ 3205 TCGType type = vecl + TCG_TYPE_V64; 3206 TCGArg a0 = args[0], a1 = args[1], a2 = args[2]; 3207 3208 switch (opc) { 3209 case INDEX_op_ld_vec: 3210 tcg_out_ld(s, type, a0, a1, a2); 3211 break; 3212 case INDEX_op_st_vec: 3213 tcg_out_st(s, type, a0, a1, a2); 3214 break; 3215 case INDEX_op_dupm_vec: 3216 tcg_out_dupm_vec(s, type, vece, a0, a1, a2); 3217 break; 3218 3219 case INDEX_op_abs_vec: 3220 tcg_out_insn(s, VRRa, VLP, a0, a1, vece); 3221 break; 3222 case INDEX_op_neg_vec: 3223 tcg_out_insn(s, VRRa, VLC, a0, a1, vece); 3224 break; 3225 case INDEX_op_not_vec: 3226 tcg_out_insn(s, VRRc, VNO, a0, a1, a1, 0); 3227 break; 3228 3229 case INDEX_op_add_vec: 3230 tcg_out_insn(s, VRRc, VA, a0, a1, a2, vece); 3231 break; 3232 case INDEX_op_sub_vec: 3233 tcg_out_insn(s, VRRc, VS, a0, a1, a2, vece); 3234 break; 3235 case INDEX_op_and_vec: 3236 tcg_out_insn(s, VRRc, VN, a0, a1, a2, 0); 3237 break; 3238 case INDEX_op_andc_vec: 3239 tcg_out_insn(s, VRRc, VNC, a0, a1, a2, 0); 3240 break; 3241 case INDEX_op_mul_vec: 3242 tcg_out_insn(s, VRRc, VML, a0, a1, a2, vece); 3243 break; 3244 case INDEX_op_or_vec: 3245 tcg_out_insn(s, VRRc, VO, a0, a1, a2, 0); 3246 break; 3247 case INDEX_op_orc_vec: 3248 tcg_out_insn(s, VRRc, VOC, a0, a1, a2, 0); 3249 break; 3250 case INDEX_op_xor_vec: 3251 tcg_out_insn(s, VRRc, VX, a0, a1, a2, 0); 3252 break; 3253 case INDEX_op_nand_vec: 3254 tcg_out_insn(s, VRRc, VNN, a0, a1, a2, 0); 3255 break; 3256 case INDEX_op_nor_vec: 3257 tcg_out_insn(s, VRRc, VNO, a0, a1, a2, 0); 3258 break; 3259 case INDEX_op_eqv_vec: 3260 tcg_out_insn(s, VRRc, VNX, a0, a1, a2, 0); 3261 break; 3262 3263 case INDEX_op_shli_vec: 3264 tcg_out_insn(s, VRSa, VESL, a0, a2, TCG_REG_NONE, a1, vece); 3265 break; 3266 case INDEX_op_shri_vec: 3267 tcg_out_insn(s, VRSa, VESRL, a0, a2, TCG_REG_NONE, a1, vece); 3268 break; 3269 case INDEX_op_sari_vec: 3270 tcg_out_insn(s, VRSa, VESRA, a0, a2, TCG_REG_NONE, a1, vece); 3271 break; 3272 case INDEX_op_rotli_vec: 3273 tcg_out_insn(s, VRSa, VERLL, a0, a2, TCG_REG_NONE, a1, vece); 3274 break; 3275 case INDEX_op_shls_vec: 3276 tcg_out_insn(s, VRSa, VESL, a0, 0, a2, a1, vece); 3277 break; 3278 case INDEX_op_shrs_vec: 3279 tcg_out_insn(s, VRSa, VESRL, a0, 0, a2, a1, vece); 3280 break; 3281 case INDEX_op_sars_vec: 3282 tcg_out_insn(s, VRSa, VESRA, a0, 0, a2, a1, vece); 3283 break; 3284 case INDEX_op_rotls_vec: 3285 tcg_out_insn(s, VRSa, VERLL, a0, 0, a2, a1, vece); 3286 break; 3287 case INDEX_op_shlv_vec: 3288 tcg_out_insn(s, VRRc, VESLV, a0, a1, a2, vece); 3289 break; 3290 case INDEX_op_shrv_vec: 3291 tcg_out_insn(s, VRRc, VESRLV, a0, a1, a2, vece); 3292 break; 3293 case INDEX_op_sarv_vec: 3294 tcg_out_insn(s, VRRc, VESRAV, a0, a1, a2, vece); 3295 break; 3296 case INDEX_op_rotlv_vec: 3297 tcg_out_insn(s, VRRc, VERLLV, a0, a1, a2, vece); 3298 break; 3299 3300 case INDEX_op_smin_vec: 3301 tcg_out_insn(s, VRRc, VMN, a0, a1, a2, vece); 3302 break; 3303 case INDEX_op_smax_vec: 3304 tcg_out_insn(s, VRRc, VMX, a0, a1, a2, vece); 3305 break; 3306 case INDEX_op_umin_vec: 3307 tcg_out_insn(s, VRRc, VMNL, a0, a1, a2, vece); 3308 break; 3309 case INDEX_op_umax_vec: 3310 tcg_out_insn(s, VRRc, VMXL, a0, a1, a2, vece); 3311 break; 3312 3313 case INDEX_op_bitsel_vec: 3314 tcg_out_insn(s, VRRe, VSEL, a0, a2, args[3], a1); 3315 break; 3316 3317 case INDEX_op_cmp_vec: 3318 tcg_out_cmp_vec(s, vece, a0, a1, a2, args[3]); 3319 break; 3320 case INDEX_op_cmpsel_vec: 3321 tcg_out_cmpsel_vec(s, vece, a0, a1, a2, args[3], const_args[3], 3322 args[4], args[5]); 3323 break; 3324 3325 case INDEX_op_s390_vuph_vec: 3326 tcg_out_insn(s, VRRa, VUPH, a0, a1, vece); 3327 break; 3328 case INDEX_op_s390_vupl_vec: 3329 tcg_out_insn(s, VRRa, VUPL, a0, a1, vece); 3330 break; 3331 case INDEX_op_s390_vpks_vec: 3332 tcg_out_insn(s, VRRc, VPKS, a0, a1, a2, vece); 3333 break; 3334 3335 case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ 3336 case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ 3337 default: 3338 g_assert_not_reached(); 3339 } 3340} 3341 3342int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) 3343{ 3344 switch (opc) { 3345 case INDEX_op_abs_vec: 3346 case INDEX_op_add_vec: 3347 case INDEX_op_and_vec: 3348 case INDEX_op_andc_vec: 3349 case INDEX_op_bitsel_vec: 3350 case INDEX_op_eqv_vec: 3351 case INDEX_op_nand_vec: 3352 case INDEX_op_neg_vec: 3353 case INDEX_op_nor_vec: 3354 case INDEX_op_not_vec: 3355 case INDEX_op_or_vec: 3356 case INDEX_op_orc_vec: 3357 case INDEX_op_rotli_vec: 3358 case INDEX_op_rotls_vec: 3359 case INDEX_op_rotlv_vec: 3360 case INDEX_op_sari_vec: 3361 case INDEX_op_sars_vec: 3362 case INDEX_op_sarv_vec: 3363 case INDEX_op_shli_vec: 3364 case INDEX_op_shls_vec: 3365 case INDEX_op_shlv_vec: 3366 case INDEX_op_shri_vec: 3367 case INDEX_op_shrs_vec: 3368 case INDEX_op_shrv_vec: 3369 case INDEX_op_smax_vec: 3370 case INDEX_op_smin_vec: 3371 case INDEX_op_sub_vec: 3372 case INDEX_op_umax_vec: 3373 case INDEX_op_umin_vec: 3374 case INDEX_op_xor_vec: 3375 case INDEX_op_cmp_vec: 3376 case INDEX_op_cmpsel_vec: 3377 return 1; 3378 case INDEX_op_rotrv_vec: 3379 return -1; 3380 case INDEX_op_mul_vec: 3381 return vece < MO_64; 3382 case INDEX_op_ssadd_vec: 3383 case INDEX_op_sssub_vec: 3384 return vece < MO_64 ? -1 : 0; 3385 default: 3386 return 0; 3387 } 3388} 3389 3390static void expand_vec_sat(TCGType type, unsigned vece, TCGv_vec v0, 3391 TCGv_vec v1, TCGv_vec v2, TCGOpcode add_sub_opc) 3392{ 3393 TCGv_vec h1 = tcg_temp_new_vec(type); 3394 TCGv_vec h2 = tcg_temp_new_vec(type); 3395 TCGv_vec l1 = tcg_temp_new_vec(type); 3396 TCGv_vec l2 = tcg_temp_new_vec(type); 3397 3398 tcg_debug_assert (vece < MO_64); 3399 3400 /* Unpack with sign-extension. */ 3401 vec_gen_2(INDEX_op_s390_vuph_vec, type, vece, 3402 tcgv_vec_arg(h1), tcgv_vec_arg(v1)); 3403 vec_gen_2(INDEX_op_s390_vuph_vec, type, vece, 3404 tcgv_vec_arg(h2), tcgv_vec_arg(v2)); 3405 3406 vec_gen_2(INDEX_op_s390_vupl_vec, type, vece, 3407 tcgv_vec_arg(l1), tcgv_vec_arg(v1)); 3408 vec_gen_2(INDEX_op_s390_vupl_vec, type, vece, 3409 tcgv_vec_arg(l2), tcgv_vec_arg(v2)); 3410 3411 /* Arithmetic on a wider element size. */ 3412 vec_gen_3(add_sub_opc, type, vece + 1, tcgv_vec_arg(h1), 3413 tcgv_vec_arg(h1), tcgv_vec_arg(h2)); 3414 vec_gen_3(add_sub_opc, type, vece + 1, tcgv_vec_arg(l1), 3415 tcgv_vec_arg(l1), tcgv_vec_arg(l2)); 3416 3417 /* Pack with saturation. */ 3418 vec_gen_3(INDEX_op_s390_vpks_vec, type, vece + 1, 3419 tcgv_vec_arg(v0), tcgv_vec_arg(h1), tcgv_vec_arg(l1)); 3420 3421 tcg_temp_free_vec(h1); 3422 tcg_temp_free_vec(h2); 3423 tcg_temp_free_vec(l1); 3424 tcg_temp_free_vec(l2); 3425} 3426 3427void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, 3428 TCGArg a0, ...) 3429{ 3430 va_list va; 3431 TCGv_vec v0, v1, v2, t0; 3432 3433 va_start(va, a0); 3434 v0 = temp_tcgv_vec(arg_temp(a0)); 3435 v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); 3436 v2 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); 3437 3438 switch (opc) { 3439 case INDEX_op_rotrv_vec: 3440 t0 = tcg_temp_new_vec(type); 3441 tcg_gen_neg_vec(vece, t0, v2); 3442 tcg_gen_rotlv_vec(vece, v0, v1, t0); 3443 tcg_temp_free_vec(t0); 3444 break; 3445 3446 case INDEX_op_ssadd_vec: 3447 expand_vec_sat(type, vece, v0, v1, v2, INDEX_op_add_vec); 3448 break; 3449 case INDEX_op_sssub_vec: 3450 expand_vec_sat(type, vece, v0, v1, v2, INDEX_op_sub_vec); 3451 break; 3452 3453 default: 3454 g_assert_not_reached(); 3455 } 3456 va_end(va); 3457} 3458 3459static TCGConstraintSetIndex 3460tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) 3461{ 3462 switch (op) { 3463 case INDEX_op_goto_ptr: 3464 return C_O0_I1(r); 3465 3466 case INDEX_op_ld8u_i32: 3467 case INDEX_op_ld8u_i64: 3468 case INDEX_op_ld8s_i32: 3469 case INDEX_op_ld8s_i64: 3470 case INDEX_op_ld16u_i32: 3471 case INDEX_op_ld16u_i64: 3472 case INDEX_op_ld16s_i32: 3473 case INDEX_op_ld16s_i64: 3474 case INDEX_op_ld_i32: 3475 case INDEX_op_ld32u_i64: 3476 case INDEX_op_ld32s_i64: 3477 case INDEX_op_ld_i64: 3478 return C_O1_I1(r, r); 3479 3480 case INDEX_op_st8_i32: 3481 case INDEX_op_st8_i64: 3482 case INDEX_op_st16_i32: 3483 case INDEX_op_st16_i64: 3484 case INDEX_op_st_i32: 3485 case INDEX_op_st32_i64: 3486 case INDEX_op_st_i64: 3487 return C_O0_I2(r, r); 3488 3489 case INDEX_op_qemu_ld_i32: 3490 case INDEX_op_qemu_ld_i64: 3491 return C_O1_I1(r, r); 3492 case INDEX_op_qemu_st_i64: 3493 case INDEX_op_qemu_st_i32: 3494 return C_O0_I2(r, r); 3495 case INDEX_op_qemu_ld_i128: 3496 return C_O2_I1(o, m, r); 3497 case INDEX_op_qemu_st_i128: 3498 return C_O0_I3(o, m, r); 3499 3500 case INDEX_op_add2_i32: 3501 case INDEX_op_sub2_i32: 3502 return C_N1_O1_I4(r, r, 0, 1, ri, r); 3503 3504 case INDEX_op_add2_i64: 3505 case INDEX_op_sub2_i64: 3506 return C_N1_O1_I4(r, r, 0, 1, rJU, r); 3507 3508 case INDEX_op_st_vec: 3509 return C_O0_I2(v, r); 3510 case INDEX_op_ld_vec: 3511 case INDEX_op_dupm_vec: 3512 return C_O1_I1(v, r); 3513 case INDEX_op_dup_vec: 3514 return C_O1_I1(v, vr); 3515 case INDEX_op_abs_vec: 3516 case INDEX_op_neg_vec: 3517 case INDEX_op_not_vec: 3518 case INDEX_op_rotli_vec: 3519 case INDEX_op_sari_vec: 3520 case INDEX_op_shli_vec: 3521 case INDEX_op_shri_vec: 3522 case INDEX_op_s390_vuph_vec: 3523 case INDEX_op_s390_vupl_vec: 3524 return C_O1_I1(v, v); 3525 case INDEX_op_add_vec: 3526 case INDEX_op_sub_vec: 3527 case INDEX_op_and_vec: 3528 case INDEX_op_andc_vec: 3529 case INDEX_op_or_vec: 3530 case INDEX_op_orc_vec: 3531 case INDEX_op_xor_vec: 3532 case INDEX_op_nand_vec: 3533 case INDEX_op_nor_vec: 3534 case INDEX_op_eqv_vec: 3535 case INDEX_op_cmp_vec: 3536 case INDEX_op_mul_vec: 3537 case INDEX_op_rotlv_vec: 3538 case INDEX_op_rotrv_vec: 3539 case INDEX_op_shlv_vec: 3540 case INDEX_op_shrv_vec: 3541 case INDEX_op_sarv_vec: 3542 case INDEX_op_smax_vec: 3543 case INDEX_op_smin_vec: 3544 case INDEX_op_umax_vec: 3545 case INDEX_op_umin_vec: 3546 case INDEX_op_s390_vpks_vec: 3547 return C_O1_I2(v, v, v); 3548 case INDEX_op_rotls_vec: 3549 case INDEX_op_shls_vec: 3550 case INDEX_op_shrs_vec: 3551 case INDEX_op_sars_vec: 3552 return C_O1_I2(v, v, r); 3553 case INDEX_op_bitsel_vec: 3554 return C_O1_I3(v, v, v, v); 3555 case INDEX_op_cmpsel_vec: 3556 return (TCG_TARGET_HAS_orc_vec 3557 ? C_O1_I4(v, v, v, vZM, v) 3558 : C_O1_I4(v, v, v, vZ, v)); 3559 3560 default: 3561 return C_NotImplemented; 3562 } 3563} 3564 3565/* 3566 * Mainline glibc added HWCAP_S390_VX before it was kernel abi. 3567 * Some distros have fixed this up locally, others have not. 3568 */ 3569#ifndef HWCAP_S390_VXRS 3570#define HWCAP_S390_VXRS 2048 3571#endif 3572 3573static void query_s390_facilities(void) 3574{ 3575 unsigned long hwcap = qemu_getauxval(AT_HWCAP); 3576 const char *which; 3577 3578 /* Is STORE FACILITY LIST EXTENDED available? Honestly, I believe this 3579 is present on all 64-bit systems, but let's check for it anyway. */ 3580 if (hwcap & HWCAP_S390_STFLE) { 3581 register int r0 __asm__("0") = ARRAY_SIZE(s390_facilities) - 1; 3582 register void *r1 __asm__("1") = s390_facilities; 3583 3584 /* stfle 0(%r1) */ 3585 asm volatile(".word 0xb2b0,0x1000" 3586 : "=r"(r0) : "r"(r0), "r"(r1) : "memory", "cc"); 3587 } 3588 3589 /* 3590 * Use of vector registers requires os support beyond the facility bit. 3591 * If the kernel does not advertise support, disable the facility bits. 3592 * There is nothing else we currently care about in the 3rd word, so 3593 * disable VECTOR with one store. 3594 */ 3595 if (!(hwcap & HWCAP_S390_VXRS)) { 3596 s390_facilities[2] = 0; 3597 } 3598 3599 /* 3600 * Minimum supported cpu revision is z196. 3601 * Check for all required facilities. 3602 * ZARCH_ACTIVE is done via preprocessor check for 64-bit. 3603 */ 3604 if (!HAVE_FACILITY(LONG_DISP)) { 3605 which = "long-displacement"; 3606 goto fail; 3607 } 3608 if (!HAVE_FACILITY(EXT_IMM)) { 3609 which = "extended-immediate"; 3610 goto fail; 3611 } 3612 if (!HAVE_FACILITY(GEN_INST_EXT)) { 3613 which = "general-instructions-extension"; 3614 goto fail; 3615 } 3616 /* 3617 * Facility 45 is a big bin that contains: distinct-operands, 3618 * fast-BCR-serialization, high-word, population-count, 3619 * interlocked-access-1, and load/store-on-condition-1 3620 */ 3621 if (!HAVE_FACILITY(45)) { 3622 which = "45"; 3623 goto fail; 3624 } 3625 return; 3626 3627 fail: 3628 error_report("%s: missing required facility %s", __func__, which); 3629 exit(EXIT_FAILURE); 3630} 3631 3632static void tcg_target_init(TCGContext *s) 3633{ 3634 query_s390_facilities(); 3635 3636 tcg_target_available_regs[TCG_TYPE_I32] = 0xffff; 3637 tcg_target_available_regs[TCG_TYPE_I64] = 0xffff; 3638 if (HAVE_FACILITY(VECTOR)) { 3639 tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull; 3640 tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull; 3641 } 3642 3643 tcg_target_call_clobber_regs = 0; 3644 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0); 3645 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1); 3646 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2); 3647 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3); 3648 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R4); 3649 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R5); 3650 /* The r6 register is technically call-saved, but it's also a parameter 3651 register, so it can get killed by setup for the qemu_st helper. */ 3652 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R6); 3653 /* The return register can be considered call-clobbered. */ 3654 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14); 3655 3656 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); 3657 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); 3658 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V2); 3659 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V3); 3660 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V4); 3661 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V5); 3662 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V6); 3663 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V7); 3664 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V16); 3665 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V17); 3666 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V18); 3667 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V19); 3668 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V20); 3669 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V21); 3670 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V22); 3671 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V23); 3672 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V24); 3673 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V25); 3674 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V26); 3675 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V27); 3676 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V28); 3677 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V29); 3678 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V30); 3679 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V31); 3680 3681 s->reserved_regs = 0; 3682 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); 3683 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP0); 3684 /* XXX many insns can't be used with R0, so we better avoid it for now */ 3685 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); 3686 tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); 3687} 3688 3689#define FRAME_SIZE ((int)(TCG_TARGET_CALL_STACK_OFFSET \ 3690 + TCG_STATIC_CALL_ARGS_SIZE \ 3691 + CPU_TEMP_BUF_NLONGS * sizeof(long))) 3692 3693static void tcg_target_qemu_prologue(TCGContext *s) 3694{ 3695 /* stmg %r6,%r15,48(%r15) (save registers) */ 3696 tcg_out_insn(s, RXY, STMG, TCG_REG_R6, TCG_REG_R15, TCG_REG_R15, 48); 3697 3698 /* aghi %r15,-frame_size */ 3699 tcg_out_insn(s, RI, AGHI, TCG_REG_R15, -FRAME_SIZE); 3700 3701 tcg_set_frame(s, TCG_REG_CALL_STACK, 3702 TCG_STATIC_CALL_ARGS_SIZE + TCG_TARGET_CALL_STACK_OFFSET, 3703 CPU_TEMP_BUF_NLONGS * sizeof(long)); 3704 3705 if (!tcg_use_softmmu && guest_base >= 0x80000) { 3706 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); 3707 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 3708 } 3709 3710 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 3711 3712 /* br %r3 (go to TB) */ 3713 tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, tcg_target_call_iarg_regs[1]); 3714 3715 /* 3716 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 3717 * and fall through to the rest of the epilogue. 3718 */ 3719 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 3720 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, 0); 3721 3722 /* TB epilogue */ 3723 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 3724 3725 /* lmg %r6,%r15,fs+48(%r15) (restore registers) */ 3726 tcg_out_insn(s, RXY, LMG, TCG_REG_R6, TCG_REG_R15, TCG_REG_R15, 3727 FRAME_SIZE + 48); 3728 3729 /* br %r14 (return) */ 3730 tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_R14); 3731} 3732 3733static void tcg_out_tb_start(TCGContext *s) 3734{ 3735 /* nothing to do */ 3736} 3737 3738static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 3739{ 3740 memset(p, 0x07, count * sizeof(tcg_insn_unit)); 3741} 3742 3743typedef struct { 3744 DebugFrameHeader h; 3745 uint8_t fde_def_cfa[4]; 3746 uint8_t fde_reg_ofs[18]; 3747} DebugFrame; 3748 3749/* We're expecting a 2 byte uleb128 encoded value. */ 3750QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14)); 3751 3752#define ELF_HOST_MACHINE EM_S390 3753 3754static const DebugFrame debug_frame = { 3755 .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ 3756 .h.cie.id = -1, 3757 .h.cie.version = 1, 3758 .h.cie.code_align = 1, 3759 .h.cie.data_align = 8, /* sleb128 8 */ 3760 .h.cie.return_column = TCG_REG_R14, 3761 3762 /* Total FDE size does not include the "len" member. */ 3763 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 3764 3765 .fde_def_cfa = { 3766 12, TCG_REG_CALL_STACK, /* DW_CFA_def_cfa %r15, ... */ 3767 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 3768 (FRAME_SIZE >> 7) 3769 }, 3770 .fde_reg_ofs = { 3771 0x86, 6, /* DW_CFA_offset, %r6, 48 */ 3772 0x87, 7, /* DW_CFA_offset, %r7, 56 */ 3773 0x88, 8, /* DW_CFA_offset, %r8, 64 */ 3774 0x89, 9, /* DW_CFA_offset, %r92, 72 */ 3775 0x8a, 10, /* DW_CFA_offset, %r10, 80 */ 3776 0x8b, 11, /* DW_CFA_offset, %r11, 88 */ 3777 0x8c, 12, /* DW_CFA_offset, %r12, 96 */ 3778 0x8d, 13, /* DW_CFA_offset, %r13, 104 */ 3779 0x8e, 14, /* DW_CFA_offset, %r14, 112 */ 3780 } 3781}; 3782 3783void tcg_register_jit(const void *buf, size_t buf_size) 3784{ 3785 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 3786} 3787