1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2009 Ulrich Hecht <uli@suse.de> 5 * Copyright (c) 2009 Alexander Graf <agraf@suse.de> 6 * Copyright (c) 2010 Richard Henderson <rth@twiddle.net> 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27#include "elf.h" 28 29/* Used for function call generation. */ 30#define TCG_TARGET_STACK_ALIGN 8 31#define TCG_TARGET_CALL_STACK_OFFSET 160 32#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EXTEND 33#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL 34#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_BY_REF 35#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF 36 37#define TCG_CT_CONST_S16 (1 << 8) 38#define TCG_CT_CONST_S32 (1 << 9) 39#define TCG_CT_CONST_U32 (1 << 10) 40#define TCG_CT_CONST_ZERO (1 << 11) 41#define TCG_CT_CONST_P32 (1 << 12) 42#define TCG_CT_CONST_INV (1 << 13) 43#define TCG_CT_CONST_INVRISBG (1 << 14) 44#define TCG_CT_CONST_CMP (1 << 15) 45#define TCG_CT_CONST_M1 (1 << 16) 46 47#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 16) 48#define ALL_VECTOR_REGS MAKE_64BIT_MASK(32, 32) 49 50/* Several places within the instruction set 0 means "no register" 51 rather than TCG_REG_R0. */ 52#define TCG_REG_NONE 0 53 54/* A scratch register that may be be used throughout the backend. */ 55#define TCG_TMP0 TCG_REG_R1 56#define TCG_VEC_TMP0 TCG_REG_V31 57 58#define TCG_GUEST_BASE_REG TCG_REG_R13 59 60/* All of the following instructions are prefixed with their instruction 61 format, and are defined as 8- or 16-bit quantities, even when the two 62 halves of the 16-bit quantity may appear 32 bits apart in the insn. 63 This makes it easy to copy the values from the tables in Appendix B. */ 64typedef enum S390Opcode { 65 RIL_AFI = 0xc209, 66 RIL_AGFI = 0xc208, 67 RIL_ALFI = 0xc20b, 68 RIL_ALGFI = 0xc20a, 69 RIL_BRASL = 0xc005, 70 RIL_BRCL = 0xc004, 71 RIL_CFI = 0xc20d, 72 RIL_CGFI = 0xc20c, 73 RIL_CLFI = 0xc20f, 74 RIL_CLGFI = 0xc20e, 75 RIL_CLRL = 0xc60f, 76 RIL_CLGRL = 0xc60a, 77 RIL_CRL = 0xc60d, 78 RIL_CGRL = 0xc608, 79 RIL_IIHF = 0xc008, 80 RIL_IILF = 0xc009, 81 RIL_LARL = 0xc000, 82 RIL_LGFI = 0xc001, 83 RIL_LGRL = 0xc408, 84 RIL_LLIHF = 0xc00e, 85 RIL_LLILF = 0xc00f, 86 RIL_LRL = 0xc40d, 87 RIL_MSFI = 0xc201, 88 RIL_MSGFI = 0xc200, 89 RIL_NIHF = 0xc00a, 90 RIL_NILF = 0xc00b, 91 RIL_OIHF = 0xc00c, 92 RIL_OILF = 0xc00d, 93 RIL_SLFI = 0xc205, 94 RIL_SLGFI = 0xc204, 95 RIL_XIHF = 0xc006, 96 RIL_XILF = 0xc007, 97 98 RI_AGHI = 0xa70b, 99 RI_AHI = 0xa70a, 100 RI_BRC = 0xa704, 101 RI_CHI = 0xa70e, 102 RI_CGHI = 0xa70f, 103 RI_IIHH = 0xa500, 104 RI_IIHL = 0xa501, 105 RI_IILH = 0xa502, 106 RI_IILL = 0xa503, 107 RI_LGHI = 0xa709, 108 RI_LLIHH = 0xa50c, 109 RI_LLIHL = 0xa50d, 110 RI_LLILH = 0xa50e, 111 RI_LLILL = 0xa50f, 112 RI_MGHI = 0xa70d, 113 RI_MHI = 0xa70c, 114 RI_NIHH = 0xa504, 115 RI_NIHL = 0xa505, 116 RI_NILH = 0xa506, 117 RI_NILL = 0xa507, 118 RI_OIHH = 0xa508, 119 RI_OIHL = 0xa509, 120 RI_OILH = 0xa50a, 121 RI_OILL = 0xa50b, 122 RI_TMLL = 0xa701, 123 RI_TMLH = 0xa700, 124 RI_TMHL = 0xa703, 125 RI_TMHH = 0xa702, 126 127 RIEb_CGRJ = 0xec64, 128 RIEb_CLGRJ = 0xec65, 129 RIEb_CLRJ = 0xec77, 130 RIEb_CRJ = 0xec76, 131 132 RIEc_CGIJ = 0xec7c, 133 RIEc_CIJ = 0xec7e, 134 RIEc_CLGIJ = 0xec7d, 135 RIEc_CLIJ = 0xec7f, 136 137 RIEf_RISBG = 0xec55, 138 139 RIEg_LOCGHI = 0xec46, 140 141 RRE_AGR = 0xb908, 142 RRE_ALGR = 0xb90a, 143 RRE_ALCR = 0xb998, 144 RRE_ALCGR = 0xb988, 145 RRE_ALGFR = 0xb91a, 146 RRE_CGR = 0xb920, 147 RRE_CLGR = 0xb921, 148 RRE_DLGR = 0xb987, 149 RRE_DLR = 0xb997, 150 RRE_DSGFR = 0xb91d, 151 RRE_DSGR = 0xb90d, 152 RRE_FLOGR = 0xb983, 153 RRE_LGBR = 0xb906, 154 RRE_LCGR = 0xb903, 155 RRE_LGFR = 0xb914, 156 RRE_LGHR = 0xb907, 157 RRE_LGR = 0xb904, 158 RRE_LLGCR = 0xb984, 159 RRE_LLGFR = 0xb916, 160 RRE_LLGHR = 0xb985, 161 RRE_LRVR = 0xb91f, 162 RRE_LRVGR = 0xb90f, 163 RRE_LTGR = 0xb902, 164 RRE_MLGR = 0xb986, 165 RRE_MSGR = 0xb90c, 166 RRE_MSR = 0xb252, 167 RRE_NGR = 0xb980, 168 RRE_OGR = 0xb981, 169 RRE_SGR = 0xb909, 170 RRE_SLGR = 0xb90b, 171 RRE_SLBR = 0xb999, 172 RRE_SLBGR = 0xb989, 173 RRE_XGR = 0xb982, 174 175 RRFa_MGRK = 0xb9ec, 176 RRFa_MSRKC = 0xb9fd, 177 RRFa_MSGRKC = 0xb9ed, 178 RRFa_NCRK = 0xb9f5, 179 RRFa_NCGRK = 0xb9e5, 180 RRFa_NNRK = 0xb974, 181 RRFa_NNGRK = 0xb964, 182 RRFa_NORK = 0xb976, 183 RRFa_NOGRK = 0xb966, 184 RRFa_NRK = 0xb9f4, 185 RRFa_NGRK = 0xb9e4, 186 RRFa_NXRK = 0xb977, 187 RRFa_NXGRK = 0xb967, 188 RRFa_OCRK = 0xb975, 189 RRFa_OCGRK = 0xb965, 190 RRFa_ORK = 0xb9f6, 191 RRFa_OGRK = 0xb9e6, 192 RRFa_SRK = 0xb9f9, 193 RRFa_SGRK = 0xb9e9, 194 RRFa_SLRK = 0xb9fb, 195 RRFa_SLGRK = 0xb9eb, 196 RRFa_XRK = 0xb9f7, 197 RRFa_XGRK = 0xb9e7, 198 199 RRFam_SELGR = 0xb9e3, 200 201 RRFc_LOCR = 0xb9f2, 202 RRFc_LOCGR = 0xb9e2, 203 RRFc_POPCNT = 0xb9e1, 204 205 RR_AR = 0x1a, 206 RR_ALR = 0x1e, 207 RR_BASR = 0x0d, 208 RR_BCR = 0x07, 209 RR_CLR = 0x15, 210 RR_CR = 0x19, 211 RR_DR = 0x1d, 212 RR_LCR = 0x13, 213 RR_LR = 0x18, 214 RR_LTR = 0x12, 215 RR_NR = 0x14, 216 RR_OR = 0x16, 217 RR_SR = 0x1b, 218 RR_SLR = 0x1f, 219 RR_XR = 0x17, 220 221 RSY_RLL = 0xeb1d, 222 RSY_RLLG = 0xeb1c, 223 RSY_SLLG = 0xeb0d, 224 RSY_SLLK = 0xebdf, 225 RSY_SRAG = 0xeb0a, 226 RSY_SRAK = 0xebdc, 227 RSY_SRLG = 0xeb0c, 228 RSY_SRLK = 0xebde, 229 230 RS_SLL = 0x89, 231 RS_SRA = 0x8a, 232 RS_SRL = 0x88, 233 234 RXY_AG = 0xe308, 235 RXY_AY = 0xe35a, 236 RXY_CG = 0xe320, 237 RXY_CLG = 0xe321, 238 RXY_CLY = 0xe355, 239 RXY_CY = 0xe359, 240 RXY_LAY = 0xe371, 241 RXY_LB = 0xe376, 242 RXY_LG = 0xe304, 243 RXY_LGB = 0xe377, 244 RXY_LGF = 0xe314, 245 RXY_LGH = 0xe315, 246 RXY_LHY = 0xe378, 247 RXY_LLGC = 0xe390, 248 RXY_LLGF = 0xe316, 249 RXY_LLGH = 0xe391, 250 RXY_LMG = 0xeb04, 251 RXY_LPQ = 0xe38f, 252 RXY_LRV = 0xe31e, 253 RXY_LRVG = 0xe30f, 254 RXY_LRVH = 0xe31f, 255 RXY_LY = 0xe358, 256 RXY_NG = 0xe380, 257 RXY_OG = 0xe381, 258 RXY_STCY = 0xe372, 259 RXY_STG = 0xe324, 260 RXY_STHY = 0xe370, 261 RXY_STMG = 0xeb24, 262 RXY_STPQ = 0xe38e, 263 RXY_STRV = 0xe33e, 264 RXY_STRVG = 0xe32f, 265 RXY_STRVH = 0xe33f, 266 RXY_STY = 0xe350, 267 RXY_XG = 0xe382, 268 269 RX_A = 0x5a, 270 RX_C = 0x59, 271 RX_L = 0x58, 272 RX_LA = 0x41, 273 RX_LH = 0x48, 274 RX_ST = 0x50, 275 RX_STC = 0x42, 276 RX_STH = 0x40, 277 278 VRIa_VGBM = 0xe744, 279 VRIa_VREPI = 0xe745, 280 VRIb_VGM = 0xe746, 281 VRIc_VREP = 0xe74d, 282 283 VRRa_VLC = 0xe7de, 284 VRRa_VLP = 0xe7df, 285 VRRa_VLR = 0xe756, 286 VRRc_VA = 0xe7f3, 287 VRRc_VCEQ = 0xe7f8, /* we leave the m5 cs field 0 */ 288 VRRc_VCH = 0xe7fb, /* " */ 289 VRRc_VCHL = 0xe7f9, /* " */ 290 VRRc_VERLLV = 0xe773, 291 VRRc_VESLV = 0xe770, 292 VRRc_VESRAV = 0xe77a, 293 VRRc_VESRLV = 0xe778, 294 VRRc_VML = 0xe7a2, 295 VRRc_VMN = 0xe7fe, 296 VRRc_VMNL = 0xe7fc, 297 VRRc_VMX = 0xe7ff, 298 VRRc_VMXL = 0xe7fd, 299 VRRc_VN = 0xe768, 300 VRRc_VNC = 0xe769, 301 VRRc_VNN = 0xe76e, 302 VRRc_VNO = 0xe76b, 303 VRRc_VNX = 0xe76c, 304 VRRc_VO = 0xe76a, 305 VRRc_VOC = 0xe76f, 306 VRRc_VPKS = 0xe797, /* we leave the m5 cs field 0 */ 307 VRRc_VS = 0xe7f7, 308 VRRa_VUPH = 0xe7d7, 309 VRRa_VUPL = 0xe7d6, 310 VRRc_VX = 0xe76d, 311 VRRe_VSEL = 0xe78d, 312 VRRf_VLVGP = 0xe762, 313 314 VRSa_VERLL = 0xe733, 315 VRSa_VESL = 0xe730, 316 VRSa_VESRA = 0xe73a, 317 VRSa_VESRL = 0xe738, 318 VRSb_VLVG = 0xe722, 319 VRSc_VLGV = 0xe721, 320 321 VRX_VL = 0xe706, 322 VRX_VLLEZ = 0xe704, 323 VRX_VLREP = 0xe705, 324 VRX_VST = 0xe70e, 325 VRX_VSTEF = 0xe70b, 326 VRX_VSTEG = 0xe70a, 327 328 NOP = 0x0707, 329} S390Opcode; 330 331#ifdef CONFIG_DEBUG_TCG 332static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 333 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", 334 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", 335 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 336 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7", 337 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15", 338 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23", 339 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31", 340}; 341#endif 342 343/* Since R6 is a potential argument register, choose it last of the 344 call-saved registers. Likewise prefer the call-clobbered registers 345 in reverse order to maximize the chance of avoiding the arguments. */ 346static const int tcg_target_reg_alloc_order[] = { 347 /* Call saved registers. */ 348 TCG_REG_R13, 349 TCG_REG_R12, 350 TCG_REG_R11, 351 TCG_REG_R10, 352 TCG_REG_R9, 353 TCG_REG_R8, 354 TCG_REG_R7, 355 TCG_REG_R6, 356 /* Call clobbered registers. */ 357 TCG_REG_R14, 358 TCG_REG_R0, 359 TCG_REG_R1, 360 /* Argument registers, in reverse order of allocation. */ 361 TCG_REG_R5, 362 TCG_REG_R4, 363 TCG_REG_R3, 364 TCG_REG_R2, 365 366 /* V8-V15 are call saved, and omitted. */ 367 TCG_REG_V0, 368 TCG_REG_V1, 369 TCG_REG_V2, 370 TCG_REG_V3, 371 TCG_REG_V4, 372 TCG_REG_V5, 373 TCG_REG_V6, 374 TCG_REG_V7, 375 TCG_REG_V16, 376 TCG_REG_V17, 377 TCG_REG_V18, 378 TCG_REG_V19, 379 TCG_REG_V20, 380 TCG_REG_V21, 381 TCG_REG_V22, 382 TCG_REG_V23, 383 TCG_REG_V24, 384 TCG_REG_V25, 385 TCG_REG_V26, 386 TCG_REG_V27, 387 TCG_REG_V28, 388 TCG_REG_V29, 389 TCG_REG_V30, 390 TCG_REG_V31, 391}; 392 393static const int tcg_target_call_iarg_regs[] = { 394 TCG_REG_R2, 395 TCG_REG_R3, 396 TCG_REG_R4, 397 TCG_REG_R5, 398 TCG_REG_R6, 399}; 400 401static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 402{ 403 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 404 tcg_debug_assert(slot == 0); 405 return TCG_REG_R2; 406} 407 408#define S390_CC_EQ 8 409#define S390_CC_LT 4 410#define S390_CC_GT 2 411#define S390_CC_OV 1 412#define S390_CC_NE (S390_CC_LT | S390_CC_GT) 413#define S390_CC_LE (S390_CC_LT | S390_CC_EQ) 414#define S390_CC_GE (S390_CC_GT | S390_CC_EQ) 415#define S390_CC_NEVER 0 416#define S390_CC_ALWAYS 15 417 418#define S390_TM_EQ 8 /* CC == 0 */ 419#define S390_TM_NE 7 /* CC in {1,2,3} */ 420 421/* Condition codes that result from a COMPARE and COMPARE LOGICAL. */ 422static const uint8_t tcg_cond_to_s390_cond[16] = { 423 [TCG_COND_EQ] = S390_CC_EQ, 424 [TCG_COND_NE] = S390_CC_NE, 425 [TCG_COND_TSTEQ] = S390_CC_EQ, 426 [TCG_COND_TSTNE] = S390_CC_NE, 427 [TCG_COND_LT] = S390_CC_LT, 428 [TCG_COND_LE] = S390_CC_LE, 429 [TCG_COND_GT] = S390_CC_GT, 430 [TCG_COND_GE] = S390_CC_GE, 431 [TCG_COND_LTU] = S390_CC_LT, 432 [TCG_COND_LEU] = S390_CC_LE, 433 [TCG_COND_GTU] = S390_CC_GT, 434 [TCG_COND_GEU] = S390_CC_GE, 435}; 436 437/* Condition codes that result from a LOAD AND TEST. Here, we have no 438 unsigned instruction variation, however since the test is vs zero we 439 can re-map the outcomes appropriately. */ 440static const uint8_t tcg_cond_to_ltr_cond[16] = { 441 [TCG_COND_EQ] = S390_CC_EQ, 442 [TCG_COND_NE] = S390_CC_NE, 443 [TCG_COND_TSTEQ] = S390_CC_ALWAYS, 444 [TCG_COND_TSTNE] = S390_CC_NEVER, 445 [TCG_COND_LT] = S390_CC_LT, 446 [TCG_COND_LE] = S390_CC_LE, 447 [TCG_COND_GT] = S390_CC_GT, 448 [TCG_COND_GE] = S390_CC_GE, 449 [TCG_COND_LTU] = S390_CC_NEVER, 450 [TCG_COND_LEU] = S390_CC_EQ, 451 [TCG_COND_GTU] = S390_CC_NE, 452 [TCG_COND_GEU] = S390_CC_ALWAYS, 453}; 454 455static const tcg_insn_unit *tb_ret_addr; 456uint64_t s390_facilities[3]; 457 458static inline bool is_general_reg(TCGReg r) 459{ 460 return r <= TCG_REG_R15; 461} 462 463static inline bool is_vector_reg(TCGReg r) 464{ 465 return r >= TCG_REG_V0 && r <= TCG_REG_V31; 466} 467 468static bool patch_reloc(tcg_insn_unit *src_rw, int type, 469 intptr_t value, intptr_t addend) 470{ 471 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 472 intptr_t pcrel2; 473 uint32_t old; 474 475 value += addend; 476 pcrel2 = (tcg_insn_unit *)value - src_rx; 477 478 switch (type) { 479 case R_390_PC16DBL: 480 if (pcrel2 == (int16_t)pcrel2) { 481 tcg_patch16(src_rw, pcrel2); 482 return true; 483 } 484 break; 485 case R_390_PC32DBL: 486 if (pcrel2 == (int32_t)pcrel2) { 487 tcg_patch32(src_rw, pcrel2); 488 return true; 489 } 490 break; 491 case R_390_20: 492 if (value == sextract64(value, 0, 20)) { 493 old = *(uint32_t *)src_rw & 0xf00000ff; 494 old |= ((value & 0xfff) << 16) | ((value & 0xff000) >> 4); 495 tcg_patch32(src_rw, old); 496 return true; 497 } 498 break; 499 default: 500 g_assert_not_reached(); 501 } 502 return false; 503} 504 505static int is_const_p16(uint64_t val) 506{ 507 for (int i = 0; i < 4; ++i) { 508 uint64_t mask = 0xffffull << (i * 16); 509 if ((val & ~mask) == 0) { 510 return i; 511 } 512 } 513 return -1; 514} 515 516static int is_const_p32(uint64_t val) 517{ 518 if ((val & 0xffffffff00000000ull) == 0) { 519 return 0; 520 } 521 if ((val & 0x00000000ffffffffull) == 0) { 522 return 1; 523 } 524 return -1; 525} 526 527/* 528 * Accept bit patterns like these: 529 * 0....01....1 530 * 1....10....0 531 * 1..10..01..1 532 * 0..01..10..0 533 * Copied from gcc sources. 534 */ 535static bool risbg_mask(uint64_t c) 536{ 537 uint64_t lsb; 538 /* We don't change the number of transitions by inverting, 539 so make sure we start with the LSB zero. */ 540 if (c & 1) { 541 c = ~c; 542 } 543 /* Reject all zeros or all ones. */ 544 if (c == 0) { 545 return false; 546 } 547 /* Find the first transition. */ 548 lsb = c & -c; 549 /* Invert to look for a second transition. */ 550 c = ~c; 551 /* Erase the first transition. */ 552 c &= -lsb; 553 /* Find the second transition, if any. */ 554 lsb = c & -c; 555 /* Match if all the bits are 1's, or if c is zero. */ 556 return c == -lsb; 557} 558 559/* Test if a constant matches the constraint. */ 560static bool tcg_target_const_match(int64_t val, int ct, 561 TCGType type, TCGCond cond, int vece) 562{ 563 uint64_t uval = val; 564 565 if (ct & TCG_CT_CONST) { 566 return true; 567 } 568 if (type == TCG_TYPE_I32) { 569 uval = (uint32_t)val; 570 val = (int32_t)val; 571 } 572 573 if (ct & TCG_CT_CONST_CMP) { 574 if (is_tst_cond(cond)) { 575 if (is_const_p16(uval) >= 0) { 576 return true; /* TMxx */ 577 } 578 if (risbg_mask(uval)) { 579 return true; /* RISBG */ 580 } 581 return false; 582 } 583 584 if (type == TCG_TYPE_I32) { 585 return true; 586 } 587 588 switch (cond) { 589 case TCG_COND_EQ: 590 case TCG_COND_NE: 591 ct |= TCG_CT_CONST_S32 | TCG_CT_CONST_U32; /* CGFI or CLGFI */ 592 break; 593 case TCG_COND_LT: 594 case TCG_COND_GE: 595 case TCG_COND_LE: 596 case TCG_COND_GT: 597 ct |= TCG_CT_CONST_S32; /* CGFI */ 598 break; 599 case TCG_COND_LTU: 600 case TCG_COND_GEU: 601 case TCG_COND_LEU: 602 case TCG_COND_GTU: 603 ct |= TCG_CT_CONST_U32; /* CLGFI */ 604 break; 605 case TCG_COND_TSTNE: 606 case TCG_COND_TSTEQ: 607 /* checked above, fallthru */ 608 default: 609 g_assert_not_reached(); 610 } 611 } 612 613 if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) { 614 return true; 615 } 616 if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) { 617 return true; 618 } 619 if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) { 620 return true; 621 } 622 if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 623 return true; 624 } 625 if ((ct & TCG_CT_CONST_M1) && val == -1) { 626 return true; 627 } 628 629 if (ct & TCG_CT_CONST_INV) { 630 val = ~val; 631 } 632 if ((ct & TCG_CT_CONST_P32) && is_const_p32(val) >= 0) { 633 return true; 634 } 635 if ((ct & TCG_CT_CONST_INVRISBG) && risbg_mask(~val)) { 636 return true; 637 } 638 return false; 639} 640 641/* Emit instructions according to the given instruction format. */ 642 643static void tcg_out_insn_RR(TCGContext *s, S390Opcode op, TCGReg r1, TCGReg r2) 644{ 645 tcg_out16(s, (op << 8) | (r1 << 4) | r2); 646} 647 648static void tcg_out_insn_RRE(TCGContext *s, S390Opcode op, 649 TCGReg r1, TCGReg r2) 650{ 651 tcg_out32(s, (op << 16) | (r1 << 4) | r2); 652} 653 654/* RRF-a without the m4 field */ 655static void tcg_out_insn_RRFa(TCGContext *s, S390Opcode op, 656 TCGReg r1, TCGReg r2, TCGReg r3) 657{ 658 tcg_out32(s, (op << 16) | (r3 << 12) | (r1 << 4) | r2); 659} 660 661/* RRF-a with the m4 field */ 662static void tcg_out_insn_RRFam(TCGContext *s, S390Opcode op, 663 TCGReg r1, TCGReg r2, TCGReg r3, int m4) 664{ 665 tcg_out32(s, (op << 16) | (r3 << 12) | (m4 << 8) | (r1 << 4) | r2); 666} 667 668static void tcg_out_insn_RRFc(TCGContext *s, S390Opcode op, 669 TCGReg r1, TCGReg r2, int m3) 670{ 671 tcg_out32(s, (op << 16) | (m3 << 12) | (r1 << 4) | r2); 672} 673 674static void tcg_out_insn_RI(TCGContext *s, S390Opcode op, TCGReg r1, int i2) 675{ 676 tcg_out32(s, (op << 16) | (r1 << 20) | (i2 & 0xffff)); 677} 678 679static void tcg_out_insn_RIEg(TCGContext *s, S390Opcode op, TCGReg r1, 680 int i2, int m3) 681{ 682 tcg_out16(s, (op & 0xff00) | (r1 << 4) | m3); 683 tcg_out32(s, (i2 << 16) | (op & 0xff)); 684} 685 686static void tcg_out_insn_RIL(TCGContext *s, S390Opcode op, TCGReg r1, int i2) 687{ 688 tcg_out16(s, op | (r1 << 4)); 689 tcg_out32(s, i2); 690} 691 692static void tcg_out_insn_RS(TCGContext *s, S390Opcode op, TCGReg r1, 693 TCGReg b2, TCGReg r3, int disp) 694{ 695 tcg_out32(s, (op << 24) | (r1 << 20) | (r3 << 16) | (b2 << 12) 696 | (disp & 0xfff)); 697} 698 699static void tcg_out_insn_RSY(TCGContext *s, S390Opcode op, TCGReg r1, 700 TCGReg b2, TCGReg r3, int disp) 701{ 702 tcg_out16(s, (op & 0xff00) | (r1 << 4) | r3); 703 tcg_out32(s, (op & 0xff) | (b2 << 28) 704 | ((disp & 0xfff) << 16) | ((disp & 0xff000) >> 4)); 705} 706 707#define tcg_out_insn_RX tcg_out_insn_RS 708#define tcg_out_insn_RXY tcg_out_insn_RSY 709 710static int RXB(TCGReg v1, TCGReg v2, TCGReg v3, TCGReg v4) 711{ 712 /* 713 * Shift bit 4 of each regno to its corresponding bit of RXB. 714 * RXB itself begins at bit 8 of the instruction so 8 - 4 = 4 715 * is the left-shift of the 4th operand. 716 */ 717 return ((v1 & 0x10) << (4 + 3)) 718 | ((v2 & 0x10) << (4 + 2)) 719 | ((v3 & 0x10) << (4 + 1)) 720 | ((v4 & 0x10) << (4 + 0)); 721} 722 723static void tcg_out_insn_VRIa(TCGContext *s, S390Opcode op, 724 TCGReg v1, uint16_t i2, int m3) 725{ 726 tcg_debug_assert(is_vector_reg(v1)); 727 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4)); 728 tcg_out16(s, i2); 729 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m3 << 12)); 730} 731 732static void tcg_out_insn_VRIb(TCGContext *s, S390Opcode op, 733 TCGReg v1, uint8_t i2, uint8_t i3, int m4) 734{ 735 tcg_debug_assert(is_vector_reg(v1)); 736 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4)); 737 tcg_out16(s, (i2 << 8) | (i3 & 0xff)); 738 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m4 << 12)); 739} 740 741static void tcg_out_insn_VRIc(TCGContext *s, S390Opcode op, 742 TCGReg v1, uint16_t i2, TCGReg v3, int m4) 743{ 744 tcg_debug_assert(is_vector_reg(v1)); 745 tcg_debug_assert(is_vector_reg(v3)); 746 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v3 & 0xf)); 747 tcg_out16(s, i2); 748 tcg_out16(s, (op & 0x00ff) | RXB(v1, v3, 0, 0) | (m4 << 12)); 749} 750 751static void tcg_out_insn_VRRa(TCGContext *s, S390Opcode op, 752 TCGReg v1, TCGReg v2, int m3) 753{ 754 tcg_debug_assert(is_vector_reg(v1)); 755 tcg_debug_assert(is_vector_reg(v2)); 756 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v2 & 0xf)); 757 tcg_out32(s, (op & 0x00ff) | RXB(v1, v2, 0, 0) | (m3 << 12)); 758} 759 760static void tcg_out_insn_VRRc(TCGContext *s, S390Opcode op, 761 TCGReg v1, TCGReg v2, TCGReg v3, int m4) 762{ 763 tcg_debug_assert(is_vector_reg(v1)); 764 tcg_debug_assert(is_vector_reg(v2)); 765 tcg_debug_assert(is_vector_reg(v3)); 766 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v2 & 0xf)); 767 tcg_out16(s, v3 << 12); 768 tcg_out16(s, (op & 0x00ff) | RXB(v1, v2, v3, 0) | (m4 << 12)); 769} 770 771static void tcg_out_insn_VRRe(TCGContext *s, S390Opcode op, 772 TCGReg v1, TCGReg v2, TCGReg v3, TCGReg v4) 773{ 774 tcg_debug_assert(is_vector_reg(v1)); 775 tcg_debug_assert(is_vector_reg(v2)); 776 tcg_debug_assert(is_vector_reg(v3)); 777 tcg_debug_assert(is_vector_reg(v4)); 778 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v2 & 0xf)); 779 tcg_out16(s, v3 << 12); 780 tcg_out16(s, (op & 0x00ff) | RXB(v1, v2, v3, v4) | (v4 << 12)); 781} 782 783static void tcg_out_insn_VRRf(TCGContext *s, S390Opcode op, 784 TCGReg v1, TCGReg r2, TCGReg r3) 785{ 786 tcg_debug_assert(is_vector_reg(v1)); 787 tcg_debug_assert(is_general_reg(r2)); 788 tcg_debug_assert(is_general_reg(r3)); 789 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | r2); 790 tcg_out16(s, r3 << 12); 791 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0)); 792} 793 794static void tcg_out_insn_VRSa(TCGContext *s, S390Opcode op, TCGReg v1, 795 intptr_t d2, TCGReg b2, TCGReg v3, int m4) 796{ 797 tcg_debug_assert(is_vector_reg(v1)); 798 tcg_debug_assert(d2 >= 0 && d2 <= 0xfff); 799 tcg_debug_assert(is_general_reg(b2)); 800 tcg_debug_assert(is_vector_reg(v3)); 801 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v3 & 0xf)); 802 tcg_out16(s, b2 << 12 | d2); 803 tcg_out16(s, (op & 0x00ff) | RXB(v1, v3, 0, 0) | (m4 << 12)); 804} 805 806static void tcg_out_insn_VRSb(TCGContext *s, S390Opcode op, TCGReg v1, 807 intptr_t d2, TCGReg b2, TCGReg r3, int m4) 808{ 809 tcg_debug_assert(is_vector_reg(v1)); 810 tcg_debug_assert(d2 >= 0 && d2 <= 0xfff); 811 tcg_debug_assert(is_general_reg(b2)); 812 tcg_debug_assert(is_general_reg(r3)); 813 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | r3); 814 tcg_out16(s, b2 << 12 | d2); 815 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m4 << 12)); 816} 817 818static void tcg_out_insn_VRSc(TCGContext *s, S390Opcode op, TCGReg r1, 819 intptr_t d2, TCGReg b2, TCGReg v3, int m4) 820{ 821 tcg_debug_assert(is_general_reg(r1)); 822 tcg_debug_assert(d2 >= 0 && d2 <= 0xfff); 823 tcg_debug_assert(is_general_reg(b2)); 824 tcg_debug_assert(is_vector_reg(v3)); 825 tcg_out16(s, (op & 0xff00) | (r1 << 4) | (v3 & 0xf)); 826 tcg_out16(s, b2 << 12 | d2); 827 tcg_out16(s, (op & 0x00ff) | RXB(0, v3, 0, 0) | (m4 << 12)); 828} 829 830static void tcg_out_insn_VRX(TCGContext *s, S390Opcode op, TCGReg v1, 831 TCGReg b2, TCGReg x2, intptr_t d2, int m3) 832{ 833 tcg_debug_assert(is_vector_reg(v1)); 834 tcg_debug_assert(d2 >= 0 && d2 <= 0xfff); 835 tcg_debug_assert(is_general_reg(x2)); 836 tcg_debug_assert(is_general_reg(b2)); 837 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | x2); 838 tcg_out16(s, (b2 << 12) | d2); 839 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m3 << 12)); 840} 841 842/* Emit an opcode with "type-checking" of the format. */ 843#define tcg_out_insn(S, FMT, OP, ...) \ 844 glue(tcg_out_insn_,FMT)(S, glue(glue(FMT,_),OP), ## __VA_ARGS__) 845 846 847/* emit 64-bit shifts */ 848static void tcg_out_sh64(TCGContext* s, S390Opcode op, TCGReg dest, 849 TCGReg src, TCGReg sh_reg, int sh_imm) 850{ 851 tcg_out_insn_RSY(s, op, dest, sh_reg, src, sh_imm); 852} 853 854/* emit 32-bit shifts */ 855static void tcg_out_sh32(TCGContext* s, S390Opcode op, TCGReg dest, 856 TCGReg sh_reg, int sh_imm) 857{ 858 tcg_out_insn_RS(s, op, dest, sh_reg, 0, sh_imm); 859} 860 861static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg dst, TCGReg src) 862{ 863 if (src == dst) { 864 return true; 865 } 866 switch (type) { 867 case TCG_TYPE_I32: 868 if (likely(is_general_reg(dst) && is_general_reg(src))) { 869 tcg_out_insn(s, RR, LR, dst, src); 870 break; 871 } 872 /* fallthru */ 873 874 case TCG_TYPE_I64: 875 if (likely(is_general_reg(dst))) { 876 if (likely(is_general_reg(src))) { 877 tcg_out_insn(s, RRE, LGR, dst, src); 878 } else { 879 tcg_out_insn(s, VRSc, VLGV, dst, 0, 0, src, 3); 880 } 881 break; 882 } else if (is_general_reg(src)) { 883 tcg_out_insn(s, VRSb, VLVG, dst, 0, 0, src, 3); 884 break; 885 } 886 /* fallthru */ 887 888 case TCG_TYPE_V64: 889 case TCG_TYPE_V128: 890 tcg_out_insn(s, VRRa, VLR, dst, src, 0); 891 break; 892 893 default: 894 g_assert_not_reached(); 895 } 896 return true; 897} 898 899static const S390Opcode li_insns[4] = { 900 RI_LLILL, RI_LLILH, RI_LLIHL, RI_LLIHH 901}; 902static const S390Opcode oi_insns[4] = { 903 RI_OILL, RI_OILH, RI_OIHL, RI_OIHH 904}; 905static const S390Opcode lif_insns[2] = { 906 RIL_LLILF, RIL_LLIHF, 907}; 908static const S390Opcode tm_insns[4] = { 909 RI_TMLL, RI_TMLH, RI_TMHL, RI_TMHH 910}; 911 912/* load a register with an immediate value */ 913static void tcg_out_movi(TCGContext *s, TCGType type, 914 TCGReg ret, tcg_target_long sval) 915{ 916 tcg_target_ulong uval = sval; 917 ptrdiff_t pc_off; 918 int i; 919 920 if (type == TCG_TYPE_I32) { 921 uval = (uint32_t)sval; 922 sval = (int32_t)sval; 923 } 924 925 /* Try all 32-bit insns that can load it in one go. */ 926 if (sval >= -0x8000 && sval < 0x8000) { 927 tcg_out_insn(s, RI, LGHI, ret, sval); 928 return; 929 } 930 931 i = is_const_p16(uval); 932 if (i >= 0) { 933 tcg_out_insn_RI(s, li_insns[i], ret, uval >> (i * 16)); 934 return; 935 } 936 937 /* Try all 48-bit insns that can load it in one go. */ 938 if (sval == (int32_t)sval) { 939 tcg_out_insn(s, RIL, LGFI, ret, sval); 940 return; 941 } 942 943 i = is_const_p32(uval); 944 if (i >= 0) { 945 tcg_out_insn_RIL(s, lif_insns[i], ret, uval >> (i * 32)); 946 return; 947 } 948 949 /* Try for PC-relative address load. For odd addresses, add one. */ 950 pc_off = tcg_pcrel_diff(s, (void *)sval) >> 1; 951 if (pc_off == (int32_t)pc_off) { 952 tcg_out_insn(s, RIL, LARL, ret, pc_off); 953 if (sval & 1) { 954 tcg_out_insn(s, RI, AGHI, ret, 1); 955 } 956 return; 957 } 958 959 /* Otherwise, load it by parts. */ 960 i = is_const_p16((uint32_t)uval); 961 if (i >= 0) { 962 tcg_out_insn_RI(s, li_insns[i], ret, uval >> (i * 16)); 963 } else { 964 tcg_out_insn(s, RIL, LLILF, ret, uval); 965 } 966 uval >>= 32; 967 i = is_const_p16(uval); 968 if (i >= 0) { 969 tcg_out_insn_RI(s, oi_insns[i + 2], ret, uval >> (i * 16)); 970 } else { 971 tcg_out_insn(s, RIL, OIHF, ret, uval); 972 } 973} 974 975/* Emit a load/store type instruction. Inputs are: 976 DATA: The register to be loaded or stored. 977 BASE+OFS: The effective address. 978 OPC_RX: If the operation has an RX format opcode (e.g. STC), otherwise 0. 979 OPC_RXY: The RXY format opcode for the operation (e.g. STCY). */ 980 981static void tcg_out_mem(TCGContext *s, S390Opcode opc_rx, S390Opcode opc_rxy, 982 TCGReg data, TCGReg base, TCGReg index, 983 tcg_target_long ofs) 984{ 985 if (ofs < -0x80000 || ofs >= 0x80000) { 986 /* Combine the low 20 bits of the offset with the actual load insn; 987 the high 44 bits must come from an immediate load. */ 988 tcg_target_long low = ((ofs & 0xfffff) ^ 0x80000) - 0x80000; 989 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - low); 990 ofs = low; 991 992 /* If we were already given an index register, add it in. */ 993 if (index != TCG_REG_NONE) { 994 tcg_out_insn(s, RRE, AGR, TCG_TMP0, index); 995 } 996 index = TCG_TMP0; 997 } 998 999 if (opc_rx && ofs >= 0 && ofs < 0x1000) { 1000 tcg_out_insn_RX(s, opc_rx, data, base, index, ofs); 1001 } else { 1002 tcg_out_insn_RXY(s, opc_rxy, data, base, index, ofs); 1003 } 1004} 1005 1006static void tcg_out_vrx_mem(TCGContext *s, S390Opcode opc_vrx, 1007 TCGReg data, TCGReg base, TCGReg index, 1008 tcg_target_long ofs, int m3) 1009{ 1010 if (ofs < 0 || ofs >= 0x1000) { 1011 if (ofs >= -0x80000 && ofs < 0x80000) { 1012 tcg_out_insn(s, RXY, LAY, TCG_TMP0, base, index, ofs); 1013 base = TCG_TMP0; 1014 index = TCG_REG_NONE; 1015 ofs = 0; 1016 } else { 1017 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs); 1018 if (index != TCG_REG_NONE) { 1019 tcg_out_insn(s, RRE, AGR, TCG_TMP0, index); 1020 } 1021 index = TCG_TMP0; 1022 ofs = 0; 1023 } 1024 } 1025 tcg_out_insn_VRX(s, opc_vrx, data, base, index, ofs, m3); 1026} 1027 1028/* load data without address translation or endianness conversion */ 1029static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg data, 1030 TCGReg base, intptr_t ofs) 1031{ 1032 switch (type) { 1033 case TCG_TYPE_I32: 1034 if (likely(is_general_reg(data))) { 1035 tcg_out_mem(s, RX_L, RXY_LY, data, base, TCG_REG_NONE, ofs); 1036 break; 1037 } 1038 tcg_out_vrx_mem(s, VRX_VLLEZ, data, base, TCG_REG_NONE, ofs, MO_32); 1039 break; 1040 1041 case TCG_TYPE_I64: 1042 if (likely(is_general_reg(data))) { 1043 tcg_out_mem(s, 0, RXY_LG, data, base, TCG_REG_NONE, ofs); 1044 break; 1045 } 1046 /* fallthru */ 1047 1048 case TCG_TYPE_V64: 1049 tcg_out_vrx_mem(s, VRX_VLLEZ, data, base, TCG_REG_NONE, ofs, MO_64); 1050 break; 1051 1052 case TCG_TYPE_V128: 1053 /* Hint quadword aligned. */ 1054 tcg_out_vrx_mem(s, VRX_VL, data, base, TCG_REG_NONE, ofs, 4); 1055 break; 1056 1057 default: 1058 g_assert_not_reached(); 1059 } 1060} 1061 1062static void tcg_out_st(TCGContext *s, TCGType type, TCGReg data, 1063 TCGReg base, intptr_t ofs) 1064{ 1065 switch (type) { 1066 case TCG_TYPE_I32: 1067 if (likely(is_general_reg(data))) { 1068 tcg_out_mem(s, RX_ST, RXY_STY, data, base, TCG_REG_NONE, ofs); 1069 } else { 1070 tcg_out_vrx_mem(s, VRX_VSTEF, data, base, TCG_REG_NONE, ofs, 1); 1071 } 1072 break; 1073 1074 case TCG_TYPE_I64: 1075 if (likely(is_general_reg(data))) { 1076 tcg_out_mem(s, 0, RXY_STG, data, base, TCG_REG_NONE, ofs); 1077 break; 1078 } 1079 /* fallthru */ 1080 1081 case TCG_TYPE_V64: 1082 tcg_out_vrx_mem(s, VRX_VSTEG, data, base, TCG_REG_NONE, ofs, 0); 1083 break; 1084 1085 case TCG_TYPE_V128: 1086 /* Hint quadword aligned. */ 1087 tcg_out_vrx_mem(s, VRX_VST, data, base, TCG_REG_NONE, ofs, 4); 1088 break; 1089 1090 default: 1091 g_assert_not_reached(); 1092 } 1093} 1094 1095static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 1096 TCGReg base, intptr_t ofs) 1097{ 1098 return false; 1099} 1100 1101static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 1102{ 1103 return false; 1104} 1105 1106static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 1107 tcg_target_long imm) 1108{ 1109 /* This function is only used for passing structs by reference. */ 1110 tcg_out_mem(s, RX_LA, RXY_LAY, rd, rs, TCG_REG_NONE, imm); 1111} 1112 1113static inline void tcg_out_risbg(TCGContext *s, TCGReg dest, TCGReg src, 1114 int msb, int lsb, int ofs, int z) 1115{ 1116 /* Format RIE-f */ 1117 tcg_out16(s, (RIEf_RISBG & 0xff00) | (dest << 4) | src); 1118 tcg_out16(s, (msb << 8) | (z << 7) | lsb); 1119 tcg_out16(s, (ofs << 8) | (RIEf_RISBG & 0xff)); 1120} 1121 1122static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) 1123{ 1124 tcg_out_insn(s, RRE, LGBR, dest, src); 1125} 1126 1127static void tcg_out_ext8u(TCGContext *s, TCGReg dest, TCGReg src) 1128{ 1129 tcg_out_insn(s, RRE, LLGCR, dest, src); 1130} 1131 1132static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) 1133{ 1134 tcg_out_insn(s, RRE, LGHR, dest, src); 1135} 1136 1137static void tcg_out_ext16u(TCGContext *s, TCGReg dest, TCGReg src) 1138{ 1139 tcg_out_insn(s, RRE, LLGHR, dest, src); 1140} 1141 1142static void tcg_out_ext32s(TCGContext *s, TCGReg dest, TCGReg src) 1143{ 1144 tcg_out_insn(s, RRE, LGFR, dest, src); 1145} 1146 1147static void tcg_out_ext32u(TCGContext *s, TCGReg dest, TCGReg src) 1148{ 1149 tcg_out_insn(s, RRE, LLGFR, dest, src); 1150} 1151 1152static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg dest, TCGReg src) 1153{ 1154 tcg_out_ext32s(s, dest, src); 1155} 1156 1157static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg dest, TCGReg src) 1158{ 1159 tcg_out_ext32u(s, dest, src); 1160} 1161 1162static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg dest, TCGReg src) 1163{ 1164 tcg_out_mov(s, TCG_TYPE_I32, dest, src); 1165} 1166 1167static void tgen_andi_risbg(TCGContext *s, TCGReg out, TCGReg in, uint64_t val) 1168{ 1169 int msb, lsb; 1170 if ((val & 0x8000000000000001ull) == 0x8000000000000001ull) { 1171 /* Achieve wraparound by swapping msb and lsb. */ 1172 msb = 64 - ctz64(~val); 1173 lsb = clz64(~val) - 1; 1174 } else { 1175 msb = clz64(val); 1176 lsb = 63 - ctz64(val); 1177 } 1178 tcg_out_risbg(s, out, in, msb, lsb, 0, 1); 1179} 1180 1181static void tgen_andi(TCGContext *s, TCGType type, TCGReg dest, uint64_t val) 1182{ 1183 static const S390Opcode ni_insns[4] = { 1184 RI_NILL, RI_NILH, RI_NIHL, RI_NIHH 1185 }; 1186 static const S390Opcode nif_insns[2] = { 1187 RIL_NILF, RIL_NIHF 1188 }; 1189 uint64_t valid = (type == TCG_TYPE_I32 ? 0xffffffffull : -1ull); 1190 int i; 1191 1192 /* Look for the zero-extensions. */ 1193 if ((val & valid) == 0xffffffff) { 1194 tcg_out_ext32u(s, dest, dest); 1195 return; 1196 } 1197 if ((val & valid) == 0xff) { 1198 tcg_out_ext8u(s, dest, dest); 1199 return; 1200 } 1201 if ((val & valid) == 0xffff) { 1202 tcg_out_ext16u(s, dest, dest); 1203 return; 1204 } 1205 1206 i = is_const_p16(~val & valid); 1207 if (i >= 0) { 1208 tcg_out_insn_RI(s, ni_insns[i], dest, val >> (i * 16)); 1209 return; 1210 } 1211 1212 i = is_const_p32(~val & valid); 1213 tcg_debug_assert(i == 0 || type != TCG_TYPE_I32); 1214 if (i >= 0) { 1215 tcg_out_insn_RIL(s, nif_insns[i], dest, val >> (i * 32)); 1216 return; 1217 } 1218 1219 if (risbg_mask(val)) { 1220 tgen_andi_risbg(s, dest, dest, val); 1221 return; 1222 } 1223 1224 g_assert_not_reached(); 1225} 1226 1227static void tgen_ori(TCGContext *s, TCGReg dest, uint64_t val) 1228{ 1229 static const S390Opcode oif_insns[2] = { 1230 RIL_OILF, RIL_OIHF 1231 }; 1232 1233 int i; 1234 1235 i = is_const_p16(val); 1236 if (i >= 0) { 1237 tcg_out_insn_RI(s, oi_insns[i], dest, val >> (i * 16)); 1238 return; 1239 } 1240 1241 i = is_const_p32(val); 1242 if (i >= 0) { 1243 tcg_out_insn_RIL(s, oif_insns[i], dest, val >> (i * 32)); 1244 return; 1245 } 1246 1247 g_assert_not_reached(); 1248} 1249 1250static void tgen_xori(TCGContext *s, TCGReg dest, uint64_t val) 1251{ 1252 switch (is_const_p32(val)) { 1253 case 0: 1254 tcg_out_insn(s, RIL, XILF, dest, val); 1255 break; 1256 case 1: 1257 tcg_out_insn(s, RIL, XIHF, dest, val >> 32); 1258 break; 1259 default: 1260 g_assert_not_reached(); 1261 } 1262} 1263 1264static int tgen_cmp2(TCGContext *s, TCGType type, TCGCond c, TCGReg r1, 1265 TCGArg c2, bool c2const, bool need_carry, int *inv_cc) 1266{ 1267 bool is_unsigned = is_unsigned_cond(c); 1268 TCGCond inv_c = tcg_invert_cond(c); 1269 S390Opcode op; 1270 1271 if (is_tst_cond(c)) { 1272 tcg_debug_assert(!need_carry); 1273 1274 if (!c2const) { 1275 if (type == TCG_TYPE_I32) { 1276 tcg_out_insn(s, RRFa, NRK, TCG_REG_R0, r1, c2); 1277 } else { 1278 tcg_out_insn(s, RRFa, NGRK, TCG_REG_R0, r1, c2); 1279 } 1280 goto exit; 1281 } 1282 1283 if (type == TCG_TYPE_I32) { 1284 c2 = (uint32_t)c2; 1285 } 1286 1287 int i = is_const_p16(c2); 1288 if (i >= 0) { 1289 tcg_out_insn_RI(s, tm_insns[i], r1, c2 >> (i * 16)); 1290 *inv_cc = c == TCG_COND_TSTEQ ? S390_TM_NE : S390_TM_EQ; 1291 return *inv_cc ^ 15; 1292 } 1293 1294 if (risbg_mask(c2)) { 1295 tgen_andi_risbg(s, TCG_REG_R0, r1, c2); 1296 goto exit; 1297 } 1298 g_assert_not_reached(); 1299 } 1300 1301 if (c2const) { 1302 if (c2 == 0) { 1303 if (!(is_unsigned && need_carry)) { 1304 if (type == TCG_TYPE_I32) { 1305 tcg_out_insn(s, RR, LTR, r1, r1); 1306 } else { 1307 tcg_out_insn(s, RRE, LTGR, r1, r1); 1308 } 1309 *inv_cc = tcg_cond_to_ltr_cond[inv_c]; 1310 return tcg_cond_to_ltr_cond[c]; 1311 } 1312 } 1313 1314 if (!is_unsigned && c2 == (int16_t)c2) { 1315 op = (type == TCG_TYPE_I32 ? RI_CHI : RI_CGHI); 1316 tcg_out_insn_RI(s, op, r1, c2); 1317 goto exit; 1318 } 1319 1320 if (type == TCG_TYPE_I32) { 1321 op = (is_unsigned ? RIL_CLFI : RIL_CFI); 1322 tcg_out_insn_RIL(s, op, r1, c2); 1323 goto exit; 1324 } 1325 1326 /* Should match TCG_CT_CONST_CMP. */ 1327 switch (c) { 1328 case TCG_COND_LT: 1329 case TCG_COND_GE: 1330 case TCG_COND_LE: 1331 case TCG_COND_GT: 1332 tcg_debug_assert(c2 == (int32_t)c2); 1333 op = RIL_CGFI; 1334 break; 1335 case TCG_COND_EQ: 1336 case TCG_COND_NE: 1337 if (c2 == (int32_t)c2) { 1338 op = RIL_CGFI; 1339 break; 1340 } 1341 /* fall through */ 1342 case TCG_COND_LTU: 1343 case TCG_COND_GEU: 1344 case TCG_COND_LEU: 1345 case TCG_COND_GTU: 1346 tcg_debug_assert(c2 == (uint32_t)c2); 1347 op = RIL_CLGFI; 1348 break; 1349 default: 1350 g_assert_not_reached(); 1351 } 1352 tcg_out_insn_RIL(s, op, r1, c2); 1353 } else if (type == TCG_TYPE_I32) { 1354 op = (is_unsigned ? RR_CLR : RR_CR); 1355 tcg_out_insn_RR(s, op, r1, c2); 1356 } else { 1357 op = (is_unsigned ? RRE_CLGR : RRE_CGR); 1358 tcg_out_insn_RRE(s, op, r1, c2); 1359 } 1360 1361 exit: 1362 *inv_cc = tcg_cond_to_s390_cond[inv_c]; 1363 return tcg_cond_to_s390_cond[c]; 1364} 1365 1366static int tgen_cmp(TCGContext *s, TCGType type, TCGCond c, TCGReg r1, 1367 TCGArg c2, bool c2const, bool need_carry) 1368{ 1369 int inv_cc; 1370 return tgen_cmp2(s, type, c, r1, c2, c2const, need_carry, &inv_cc); 1371} 1372 1373static void tgen_setcond_int(TCGContext *s, TCGType type, TCGCond cond, 1374 TCGReg dest, TCGReg c1, TCGArg c2, 1375 bool c2const, bool neg) 1376{ 1377 int cc; 1378 1379 /* With LOC2, we can always emit the minimum 3 insns. */ 1380 if (HAVE_FACILITY(LOAD_ON_COND2)) { 1381 /* Emit: d = 0, d = (cc ? 1 : d). */ 1382 cc = tgen_cmp(s, type, cond, c1, c2, c2const, false); 1383 tcg_out_movi(s, TCG_TYPE_I64, dest, 0); 1384 tcg_out_insn(s, RIEg, LOCGHI, dest, neg ? -1 : 1, cc); 1385 return; 1386 } 1387 1388 switch (cond) { 1389 case TCG_COND_GEU: 1390 case TCG_COND_LTU: 1391 case TCG_COND_LT: 1392 case TCG_COND_GE: 1393 /* Swap operands so that we can use LEU/GTU/GT/LE. */ 1394 if (!c2const) { 1395 TCGReg t = c1; 1396 c1 = c2; 1397 c2 = t; 1398 cond = tcg_swap_cond(cond); 1399 } 1400 break; 1401 default: 1402 break; 1403 } 1404 1405 switch (cond) { 1406 case TCG_COND_NE: 1407 /* X != 0 is X > 0. */ 1408 if (c2const && c2 == 0) { 1409 cond = TCG_COND_GTU; 1410 } else { 1411 break; 1412 } 1413 /* fallthru */ 1414 1415 case TCG_COND_GTU: 1416 case TCG_COND_GT: 1417 /* 1418 * The result of a compare has CC=2 for GT and CC=3 unused. 1419 * ADD LOGICAL WITH CARRY considers (CC & 2) the carry bit. 1420 */ 1421 tgen_cmp(s, type, cond, c1, c2, c2const, true); 1422 tcg_out_movi(s, type, dest, 0); 1423 tcg_out_insn(s, RRE, ALCGR, dest, dest); 1424 if (neg) { 1425 if (type == TCG_TYPE_I32) { 1426 tcg_out_insn(s, RR, LCR, dest, dest); 1427 } else { 1428 tcg_out_insn(s, RRE, LCGR, dest, dest); 1429 } 1430 } 1431 return; 1432 1433 case TCG_COND_EQ: 1434 /* X == 0 is X <= 0. */ 1435 if (c2const && c2 == 0) { 1436 cond = TCG_COND_LEU; 1437 } else { 1438 break; 1439 } 1440 /* fallthru */ 1441 1442 case TCG_COND_LEU: 1443 case TCG_COND_LE: 1444 /* 1445 * As above, but we're looking for borrow, or !carry. 1446 * The second insn computes d - d - borrow, or -1 for true 1447 * and 0 for false. So we must mask to 1 bit afterward. 1448 */ 1449 tgen_cmp(s, type, cond, c1, c2, c2const, true); 1450 tcg_out_insn(s, RRE, SLBGR, dest, dest); 1451 if (!neg) { 1452 tgen_andi(s, type, dest, 1); 1453 } 1454 return; 1455 1456 default: 1457 g_assert_not_reached(); 1458 } 1459 1460 cc = tgen_cmp(s, type, cond, c1, c2, c2const, false); 1461 /* Emit: d = 0, t = 1, d = (cc ? t : d). */ 1462 tcg_out_movi(s, TCG_TYPE_I64, dest, 0); 1463 tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, neg ? -1 : 1); 1464 tcg_out_insn(s, RRFc, LOCGR, dest, TCG_TMP0, cc); 1465} 1466 1467static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, 1468 TCGReg dest, TCGReg arg1, TCGReg arg2) 1469{ 1470 tgen_setcond_int(s, type, cond, dest, arg1, arg2, false, false); 1471} 1472 1473static void tgen_setcondi(TCGContext *s, TCGType type, TCGCond cond, 1474 TCGReg dest, TCGReg arg1, tcg_target_long arg2) 1475{ 1476 tgen_setcond_int(s, type, cond, dest, arg1, arg2, true, false); 1477} 1478 1479static const TCGOutOpSetcond outop_setcond = { 1480 .base.static_constraint = C_O1_I2(r, r, rC), 1481 .out_rrr = tgen_setcond, 1482 .out_rri = tgen_setcondi, 1483}; 1484 1485static void tgen_negsetcond(TCGContext *s, TCGType type, TCGCond cond, 1486 TCGReg dest, TCGReg arg1, TCGReg arg2) 1487{ 1488 tgen_setcond_int(s, type, cond, dest, arg1, arg2, false, true); 1489} 1490 1491static void tgen_negsetcondi(TCGContext *s, TCGType type, TCGCond cond, 1492 TCGReg dest, TCGReg arg1, tcg_target_long arg2) 1493{ 1494 tgen_setcond_int(s, type, cond, dest, arg1, arg2, true, true); 1495} 1496 1497static const TCGOutOpSetcond outop_negsetcond = { 1498 .base.static_constraint = C_O1_I2(r, r, rC), 1499 .out_rrr = tgen_negsetcond, 1500 .out_rri = tgen_negsetcondi, 1501}; 1502 1503static void tgen_movcond_int(TCGContext *s, TCGType type, TCGReg dest, 1504 TCGArg v3, int v3const, TCGReg v4, 1505 int cc, int inv_cc) 1506{ 1507 TCGReg src; 1508 1509 if (v3const) { 1510 if (dest == v4) { 1511 if (HAVE_FACILITY(LOAD_ON_COND2)) { 1512 /* Emit: if (cc) dest = v3. */ 1513 tcg_out_insn(s, RIEg, LOCGHI, dest, v3, cc); 1514 return; 1515 } 1516 tcg_out_insn(s, RI, LGHI, TCG_TMP0, v3); 1517 src = TCG_TMP0; 1518 } else { 1519 /* LGR+LOCGHI is larger than LGHI+LOCGR. */ 1520 tcg_out_insn(s, RI, LGHI, dest, v3); 1521 cc = inv_cc; 1522 src = v4; 1523 } 1524 } else { 1525 if (HAVE_FACILITY(MISC_INSN_EXT3)) { 1526 /* Emit: dest = cc ? v3 : v4. */ 1527 tcg_out_insn(s, RRFam, SELGR, dest, v3, v4, cc); 1528 return; 1529 } 1530 if (dest == v4) { 1531 src = v3; 1532 } else { 1533 tcg_out_mov(s, type, dest, v3); 1534 cc = inv_cc; 1535 src = v4; 1536 } 1537 } 1538 1539 /* Emit: if (cc) dest = src. */ 1540 tcg_out_insn(s, RRFc, LOCGR, dest, src, cc); 1541} 1542 1543static void tgen_movcond(TCGContext *s, TCGType type, TCGCond c, 1544 TCGReg dest, TCGReg c1, TCGArg c2, bool c2const, 1545 TCGArg v3, bool v3const, TCGArg v4, bool v4const) 1546{ 1547 int cc, inv_cc; 1548 1549 cc = tgen_cmp2(s, type, c, c1, c2, c2const, false, &inv_cc); 1550 tgen_movcond_int(s, type, dest, v3, v3const, v4, cc, inv_cc); 1551} 1552 1553static const TCGOutOpMovcond outop_movcond = { 1554 .base.static_constraint = C_O1_I4(r, r, rC, rI, r), 1555 .out = tgen_movcond, 1556}; 1557 1558static void tgen_deposit(TCGContext *s, TCGReg dest, TCGReg src, 1559 int ofs, int len, int z) 1560{ 1561 int lsb = (63 - ofs); 1562 int msb = lsb - (len - 1); 1563 tcg_out_risbg(s, dest, src, msb, lsb, ofs, z); 1564} 1565 1566static void tgen_extract(TCGContext *s, TCGReg dest, TCGReg src, 1567 int ofs, int len) 1568{ 1569 if (ofs == 0) { 1570 switch (len) { 1571 case 8: 1572 tcg_out_ext8u(s, dest, src); 1573 return; 1574 case 16: 1575 tcg_out_ext16u(s, dest, src); 1576 return; 1577 case 32: 1578 tcg_out_ext32u(s, dest, src); 1579 return; 1580 } 1581 } 1582 tcg_out_risbg(s, dest, src, 64 - len, 63, 64 - ofs, 1); 1583} 1584 1585static void tgen_sextract(TCGContext *s, TCGReg dest, TCGReg src, 1586 int ofs, int len) 1587{ 1588 if (ofs == 0) { 1589 switch (len) { 1590 case 8: 1591 tcg_out_ext8s(s, TCG_TYPE_REG, dest, src); 1592 return; 1593 case 16: 1594 tcg_out_ext16s(s, TCG_TYPE_REG, dest, src); 1595 return; 1596 case 32: 1597 tcg_out_ext32s(s, dest, src); 1598 return; 1599 } 1600 } 1601 g_assert_not_reached(); 1602} 1603 1604static void tgen_gotoi(TCGContext *s, int cc, const tcg_insn_unit *dest) 1605{ 1606 ptrdiff_t off = tcg_pcrel_diff(s, dest) >> 1; 1607 if (off == (int16_t)off) { 1608 tcg_out_insn(s, RI, BRC, cc, off); 1609 } else if (off == (int32_t)off) { 1610 tcg_out_insn(s, RIL, BRCL, cc, off); 1611 } else { 1612 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)dest); 1613 tcg_out_insn(s, RR, BCR, cc, TCG_TMP0); 1614 } 1615} 1616 1617static void tgen_branch(TCGContext *s, int cc, TCGLabel *l) 1618{ 1619 if (l->has_value) { 1620 tgen_gotoi(s, cc, l->u.value_ptr); 1621 } else { 1622 tcg_out16(s, RI_BRC | (cc << 4)); 1623 tcg_out_reloc(s, s->code_ptr, R_390_PC16DBL, l, 2); 1624 s->code_ptr += 1; 1625 } 1626} 1627 1628static void tgen_compare_branch(TCGContext *s, S390Opcode opc, int cc, 1629 TCGReg r1, TCGReg r2, TCGLabel *l) 1630{ 1631 tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2); 1632 /* Format RIE-b */ 1633 tcg_out16(s, (opc & 0xff00) | (r1 << 4) | r2); 1634 tcg_out16(s, 0); 1635 tcg_out16(s, cc << 12 | (opc & 0xff)); 1636} 1637 1638static void tgen_compare_imm_branch(TCGContext *s, S390Opcode opc, int cc, 1639 TCGReg r1, int i2, TCGLabel *l) 1640{ 1641 tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2); 1642 /* Format RIE-c */ 1643 tcg_out16(s, (opc & 0xff00) | (r1 << 4) | cc); 1644 tcg_out16(s, 0); 1645 tcg_out16(s, (i2 << 8) | (opc & 0xff)); 1646} 1647 1648static void tgen_brcond(TCGContext *s, TCGType type, TCGCond c, 1649 TCGReg r1, TCGArg c2, int c2const, TCGLabel *l) 1650{ 1651 int cc; 1652 1653 if (!is_tst_cond(c)) { 1654 bool is_unsigned = is_unsigned_cond(c); 1655 bool in_range; 1656 S390Opcode opc; 1657 1658 cc = tcg_cond_to_s390_cond[c]; 1659 1660 if (!c2const) { 1661 opc = (type == TCG_TYPE_I32 1662 ? (is_unsigned ? RIEb_CLRJ : RIEb_CRJ) 1663 : (is_unsigned ? RIEb_CLGRJ : RIEb_CGRJ)); 1664 tgen_compare_branch(s, opc, cc, r1, c2, l); 1665 return; 1666 } 1667 1668 /* 1669 * COMPARE IMMEDIATE AND BRANCH RELATIVE has an 8-bit immediate field. 1670 * If the immediate we've been given does not fit that range, we'll 1671 * fall back to separate compare and branch instructions using the 1672 * larger comparison range afforded by COMPARE IMMEDIATE. 1673 */ 1674 if (type == TCG_TYPE_I32) { 1675 if (is_unsigned) { 1676 opc = RIEc_CLIJ; 1677 in_range = (uint32_t)c2 == (uint8_t)c2; 1678 } else { 1679 opc = RIEc_CIJ; 1680 in_range = (int32_t)c2 == (int8_t)c2; 1681 } 1682 } else { 1683 if (is_unsigned) { 1684 opc = RIEc_CLGIJ; 1685 in_range = (uint64_t)c2 == (uint8_t)c2; 1686 } else { 1687 opc = RIEc_CGIJ; 1688 in_range = (int64_t)c2 == (int8_t)c2; 1689 } 1690 } 1691 if (in_range) { 1692 tgen_compare_imm_branch(s, opc, cc, r1, c2, l); 1693 return; 1694 } 1695 } 1696 1697 cc = tgen_cmp(s, type, c, r1, c2, c2const, false); 1698 tgen_branch(s, cc, l); 1699} 1700 1701static void tgen_brcondr(TCGContext *s, TCGType type, TCGCond c, 1702 TCGReg a0, TCGReg a1, TCGLabel *l) 1703{ 1704 tgen_brcond(s, type, c, a0, a1, false, l); 1705} 1706 1707static void tgen_brcondi(TCGContext *s, TCGType type, TCGCond c, 1708 TCGReg a0, tcg_target_long a1, TCGLabel *l) 1709{ 1710 tgen_brcond(s, type, c, a0, a1, true, l); 1711} 1712 1713static const TCGOutOpBrcond outop_brcond = { 1714 .base.static_constraint = C_O0_I2(r, rC), 1715 .out_rr = tgen_brcondr, 1716 .out_ri = tgen_brcondi, 1717}; 1718 1719static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *dest) 1720{ 1721 ptrdiff_t off = tcg_pcrel_diff(s, dest) >> 1; 1722 if (off == (int32_t)off) { 1723 tcg_out_insn(s, RIL, BRASL, TCG_REG_R14, off); 1724 } else { 1725 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)dest); 1726 tcg_out_insn(s, RR, BASR, TCG_REG_R14, TCG_TMP0); 1727 } 1728} 1729 1730static void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest, 1731 const TCGHelperInfo *info) 1732{ 1733 tcg_out_call_int(s, dest); 1734} 1735 1736typedef struct { 1737 TCGReg base; 1738 TCGReg index; 1739 int disp; 1740 TCGAtomAlign aa; 1741} HostAddress; 1742 1743bool tcg_target_has_memory_bswap(MemOp memop) 1744{ 1745 TCGAtomAlign aa; 1746 1747 if ((memop & MO_SIZE) <= MO_64) { 1748 return true; 1749 } 1750 1751 /* 1752 * Reject 16-byte memop with 16-byte atomicity, 1753 * but do allow a pair of 64-bit operations. 1754 */ 1755 aa = atom_and_align_for_opc(tcg_ctx, memop, MO_ATOM_IFALIGN, true); 1756 return aa.atom <= MO_64; 1757} 1758 1759static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg data, 1760 HostAddress h) 1761{ 1762 switch (opc & (MO_SSIZE | MO_BSWAP)) { 1763 case MO_UB: 1764 tcg_out_insn(s, RXY, LLGC, data, h.base, h.index, h.disp); 1765 break; 1766 case MO_SB: 1767 tcg_out_insn(s, RXY, LGB, data, h.base, h.index, h.disp); 1768 break; 1769 1770 case MO_UW | MO_BSWAP: 1771 /* swapped unsigned halfword load with upper bits zeroed */ 1772 tcg_out_insn(s, RXY, LRVH, data, h.base, h.index, h.disp); 1773 tcg_out_ext16u(s, data, data); 1774 break; 1775 case MO_UW: 1776 tcg_out_insn(s, RXY, LLGH, data, h.base, h.index, h.disp); 1777 break; 1778 1779 case MO_SW | MO_BSWAP: 1780 /* swapped sign-extended halfword load */ 1781 tcg_out_insn(s, RXY, LRVH, data, h.base, h.index, h.disp); 1782 tcg_out_ext16s(s, TCG_TYPE_REG, data, data); 1783 break; 1784 case MO_SW: 1785 tcg_out_insn(s, RXY, LGH, data, h.base, h.index, h.disp); 1786 break; 1787 1788 case MO_UL | MO_BSWAP: 1789 /* swapped unsigned int load with upper bits zeroed */ 1790 tcg_out_insn(s, RXY, LRV, data, h.base, h.index, h.disp); 1791 tcg_out_ext32u(s, data, data); 1792 break; 1793 case MO_UL: 1794 tcg_out_insn(s, RXY, LLGF, data, h.base, h.index, h.disp); 1795 break; 1796 1797 case MO_SL | MO_BSWAP: 1798 /* swapped sign-extended int load */ 1799 tcg_out_insn(s, RXY, LRV, data, h.base, h.index, h.disp); 1800 tcg_out_ext32s(s, data, data); 1801 break; 1802 case MO_SL: 1803 tcg_out_insn(s, RXY, LGF, data, h.base, h.index, h.disp); 1804 break; 1805 1806 case MO_UQ | MO_BSWAP: 1807 tcg_out_insn(s, RXY, LRVG, data, h.base, h.index, h.disp); 1808 break; 1809 case MO_UQ: 1810 tcg_out_insn(s, RXY, LG, data, h.base, h.index, h.disp); 1811 break; 1812 1813 default: 1814 g_assert_not_reached(); 1815 } 1816} 1817 1818static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg data, 1819 HostAddress h) 1820{ 1821 switch (opc & (MO_SIZE | MO_BSWAP)) { 1822 case MO_UB: 1823 if (h.disp >= 0 && h.disp < 0x1000) { 1824 tcg_out_insn(s, RX, STC, data, h.base, h.index, h.disp); 1825 } else { 1826 tcg_out_insn(s, RXY, STCY, data, h.base, h.index, h.disp); 1827 } 1828 break; 1829 1830 case MO_UW | MO_BSWAP: 1831 tcg_out_insn(s, RXY, STRVH, data, h.base, h.index, h.disp); 1832 break; 1833 case MO_UW: 1834 if (h.disp >= 0 && h.disp < 0x1000) { 1835 tcg_out_insn(s, RX, STH, data, h.base, h.index, h.disp); 1836 } else { 1837 tcg_out_insn(s, RXY, STHY, data, h.base, h.index, h.disp); 1838 } 1839 break; 1840 1841 case MO_UL | MO_BSWAP: 1842 tcg_out_insn(s, RXY, STRV, data, h.base, h.index, h.disp); 1843 break; 1844 case MO_UL: 1845 if (h.disp >= 0 && h.disp < 0x1000) { 1846 tcg_out_insn(s, RX, ST, data, h.base, h.index, h.disp); 1847 } else { 1848 tcg_out_insn(s, RXY, STY, data, h.base, h.index, h.disp); 1849 } 1850 break; 1851 1852 case MO_UQ | MO_BSWAP: 1853 tcg_out_insn(s, RXY, STRVG, data, h.base, h.index, h.disp); 1854 break; 1855 case MO_UQ: 1856 tcg_out_insn(s, RXY, STG, data, h.base, h.index, h.disp); 1857 break; 1858 1859 default: 1860 g_assert_not_reached(); 1861 } 1862} 1863 1864static const TCGLdstHelperParam ldst_helper_param = { 1865 .ntmp = 1, .tmp = { TCG_TMP0 } 1866}; 1867 1868static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1869{ 1870 MemOp opc = get_memop(lb->oi); 1871 1872 if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL, 1873 (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 2)) { 1874 return false; 1875 } 1876 1877 tcg_out_ld_helper_args(s, lb, &ldst_helper_param); 1878 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE]); 1879 tcg_out_ld_helper_ret(s, lb, false, &ldst_helper_param); 1880 1881 tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr); 1882 return true; 1883} 1884 1885static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1886{ 1887 MemOp opc = get_memop(lb->oi); 1888 1889 if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL, 1890 (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 2)) { 1891 return false; 1892 } 1893 1894 tcg_out_st_helper_args(s, lb, &ldst_helper_param); 1895 tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE]); 1896 1897 tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr); 1898 return true; 1899} 1900 1901/* We're expecting to use a 20-bit negative offset on the tlb memory ops. */ 1902#define MIN_TLB_MASK_TABLE_OFS -(1 << 19) 1903 1904/* 1905 * For system-mode, perform the TLB load and compare. 1906 * For user-mode, perform any required alignment tests. 1907 * In both cases, return a TCGLabelQemuLdst structure if the slow path 1908 * is required and fill in @h with the host address for the fast path. 1909 */ 1910static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 1911 TCGReg addr_reg, MemOpIdx oi, 1912 bool is_ld) 1913{ 1914 TCGType addr_type = s->addr_type; 1915 TCGLabelQemuLdst *ldst = NULL; 1916 MemOp opc = get_memop(oi); 1917 MemOp s_bits = opc & MO_SIZE; 1918 unsigned a_mask; 1919 1920 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, s_bits == MO_128); 1921 a_mask = (1 << h->aa.align) - 1; 1922 1923 if (tcg_use_softmmu) { 1924 unsigned s_mask = (1 << s_bits) - 1; 1925 int mem_index = get_mmuidx(oi); 1926 int fast_off = tlb_mask_table_ofs(s, mem_index); 1927 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); 1928 int table_off = fast_off + offsetof(CPUTLBDescFast, table); 1929 int ofs, a_off; 1930 uint64_t tlb_mask; 1931 1932 ldst = new_ldst_label(s); 1933 ldst->is_ld = is_ld; 1934 ldst->oi = oi; 1935 ldst->addr_reg = addr_reg; 1936 1937 tcg_out_sh64(s, RSY_SRLG, TCG_TMP0, addr_reg, TCG_REG_NONE, 1938 s->page_bits - CPU_TLB_ENTRY_BITS); 1939 1940 tcg_out_insn(s, RXY, NG, TCG_TMP0, TCG_AREG0, TCG_REG_NONE, mask_off); 1941 tcg_out_insn(s, RXY, AG, TCG_TMP0, TCG_AREG0, TCG_REG_NONE, table_off); 1942 1943 /* 1944 * For aligned accesses, we check the first byte and include the 1945 * alignment bits within the address. For unaligned access, we 1946 * check that we don't cross pages using the address of the last 1947 * byte of the access. 1948 */ 1949 a_off = (a_mask >= s_mask ? 0 : s_mask - a_mask); 1950 tlb_mask = (uint64_t)s->page_mask | a_mask; 1951 if (a_off == 0) { 1952 tgen_andi_risbg(s, TCG_REG_R0, addr_reg, tlb_mask); 1953 } else { 1954 tcg_out_insn(s, RX, LA, TCG_REG_R0, addr_reg, TCG_REG_NONE, a_off); 1955 tgen_andi(s, addr_type, TCG_REG_R0, tlb_mask); 1956 } 1957 1958 if (is_ld) { 1959 ofs = offsetof(CPUTLBEntry, addr_read); 1960 } else { 1961 ofs = offsetof(CPUTLBEntry, addr_write); 1962 } 1963 if (addr_type == TCG_TYPE_I32) { 1964 ofs += HOST_BIG_ENDIAN * 4; 1965 tcg_out_insn(s, RX, C, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs); 1966 } else { 1967 tcg_out_insn(s, RXY, CG, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs); 1968 } 1969 1970 tcg_out16(s, RI_BRC | (S390_CC_NE << 4)); 1971 ldst->label_ptr[0] = s->code_ptr++; 1972 1973 h->index = TCG_TMP0; 1974 tcg_out_insn(s, RXY, LG, h->index, TCG_TMP0, TCG_REG_NONE, 1975 offsetof(CPUTLBEntry, addend)); 1976 1977 if (addr_type == TCG_TYPE_I32) { 1978 tcg_out_insn(s, RRE, ALGFR, h->index, addr_reg); 1979 h->base = TCG_REG_NONE; 1980 } else { 1981 h->base = addr_reg; 1982 } 1983 h->disp = 0; 1984 } else { 1985 if (a_mask) { 1986 ldst = new_ldst_label(s); 1987 ldst->is_ld = is_ld; 1988 ldst->oi = oi; 1989 ldst->addr_reg = addr_reg; 1990 1991 tcg_debug_assert(a_mask <= 0xffff); 1992 tcg_out_insn(s, RI, TMLL, addr_reg, a_mask); 1993 1994 tcg_out16(s, RI_BRC | (S390_TM_NE << 4)); 1995 ldst->label_ptr[0] = s->code_ptr++; 1996 } 1997 1998 h->base = addr_reg; 1999 if (addr_type == TCG_TYPE_I32) { 2000 tcg_out_ext32u(s, TCG_TMP0, addr_reg); 2001 h->base = TCG_TMP0; 2002 } 2003 if (guest_base < 0x80000) { 2004 h->index = TCG_REG_NONE; 2005 h->disp = guest_base; 2006 } else { 2007 h->index = TCG_GUEST_BASE_REG; 2008 h->disp = 0; 2009 } 2010 } 2011 2012 return ldst; 2013} 2014 2015static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_reg, 2016 MemOpIdx oi, TCGType data_type) 2017{ 2018 TCGLabelQemuLdst *ldst; 2019 HostAddress h; 2020 2021 ldst = prepare_host_addr(s, &h, addr_reg, oi, true); 2022 tcg_out_qemu_ld_direct(s, get_memop(oi), data_reg, h); 2023 2024 if (ldst) { 2025 ldst->type = data_type; 2026 ldst->datalo_reg = data_reg; 2027 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 2028 } 2029} 2030 2031static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_reg, 2032 MemOpIdx oi, TCGType data_type) 2033{ 2034 TCGLabelQemuLdst *ldst; 2035 HostAddress h; 2036 2037 ldst = prepare_host_addr(s, &h, addr_reg, oi, false); 2038 tcg_out_qemu_st_direct(s, get_memop(oi), data_reg, h); 2039 2040 if (ldst) { 2041 ldst->type = data_type; 2042 ldst->datalo_reg = data_reg; 2043 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 2044 } 2045} 2046 2047static void tcg_out_qemu_ldst_i128(TCGContext *s, TCGReg datalo, TCGReg datahi, 2048 TCGReg addr_reg, MemOpIdx oi, bool is_ld) 2049{ 2050 TCGLabel *l1 = NULL, *l2 = NULL; 2051 TCGLabelQemuLdst *ldst; 2052 HostAddress h; 2053 bool need_bswap; 2054 bool use_pair; 2055 S390Opcode insn; 2056 2057 ldst = prepare_host_addr(s, &h, addr_reg, oi, is_ld); 2058 2059 use_pair = h.aa.atom < MO_128; 2060 need_bswap = get_memop(oi) & MO_BSWAP; 2061 2062 if (!use_pair) { 2063 /* 2064 * Atomicity requires we use LPQ. If we've already checked for 2065 * 16-byte alignment, that's all we need. If we arrive with 2066 * lesser alignment, we have determined that less than 16-byte 2067 * alignment can be satisfied with two 8-byte loads. 2068 */ 2069 if (h.aa.align < MO_128) { 2070 use_pair = true; 2071 l1 = gen_new_label(); 2072 l2 = gen_new_label(); 2073 2074 tcg_out_insn(s, RI, TMLL, addr_reg, 15); 2075 tgen_branch(s, S390_TM_NE, l1); 2076 } 2077 2078 tcg_debug_assert(!need_bswap); 2079 tcg_debug_assert(datalo & 1); 2080 tcg_debug_assert(datahi == datalo - 1); 2081 insn = is_ld ? RXY_LPQ : RXY_STPQ; 2082 tcg_out_insn_RXY(s, insn, datahi, h.base, h.index, h.disp); 2083 2084 if (use_pair) { 2085 tgen_branch(s, S390_CC_ALWAYS, l2); 2086 tcg_out_label(s, l1); 2087 } 2088 } 2089 if (use_pair) { 2090 TCGReg d1, d2; 2091 2092 if (need_bswap) { 2093 d1 = datalo, d2 = datahi; 2094 insn = is_ld ? RXY_LRVG : RXY_STRVG; 2095 } else { 2096 d1 = datahi, d2 = datalo; 2097 insn = is_ld ? RXY_LG : RXY_STG; 2098 } 2099 2100 if (h.base == d1 || h.index == d1) { 2101 tcg_out_insn(s, RXY, LAY, TCG_TMP0, h.base, h.index, h.disp); 2102 h.base = TCG_TMP0; 2103 h.index = TCG_REG_NONE; 2104 h.disp = 0; 2105 } 2106 tcg_out_insn_RXY(s, insn, d1, h.base, h.index, h.disp); 2107 tcg_out_insn_RXY(s, insn, d2, h.base, h.index, h.disp + 8); 2108 } 2109 if (l2) { 2110 tcg_out_label(s, l2); 2111 } 2112 2113 if (ldst) { 2114 ldst->type = TCG_TYPE_I128; 2115 ldst->datalo_reg = datalo; 2116 ldst->datahi_reg = datahi; 2117 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 2118 } 2119} 2120 2121static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) 2122{ 2123 /* Reuse the zeroing that exists for goto_ptr. */ 2124 if (a0 == 0) { 2125 tgen_gotoi(s, S390_CC_ALWAYS, tcg_code_gen_epilogue); 2126 } else { 2127 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, a0); 2128 tgen_gotoi(s, S390_CC_ALWAYS, tb_ret_addr); 2129 } 2130} 2131 2132static void tcg_out_goto_tb(TCGContext *s, int which) 2133{ 2134 /* 2135 * Branch displacement must be aligned for atomic patching; 2136 * see if we need to add extra nop before branch 2137 */ 2138 if (!QEMU_PTR_IS_ALIGNED(s->code_ptr + 1, 4)) { 2139 tcg_out16(s, NOP); 2140 } 2141 tcg_out16(s, RIL_BRCL | (S390_CC_ALWAYS << 4)); 2142 set_jmp_insn_offset(s, which); 2143 s->code_ptr += 2; 2144 set_jmp_reset_offset(s, which); 2145} 2146 2147void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 2148 uintptr_t jmp_rx, uintptr_t jmp_rw) 2149{ 2150 if (!HAVE_FACILITY(GEN_INST_EXT)) { 2151 return; 2152 } 2153 /* patch the branch destination */ 2154 uintptr_t addr = tb->jmp_target_addr[n]; 2155 intptr_t disp = addr - (jmp_rx - 2); 2156 qatomic_set((int32_t *)jmp_rw, disp / 2); 2157 /* no need to flush icache explicitly */ 2158} 2159 2160 2161static void tgen_add(TCGContext *s, TCGType type, 2162 TCGReg a0, TCGReg a1, TCGReg a2) 2163{ 2164 if (a0 != a1) { 2165 tcg_out_insn(s, RX, LA, a0, a1, a2, 0); 2166 } else if (type == TCG_TYPE_I32) { 2167 tcg_out_insn(s, RR, AR, a0, a2); 2168 } else { 2169 tcg_out_insn(s, RRE, AGR, a0, a2); 2170 } 2171} 2172 2173static void tgen_addi(TCGContext *s, TCGType type, 2174 TCGReg a0, TCGReg a1, tcg_target_long a2) 2175{ 2176 if (a0 == a1) { 2177 if (type == TCG_TYPE_I32) { 2178 if (a2 == (int16_t)a2) { 2179 tcg_out_insn(s, RI, AHI, a0, a2); 2180 } else { 2181 tcg_out_insn(s, RIL, AFI, a0, a2); 2182 } 2183 return; 2184 } 2185 if (a2 == (int16_t)a2) { 2186 tcg_out_insn(s, RI, AGHI, a0, a2); 2187 return; 2188 } 2189 if (a2 == (int32_t)a2) { 2190 tcg_out_insn(s, RIL, AGFI, a0, a2); 2191 return; 2192 } 2193 if (a2 == (uint32_t)a2) { 2194 tcg_out_insn(s, RIL, ALGFI, a0, a2); 2195 return; 2196 } 2197 if (-a2 == (uint32_t)-a2) { 2198 tcg_out_insn(s, RIL, SLGFI, a0, -a2); 2199 return; 2200 } 2201 } 2202 tcg_out_mem(s, RX_LA, RXY_LAY, a0, a1, TCG_REG_NONE, a2); 2203} 2204 2205static const TCGOutOpBinary outop_add = { 2206 .base.static_constraint = C_O1_I2(r, r, ri), 2207 .out_rrr = tgen_add, 2208 .out_rri = tgen_addi, 2209}; 2210 2211static void tgen_and(TCGContext *s, TCGType type, 2212 TCGReg a0, TCGReg a1, TCGReg a2) 2213{ 2214 if (type != TCG_TYPE_I32) { 2215 tcg_out_insn(s, RRFa, NGRK, a0, a1, a2); 2216 } else if (a0 == a1) { 2217 tcg_out_insn(s, RR, NR, a0, a2); 2218 } else { 2219 tcg_out_insn(s, RRFa, NRK, a0, a1, a2); 2220 } 2221} 2222 2223static void tgen_andi_3(TCGContext *s, TCGType type, 2224 TCGReg a0, TCGReg a1, tcg_target_long a2) 2225{ 2226 tcg_out_mov(s, type, a0, a1); 2227 tgen_andi(s, type, a0, a2); 2228} 2229 2230static const TCGOutOpBinary outop_and = { 2231 .base.static_constraint = C_O1_I2(r, r, rNKR), 2232 .out_rrr = tgen_and, 2233 .out_rri = tgen_andi_3, 2234}; 2235 2236static void tgen_andc(TCGContext *s, TCGType type, 2237 TCGReg a0, TCGReg a1, TCGReg a2) 2238{ 2239 if (type == TCG_TYPE_I32) { 2240 tcg_out_insn(s, RRFa, NCRK, a0, a1, a2); 2241 } else { 2242 tcg_out_insn(s, RRFa, NCGRK, a0, a1, a2); 2243 } 2244} 2245 2246static TCGConstraintSetIndex cset_misc3_rrr(TCGType type, unsigned flags) 2247{ 2248 return HAVE_FACILITY(MISC_INSN_EXT3) ? C_O1_I2(r, r, r) : C_NotImplemented; 2249} 2250 2251static const TCGOutOpBinary outop_andc = { 2252 .base.static_constraint = C_Dynamic, 2253 .base.dynamic_constraint = cset_misc3_rrr, 2254 .out_rrr = tgen_andc, 2255}; 2256 2257static void tgen_clz_int(TCGContext *s, TCGReg dest, TCGReg a1, 2258 TCGArg a2, int a2const) 2259{ 2260 /* 2261 * Since this sets both R and R+1, we have no choice but to store the 2262 * result into R0, allowing R1 == TCG_TMP0 to be clobbered as well. 2263 */ 2264 QEMU_BUILD_BUG_ON(TCG_TMP0 != TCG_REG_R1); 2265 tcg_out_insn(s, RRE, FLOGR, TCG_REG_R0, a1); 2266 2267 if (a2const && a2 == 64) { 2268 tcg_out_mov(s, TCG_TYPE_I64, dest, TCG_REG_R0); 2269 return; 2270 } 2271 2272 /* 2273 * Conditions from FLOGR are: 2274 * 2 -> one bit found 2275 * 8 -> no one bit found 2276 */ 2277 tgen_movcond_int(s, TCG_TYPE_I64, dest, a2, a2const, TCG_REG_R0, 8, 2); 2278} 2279 2280static void tgen_clz(TCGContext *s, TCGType type, 2281 TCGReg a0, TCGReg a1, TCGReg a2) 2282{ 2283 tgen_clz_int(s, a0, a1, a2, false); 2284} 2285 2286static void tgen_clzi(TCGContext *s, TCGType type, 2287 TCGReg a0, TCGReg a1, tcg_target_long a2) 2288{ 2289 tgen_clz_int(s, a0, a1, a2, true); 2290} 2291 2292static TCGConstraintSetIndex cset_clz(TCGType type, unsigned flags) 2293{ 2294 return type == TCG_TYPE_I64 ? C_O1_I2(r, r, rI) : C_NotImplemented; 2295} 2296 2297static const TCGOutOpBinary outop_clz = { 2298 .base.static_constraint = C_Dynamic, 2299 .base.dynamic_constraint = cset_clz, 2300 .out_rrr = tgen_clz, 2301 .out_rri = tgen_clzi, 2302}; 2303 2304static void tgen_ctpop(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) 2305{ 2306 /* With MIE3, and bit 0 of m4 set, we get the complete result. */ 2307 if (HAVE_FACILITY(MISC_INSN_EXT3)) { 2308 if (type == TCG_TYPE_I32) { 2309 tcg_out_ext32u(s, dest, src); 2310 src = dest; 2311 } 2312 tcg_out_insn(s, RRFc, POPCNT, dest, src, 8); 2313 return; 2314 } 2315 2316 /* Without MIE3, each byte gets the count of bits for the byte. */ 2317 tcg_out_insn(s, RRFc, POPCNT, dest, src, 0); 2318 2319 /* Multiply to sum each byte at the top of the word. */ 2320 if (type == TCG_TYPE_I32) { 2321 tcg_out_insn(s, RIL, MSFI, dest, 0x01010101); 2322 tcg_out_sh32(s, RS_SRL, dest, TCG_REG_NONE, 24); 2323 } else { 2324 tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 0x0101010101010101ull); 2325 tcg_out_insn(s, RRE, MSGR, dest, TCG_TMP0); 2326 tcg_out_sh64(s, RSY_SRLG, dest, dest, TCG_REG_NONE, 56); 2327 } 2328} 2329 2330static const TCGOutOpUnary outop_ctpop = { 2331 .base.static_constraint = C_O1_I1(r, r), 2332 .out_rr = tgen_ctpop, 2333}; 2334 2335static const TCGOutOpBinary outop_ctz = { 2336 .base.static_constraint = C_NotImplemented, 2337}; 2338 2339static const TCGOutOpBinary outop_divs = { 2340 .base.static_constraint = C_NotImplemented, 2341}; 2342 2343static void tgen_divs2(TCGContext *s, TCGType type, 2344 TCGReg a0, TCGReg a1, TCGReg a4) 2345{ 2346 tcg_debug_assert((a1 & 1) == 0); 2347 tcg_debug_assert(a0 == a1 + 1); 2348 if (type == TCG_TYPE_I32) { 2349 tcg_out_insn(s, RR, DR, a1, a4); 2350 } else { 2351 /* 2352 * TODO: Move the sign-extend of the numerator from a2 into a3 2353 * into the tcg backend, instead of in early expansion. It is 2354 * required for 32-bit DR, but not 64-bit DSGR. 2355 */ 2356 tcg_out_insn(s, RRE, DSGR, a1, a4); 2357 } 2358} 2359 2360static const TCGOutOpDivRem outop_divs2 = { 2361 .base.static_constraint = C_O2_I3(o, m, 0, 1, r), 2362 .out_rr01r = tgen_divs2, 2363}; 2364 2365static const TCGOutOpBinary outop_divu = { 2366 .base.static_constraint = C_NotImplemented, 2367}; 2368 2369static void tgen_divu2(TCGContext *s, TCGType type, 2370 TCGReg a0, TCGReg a1, TCGReg a4) 2371{ 2372 tcg_debug_assert((a1 & 1) == 0); 2373 tcg_debug_assert(a0 == a1 + 1); 2374 if (type == TCG_TYPE_I32) { 2375 tcg_out_insn(s, RRE, DLR, a1, a4); 2376 } else { 2377 tcg_out_insn(s, RRE, DLGR, a1, a4); 2378 } 2379} 2380 2381static const TCGOutOpDivRem outop_divu2 = { 2382 .base.static_constraint = C_O2_I3(o, m, 0, 1, r), 2383 .out_rr01r = tgen_divu2, 2384}; 2385 2386static void tgen_eqv(TCGContext *s, TCGType type, 2387 TCGReg a0, TCGReg a1, TCGReg a2) 2388{ 2389 if (type == TCG_TYPE_I32) { 2390 tcg_out_insn(s, RRFa, NXRK, a0, a1, a2); 2391 } else { 2392 tcg_out_insn(s, RRFa, NXGRK, a0, a1, a2); 2393 } 2394} 2395 2396static const TCGOutOpBinary outop_eqv = { 2397 .base.static_constraint = C_Dynamic, 2398 .base.dynamic_constraint = cset_misc3_rrr, 2399 .out_rrr = tgen_eqv, 2400}; 2401 2402static void tgen_mul(TCGContext *s, TCGType type, 2403 TCGReg a0, TCGReg a1, TCGReg a2) 2404{ 2405 if (type == TCG_TYPE_I32) { 2406 if (a0 == a1) { 2407 tcg_out_insn(s, RRE, MSR, a0, a2); 2408 } else { 2409 tcg_out_insn(s, RRFa, MSRKC, a0, a1, a2); 2410 } 2411 } else { 2412 if (a0 == a1) { 2413 tcg_out_insn(s, RRE, MSGR, a0, a2); 2414 } else { 2415 tcg_out_insn(s, RRFa, MSGRKC, a0, a1, a2); 2416 } 2417 } 2418} 2419 2420static void tgen_muli(TCGContext *s, TCGType type, 2421 TCGReg a0, TCGReg a1, tcg_target_long a2) 2422{ 2423 tcg_out_mov(s, type, a0, a1); 2424 if (type == TCG_TYPE_I32) { 2425 if (a2 == (int16_t)a2) { 2426 tcg_out_insn(s, RI, MHI, a0, a2); 2427 } else { 2428 tcg_out_insn(s, RIL, MSFI, a0, a2); 2429 } 2430 } else { 2431 if (a2 == (int16_t)a2) { 2432 tcg_out_insn(s, RI, MGHI, a0, a2); 2433 } else { 2434 tcg_out_insn(s, RIL, MSGFI, a0, a2); 2435 } 2436 } 2437} 2438 2439static TCGConstraintSetIndex cset_mul(TCGType type, unsigned flags) 2440{ 2441 return (HAVE_FACILITY(MISC_INSN_EXT2) 2442 ? C_O1_I2(r, r, rJ) 2443 : C_O1_I2(r, 0, rJ)); 2444} 2445 2446static const TCGOutOpBinary outop_mul = { 2447 .base.static_constraint = C_Dynamic, 2448 .base.dynamic_constraint = cset_mul, 2449 .out_rrr = tgen_mul, 2450 .out_rri = tgen_muli, 2451}; 2452 2453static void tgen_muls2(TCGContext *s, TCGType type, 2454 TCGReg a0, TCGReg a1, TCGReg a2, TCGReg a3) 2455{ 2456 tcg_debug_assert((a1 & 1) == 0); 2457 tcg_debug_assert(a0 == a1 + 1); 2458 tcg_out_insn(s, RRFa, MGRK, a1, a2, a3); 2459} 2460 2461static TCGConstraintSetIndex cset_muls2(TCGType type, unsigned flags) 2462{ 2463 return (type == TCG_TYPE_I64 && HAVE_FACILITY(MISC_INSN_EXT2) 2464 ? C_O2_I2(o, m, r, r) : C_NotImplemented); 2465} 2466 2467static const TCGOutOpMul2 outop_muls2 = { 2468 .base.static_constraint = C_Dynamic, 2469 .base.dynamic_constraint = cset_muls2, 2470 .out_rrrr = tgen_muls2, 2471}; 2472 2473static const TCGOutOpBinary outop_mulsh = { 2474 .base.static_constraint = C_NotImplemented, 2475}; 2476 2477static void tgen_mulu2(TCGContext *s, TCGType type, 2478 TCGReg a0, TCGReg a1, TCGReg a2, TCGReg a3) 2479{ 2480 tcg_debug_assert(a0 == a2); 2481 tcg_debug_assert((a1 & 1) == 0); 2482 tcg_debug_assert(a0 == a1 + 1); 2483 tcg_out_insn(s, RRE, MLGR, a1, a3); 2484} 2485 2486static TCGConstraintSetIndex cset_mulu2(TCGType type, unsigned flags) 2487{ 2488 return (type == TCG_TYPE_I64 && HAVE_FACILITY(MISC_INSN_EXT2) 2489 ? C_O2_I2(o, m, 0, r) : C_NotImplemented); 2490} 2491 2492static const TCGOutOpMul2 outop_mulu2 = { 2493 .base.static_constraint = C_Dynamic, 2494 .base.dynamic_constraint = cset_mulu2, 2495 .out_rrrr = tgen_mulu2, 2496}; 2497 2498static const TCGOutOpBinary outop_muluh = { 2499 .base.static_constraint = C_NotImplemented, 2500}; 2501 2502static void tgen_nand(TCGContext *s, TCGType type, 2503 TCGReg a0, TCGReg a1, TCGReg a2) 2504{ 2505 if (type == TCG_TYPE_I32) { 2506 tcg_out_insn(s, RRFa, NNRK, a0, a1, a2); 2507 } else { 2508 tcg_out_insn(s, RRFa, NNGRK, a0, a1, a2); 2509 } 2510} 2511 2512static const TCGOutOpBinary outop_nand = { 2513 .base.static_constraint = C_Dynamic, 2514 .base.dynamic_constraint = cset_misc3_rrr, 2515 .out_rrr = tgen_nand, 2516}; 2517 2518static void tgen_nor(TCGContext *s, TCGType type, 2519 TCGReg a0, TCGReg a1, TCGReg a2) 2520{ 2521 if (type == TCG_TYPE_I32) { 2522 tcg_out_insn(s, RRFa, NORK, a0, a1, a2); 2523 } else { 2524 tcg_out_insn(s, RRFa, NOGRK, a0, a1, a2); 2525 } 2526} 2527 2528static const TCGOutOpBinary outop_nor = { 2529 .base.static_constraint = C_Dynamic, 2530 .base.dynamic_constraint = cset_misc3_rrr, 2531 .out_rrr = tgen_nor, 2532}; 2533 2534static void tgen_or(TCGContext *s, TCGType type, 2535 TCGReg a0, TCGReg a1, TCGReg a2) 2536{ 2537 if (type != TCG_TYPE_I32) { 2538 tcg_out_insn(s, RRFa, OGRK, a0, a1, a2); 2539 } else if (a0 == a1) { 2540 tcg_out_insn(s, RR, OR, a0, a2); 2541 } else { 2542 tcg_out_insn(s, RRFa, ORK, a0, a1, a2); 2543 } 2544} 2545 2546static void tgen_ori_3(TCGContext *s, TCGType type, 2547 TCGReg a0, TCGReg a1, tcg_target_long a2) 2548{ 2549 tcg_out_mov(s, type, a0, a1); 2550 tgen_ori(s, a0, type == TCG_TYPE_I32 ? (uint32_t)a2 : a2); 2551} 2552 2553static const TCGOutOpBinary outop_or = { 2554 .base.static_constraint = C_O1_I2(r, r, rK), 2555 .out_rrr = tgen_or, 2556 .out_rri = tgen_ori_3, 2557}; 2558 2559static void tgen_orc(TCGContext *s, TCGType type, 2560 TCGReg a0, TCGReg a1, TCGReg a2) 2561{ 2562 if (type == TCG_TYPE_I32) { 2563 tcg_out_insn(s, RRFa, OCRK, a0, a1, a2); 2564 } else { 2565 tcg_out_insn(s, RRFa, OCGRK, a0, a1, a2); 2566 } 2567} 2568 2569static const TCGOutOpBinary outop_orc = { 2570 .base.static_constraint = C_Dynamic, 2571 .base.dynamic_constraint = cset_misc3_rrr, 2572 .out_rrr = tgen_orc, 2573}; 2574 2575static const TCGOutOpBinary outop_rems = { 2576 .base.static_constraint = C_NotImplemented, 2577}; 2578 2579static const TCGOutOpBinary outop_remu = { 2580 .base.static_constraint = C_NotImplemented, 2581}; 2582 2583static void tgen_rotl_int(TCGContext *s, TCGType type, TCGReg dst, 2584 TCGReg src, TCGReg v, tcg_target_long i) 2585{ 2586 S390Opcode insn = type == TCG_TYPE_I32 ? RSY_RLL : RSY_RLLG; 2587 tcg_out_sh64(s, insn, dst, src, v, i); 2588} 2589 2590static void tgen_rotl(TCGContext *s, TCGType type, 2591 TCGReg a0, TCGReg a1, TCGReg a2) 2592{ 2593 tgen_rotl_int(s, type, a0, a1, a2, 0); 2594} 2595 2596static void tgen_rotli(TCGContext *s, TCGType type, 2597 TCGReg a0, TCGReg a1, tcg_target_long a2) 2598{ 2599 tgen_rotl_int(s, type, a0, a1, TCG_REG_NONE, a2); 2600} 2601 2602static const TCGOutOpBinary outop_rotl = { 2603 .base.static_constraint = C_O1_I2(r, r, ri), 2604 .out_rrr = tgen_rotl, 2605 .out_rri = tgen_rotli, 2606}; 2607 2608static const TCGOutOpBinary outop_rotr = { 2609 .base.static_constraint = C_NotImplemented, 2610}; 2611 2612static void tgen_sar_int(TCGContext *s, TCGType type, TCGReg dst, 2613 TCGReg src, TCGReg v, tcg_target_long i) 2614{ 2615 if (type != TCG_TYPE_I32) { 2616 tcg_out_sh64(s, RSY_SRAG, dst, src, v, i); 2617 } else if (dst == src) { 2618 tcg_out_sh32(s, RS_SRA, dst, v, i); 2619 } else { 2620 tcg_out_sh64(s, RSY_SRAK, dst, src, v, i); 2621 } 2622} 2623 2624static void tgen_sar(TCGContext *s, TCGType type, 2625 TCGReg a0, TCGReg a1, TCGReg a2) 2626{ 2627 tgen_sar_int(s, type, a0, a1, a2, 0); 2628} 2629 2630static void tgen_sari(TCGContext *s, TCGType type, 2631 TCGReg a0, TCGReg a1, tcg_target_long a2) 2632{ 2633 tgen_sar_int(s, type, a0, a1, TCG_REG_NONE, a2); 2634} 2635 2636static const TCGOutOpBinary outop_sar = { 2637 .base.static_constraint = C_O1_I2(r, r, ri), 2638 .out_rrr = tgen_sar, 2639 .out_rri = tgen_sari, 2640}; 2641 2642static void tgen_shl_int(TCGContext *s, TCGType type, TCGReg dst, 2643 TCGReg src, TCGReg v, tcg_target_long i) 2644{ 2645 if (type != TCG_TYPE_I32) { 2646 tcg_out_sh64(s, RSY_SLLG, dst, src, v, i); 2647 } else if (dst == src) { 2648 tcg_out_sh32(s, RS_SLL, dst, v, i); 2649 } else { 2650 tcg_out_sh64(s, RSY_SLLK, dst, src, v, i); 2651 } 2652} 2653 2654static void tgen_shl(TCGContext *s, TCGType type, 2655 TCGReg a0, TCGReg a1, TCGReg a2) 2656{ 2657 tgen_shl_int(s, type, a0, a1, a2, 0); 2658} 2659 2660static void tgen_shli(TCGContext *s, TCGType type, 2661 TCGReg a0, TCGReg a1, tcg_target_long a2) 2662{ 2663 tgen_shl_int(s, type, a0, a1, TCG_REG_NONE, a2); 2664} 2665 2666static const TCGOutOpBinary outop_shl = { 2667 .base.static_constraint = C_O1_I2(r, r, ri), 2668 .out_rrr = tgen_shl, 2669 .out_rri = tgen_shli, 2670}; 2671 2672static void tgen_shr_int(TCGContext *s, TCGType type, TCGReg dst, 2673 TCGReg src, TCGReg v, tcg_target_long i) 2674{ 2675 if (type != TCG_TYPE_I32) { 2676 tcg_out_sh64(s, RSY_SRLG, dst, src, v, i); 2677 } else if (dst == src) { 2678 tcg_out_sh32(s, RS_SRL, dst, v, i); 2679 } else { 2680 tcg_out_sh64(s, RSY_SRLK, dst, src, v, i); 2681 } 2682} 2683 2684static void tgen_shr(TCGContext *s, TCGType type, 2685 TCGReg a0, TCGReg a1, TCGReg a2) 2686{ 2687 tgen_shr_int(s, type, a0, a1, a2, 0); 2688} 2689 2690static void tgen_shri(TCGContext *s, TCGType type, 2691 TCGReg a0, TCGReg a1, tcg_target_long a2) 2692{ 2693 tgen_shr_int(s, type, a0, a1, TCG_REG_NONE, a2); 2694} 2695 2696static const TCGOutOpBinary outop_shr = { 2697 .base.static_constraint = C_O1_I2(r, r, ri), 2698 .out_rrr = tgen_shr, 2699 .out_rri = tgen_shri, 2700}; 2701 2702static void tgen_sub(TCGContext *s, TCGType type, 2703 TCGReg a0, TCGReg a1, TCGReg a2) 2704{ 2705 if (type != TCG_TYPE_I32) { 2706 tcg_out_insn(s, RRFa, SGRK, a0, a1, a2); 2707 } else if (a0 == a1) { 2708 tcg_out_insn(s, RR, SR, a0, a2); 2709 } else { 2710 tcg_out_insn(s, RRFa, SRK, a0, a1, a2); 2711 } 2712} 2713 2714static const TCGOutOpSubtract outop_sub = { 2715 .base.static_constraint = C_O1_I2(r, r, r), 2716 .out_rrr = tgen_sub, 2717}; 2718 2719static void tgen_xor(TCGContext *s, TCGType type, 2720 TCGReg a0, TCGReg a1, TCGReg a2) 2721{ 2722 if (type != TCG_TYPE_I32) { 2723 tcg_out_insn(s, RRFa, XGRK, a0, a1, a2); 2724 } else if (a0 == a1) { 2725 tcg_out_insn(s, RR, XR, a0, a2); 2726 } else { 2727 tcg_out_insn(s, RRFa, XRK, a0, a1, a2); 2728 } 2729} 2730 2731static void tgen_xori_3(TCGContext *s, TCGType type, 2732 TCGReg a0, TCGReg a1, tcg_target_long a2) 2733{ 2734 tcg_out_mov(s, type, a0, a1); 2735 tgen_xori(s, a0, type == TCG_TYPE_I32 ? (uint32_t)a2 : a2); 2736} 2737 2738static const TCGOutOpBinary outop_xor = { 2739 .base.static_constraint = C_O1_I2(r, r, rK), 2740 .out_rrr = tgen_xor, 2741 .out_rri = tgen_xori_3, 2742}; 2743 2744static void tgen_bswap16(TCGContext *s, TCGType type, 2745 TCGReg a0, TCGReg a1, unsigned flags) 2746{ 2747 if (type == TCG_TYPE_I32) { 2748 tcg_out_insn(s, RRE, LRVR, a0, a1); 2749 tcg_out_sh32(s, (flags & TCG_BSWAP_OS ? RS_SRA : RS_SRL), 2750 a0, TCG_REG_NONE, 16); 2751 } else { 2752 tcg_out_insn(s, RRE, LRVGR, a0, a1); 2753 tcg_out_sh64(s, (flags & TCG_BSWAP_OS ? RSY_SRAG : RSY_SRLG), 2754 a0, a0, TCG_REG_NONE, 48); 2755 } 2756} 2757 2758static const TCGOutOpBswap outop_bswap16 = { 2759 .base.static_constraint = C_O1_I1(r, r), 2760 .out_rr = tgen_bswap16, 2761}; 2762 2763static void tgen_bswap32(TCGContext *s, TCGType type, 2764 TCGReg a0, TCGReg a1, unsigned flags) 2765{ 2766 tcg_out_insn(s, RRE, LRVR, a0, a1); 2767 if (flags & TCG_BSWAP_OS) { 2768 tcg_out_ext32s(s, a0, a0); 2769 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 2770 tcg_out_ext32u(s, a0, a0); 2771 } 2772} 2773 2774static const TCGOutOpBswap outop_bswap32 = { 2775 .base.static_constraint = C_O1_I1(r, r), 2776 .out_rr = tgen_bswap32, 2777}; 2778 2779static void tgen_bswap64(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2780{ 2781 tcg_out_insn(s, RRE, LRVGR, a0, a1); 2782} 2783 2784static const TCGOutOpUnary outop_bswap64 = { 2785 .base.static_constraint = C_O1_I1(r, r), 2786 .out_rr = tgen_bswap64, 2787}; 2788 2789static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2790{ 2791 if (type == TCG_TYPE_I32) { 2792 tcg_out_insn(s, RR, LCR, a0, a1); 2793 } else { 2794 tcg_out_insn(s, RRE, LCGR, a0, a1); 2795 } 2796} 2797 2798static const TCGOutOpUnary outop_neg = { 2799 .base.static_constraint = C_O1_I1(r, r), 2800 .out_rr = tgen_neg, 2801}; 2802 2803static void tgen_not(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2804{ 2805 tgen_nor(s, type, a0, a1, a1); 2806} 2807 2808static TCGConstraintSetIndex cset_not(TCGType type, unsigned flags) 2809{ 2810 return HAVE_FACILITY(MISC_INSN_EXT3) ? C_O1_I1(r, r) : C_NotImplemented; 2811} 2812 2813static const TCGOutOpUnary outop_not = { 2814 .base.static_constraint = C_Dynamic, 2815 .base.dynamic_constraint = cset_not, 2816 .out_rr = tgen_not, 2817}; 2818 2819 2820# define OP_32_64(x) \ 2821 case glue(glue(INDEX_op_,x),_i32): \ 2822 case glue(glue(INDEX_op_,x),_i64) 2823 2824static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, 2825 const TCGArg args[TCG_MAX_OP_ARGS], 2826 const int const_args[TCG_MAX_OP_ARGS]) 2827{ 2828 TCGArg a0, a1, a2; 2829 2830 switch (opc) { 2831 case INDEX_op_goto_ptr: 2832 a0 = args[0]; 2833 tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, a0); 2834 break; 2835 2836 OP_32_64(ld8u): 2837 /* ??? LLC (RXY format) is only present with the extended-immediate 2838 facility, whereas LLGC is always present. */ 2839 tcg_out_mem(s, 0, RXY_LLGC, args[0], args[1], TCG_REG_NONE, args[2]); 2840 break; 2841 2842 OP_32_64(ld8s): 2843 /* ??? LB is no smaller than LGB, so no point to using it. */ 2844 tcg_out_mem(s, 0, RXY_LGB, args[0], args[1], TCG_REG_NONE, args[2]); 2845 break; 2846 2847 OP_32_64(ld16u): 2848 /* ??? LLH (RXY format) is only present with the extended-immediate 2849 facility, whereas LLGH is always present. */ 2850 tcg_out_mem(s, 0, RXY_LLGH, args[0], args[1], TCG_REG_NONE, args[2]); 2851 break; 2852 2853 case INDEX_op_ld16s_i32: 2854 tcg_out_mem(s, RX_LH, RXY_LHY, args[0], args[1], TCG_REG_NONE, args[2]); 2855 break; 2856 2857 case INDEX_op_ld_i32: 2858 tcg_out_ld(s, TCG_TYPE_I32, args[0], args[1], args[2]); 2859 break; 2860 2861 OP_32_64(st8): 2862 tcg_out_mem(s, RX_STC, RXY_STCY, args[0], args[1], 2863 TCG_REG_NONE, args[2]); 2864 break; 2865 2866 OP_32_64(st16): 2867 tcg_out_mem(s, RX_STH, RXY_STHY, args[0], args[1], 2868 TCG_REG_NONE, args[2]); 2869 break; 2870 2871 case INDEX_op_st_i32: 2872 tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]); 2873 break; 2874 2875 case INDEX_op_add2_i32: 2876 if (const_args[4]) { 2877 tcg_out_insn(s, RIL, ALFI, args[0], args[4]); 2878 } else { 2879 tcg_out_insn(s, RR, ALR, args[0], args[4]); 2880 } 2881 tcg_out_insn(s, RRE, ALCR, args[1], args[5]); 2882 break; 2883 case INDEX_op_sub2_i32: 2884 if (const_args[4]) { 2885 tcg_out_insn(s, RIL, SLFI, args[0], args[4]); 2886 } else { 2887 tcg_out_insn(s, RR, SLR, args[0], args[4]); 2888 } 2889 tcg_out_insn(s, RRE, SLBR, args[1], args[5]); 2890 break; 2891 2892 case INDEX_op_br: 2893 tgen_branch(s, S390_CC_ALWAYS, arg_label(args[0])); 2894 break; 2895 2896 case INDEX_op_qemu_ld_i32: 2897 tcg_out_qemu_ld(s, args[0], args[1], args[2], TCG_TYPE_I32); 2898 break; 2899 case INDEX_op_qemu_ld_i64: 2900 tcg_out_qemu_ld(s, args[0], args[1], args[2], TCG_TYPE_I64); 2901 break; 2902 case INDEX_op_qemu_st_i32: 2903 tcg_out_qemu_st(s, args[0], args[1], args[2], TCG_TYPE_I32); 2904 break; 2905 case INDEX_op_qemu_st_i64: 2906 tcg_out_qemu_st(s, args[0], args[1], args[2], TCG_TYPE_I64); 2907 break; 2908 case INDEX_op_qemu_ld_i128: 2909 tcg_out_qemu_ldst_i128(s, args[0], args[1], args[2], args[3], true); 2910 break; 2911 case INDEX_op_qemu_st_i128: 2912 tcg_out_qemu_ldst_i128(s, args[0], args[1], args[2], args[3], false); 2913 break; 2914 2915 case INDEX_op_ld16s_i64: 2916 tcg_out_mem(s, 0, RXY_LGH, args[0], args[1], TCG_REG_NONE, args[2]); 2917 break; 2918 case INDEX_op_ld32u_i64: 2919 tcg_out_mem(s, 0, RXY_LLGF, args[0], args[1], TCG_REG_NONE, args[2]); 2920 break; 2921 case INDEX_op_ld32s_i64: 2922 tcg_out_mem(s, 0, RXY_LGF, args[0], args[1], TCG_REG_NONE, args[2]); 2923 break; 2924 case INDEX_op_ld_i64: 2925 tcg_out_ld(s, TCG_TYPE_I64, args[0], args[1], args[2]); 2926 break; 2927 2928 case INDEX_op_st32_i64: 2929 tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]); 2930 break; 2931 case INDEX_op_st_i64: 2932 tcg_out_st(s, TCG_TYPE_I64, args[0], args[1], args[2]); 2933 break; 2934 2935 case INDEX_op_add2_i64: 2936 if (const_args[4]) { 2937 if ((int64_t)args[4] >= 0) { 2938 tcg_out_insn(s, RIL, ALGFI, args[0], args[4]); 2939 } else { 2940 tcg_out_insn(s, RIL, SLGFI, args[0], -args[4]); 2941 } 2942 } else { 2943 tcg_out_insn(s, RRE, ALGR, args[0], args[4]); 2944 } 2945 tcg_out_insn(s, RRE, ALCGR, args[1], args[5]); 2946 break; 2947 case INDEX_op_sub2_i64: 2948 if (const_args[4]) { 2949 if ((int64_t)args[4] >= 0) { 2950 tcg_out_insn(s, RIL, SLGFI, args[0], args[4]); 2951 } else { 2952 tcg_out_insn(s, RIL, ALGFI, args[0], -args[4]); 2953 } 2954 } else { 2955 tcg_out_insn(s, RRE, SLGR, args[0], args[4]); 2956 } 2957 tcg_out_insn(s, RRE, SLBGR, args[1], args[5]); 2958 break; 2959 2960 OP_32_64(deposit): 2961 a0 = args[0], a1 = args[1], a2 = args[2]; 2962 if (const_args[1]) { 2963 tgen_deposit(s, a0, a2, args[3], args[4], 1); 2964 } else { 2965 /* Since we can't support "0Z" as a constraint, we allow a1 in 2966 any register. Fix things up as if a matching constraint. */ 2967 if (a0 != a1) { 2968 if (a0 == a2) { 2969 tcg_out_mov(s, type, TCG_TMP0, a2); 2970 a2 = TCG_TMP0; 2971 } 2972 tcg_out_mov(s, type, a0, a1); 2973 } 2974 tgen_deposit(s, a0, a2, args[3], args[4], 0); 2975 } 2976 break; 2977 2978 OP_32_64(extract): 2979 tgen_extract(s, args[0], args[1], args[2], args[3]); 2980 break; 2981 OP_32_64(sextract): 2982 tgen_sextract(s, args[0], args[1], args[2], args[3]); 2983 break; 2984 2985 case INDEX_op_mb: 2986 /* The host memory model is quite strong, we simply need to 2987 serialize the instruction stream. */ 2988 if (args[0] & TCG_MO_ST_LD) { 2989 /* fast-bcr-serialization facility (45) is present */ 2990 tcg_out_insn(s, RR, BCR, 14, 0); 2991 } 2992 break; 2993 2994 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2995 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 2996 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 2997 case INDEX_op_ext_i32_i64: /* Always emitted via tcg_reg_alloc_op. */ 2998 case INDEX_op_extu_i32_i64: 2999 case INDEX_op_extrl_i64_i32: 3000 default: 3001 g_assert_not_reached(); 3002 } 3003} 3004 3005static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 3006 TCGReg dst, TCGReg src) 3007{ 3008 if (is_general_reg(src)) { 3009 /* Replicate general register into two MO_64. */ 3010 tcg_out_insn(s, VRRf, VLVGP, dst, src, src); 3011 if (vece == MO_64) { 3012 return true; 3013 } 3014 src = dst; 3015 } 3016 3017 /* 3018 * Recall that the "standard" integer, within a vector, is the 3019 * rightmost element of the leftmost doubleword, a-la VLLEZ. 3020 */ 3021 tcg_out_insn(s, VRIc, VREP, dst, (8 >> vece) - 1, src, vece); 3022 return true; 3023} 3024 3025static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 3026 TCGReg dst, TCGReg base, intptr_t offset) 3027{ 3028 tcg_out_vrx_mem(s, VRX_VLREP, dst, base, TCG_REG_NONE, offset, vece); 3029 return true; 3030} 3031 3032static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 3033 TCGReg dst, int64_t val) 3034{ 3035 int i, mask, msb, lsb; 3036 3037 /* Look for int16_t elements. */ 3038 if (vece <= MO_16 || 3039 (vece == MO_32 ? (int32_t)val : val) == (int16_t)val) { 3040 tcg_out_insn(s, VRIa, VREPI, dst, val, vece); 3041 return; 3042 } 3043 3044 /* Look for bit masks. */ 3045 if (vece == MO_32) { 3046 if (risbg_mask((int32_t)val)) { 3047 /* Handle wraparound by swapping msb and lsb. */ 3048 if ((val & 0x80000001u) == 0x80000001u) { 3049 msb = 32 - ctz32(~val); 3050 lsb = clz32(~val) - 1; 3051 } else { 3052 msb = clz32(val); 3053 lsb = 31 - ctz32(val); 3054 } 3055 tcg_out_insn(s, VRIb, VGM, dst, msb, lsb, MO_32); 3056 return; 3057 } 3058 } else { 3059 if (risbg_mask(val)) { 3060 /* Handle wraparound by swapping msb and lsb. */ 3061 if ((val & 0x8000000000000001ull) == 0x8000000000000001ull) { 3062 /* Handle wraparound by swapping msb and lsb. */ 3063 msb = 64 - ctz64(~val); 3064 lsb = clz64(~val) - 1; 3065 } else { 3066 msb = clz64(val); 3067 lsb = 63 - ctz64(val); 3068 } 3069 tcg_out_insn(s, VRIb, VGM, dst, msb, lsb, MO_64); 3070 return; 3071 } 3072 } 3073 3074 /* Look for all bytes 0x00 or 0xff. */ 3075 for (i = mask = 0; i < 8; i++) { 3076 uint8_t byte = val >> (i * 8); 3077 if (byte == 0xff) { 3078 mask |= 1 << i; 3079 } else if (byte != 0) { 3080 break; 3081 } 3082 } 3083 if (i == 8) { 3084 tcg_out_insn(s, VRIa, VGBM, dst, mask * 0x0101, 0); 3085 return; 3086 } 3087 3088 /* Otherwise, stuff it in the constant pool. */ 3089 tcg_out_insn(s, RIL, LARL, TCG_TMP0, 0); 3090 new_pool_label(s, val, R_390_PC32DBL, s->code_ptr - 2, 2); 3091 tcg_out_insn(s, VRX, VLREP, dst, TCG_TMP0, TCG_REG_NONE, 0, MO_64); 3092} 3093 3094static bool tcg_out_cmp_vec_noinv(TCGContext *s, unsigned vece, TCGReg a0, 3095 TCGReg a1, TCGReg a2, TCGCond cond) 3096{ 3097 bool need_swap = false, need_inv = false; 3098 3099 switch (cond) { 3100 case TCG_COND_EQ: 3101 case TCG_COND_GT: 3102 case TCG_COND_GTU: 3103 break; 3104 case TCG_COND_NE: 3105 case TCG_COND_LE: 3106 case TCG_COND_LEU: 3107 need_inv = true; 3108 break; 3109 case TCG_COND_LT: 3110 case TCG_COND_LTU: 3111 need_swap = true; 3112 break; 3113 case TCG_COND_GE: 3114 case TCG_COND_GEU: 3115 need_swap = need_inv = true; 3116 break; 3117 default: 3118 g_assert_not_reached(); 3119 } 3120 3121 if (need_inv) { 3122 cond = tcg_invert_cond(cond); 3123 } 3124 if (need_swap) { 3125 TCGReg swap = a1; 3126 a1 = a2; 3127 a2 = swap; 3128 cond = tcg_swap_cond(cond); 3129 } 3130 3131 switch (cond) { 3132 case TCG_COND_EQ: 3133 tcg_out_insn(s, VRRc, VCEQ, a0, a1, a2, vece); 3134 break; 3135 case TCG_COND_GT: 3136 tcg_out_insn(s, VRRc, VCH, a0, a1, a2, vece); 3137 break; 3138 case TCG_COND_GTU: 3139 tcg_out_insn(s, VRRc, VCHL, a0, a1, a2, vece); 3140 break; 3141 default: 3142 g_assert_not_reached(); 3143 } 3144 return need_inv; 3145} 3146 3147static void tcg_out_cmp_vec(TCGContext *s, unsigned vece, TCGReg a0, 3148 TCGReg a1, TCGReg a2, TCGCond cond) 3149{ 3150 if (tcg_out_cmp_vec_noinv(s, vece, a0, a1, a2, cond)) { 3151 tcg_out_insn(s, VRRc, VNO, a0, a0, a0, 0); 3152 } 3153} 3154 3155static void tcg_out_cmpsel_vec(TCGContext *s, unsigned vece, TCGReg a0, 3156 TCGReg c1, TCGReg c2, TCGArg v3, 3157 int const_v3, TCGReg v4, TCGCond cond) 3158{ 3159 bool inv = tcg_out_cmp_vec_noinv(s, vece, TCG_VEC_TMP0, c1, c2, cond); 3160 3161 if (!const_v3) { 3162 if (inv) { 3163 tcg_out_insn(s, VRRe, VSEL, a0, v4, v3, TCG_VEC_TMP0); 3164 } else { 3165 tcg_out_insn(s, VRRe, VSEL, a0, v3, v4, TCG_VEC_TMP0); 3166 } 3167 } else if (v3) { 3168 if (inv) { 3169 tcg_out_insn(s, VRRc, VOC, a0, v4, TCG_VEC_TMP0, 0); 3170 } else { 3171 tcg_out_insn(s, VRRc, VO, a0, v4, TCG_VEC_TMP0, 0); 3172 } 3173 } else { 3174 if (inv) { 3175 tcg_out_insn(s, VRRc, VN, a0, v4, TCG_VEC_TMP0, 0); 3176 } else { 3177 tcg_out_insn(s, VRRc, VNC, a0, v4, TCG_VEC_TMP0, 0); 3178 } 3179 } 3180} 3181 3182static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 3183 unsigned vecl, unsigned vece, 3184 const TCGArg args[TCG_MAX_OP_ARGS], 3185 const int const_args[TCG_MAX_OP_ARGS]) 3186{ 3187 TCGType type = vecl + TCG_TYPE_V64; 3188 TCGArg a0 = args[0], a1 = args[1], a2 = args[2]; 3189 3190 switch (opc) { 3191 case INDEX_op_ld_vec: 3192 tcg_out_ld(s, type, a0, a1, a2); 3193 break; 3194 case INDEX_op_st_vec: 3195 tcg_out_st(s, type, a0, a1, a2); 3196 break; 3197 case INDEX_op_dupm_vec: 3198 tcg_out_dupm_vec(s, type, vece, a0, a1, a2); 3199 break; 3200 3201 case INDEX_op_abs_vec: 3202 tcg_out_insn(s, VRRa, VLP, a0, a1, vece); 3203 break; 3204 case INDEX_op_neg_vec: 3205 tcg_out_insn(s, VRRa, VLC, a0, a1, vece); 3206 break; 3207 case INDEX_op_not_vec: 3208 tcg_out_insn(s, VRRc, VNO, a0, a1, a1, 0); 3209 break; 3210 3211 case INDEX_op_add_vec: 3212 tcg_out_insn(s, VRRc, VA, a0, a1, a2, vece); 3213 break; 3214 case INDEX_op_sub_vec: 3215 tcg_out_insn(s, VRRc, VS, a0, a1, a2, vece); 3216 break; 3217 case INDEX_op_and_vec: 3218 tcg_out_insn(s, VRRc, VN, a0, a1, a2, 0); 3219 break; 3220 case INDEX_op_andc_vec: 3221 tcg_out_insn(s, VRRc, VNC, a0, a1, a2, 0); 3222 break; 3223 case INDEX_op_mul_vec: 3224 tcg_out_insn(s, VRRc, VML, a0, a1, a2, vece); 3225 break; 3226 case INDEX_op_or_vec: 3227 tcg_out_insn(s, VRRc, VO, a0, a1, a2, 0); 3228 break; 3229 case INDEX_op_orc_vec: 3230 tcg_out_insn(s, VRRc, VOC, a0, a1, a2, 0); 3231 break; 3232 case INDEX_op_xor_vec: 3233 tcg_out_insn(s, VRRc, VX, a0, a1, a2, 0); 3234 break; 3235 case INDEX_op_nand_vec: 3236 tcg_out_insn(s, VRRc, VNN, a0, a1, a2, 0); 3237 break; 3238 case INDEX_op_nor_vec: 3239 tcg_out_insn(s, VRRc, VNO, a0, a1, a2, 0); 3240 break; 3241 case INDEX_op_eqv_vec: 3242 tcg_out_insn(s, VRRc, VNX, a0, a1, a2, 0); 3243 break; 3244 3245 case INDEX_op_shli_vec: 3246 tcg_out_insn(s, VRSa, VESL, a0, a2, TCG_REG_NONE, a1, vece); 3247 break; 3248 case INDEX_op_shri_vec: 3249 tcg_out_insn(s, VRSa, VESRL, a0, a2, TCG_REG_NONE, a1, vece); 3250 break; 3251 case INDEX_op_sari_vec: 3252 tcg_out_insn(s, VRSa, VESRA, a0, a2, TCG_REG_NONE, a1, vece); 3253 break; 3254 case INDEX_op_rotli_vec: 3255 tcg_out_insn(s, VRSa, VERLL, a0, a2, TCG_REG_NONE, a1, vece); 3256 break; 3257 case INDEX_op_shls_vec: 3258 tcg_out_insn(s, VRSa, VESL, a0, 0, a2, a1, vece); 3259 break; 3260 case INDEX_op_shrs_vec: 3261 tcg_out_insn(s, VRSa, VESRL, a0, 0, a2, a1, vece); 3262 break; 3263 case INDEX_op_sars_vec: 3264 tcg_out_insn(s, VRSa, VESRA, a0, 0, a2, a1, vece); 3265 break; 3266 case INDEX_op_rotls_vec: 3267 tcg_out_insn(s, VRSa, VERLL, a0, 0, a2, a1, vece); 3268 break; 3269 case INDEX_op_shlv_vec: 3270 tcg_out_insn(s, VRRc, VESLV, a0, a1, a2, vece); 3271 break; 3272 case INDEX_op_shrv_vec: 3273 tcg_out_insn(s, VRRc, VESRLV, a0, a1, a2, vece); 3274 break; 3275 case INDEX_op_sarv_vec: 3276 tcg_out_insn(s, VRRc, VESRAV, a0, a1, a2, vece); 3277 break; 3278 case INDEX_op_rotlv_vec: 3279 tcg_out_insn(s, VRRc, VERLLV, a0, a1, a2, vece); 3280 break; 3281 3282 case INDEX_op_smin_vec: 3283 tcg_out_insn(s, VRRc, VMN, a0, a1, a2, vece); 3284 break; 3285 case INDEX_op_smax_vec: 3286 tcg_out_insn(s, VRRc, VMX, a0, a1, a2, vece); 3287 break; 3288 case INDEX_op_umin_vec: 3289 tcg_out_insn(s, VRRc, VMNL, a0, a1, a2, vece); 3290 break; 3291 case INDEX_op_umax_vec: 3292 tcg_out_insn(s, VRRc, VMXL, a0, a1, a2, vece); 3293 break; 3294 3295 case INDEX_op_bitsel_vec: 3296 tcg_out_insn(s, VRRe, VSEL, a0, a2, args[3], a1); 3297 break; 3298 3299 case INDEX_op_cmp_vec: 3300 tcg_out_cmp_vec(s, vece, a0, a1, a2, args[3]); 3301 break; 3302 case INDEX_op_cmpsel_vec: 3303 tcg_out_cmpsel_vec(s, vece, a0, a1, a2, args[3], const_args[3], 3304 args[4], args[5]); 3305 break; 3306 3307 case INDEX_op_s390_vuph_vec: 3308 tcg_out_insn(s, VRRa, VUPH, a0, a1, vece); 3309 break; 3310 case INDEX_op_s390_vupl_vec: 3311 tcg_out_insn(s, VRRa, VUPL, a0, a1, vece); 3312 break; 3313 case INDEX_op_s390_vpks_vec: 3314 tcg_out_insn(s, VRRc, VPKS, a0, a1, a2, vece); 3315 break; 3316 3317 case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ 3318 case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ 3319 default: 3320 g_assert_not_reached(); 3321 } 3322} 3323 3324int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) 3325{ 3326 switch (opc) { 3327 case INDEX_op_abs_vec: 3328 case INDEX_op_add_vec: 3329 case INDEX_op_and_vec: 3330 case INDEX_op_andc_vec: 3331 case INDEX_op_bitsel_vec: 3332 case INDEX_op_eqv_vec: 3333 case INDEX_op_nand_vec: 3334 case INDEX_op_neg_vec: 3335 case INDEX_op_nor_vec: 3336 case INDEX_op_not_vec: 3337 case INDEX_op_or_vec: 3338 case INDEX_op_orc_vec: 3339 case INDEX_op_rotli_vec: 3340 case INDEX_op_rotls_vec: 3341 case INDEX_op_rotlv_vec: 3342 case INDEX_op_sari_vec: 3343 case INDEX_op_sars_vec: 3344 case INDEX_op_sarv_vec: 3345 case INDEX_op_shli_vec: 3346 case INDEX_op_shls_vec: 3347 case INDEX_op_shlv_vec: 3348 case INDEX_op_shri_vec: 3349 case INDEX_op_shrs_vec: 3350 case INDEX_op_shrv_vec: 3351 case INDEX_op_smax_vec: 3352 case INDEX_op_smin_vec: 3353 case INDEX_op_sub_vec: 3354 case INDEX_op_umax_vec: 3355 case INDEX_op_umin_vec: 3356 case INDEX_op_xor_vec: 3357 case INDEX_op_cmp_vec: 3358 case INDEX_op_cmpsel_vec: 3359 return 1; 3360 case INDEX_op_rotrv_vec: 3361 return -1; 3362 case INDEX_op_mul_vec: 3363 return vece < MO_64; 3364 case INDEX_op_ssadd_vec: 3365 case INDEX_op_sssub_vec: 3366 return vece < MO_64 ? -1 : 0; 3367 default: 3368 return 0; 3369 } 3370} 3371 3372static void expand_vec_sat(TCGType type, unsigned vece, TCGv_vec v0, 3373 TCGv_vec v1, TCGv_vec v2, TCGOpcode add_sub_opc) 3374{ 3375 TCGv_vec h1 = tcg_temp_new_vec(type); 3376 TCGv_vec h2 = tcg_temp_new_vec(type); 3377 TCGv_vec l1 = tcg_temp_new_vec(type); 3378 TCGv_vec l2 = tcg_temp_new_vec(type); 3379 3380 tcg_debug_assert (vece < MO_64); 3381 3382 /* Unpack with sign-extension. */ 3383 vec_gen_2(INDEX_op_s390_vuph_vec, type, vece, 3384 tcgv_vec_arg(h1), tcgv_vec_arg(v1)); 3385 vec_gen_2(INDEX_op_s390_vuph_vec, type, vece, 3386 tcgv_vec_arg(h2), tcgv_vec_arg(v2)); 3387 3388 vec_gen_2(INDEX_op_s390_vupl_vec, type, vece, 3389 tcgv_vec_arg(l1), tcgv_vec_arg(v1)); 3390 vec_gen_2(INDEX_op_s390_vupl_vec, type, vece, 3391 tcgv_vec_arg(l2), tcgv_vec_arg(v2)); 3392 3393 /* Arithmetic on a wider element size. */ 3394 vec_gen_3(add_sub_opc, type, vece + 1, tcgv_vec_arg(h1), 3395 tcgv_vec_arg(h1), tcgv_vec_arg(h2)); 3396 vec_gen_3(add_sub_opc, type, vece + 1, tcgv_vec_arg(l1), 3397 tcgv_vec_arg(l1), tcgv_vec_arg(l2)); 3398 3399 /* Pack with saturation. */ 3400 vec_gen_3(INDEX_op_s390_vpks_vec, type, vece + 1, 3401 tcgv_vec_arg(v0), tcgv_vec_arg(h1), tcgv_vec_arg(l1)); 3402 3403 tcg_temp_free_vec(h1); 3404 tcg_temp_free_vec(h2); 3405 tcg_temp_free_vec(l1); 3406 tcg_temp_free_vec(l2); 3407} 3408 3409void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, 3410 TCGArg a0, ...) 3411{ 3412 va_list va; 3413 TCGv_vec v0, v1, v2, t0; 3414 3415 va_start(va, a0); 3416 v0 = temp_tcgv_vec(arg_temp(a0)); 3417 v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); 3418 v2 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); 3419 3420 switch (opc) { 3421 case INDEX_op_rotrv_vec: 3422 t0 = tcg_temp_new_vec(type); 3423 tcg_gen_neg_vec(vece, t0, v2); 3424 tcg_gen_rotlv_vec(vece, v0, v1, t0); 3425 tcg_temp_free_vec(t0); 3426 break; 3427 3428 case INDEX_op_ssadd_vec: 3429 expand_vec_sat(type, vece, v0, v1, v2, INDEX_op_add_vec); 3430 break; 3431 case INDEX_op_sssub_vec: 3432 expand_vec_sat(type, vece, v0, v1, v2, INDEX_op_sub_vec); 3433 break; 3434 3435 default: 3436 g_assert_not_reached(); 3437 } 3438 va_end(va); 3439} 3440 3441static TCGConstraintSetIndex 3442tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) 3443{ 3444 switch (op) { 3445 case INDEX_op_goto_ptr: 3446 return C_O0_I1(r); 3447 3448 case INDEX_op_ld8u_i32: 3449 case INDEX_op_ld8u_i64: 3450 case INDEX_op_ld8s_i32: 3451 case INDEX_op_ld8s_i64: 3452 case INDEX_op_ld16u_i32: 3453 case INDEX_op_ld16u_i64: 3454 case INDEX_op_ld16s_i32: 3455 case INDEX_op_ld16s_i64: 3456 case INDEX_op_ld_i32: 3457 case INDEX_op_ld32u_i64: 3458 case INDEX_op_ld32s_i64: 3459 case INDEX_op_ld_i64: 3460 return C_O1_I1(r, r); 3461 3462 case INDEX_op_st8_i32: 3463 case INDEX_op_st8_i64: 3464 case INDEX_op_st16_i32: 3465 case INDEX_op_st16_i64: 3466 case INDEX_op_st_i32: 3467 case INDEX_op_st32_i64: 3468 case INDEX_op_st_i64: 3469 return C_O0_I2(r, r); 3470 3471 case INDEX_op_ext_i32_i64: 3472 case INDEX_op_extu_i32_i64: 3473 case INDEX_op_extract_i32: 3474 case INDEX_op_extract_i64: 3475 case INDEX_op_sextract_i32: 3476 case INDEX_op_sextract_i64: 3477 return C_O1_I1(r, r); 3478 3479 case INDEX_op_qemu_ld_i32: 3480 case INDEX_op_qemu_ld_i64: 3481 return C_O1_I1(r, r); 3482 case INDEX_op_qemu_st_i64: 3483 case INDEX_op_qemu_st_i32: 3484 return C_O0_I2(r, r); 3485 case INDEX_op_qemu_ld_i128: 3486 return C_O2_I1(o, m, r); 3487 case INDEX_op_qemu_st_i128: 3488 return C_O0_I3(o, m, r); 3489 3490 case INDEX_op_deposit_i32: 3491 case INDEX_op_deposit_i64: 3492 return C_O1_I2(r, rZ, r); 3493 3494 case INDEX_op_add2_i32: 3495 case INDEX_op_sub2_i32: 3496 return C_N1_O1_I4(r, r, 0, 1, ri, r); 3497 3498 case INDEX_op_add2_i64: 3499 case INDEX_op_sub2_i64: 3500 return C_N1_O1_I4(r, r, 0, 1, rJU, r); 3501 3502 case INDEX_op_st_vec: 3503 return C_O0_I2(v, r); 3504 case INDEX_op_ld_vec: 3505 case INDEX_op_dupm_vec: 3506 return C_O1_I1(v, r); 3507 case INDEX_op_dup_vec: 3508 return C_O1_I1(v, vr); 3509 case INDEX_op_abs_vec: 3510 case INDEX_op_neg_vec: 3511 case INDEX_op_not_vec: 3512 case INDEX_op_rotli_vec: 3513 case INDEX_op_sari_vec: 3514 case INDEX_op_shli_vec: 3515 case INDEX_op_shri_vec: 3516 case INDEX_op_s390_vuph_vec: 3517 case INDEX_op_s390_vupl_vec: 3518 return C_O1_I1(v, v); 3519 case INDEX_op_add_vec: 3520 case INDEX_op_sub_vec: 3521 case INDEX_op_and_vec: 3522 case INDEX_op_andc_vec: 3523 case INDEX_op_or_vec: 3524 case INDEX_op_orc_vec: 3525 case INDEX_op_xor_vec: 3526 case INDEX_op_nand_vec: 3527 case INDEX_op_nor_vec: 3528 case INDEX_op_eqv_vec: 3529 case INDEX_op_cmp_vec: 3530 case INDEX_op_mul_vec: 3531 case INDEX_op_rotlv_vec: 3532 case INDEX_op_rotrv_vec: 3533 case INDEX_op_shlv_vec: 3534 case INDEX_op_shrv_vec: 3535 case INDEX_op_sarv_vec: 3536 case INDEX_op_smax_vec: 3537 case INDEX_op_smin_vec: 3538 case INDEX_op_umax_vec: 3539 case INDEX_op_umin_vec: 3540 case INDEX_op_s390_vpks_vec: 3541 return C_O1_I2(v, v, v); 3542 case INDEX_op_rotls_vec: 3543 case INDEX_op_shls_vec: 3544 case INDEX_op_shrs_vec: 3545 case INDEX_op_sars_vec: 3546 return C_O1_I2(v, v, r); 3547 case INDEX_op_bitsel_vec: 3548 return C_O1_I3(v, v, v, v); 3549 case INDEX_op_cmpsel_vec: 3550 return (TCG_TARGET_HAS_orc_vec 3551 ? C_O1_I4(v, v, v, vZM, v) 3552 : C_O1_I4(v, v, v, vZ, v)); 3553 3554 default: 3555 return C_NotImplemented; 3556 } 3557} 3558 3559/* 3560 * Mainline glibc added HWCAP_S390_VX before it was kernel abi. 3561 * Some distros have fixed this up locally, others have not. 3562 */ 3563#ifndef HWCAP_S390_VXRS 3564#define HWCAP_S390_VXRS 2048 3565#endif 3566 3567static void query_s390_facilities(void) 3568{ 3569 unsigned long hwcap = qemu_getauxval(AT_HWCAP); 3570 const char *which; 3571 3572 /* Is STORE FACILITY LIST EXTENDED available? Honestly, I believe this 3573 is present on all 64-bit systems, but let's check for it anyway. */ 3574 if (hwcap & HWCAP_S390_STFLE) { 3575 register int r0 __asm__("0") = ARRAY_SIZE(s390_facilities) - 1; 3576 register void *r1 __asm__("1") = s390_facilities; 3577 3578 /* stfle 0(%r1) */ 3579 asm volatile(".word 0xb2b0,0x1000" 3580 : "=r"(r0) : "r"(r0), "r"(r1) : "memory", "cc"); 3581 } 3582 3583 /* 3584 * Use of vector registers requires os support beyond the facility bit. 3585 * If the kernel does not advertise support, disable the facility bits. 3586 * There is nothing else we currently care about in the 3rd word, so 3587 * disable VECTOR with one store. 3588 */ 3589 if (!(hwcap & HWCAP_S390_VXRS)) { 3590 s390_facilities[2] = 0; 3591 } 3592 3593 /* 3594 * Minimum supported cpu revision is z196. 3595 * Check for all required facilities. 3596 * ZARCH_ACTIVE is done via preprocessor check for 64-bit. 3597 */ 3598 if (!HAVE_FACILITY(LONG_DISP)) { 3599 which = "long-displacement"; 3600 goto fail; 3601 } 3602 if (!HAVE_FACILITY(EXT_IMM)) { 3603 which = "extended-immediate"; 3604 goto fail; 3605 } 3606 if (!HAVE_FACILITY(GEN_INST_EXT)) { 3607 which = "general-instructions-extension"; 3608 goto fail; 3609 } 3610 /* 3611 * Facility 45 is a big bin that contains: distinct-operands, 3612 * fast-BCR-serialization, high-word, population-count, 3613 * interlocked-access-1, and load/store-on-condition-1 3614 */ 3615 if (!HAVE_FACILITY(45)) { 3616 which = "45"; 3617 goto fail; 3618 } 3619 return; 3620 3621 fail: 3622 error_report("%s: missing required facility %s", __func__, which); 3623 exit(EXIT_FAILURE); 3624} 3625 3626static void tcg_target_init(TCGContext *s) 3627{ 3628 query_s390_facilities(); 3629 3630 tcg_target_available_regs[TCG_TYPE_I32] = 0xffff; 3631 tcg_target_available_regs[TCG_TYPE_I64] = 0xffff; 3632 if (HAVE_FACILITY(VECTOR)) { 3633 tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull; 3634 tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull; 3635 } 3636 3637 tcg_target_call_clobber_regs = 0; 3638 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0); 3639 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1); 3640 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2); 3641 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3); 3642 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R4); 3643 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R5); 3644 /* The r6 register is technically call-saved, but it's also a parameter 3645 register, so it can get killed by setup for the qemu_st helper. */ 3646 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R6); 3647 /* The return register can be considered call-clobbered. */ 3648 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14); 3649 3650 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); 3651 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); 3652 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V2); 3653 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V3); 3654 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V4); 3655 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V5); 3656 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V6); 3657 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V7); 3658 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V16); 3659 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V17); 3660 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V18); 3661 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V19); 3662 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V20); 3663 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V21); 3664 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V22); 3665 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V23); 3666 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V24); 3667 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V25); 3668 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V26); 3669 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V27); 3670 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V28); 3671 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V29); 3672 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V30); 3673 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V31); 3674 3675 s->reserved_regs = 0; 3676 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); 3677 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP0); 3678 /* XXX many insns can't be used with R0, so we better avoid it for now */ 3679 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); 3680 tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); 3681} 3682 3683#define FRAME_SIZE ((int)(TCG_TARGET_CALL_STACK_OFFSET \ 3684 + TCG_STATIC_CALL_ARGS_SIZE \ 3685 + CPU_TEMP_BUF_NLONGS * sizeof(long))) 3686 3687static void tcg_target_qemu_prologue(TCGContext *s) 3688{ 3689 /* stmg %r6,%r15,48(%r15) (save registers) */ 3690 tcg_out_insn(s, RXY, STMG, TCG_REG_R6, TCG_REG_R15, TCG_REG_R15, 48); 3691 3692 /* aghi %r15,-frame_size */ 3693 tcg_out_insn(s, RI, AGHI, TCG_REG_R15, -FRAME_SIZE); 3694 3695 tcg_set_frame(s, TCG_REG_CALL_STACK, 3696 TCG_STATIC_CALL_ARGS_SIZE + TCG_TARGET_CALL_STACK_OFFSET, 3697 CPU_TEMP_BUF_NLONGS * sizeof(long)); 3698 3699 if (!tcg_use_softmmu && guest_base >= 0x80000) { 3700 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); 3701 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 3702 } 3703 3704 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 3705 3706 /* br %r3 (go to TB) */ 3707 tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, tcg_target_call_iarg_regs[1]); 3708 3709 /* 3710 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 3711 * and fall through to the rest of the epilogue. 3712 */ 3713 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 3714 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, 0); 3715 3716 /* TB epilogue */ 3717 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 3718 3719 /* lmg %r6,%r15,fs+48(%r15) (restore registers) */ 3720 tcg_out_insn(s, RXY, LMG, TCG_REG_R6, TCG_REG_R15, TCG_REG_R15, 3721 FRAME_SIZE + 48); 3722 3723 /* br %r14 (return) */ 3724 tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_R14); 3725} 3726 3727static void tcg_out_tb_start(TCGContext *s) 3728{ 3729 /* nothing to do */ 3730} 3731 3732static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 3733{ 3734 memset(p, 0x07, count * sizeof(tcg_insn_unit)); 3735} 3736 3737typedef struct { 3738 DebugFrameHeader h; 3739 uint8_t fde_def_cfa[4]; 3740 uint8_t fde_reg_ofs[18]; 3741} DebugFrame; 3742 3743/* We're expecting a 2 byte uleb128 encoded value. */ 3744QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14)); 3745 3746#define ELF_HOST_MACHINE EM_S390 3747 3748static const DebugFrame debug_frame = { 3749 .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ 3750 .h.cie.id = -1, 3751 .h.cie.version = 1, 3752 .h.cie.code_align = 1, 3753 .h.cie.data_align = 8, /* sleb128 8 */ 3754 .h.cie.return_column = TCG_REG_R14, 3755 3756 /* Total FDE size does not include the "len" member. */ 3757 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 3758 3759 .fde_def_cfa = { 3760 12, TCG_REG_CALL_STACK, /* DW_CFA_def_cfa %r15, ... */ 3761 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 3762 (FRAME_SIZE >> 7) 3763 }, 3764 .fde_reg_ofs = { 3765 0x86, 6, /* DW_CFA_offset, %r6, 48 */ 3766 0x87, 7, /* DW_CFA_offset, %r7, 56 */ 3767 0x88, 8, /* DW_CFA_offset, %r8, 64 */ 3768 0x89, 9, /* DW_CFA_offset, %r92, 72 */ 3769 0x8a, 10, /* DW_CFA_offset, %r10, 80 */ 3770 0x8b, 11, /* DW_CFA_offset, %r11, 88 */ 3771 0x8c, 12, /* DW_CFA_offset, %r12, 96 */ 3772 0x8d, 13, /* DW_CFA_offset, %r13, 104 */ 3773 0x8e, 14, /* DW_CFA_offset, %r14, 112 */ 3774 } 3775}; 3776 3777void tcg_register_jit(const void *buf, size_t buf_size) 3778{ 3779 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 3780} 3781