1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2009 Ulrich Hecht <uli@suse.de> 5 * Copyright (c) 2009 Alexander Graf <agraf@suse.de> 6 * Copyright (c) 2010 Richard Henderson <rth@twiddle.net> 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27/* We only support generating code for 64-bit mode. */ 28#if TCG_TARGET_REG_BITS != 64 29#error "unsupported code generation mode" 30#endif 31 32#include "../tcg-ldst.c.inc" 33#include "../tcg-pool.c.inc" 34#include "elf.h" 35 36#define TCG_CT_CONST_S16 (1 << 8) 37#define TCG_CT_CONST_S32 (1 << 9) 38#define TCG_CT_CONST_S33 (1 << 10) 39#define TCG_CT_CONST_ZERO (1 << 11) 40#define TCG_CT_CONST_P32 (1 << 12) 41#define TCG_CT_CONST_INV (1 << 13) 42#define TCG_CT_CONST_INVRISBG (1 << 14) 43 44#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 16) 45#define ALL_VECTOR_REGS MAKE_64BIT_MASK(32, 32) 46 47/* Several places within the instruction set 0 means "no register" 48 rather than TCG_REG_R0. */ 49#define TCG_REG_NONE 0 50 51/* A scratch register that may be be used throughout the backend. */ 52#define TCG_TMP0 TCG_REG_R1 53 54#ifndef CONFIG_SOFTMMU 55#define TCG_GUEST_BASE_REG TCG_REG_R13 56#endif 57 58/* All of the following instructions are prefixed with their instruction 59 format, and are defined as 8- or 16-bit quantities, even when the two 60 halves of the 16-bit quantity may appear 32 bits apart in the insn. 61 This makes it easy to copy the values from the tables in Appendix B. */ 62typedef enum S390Opcode { 63 RIL_AFI = 0xc209, 64 RIL_AGFI = 0xc208, 65 RIL_ALFI = 0xc20b, 66 RIL_ALGFI = 0xc20a, 67 RIL_BRASL = 0xc005, 68 RIL_BRCL = 0xc004, 69 RIL_CFI = 0xc20d, 70 RIL_CGFI = 0xc20c, 71 RIL_CLFI = 0xc20f, 72 RIL_CLGFI = 0xc20e, 73 RIL_CLRL = 0xc60f, 74 RIL_CLGRL = 0xc60a, 75 RIL_CRL = 0xc60d, 76 RIL_CGRL = 0xc608, 77 RIL_IIHF = 0xc008, 78 RIL_IILF = 0xc009, 79 RIL_LARL = 0xc000, 80 RIL_LGFI = 0xc001, 81 RIL_LGRL = 0xc408, 82 RIL_LLIHF = 0xc00e, 83 RIL_LLILF = 0xc00f, 84 RIL_LRL = 0xc40d, 85 RIL_MSFI = 0xc201, 86 RIL_MSGFI = 0xc200, 87 RIL_NIHF = 0xc00a, 88 RIL_NILF = 0xc00b, 89 RIL_OIHF = 0xc00c, 90 RIL_OILF = 0xc00d, 91 RIL_SLFI = 0xc205, 92 RIL_SLGFI = 0xc204, 93 RIL_XIHF = 0xc006, 94 RIL_XILF = 0xc007, 95 96 RI_AGHI = 0xa70b, 97 RI_AHI = 0xa70a, 98 RI_BRC = 0xa704, 99 RI_CHI = 0xa70e, 100 RI_CGHI = 0xa70f, 101 RI_IIHH = 0xa500, 102 RI_IIHL = 0xa501, 103 RI_IILH = 0xa502, 104 RI_IILL = 0xa503, 105 RI_LGHI = 0xa709, 106 RI_LLIHH = 0xa50c, 107 RI_LLIHL = 0xa50d, 108 RI_LLILH = 0xa50e, 109 RI_LLILL = 0xa50f, 110 RI_MGHI = 0xa70d, 111 RI_MHI = 0xa70c, 112 RI_NIHH = 0xa504, 113 RI_NIHL = 0xa505, 114 RI_NILH = 0xa506, 115 RI_NILL = 0xa507, 116 RI_OIHH = 0xa508, 117 RI_OIHL = 0xa509, 118 RI_OILH = 0xa50a, 119 RI_OILL = 0xa50b, 120 RI_TMLL = 0xa701, 121 122 RIEb_CGRJ = 0xec64, 123 RIEb_CLGRJ = 0xec65, 124 RIEb_CLRJ = 0xec77, 125 RIEb_CRJ = 0xec76, 126 127 RIEc_CGIJ = 0xec7c, 128 RIEc_CIJ = 0xec7e, 129 RIEc_CLGIJ = 0xec7d, 130 RIEc_CLIJ = 0xec7f, 131 132 RIEf_RISBG = 0xec55, 133 134 RIEg_LOCGHI = 0xec46, 135 136 RRE_AGR = 0xb908, 137 RRE_ALGR = 0xb90a, 138 RRE_ALCR = 0xb998, 139 RRE_ALCGR = 0xb988, 140 RRE_ALGFR = 0xb91a, 141 RRE_CGR = 0xb920, 142 RRE_CLGR = 0xb921, 143 RRE_DLGR = 0xb987, 144 RRE_DLR = 0xb997, 145 RRE_DSGFR = 0xb91d, 146 RRE_DSGR = 0xb90d, 147 RRE_FLOGR = 0xb983, 148 RRE_LGBR = 0xb906, 149 RRE_LCGR = 0xb903, 150 RRE_LGFR = 0xb914, 151 RRE_LGHR = 0xb907, 152 RRE_LGR = 0xb904, 153 RRE_LLGCR = 0xb984, 154 RRE_LLGFR = 0xb916, 155 RRE_LLGHR = 0xb985, 156 RRE_LRVR = 0xb91f, 157 RRE_LRVGR = 0xb90f, 158 RRE_LTGR = 0xb902, 159 RRE_MLGR = 0xb986, 160 RRE_MSGR = 0xb90c, 161 RRE_MSR = 0xb252, 162 RRE_NGR = 0xb980, 163 RRE_OGR = 0xb981, 164 RRE_SGR = 0xb909, 165 RRE_SLGR = 0xb90b, 166 RRE_SLBR = 0xb999, 167 RRE_SLBGR = 0xb989, 168 RRE_XGR = 0xb982, 169 170 RRFa_MGRK = 0xb9ec, 171 RRFa_MSRKC = 0xb9fd, 172 RRFa_MSGRKC = 0xb9ed, 173 RRFa_NCRK = 0xb9f5, 174 RRFa_NCGRK = 0xb9e5, 175 RRFa_NNRK = 0xb974, 176 RRFa_NNGRK = 0xb964, 177 RRFa_NORK = 0xb976, 178 RRFa_NOGRK = 0xb966, 179 RRFa_NRK = 0xb9f4, 180 RRFa_NGRK = 0xb9e4, 181 RRFa_NXRK = 0xb977, 182 RRFa_NXGRK = 0xb967, 183 RRFa_OCRK = 0xb975, 184 RRFa_OCGRK = 0xb965, 185 RRFa_ORK = 0xb9f6, 186 RRFa_OGRK = 0xb9e6, 187 RRFa_SRK = 0xb9f9, 188 RRFa_SGRK = 0xb9e9, 189 RRFa_SLRK = 0xb9fb, 190 RRFa_SLGRK = 0xb9eb, 191 RRFa_XRK = 0xb9f7, 192 RRFa_XGRK = 0xb9e7, 193 194 RRFam_SELGR = 0xb9e3, 195 196 RRFc_LOCR = 0xb9f2, 197 RRFc_LOCGR = 0xb9e2, 198 RRFc_POPCNT = 0xb9e1, 199 200 RR_AR = 0x1a, 201 RR_ALR = 0x1e, 202 RR_BASR = 0x0d, 203 RR_BCR = 0x07, 204 RR_CLR = 0x15, 205 RR_CR = 0x19, 206 RR_DR = 0x1d, 207 RR_LCR = 0x13, 208 RR_LR = 0x18, 209 RR_LTR = 0x12, 210 RR_NR = 0x14, 211 RR_OR = 0x16, 212 RR_SR = 0x1b, 213 RR_SLR = 0x1f, 214 RR_XR = 0x17, 215 216 RSY_RLL = 0xeb1d, 217 RSY_RLLG = 0xeb1c, 218 RSY_SLLG = 0xeb0d, 219 RSY_SLLK = 0xebdf, 220 RSY_SRAG = 0xeb0a, 221 RSY_SRAK = 0xebdc, 222 RSY_SRLG = 0xeb0c, 223 RSY_SRLK = 0xebde, 224 225 RS_SLL = 0x89, 226 RS_SRA = 0x8a, 227 RS_SRL = 0x88, 228 229 RXY_AG = 0xe308, 230 RXY_AY = 0xe35a, 231 RXY_CG = 0xe320, 232 RXY_CLG = 0xe321, 233 RXY_CLY = 0xe355, 234 RXY_CY = 0xe359, 235 RXY_LAY = 0xe371, 236 RXY_LB = 0xe376, 237 RXY_LG = 0xe304, 238 RXY_LGB = 0xe377, 239 RXY_LGF = 0xe314, 240 RXY_LGH = 0xe315, 241 RXY_LHY = 0xe378, 242 RXY_LLGC = 0xe390, 243 RXY_LLGF = 0xe316, 244 RXY_LLGH = 0xe391, 245 RXY_LMG = 0xeb04, 246 RXY_LRV = 0xe31e, 247 RXY_LRVG = 0xe30f, 248 RXY_LRVH = 0xe31f, 249 RXY_LY = 0xe358, 250 RXY_NG = 0xe380, 251 RXY_OG = 0xe381, 252 RXY_STCY = 0xe372, 253 RXY_STG = 0xe324, 254 RXY_STHY = 0xe370, 255 RXY_STMG = 0xeb24, 256 RXY_STRV = 0xe33e, 257 RXY_STRVG = 0xe32f, 258 RXY_STRVH = 0xe33f, 259 RXY_STY = 0xe350, 260 RXY_XG = 0xe382, 261 262 RX_A = 0x5a, 263 RX_C = 0x59, 264 RX_L = 0x58, 265 RX_LA = 0x41, 266 RX_LH = 0x48, 267 RX_ST = 0x50, 268 RX_STC = 0x42, 269 RX_STH = 0x40, 270 271 VRIa_VGBM = 0xe744, 272 VRIa_VREPI = 0xe745, 273 VRIb_VGM = 0xe746, 274 VRIc_VREP = 0xe74d, 275 276 VRRa_VLC = 0xe7de, 277 VRRa_VLP = 0xe7df, 278 VRRa_VLR = 0xe756, 279 VRRc_VA = 0xe7f3, 280 VRRc_VCEQ = 0xe7f8, /* we leave the m5 cs field 0 */ 281 VRRc_VCH = 0xe7fb, /* " */ 282 VRRc_VCHL = 0xe7f9, /* " */ 283 VRRc_VERLLV = 0xe773, 284 VRRc_VESLV = 0xe770, 285 VRRc_VESRAV = 0xe77a, 286 VRRc_VESRLV = 0xe778, 287 VRRc_VML = 0xe7a2, 288 VRRc_VMN = 0xe7fe, 289 VRRc_VMNL = 0xe7fc, 290 VRRc_VMX = 0xe7ff, 291 VRRc_VMXL = 0xe7fd, 292 VRRc_VN = 0xe768, 293 VRRc_VNC = 0xe769, 294 VRRc_VNN = 0xe76e, 295 VRRc_VNO = 0xe76b, 296 VRRc_VNX = 0xe76c, 297 VRRc_VO = 0xe76a, 298 VRRc_VOC = 0xe76f, 299 VRRc_VPKS = 0xe797, /* we leave the m5 cs field 0 */ 300 VRRc_VS = 0xe7f7, 301 VRRa_VUPH = 0xe7d7, 302 VRRa_VUPL = 0xe7d6, 303 VRRc_VX = 0xe76d, 304 VRRe_VSEL = 0xe78d, 305 VRRf_VLVGP = 0xe762, 306 307 VRSa_VERLL = 0xe733, 308 VRSa_VESL = 0xe730, 309 VRSa_VESRA = 0xe73a, 310 VRSa_VESRL = 0xe738, 311 VRSb_VLVG = 0xe722, 312 VRSc_VLGV = 0xe721, 313 314 VRX_VL = 0xe706, 315 VRX_VLLEZ = 0xe704, 316 VRX_VLREP = 0xe705, 317 VRX_VST = 0xe70e, 318 VRX_VSTEF = 0xe70b, 319 VRX_VSTEG = 0xe70a, 320 321 NOP = 0x0707, 322} S390Opcode; 323 324#ifdef CONFIG_DEBUG_TCG 325static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 326 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", 327 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", 328 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 329 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7", 330 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15", 331 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23", 332 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31", 333}; 334#endif 335 336/* Since R6 is a potential argument register, choose it last of the 337 call-saved registers. Likewise prefer the call-clobbered registers 338 in reverse order to maximize the chance of avoiding the arguments. */ 339static const int tcg_target_reg_alloc_order[] = { 340 /* Call saved registers. */ 341 TCG_REG_R13, 342 TCG_REG_R12, 343 TCG_REG_R11, 344 TCG_REG_R10, 345 TCG_REG_R9, 346 TCG_REG_R8, 347 TCG_REG_R7, 348 TCG_REG_R6, 349 /* Call clobbered registers. */ 350 TCG_REG_R14, 351 TCG_REG_R0, 352 TCG_REG_R1, 353 /* Argument registers, in reverse order of allocation. */ 354 TCG_REG_R5, 355 TCG_REG_R4, 356 TCG_REG_R3, 357 TCG_REG_R2, 358 359 /* V8-V15 are call saved, and omitted. */ 360 TCG_REG_V0, 361 TCG_REG_V1, 362 TCG_REG_V2, 363 TCG_REG_V3, 364 TCG_REG_V4, 365 TCG_REG_V5, 366 TCG_REG_V6, 367 TCG_REG_V7, 368 TCG_REG_V16, 369 TCG_REG_V17, 370 TCG_REG_V18, 371 TCG_REG_V19, 372 TCG_REG_V20, 373 TCG_REG_V21, 374 TCG_REG_V22, 375 TCG_REG_V23, 376 TCG_REG_V24, 377 TCG_REG_V25, 378 TCG_REG_V26, 379 TCG_REG_V27, 380 TCG_REG_V28, 381 TCG_REG_V29, 382 TCG_REG_V30, 383 TCG_REG_V31, 384}; 385 386static const int tcg_target_call_iarg_regs[] = { 387 TCG_REG_R2, 388 TCG_REG_R3, 389 TCG_REG_R4, 390 TCG_REG_R5, 391 TCG_REG_R6, 392}; 393 394static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 395{ 396 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 397 tcg_debug_assert(slot == 0); 398 return TCG_REG_R2; 399} 400 401#define S390_CC_EQ 8 402#define S390_CC_LT 4 403#define S390_CC_GT 2 404#define S390_CC_OV 1 405#define S390_CC_NE (S390_CC_LT | S390_CC_GT) 406#define S390_CC_LE (S390_CC_LT | S390_CC_EQ) 407#define S390_CC_GE (S390_CC_GT | S390_CC_EQ) 408#define S390_CC_NEVER 0 409#define S390_CC_ALWAYS 15 410 411/* Condition codes that result from a COMPARE and COMPARE LOGICAL. */ 412static const uint8_t tcg_cond_to_s390_cond[] = { 413 [TCG_COND_EQ] = S390_CC_EQ, 414 [TCG_COND_NE] = S390_CC_NE, 415 [TCG_COND_LT] = S390_CC_LT, 416 [TCG_COND_LE] = S390_CC_LE, 417 [TCG_COND_GT] = S390_CC_GT, 418 [TCG_COND_GE] = S390_CC_GE, 419 [TCG_COND_LTU] = S390_CC_LT, 420 [TCG_COND_LEU] = S390_CC_LE, 421 [TCG_COND_GTU] = S390_CC_GT, 422 [TCG_COND_GEU] = S390_CC_GE, 423}; 424 425/* Condition codes that result from a LOAD AND TEST. Here, we have no 426 unsigned instruction variation, however since the test is vs zero we 427 can re-map the outcomes appropriately. */ 428static const uint8_t tcg_cond_to_ltr_cond[] = { 429 [TCG_COND_EQ] = S390_CC_EQ, 430 [TCG_COND_NE] = S390_CC_NE, 431 [TCG_COND_LT] = S390_CC_LT, 432 [TCG_COND_LE] = S390_CC_LE, 433 [TCG_COND_GT] = S390_CC_GT, 434 [TCG_COND_GE] = S390_CC_GE, 435 [TCG_COND_LTU] = S390_CC_NEVER, 436 [TCG_COND_LEU] = S390_CC_EQ, 437 [TCG_COND_GTU] = S390_CC_NE, 438 [TCG_COND_GEU] = S390_CC_ALWAYS, 439}; 440 441static const tcg_insn_unit *tb_ret_addr; 442uint64_t s390_facilities[3]; 443 444static inline bool is_general_reg(TCGReg r) 445{ 446 return r <= TCG_REG_R15; 447} 448 449static inline bool is_vector_reg(TCGReg r) 450{ 451 return r >= TCG_REG_V0 && r <= TCG_REG_V31; 452} 453 454static bool patch_reloc(tcg_insn_unit *src_rw, int type, 455 intptr_t value, intptr_t addend) 456{ 457 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 458 intptr_t pcrel2; 459 uint32_t old; 460 461 value += addend; 462 pcrel2 = (tcg_insn_unit *)value - src_rx; 463 464 switch (type) { 465 case R_390_PC16DBL: 466 if (pcrel2 == (int16_t)pcrel2) { 467 tcg_patch16(src_rw, pcrel2); 468 return true; 469 } 470 break; 471 case R_390_PC32DBL: 472 if (pcrel2 == (int32_t)pcrel2) { 473 tcg_patch32(src_rw, pcrel2); 474 return true; 475 } 476 break; 477 case R_390_20: 478 if (value == sextract64(value, 0, 20)) { 479 old = *(uint32_t *)src_rw & 0xf00000ff; 480 old |= ((value & 0xfff) << 16) | ((value & 0xff000) >> 4); 481 tcg_patch32(src_rw, old); 482 return true; 483 } 484 break; 485 default: 486 g_assert_not_reached(); 487 } 488 return false; 489} 490 491static int is_const_p16(uint64_t val) 492{ 493 for (int i = 0; i < 4; ++i) { 494 uint64_t mask = 0xffffull << (i * 16); 495 if ((val & ~mask) == 0) { 496 return i; 497 } 498 } 499 return -1; 500} 501 502static int is_const_p32(uint64_t val) 503{ 504 if ((val & 0xffffffff00000000ull) == 0) { 505 return 0; 506 } 507 if ((val & 0x00000000ffffffffull) == 0) { 508 return 1; 509 } 510 return -1; 511} 512 513/* 514 * Accept bit patterns like these: 515 * 0....01....1 516 * 1....10....0 517 * 1..10..01..1 518 * 0..01..10..0 519 * Copied from gcc sources. 520 */ 521static bool risbg_mask(uint64_t c) 522{ 523 uint64_t lsb; 524 /* We don't change the number of transitions by inverting, 525 so make sure we start with the LSB zero. */ 526 if (c & 1) { 527 c = ~c; 528 } 529 /* Reject all zeros or all ones. */ 530 if (c == 0) { 531 return false; 532 } 533 /* Find the first transition. */ 534 lsb = c & -c; 535 /* Invert to look for a second transition. */ 536 c = ~c; 537 /* Erase the first transition. */ 538 c &= -lsb; 539 /* Find the second transition, if any. */ 540 lsb = c & -c; 541 /* Match if all the bits are 1's, or if c is zero. */ 542 return c == -lsb; 543} 544 545/* Test if a constant matches the constraint. */ 546static bool tcg_target_const_match(int64_t val, TCGType type, int ct) 547{ 548 if (ct & TCG_CT_CONST) { 549 return 1; 550 } 551 552 if (type == TCG_TYPE_I32) { 553 val = (int32_t)val; 554 } 555 556 /* The following are mutually exclusive. */ 557 if (ct & TCG_CT_CONST_S16) { 558 return val == (int16_t)val; 559 } else if (ct & TCG_CT_CONST_S32) { 560 return val == (int32_t)val; 561 } else if (ct & TCG_CT_CONST_S33) { 562 return val >= -0xffffffffll && val <= 0xffffffffll; 563 } else if (ct & TCG_CT_CONST_ZERO) { 564 return val == 0; 565 } 566 567 if (ct & TCG_CT_CONST_INV) { 568 val = ~val; 569 } 570 /* 571 * Note that is_const_p16 is a subset of is_const_p32, 572 * so we don't need both constraints. 573 */ 574 if ((ct & TCG_CT_CONST_P32) && is_const_p32(val) >= 0) { 575 return true; 576 } 577 if ((ct & TCG_CT_CONST_INVRISBG) && risbg_mask(~val)) { 578 return true; 579 } 580 581 return 0; 582} 583 584/* Emit instructions according to the given instruction format. */ 585 586static void tcg_out_insn_RR(TCGContext *s, S390Opcode op, TCGReg r1, TCGReg r2) 587{ 588 tcg_out16(s, (op << 8) | (r1 << 4) | r2); 589} 590 591static void tcg_out_insn_RRE(TCGContext *s, S390Opcode op, 592 TCGReg r1, TCGReg r2) 593{ 594 tcg_out32(s, (op << 16) | (r1 << 4) | r2); 595} 596 597/* RRF-a without the m4 field */ 598static void tcg_out_insn_RRFa(TCGContext *s, S390Opcode op, 599 TCGReg r1, TCGReg r2, TCGReg r3) 600{ 601 tcg_out32(s, (op << 16) | (r3 << 12) | (r1 << 4) | r2); 602} 603 604/* RRF-a with the m4 field */ 605static void tcg_out_insn_RRFam(TCGContext *s, S390Opcode op, 606 TCGReg r1, TCGReg r2, TCGReg r3, int m4) 607{ 608 tcg_out32(s, (op << 16) | (r3 << 12) | (m4 << 8) | (r1 << 4) | r2); 609} 610 611static void tcg_out_insn_RRFc(TCGContext *s, S390Opcode op, 612 TCGReg r1, TCGReg r2, int m3) 613{ 614 tcg_out32(s, (op << 16) | (m3 << 12) | (r1 << 4) | r2); 615} 616 617static void tcg_out_insn_RI(TCGContext *s, S390Opcode op, TCGReg r1, int i2) 618{ 619 tcg_out32(s, (op << 16) | (r1 << 20) | (i2 & 0xffff)); 620} 621 622static void tcg_out_insn_RIEg(TCGContext *s, S390Opcode op, TCGReg r1, 623 int i2, int m3) 624{ 625 tcg_out16(s, (op & 0xff00) | (r1 << 4) | m3); 626 tcg_out32(s, (i2 << 16) | (op & 0xff)); 627} 628 629static void tcg_out_insn_RIL(TCGContext *s, S390Opcode op, TCGReg r1, int i2) 630{ 631 tcg_out16(s, op | (r1 << 4)); 632 tcg_out32(s, i2); 633} 634 635static void tcg_out_insn_RS(TCGContext *s, S390Opcode op, TCGReg r1, 636 TCGReg b2, TCGReg r3, int disp) 637{ 638 tcg_out32(s, (op << 24) | (r1 << 20) | (r3 << 16) | (b2 << 12) 639 | (disp & 0xfff)); 640} 641 642static void tcg_out_insn_RSY(TCGContext *s, S390Opcode op, TCGReg r1, 643 TCGReg b2, TCGReg r3, int disp) 644{ 645 tcg_out16(s, (op & 0xff00) | (r1 << 4) | r3); 646 tcg_out32(s, (op & 0xff) | (b2 << 28) 647 | ((disp & 0xfff) << 16) | ((disp & 0xff000) >> 4)); 648} 649 650#define tcg_out_insn_RX tcg_out_insn_RS 651#define tcg_out_insn_RXY tcg_out_insn_RSY 652 653static int RXB(TCGReg v1, TCGReg v2, TCGReg v3, TCGReg v4) 654{ 655 /* 656 * Shift bit 4 of each regno to its corresponding bit of RXB. 657 * RXB itself begins at bit 8 of the instruction so 8 - 4 = 4 658 * is the left-shift of the 4th operand. 659 */ 660 return ((v1 & 0x10) << (4 + 3)) 661 | ((v2 & 0x10) << (4 + 2)) 662 | ((v3 & 0x10) << (4 + 1)) 663 | ((v4 & 0x10) << (4 + 0)); 664} 665 666static void tcg_out_insn_VRIa(TCGContext *s, S390Opcode op, 667 TCGReg v1, uint16_t i2, int m3) 668{ 669 tcg_debug_assert(is_vector_reg(v1)); 670 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4)); 671 tcg_out16(s, i2); 672 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m3 << 12)); 673} 674 675static void tcg_out_insn_VRIb(TCGContext *s, S390Opcode op, 676 TCGReg v1, uint8_t i2, uint8_t i3, int m4) 677{ 678 tcg_debug_assert(is_vector_reg(v1)); 679 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4)); 680 tcg_out16(s, (i2 << 8) | (i3 & 0xff)); 681 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m4 << 12)); 682} 683 684static void tcg_out_insn_VRIc(TCGContext *s, S390Opcode op, 685 TCGReg v1, uint16_t i2, TCGReg v3, int m4) 686{ 687 tcg_debug_assert(is_vector_reg(v1)); 688 tcg_debug_assert(is_vector_reg(v3)); 689 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v3 & 0xf)); 690 tcg_out16(s, i2); 691 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, v3, 0) | (m4 << 12)); 692} 693 694static void tcg_out_insn_VRRa(TCGContext *s, S390Opcode op, 695 TCGReg v1, TCGReg v2, int m3) 696{ 697 tcg_debug_assert(is_vector_reg(v1)); 698 tcg_debug_assert(is_vector_reg(v2)); 699 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v2 & 0xf)); 700 tcg_out32(s, (op & 0x00ff) | RXB(v1, v2, 0, 0) | (m3 << 12)); 701} 702 703static void tcg_out_insn_VRRc(TCGContext *s, S390Opcode op, 704 TCGReg v1, TCGReg v2, TCGReg v3, int m4) 705{ 706 tcg_debug_assert(is_vector_reg(v1)); 707 tcg_debug_assert(is_vector_reg(v2)); 708 tcg_debug_assert(is_vector_reg(v3)); 709 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v2 & 0xf)); 710 tcg_out16(s, v3 << 12); 711 tcg_out16(s, (op & 0x00ff) | RXB(v1, v2, v3, 0) | (m4 << 12)); 712} 713 714static void tcg_out_insn_VRRe(TCGContext *s, S390Opcode op, 715 TCGReg v1, TCGReg v2, TCGReg v3, TCGReg v4) 716{ 717 tcg_debug_assert(is_vector_reg(v1)); 718 tcg_debug_assert(is_vector_reg(v2)); 719 tcg_debug_assert(is_vector_reg(v3)); 720 tcg_debug_assert(is_vector_reg(v4)); 721 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v2 & 0xf)); 722 tcg_out16(s, v3 << 12); 723 tcg_out16(s, (op & 0x00ff) | RXB(v1, v2, v3, v4) | (v4 << 12)); 724} 725 726static void tcg_out_insn_VRRf(TCGContext *s, S390Opcode op, 727 TCGReg v1, TCGReg r2, TCGReg r3) 728{ 729 tcg_debug_assert(is_vector_reg(v1)); 730 tcg_debug_assert(is_general_reg(r2)); 731 tcg_debug_assert(is_general_reg(r3)); 732 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | r2); 733 tcg_out16(s, r3 << 12); 734 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0)); 735} 736 737static void tcg_out_insn_VRSa(TCGContext *s, S390Opcode op, TCGReg v1, 738 intptr_t d2, TCGReg b2, TCGReg v3, int m4) 739{ 740 tcg_debug_assert(is_vector_reg(v1)); 741 tcg_debug_assert(d2 >= 0 && d2 <= 0xfff); 742 tcg_debug_assert(is_general_reg(b2)); 743 tcg_debug_assert(is_vector_reg(v3)); 744 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v3 & 0xf)); 745 tcg_out16(s, b2 << 12 | d2); 746 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, v3, 0) | (m4 << 12)); 747} 748 749static void tcg_out_insn_VRSb(TCGContext *s, S390Opcode op, TCGReg v1, 750 intptr_t d2, TCGReg b2, TCGReg r3, int m4) 751{ 752 tcg_debug_assert(is_vector_reg(v1)); 753 tcg_debug_assert(d2 >= 0 && d2 <= 0xfff); 754 tcg_debug_assert(is_general_reg(b2)); 755 tcg_debug_assert(is_general_reg(r3)); 756 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | r3); 757 tcg_out16(s, b2 << 12 | d2); 758 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m4 << 12)); 759} 760 761static void tcg_out_insn_VRSc(TCGContext *s, S390Opcode op, TCGReg r1, 762 intptr_t d2, TCGReg b2, TCGReg v3, int m4) 763{ 764 tcg_debug_assert(is_general_reg(r1)); 765 tcg_debug_assert(d2 >= 0 && d2 <= 0xfff); 766 tcg_debug_assert(is_general_reg(b2)); 767 tcg_debug_assert(is_vector_reg(v3)); 768 tcg_out16(s, (op & 0xff00) | (r1 << 4) | (v3 & 0xf)); 769 tcg_out16(s, b2 << 12 | d2); 770 tcg_out16(s, (op & 0x00ff) | RXB(0, 0, v3, 0) | (m4 << 12)); 771} 772 773static void tcg_out_insn_VRX(TCGContext *s, S390Opcode op, TCGReg v1, 774 TCGReg b2, TCGReg x2, intptr_t d2, int m3) 775{ 776 tcg_debug_assert(is_vector_reg(v1)); 777 tcg_debug_assert(d2 >= 0 && d2 <= 0xfff); 778 tcg_debug_assert(is_general_reg(x2)); 779 tcg_debug_assert(is_general_reg(b2)); 780 tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | x2); 781 tcg_out16(s, (b2 << 12) | d2); 782 tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m3 << 12)); 783} 784 785/* Emit an opcode with "type-checking" of the format. */ 786#define tcg_out_insn(S, FMT, OP, ...) \ 787 glue(tcg_out_insn_,FMT)(S, glue(glue(FMT,_),OP), ## __VA_ARGS__) 788 789 790/* emit 64-bit shifts */ 791static void tcg_out_sh64(TCGContext* s, S390Opcode op, TCGReg dest, 792 TCGReg src, TCGReg sh_reg, int sh_imm) 793{ 794 tcg_out_insn_RSY(s, op, dest, sh_reg, src, sh_imm); 795} 796 797/* emit 32-bit shifts */ 798static void tcg_out_sh32(TCGContext* s, S390Opcode op, TCGReg dest, 799 TCGReg sh_reg, int sh_imm) 800{ 801 tcg_out_insn_RS(s, op, dest, sh_reg, 0, sh_imm); 802} 803 804static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg dst, TCGReg src) 805{ 806 if (src == dst) { 807 return true; 808 } 809 switch (type) { 810 case TCG_TYPE_I32: 811 if (likely(is_general_reg(dst) && is_general_reg(src))) { 812 tcg_out_insn(s, RR, LR, dst, src); 813 break; 814 } 815 /* fallthru */ 816 817 case TCG_TYPE_I64: 818 if (likely(is_general_reg(dst))) { 819 if (likely(is_general_reg(src))) { 820 tcg_out_insn(s, RRE, LGR, dst, src); 821 } else { 822 tcg_out_insn(s, VRSc, VLGV, dst, 0, 0, src, 3); 823 } 824 break; 825 } else if (is_general_reg(src)) { 826 tcg_out_insn(s, VRSb, VLVG, dst, 0, 0, src, 3); 827 break; 828 } 829 /* fallthru */ 830 831 case TCG_TYPE_V64: 832 case TCG_TYPE_V128: 833 tcg_out_insn(s, VRRa, VLR, dst, src, 0); 834 break; 835 836 default: 837 g_assert_not_reached(); 838 } 839 return true; 840} 841 842static const S390Opcode li_insns[4] = { 843 RI_LLILL, RI_LLILH, RI_LLIHL, RI_LLIHH 844}; 845static const S390Opcode oi_insns[4] = { 846 RI_OILL, RI_OILH, RI_OIHL, RI_OIHH 847}; 848static const S390Opcode lif_insns[2] = { 849 RIL_LLILF, RIL_LLIHF, 850}; 851 852/* load a register with an immediate value */ 853static void tcg_out_movi(TCGContext *s, TCGType type, 854 TCGReg ret, tcg_target_long sval) 855{ 856 tcg_target_ulong uval = sval; 857 ptrdiff_t pc_off; 858 int i; 859 860 if (type == TCG_TYPE_I32) { 861 uval = (uint32_t)sval; 862 sval = (int32_t)sval; 863 } 864 865 /* Try all 32-bit insns that can load it in one go. */ 866 if (sval >= -0x8000 && sval < 0x8000) { 867 tcg_out_insn(s, RI, LGHI, ret, sval); 868 return; 869 } 870 871 i = is_const_p16(uval); 872 if (i >= 0) { 873 tcg_out_insn_RI(s, li_insns[i], ret, uval >> (i * 16)); 874 return; 875 } 876 877 /* Try all 48-bit insns that can load it in one go. */ 878 if (sval == (int32_t)sval) { 879 tcg_out_insn(s, RIL, LGFI, ret, sval); 880 return; 881 } 882 883 i = is_const_p32(uval); 884 if (i >= 0) { 885 tcg_out_insn_RIL(s, lif_insns[i], ret, uval >> (i * 32)); 886 return; 887 } 888 889 /* Try for PC-relative address load. For odd addresses, add one. */ 890 pc_off = tcg_pcrel_diff(s, (void *)sval) >> 1; 891 if (pc_off == (int32_t)pc_off) { 892 tcg_out_insn(s, RIL, LARL, ret, pc_off); 893 if (sval & 1) { 894 tcg_out_insn(s, RI, AGHI, ret, 1); 895 } 896 return; 897 } 898 899 /* Otherwise, load it by parts. */ 900 i = is_const_p16((uint32_t)uval); 901 if (i >= 0) { 902 tcg_out_insn_RI(s, li_insns[i], ret, uval >> (i * 16)); 903 } else { 904 tcg_out_insn(s, RIL, LLILF, ret, uval); 905 } 906 uval >>= 32; 907 i = is_const_p16(uval); 908 if (i >= 0) { 909 tcg_out_insn_RI(s, oi_insns[i + 2], ret, uval >> (i * 16)); 910 } else { 911 tcg_out_insn(s, RIL, OIHF, ret, uval); 912 } 913} 914 915/* Emit a load/store type instruction. Inputs are: 916 DATA: The register to be loaded or stored. 917 BASE+OFS: The effective address. 918 OPC_RX: If the operation has an RX format opcode (e.g. STC), otherwise 0. 919 OPC_RXY: The RXY format opcode for the operation (e.g. STCY). */ 920 921static void tcg_out_mem(TCGContext *s, S390Opcode opc_rx, S390Opcode opc_rxy, 922 TCGReg data, TCGReg base, TCGReg index, 923 tcg_target_long ofs) 924{ 925 if (ofs < -0x80000 || ofs >= 0x80000) { 926 /* Combine the low 20 bits of the offset with the actual load insn; 927 the high 44 bits must come from an immediate load. */ 928 tcg_target_long low = ((ofs & 0xfffff) ^ 0x80000) - 0x80000; 929 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - low); 930 ofs = low; 931 932 /* If we were already given an index register, add it in. */ 933 if (index != TCG_REG_NONE) { 934 tcg_out_insn(s, RRE, AGR, TCG_TMP0, index); 935 } 936 index = TCG_TMP0; 937 } 938 939 if (opc_rx && ofs >= 0 && ofs < 0x1000) { 940 tcg_out_insn_RX(s, opc_rx, data, base, index, ofs); 941 } else { 942 tcg_out_insn_RXY(s, opc_rxy, data, base, index, ofs); 943 } 944} 945 946static void tcg_out_vrx_mem(TCGContext *s, S390Opcode opc_vrx, 947 TCGReg data, TCGReg base, TCGReg index, 948 tcg_target_long ofs, int m3) 949{ 950 if (ofs < 0 || ofs >= 0x1000) { 951 if (ofs >= -0x80000 && ofs < 0x80000) { 952 tcg_out_insn(s, RXY, LAY, TCG_TMP0, base, index, ofs); 953 base = TCG_TMP0; 954 index = TCG_REG_NONE; 955 ofs = 0; 956 } else { 957 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs); 958 if (index != TCG_REG_NONE) { 959 tcg_out_insn(s, RRE, AGR, TCG_TMP0, index); 960 } 961 index = TCG_TMP0; 962 ofs = 0; 963 } 964 } 965 tcg_out_insn_VRX(s, opc_vrx, data, base, index, ofs, m3); 966} 967 968/* load data without address translation or endianness conversion */ 969static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg data, 970 TCGReg base, intptr_t ofs) 971{ 972 switch (type) { 973 case TCG_TYPE_I32: 974 if (likely(is_general_reg(data))) { 975 tcg_out_mem(s, RX_L, RXY_LY, data, base, TCG_REG_NONE, ofs); 976 break; 977 } 978 tcg_out_vrx_mem(s, VRX_VLLEZ, data, base, TCG_REG_NONE, ofs, MO_32); 979 break; 980 981 case TCG_TYPE_I64: 982 if (likely(is_general_reg(data))) { 983 tcg_out_mem(s, 0, RXY_LG, data, base, TCG_REG_NONE, ofs); 984 break; 985 } 986 /* fallthru */ 987 988 case TCG_TYPE_V64: 989 tcg_out_vrx_mem(s, VRX_VLLEZ, data, base, TCG_REG_NONE, ofs, MO_64); 990 break; 991 992 case TCG_TYPE_V128: 993 /* Hint quadword aligned. */ 994 tcg_out_vrx_mem(s, VRX_VL, data, base, TCG_REG_NONE, ofs, 4); 995 break; 996 997 default: 998 g_assert_not_reached(); 999 } 1000} 1001 1002static void tcg_out_st(TCGContext *s, TCGType type, TCGReg data, 1003 TCGReg base, intptr_t ofs) 1004{ 1005 switch (type) { 1006 case TCG_TYPE_I32: 1007 if (likely(is_general_reg(data))) { 1008 tcg_out_mem(s, RX_ST, RXY_STY, data, base, TCG_REG_NONE, ofs); 1009 } else { 1010 tcg_out_vrx_mem(s, VRX_VSTEF, data, base, TCG_REG_NONE, ofs, 1); 1011 } 1012 break; 1013 1014 case TCG_TYPE_I64: 1015 if (likely(is_general_reg(data))) { 1016 tcg_out_mem(s, 0, RXY_STG, data, base, TCG_REG_NONE, ofs); 1017 break; 1018 } 1019 /* fallthru */ 1020 1021 case TCG_TYPE_V64: 1022 tcg_out_vrx_mem(s, VRX_VSTEG, data, base, TCG_REG_NONE, ofs, 0); 1023 break; 1024 1025 case TCG_TYPE_V128: 1026 /* Hint quadword aligned. */ 1027 tcg_out_vrx_mem(s, VRX_VST, data, base, TCG_REG_NONE, ofs, 4); 1028 break; 1029 1030 default: 1031 g_assert_not_reached(); 1032 } 1033} 1034 1035static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 1036 TCGReg base, intptr_t ofs) 1037{ 1038 return false; 1039} 1040 1041static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 1042{ 1043 return false; 1044} 1045 1046static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 1047 tcg_target_long imm) 1048{ 1049 /* This function is only used for passing structs by reference. */ 1050 tcg_out_mem(s, RX_LA, RXY_LAY, rd, rs, TCG_REG_NONE, imm); 1051} 1052 1053static inline void tcg_out_risbg(TCGContext *s, TCGReg dest, TCGReg src, 1054 int msb, int lsb, int ofs, int z) 1055{ 1056 /* Format RIE-f */ 1057 tcg_out16(s, (RIEf_RISBG & 0xff00) | (dest << 4) | src); 1058 tcg_out16(s, (msb << 8) | (z << 7) | lsb); 1059 tcg_out16(s, (ofs << 8) | (RIEf_RISBG & 0xff)); 1060} 1061 1062static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) 1063{ 1064 tcg_out_insn(s, RRE, LGBR, dest, src); 1065} 1066 1067static void tcg_out_ext8u(TCGContext *s, TCGReg dest, TCGReg src) 1068{ 1069 tcg_out_insn(s, RRE, LLGCR, dest, src); 1070} 1071 1072static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) 1073{ 1074 tcg_out_insn(s, RRE, LGHR, dest, src); 1075} 1076 1077static void tcg_out_ext16u(TCGContext *s, TCGReg dest, TCGReg src) 1078{ 1079 tcg_out_insn(s, RRE, LLGHR, dest, src); 1080} 1081 1082static void tcg_out_ext32s(TCGContext *s, TCGReg dest, TCGReg src) 1083{ 1084 tcg_out_insn(s, RRE, LGFR, dest, src); 1085} 1086 1087static void tcg_out_ext32u(TCGContext *s, TCGReg dest, TCGReg src) 1088{ 1089 tcg_out_insn(s, RRE, LLGFR, dest, src); 1090} 1091 1092static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg dest, TCGReg src) 1093{ 1094 tcg_out_ext32s(s, dest, src); 1095} 1096 1097static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg dest, TCGReg src) 1098{ 1099 tcg_out_ext32u(s, dest, src); 1100} 1101 1102static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg dest, TCGReg src) 1103{ 1104 tcg_out_mov(s, TCG_TYPE_I32, dest, src); 1105} 1106 1107static void tgen_andi_risbg(TCGContext *s, TCGReg out, TCGReg in, uint64_t val) 1108{ 1109 int msb, lsb; 1110 if ((val & 0x8000000000000001ull) == 0x8000000000000001ull) { 1111 /* Achieve wraparound by swapping msb and lsb. */ 1112 msb = 64 - ctz64(~val); 1113 lsb = clz64(~val) - 1; 1114 } else { 1115 msb = clz64(val); 1116 lsb = 63 - ctz64(val); 1117 } 1118 tcg_out_risbg(s, out, in, msb, lsb, 0, 1); 1119} 1120 1121static void tgen_andi(TCGContext *s, TCGType type, TCGReg dest, uint64_t val) 1122{ 1123 static const S390Opcode ni_insns[4] = { 1124 RI_NILL, RI_NILH, RI_NIHL, RI_NIHH 1125 }; 1126 static const S390Opcode nif_insns[2] = { 1127 RIL_NILF, RIL_NIHF 1128 }; 1129 uint64_t valid = (type == TCG_TYPE_I32 ? 0xffffffffull : -1ull); 1130 int i; 1131 1132 /* Look for the zero-extensions. */ 1133 if ((val & valid) == 0xffffffff) { 1134 tcg_out_ext32u(s, dest, dest); 1135 return; 1136 } 1137 if ((val & valid) == 0xff) { 1138 tcg_out_ext8u(s, dest, dest); 1139 return; 1140 } 1141 if ((val & valid) == 0xffff) { 1142 tcg_out_ext16u(s, dest, dest); 1143 return; 1144 } 1145 1146 i = is_const_p16(~val & valid); 1147 if (i >= 0) { 1148 tcg_out_insn_RI(s, ni_insns[i], dest, val >> (i * 16)); 1149 return; 1150 } 1151 1152 i = is_const_p32(~val & valid); 1153 tcg_debug_assert(i == 0 || type != TCG_TYPE_I32); 1154 if (i >= 0) { 1155 tcg_out_insn_RIL(s, nif_insns[i], dest, val >> (i * 32)); 1156 return; 1157 } 1158 1159 if (risbg_mask(val)) { 1160 tgen_andi_risbg(s, dest, dest, val); 1161 return; 1162 } 1163 1164 g_assert_not_reached(); 1165} 1166 1167static void tgen_ori(TCGContext *s, TCGReg dest, uint64_t val) 1168{ 1169 static const S390Opcode oif_insns[2] = { 1170 RIL_OILF, RIL_OIHF 1171 }; 1172 1173 int i; 1174 1175 i = is_const_p16(val); 1176 if (i >= 0) { 1177 tcg_out_insn_RI(s, oi_insns[i], dest, val >> (i * 16)); 1178 return; 1179 } 1180 1181 i = is_const_p32(val); 1182 if (i >= 0) { 1183 tcg_out_insn_RIL(s, oif_insns[i], dest, val >> (i * 32)); 1184 return; 1185 } 1186 1187 g_assert_not_reached(); 1188} 1189 1190static void tgen_xori(TCGContext *s, TCGReg dest, uint64_t val) 1191{ 1192 switch (is_const_p32(val)) { 1193 case 0: 1194 tcg_out_insn(s, RIL, XILF, dest, val); 1195 break; 1196 case 1: 1197 tcg_out_insn(s, RIL, XIHF, dest, val >> 32); 1198 break; 1199 default: 1200 g_assert_not_reached(); 1201 } 1202} 1203 1204static int tgen_cmp2(TCGContext *s, TCGType type, TCGCond c, TCGReg r1, 1205 TCGArg c2, bool c2const, bool need_carry, int *inv_cc) 1206{ 1207 bool is_unsigned = is_unsigned_cond(c); 1208 TCGCond inv_c = tcg_invert_cond(c); 1209 S390Opcode op; 1210 1211 if (c2const) { 1212 if (c2 == 0) { 1213 if (!(is_unsigned && need_carry)) { 1214 if (type == TCG_TYPE_I32) { 1215 tcg_out_insn(s, RR, LTR, r1, r1); 1216 } else { 1217 tcg_out_insn(s, RRE, LTGR, r1, r1); 1218 } 1219 *inv_cc = tcg_cond_to_ltr_cond[inv_c]; 1220 return tcg_cond_to_ltr_cond[c]; 1221 } 1222 } 1223 1224 if (!is_unsigned && c2 == (int16_t)c2) { 1225 op = (type == TCG_TYPE_I32 ? RI_CHI : RI_CGHI); 1226 tcg_out_insn_RI(s, op, r1, c2); 1227 goto exit; 1228 } 1229 1230 if (type == TCG_TYPE_I32) { 1231 op = (is_unsigned ? RIL_CLFI : RIL_CFI); 1232 tcg_out_insn_RIL(s, op, r1, c2); 1233 goto exit; 1234 } 1235 1236 /* 1237 * Constraints are for a signed 33-bit operand, which is a 1238 * convenient superset of this signed/unsigned test. 1239 */ 1240 if (c2 == (is_unsigned ? (TCGArg)(uint32_t)c2 : (TCGArg)(int32_t)c2)) { 1241 op = (is_unsigned ? RIL_CLGFI : RIL_CGFI); 1242 tcg_out_insn_RIL(s, op, r1, c2); 1243 goto exit; 1244 } 1245 1246 /* Load everything else into a register. */ 1247 tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, c2); 1248 c2 = TCG_TMP0; 1249 } 1250 1251 if (type == TCG_TYPE_I32) { 1252 op = (is_unsigned ? RR_CLR : RR_CR); 1253 tcg_out_insn_RR(s, op, r1, c2); 1254 } else { 1255 op = (is_unsigned ? RRE_CLGR : RRE_CGR); 1256 tcg_out_insn_RRE(s, op, r1, c2); 1257 } 1258 1259 exit: 1260 *inv_cc = tcg_cond_to_s390_cond[inv_c]; 1261 return tcg_cond_to_s390_cond[c]; 1262} 1263 1264static int tgen_cmp(TCGContext *s, TCGType type, TCGCond c, TCGReg r1, 1265 TCGArg c2, bool c2const, bool need_carry) 1266{ 1267 int inv_cc; 1268 return tgen_cmp2(s, type, c, r1, c2, c2const, need_carry, &inv_cc); 1269} 1270 1271static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, 1272 TCGReg dest, TCGReg c1, TCGArg c2, int c2const) 1273{ 1274 int cc; 1275 1276 /* With LOC2, we can always emit the minimum 3 insns. */ 1277 if (HAVE_FACILITY(LOAD_ON_COND2)) { 1278 /* Emit: d = 0, d = (cc ? 1 : d). */ 1279 cc = tgen_cmp(s, type, cond, c1, c2, c2const, false); 1280 tcg_out_movi(s, TCG_TYPE_I64, dest, 0); 1281 tcg_out_insn(s, RIEg, LOCGHI, dest, 1, cc); 1282 return; 1283 } 1284 1285 restart: 1286 switch (cond) { 1287 case TCG_COND_NE: 1288 /* X != 0 is X > 0. */ 1289 if (c2const && c2 == 0) { 1290 cond = TCG_COND_GTU; 1291 } else { 1292 break; 1293 } 1294 /* fallthru */ 1295 1296 case TCG_COND_GTU: 1297 case TCG_COND_GT: 1298 /* The result of a compare has CC=2 for GT and CC=3 unused. 1299 ADD LOGICAL WITH CARRY considers (CC & 2) the carry bit. */ 1300 tgen_cmp(s, type, cond, c1, c2, c2const, true); 1301 tcg_out_movi(s, type, dest, 0); 1302 tcg_out_insn(s, RRE, ALCGR, dest, dest); 1303 return; 1304 1305 case TCG_COND_EQ: 1306 /* X == 0 is X <= 0. */ 1307 if (c2const && c2 == 0) { 1308 cond = TCG_COND_LEU; 1309 } else { 1310 break; 1311 } 1312 /* fallthru */ 1313 1314 case TCG_COND_LEU: 1315 case TCG_COND_LE: 1316 /* As above, but we're looking for borrow, or !carry. 1317 The second insn computes d - d - borrow, or -1 for true 1318 and 0 for false. So we must mask to 1 bit afterward. */ 1319 tgen_cmp(s, type, cond, c1, c2, c2const, true); 1320 tcg_out_insn(s, RRE, SLBGR, dest, dest); 1321 tgen_andi(s, type, dest, 1); 1322 return; 1323 1324 case TCG_COND_GEU: 1325 case TCG_COND_LTU: 1326 case TCG_COND_LT: 1327 case TCG_COND_GE: 1328 /* Swap operands so that we can use LEU/GTU/GT/LE. */ 1329 if (!c2const) { 1330 TCGReg t = c1; 1331 c1 = c2; 1332 c2 = t; 1333 cond = tcg_swap_cond(cond); 1334 goto restart; 1335 } 1336 break; 1337 1338 default: 1339 g_assert_not_reached(); 1340 } 1341 1342 cc = tgen_cmp(s, type, cond, c1, c2, c2const, false); 1343 /* Emit: d = 0, t = 1, d = (cc ? t : d). */ 1344 tcg_out_movi(s, TCG_TYPE_I64, dest, 0); 1345 tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 1); 1346 tcg_out_insn(s, RRFc, LOCGR, dest, TCG_TMP0, cc); 1347} 1348 1349static void tgen_movcond_int(TCGContext *s, TCGType type, TCGReg dest, 1350 TCGArg v3, int v3const, TCGReg v4, 1351 int cc, int inv_cc) 1352{ 1353 TCGReg src; 1354 1355 if (v3const) { 1356 if (dest == v4) { 1357 if (HAVE_FACILITY(LOAD_ON_COND2)) { 1358 /* Emit: if (cc) dest = v3. */ 1359 tcg_out_insn(s, RIEg, LOCGHI, dest, v3, cc); 1360 return; 1361 } 1362 tcg_out_insn(s, RI, LGHI, TCG_TMP0, v3); 1363 src = TCG_TMP0; 1364 } else { 1365 /* LGR+LOCGHI is larger than LGHI+LOCGR. */ 1366 tcg_out_insn(s, RI, LGHI, dest, v3); 1367 cc = inv_cc; 1368 src = v4; 1369 } 1370 } else { 1371 if (HAVE_FACILITY(MISC_INSN_EXT3)) { 1372 /* Emit: dest = cc ? v3 : v4. */ 1373 tcg_out_insn(s, RRFam, SELGR, dest, v3, v4, cc); 1374 return; 1375 } 1376 if (dest == v4) { 1377 src = v3; 1378 } else { 1379 tcg_out_mov(s, type, dest, v3); 1380 cc = inv_cc; 1381 src = v4; 1382 } 1383 } 1384 1385 /* Emit: if (cc) dest = src. */ 1386 tcg_out_insn(s, RRFc, LOCGR, dest, src, cc); 1387} 1388 1389static void tgen_movcond(TCGContext *s, TCGType type, TCGCond c, TCGReg dest, 1390 TCGReg c1, TCGArg c2, int c2const, 1391 TCGArg v3, int v3const, TCGReg v4) 1392{ 1393 int cc, inv_cc; 1394 1395 cc = tgen_cmp2(s, type, c, c1, c2, c2const, false, &inv_cc); 1396 tgen_movcond_int(s, type, dest, v3, v3const, v4, cc, inv_cc); 1397} 1398 1399static void tgen_clz(TCGContext *s, TCGReg dest, TCGReg a1, 1400 TCGArg a2, int a2const) 1401{ 1402 /* Since this sets both R and R+1, we have no choice but to store the 1403 result into R0, allowing R1 == TCG_TMP0 to be clobbered as well. */ 1404 QEMU_BUILD_BUG_ON(TCG_TMP0 != TCG_REG_R1); 1405 tcg_out_insn(s, RRE, FLOGR, TCG_REG_R0, a1); 1406 1407 if (a2const && a2 == 64) { 1408 tcg_out_mov(s, TCG_TYPE_I64, dest, TCG_REG_R0); 1409 return; 1410 } 1411 1412 /* 1413 * Conditions from FLOGR are: 1414 * 2 -> one bit found 1415 * 8 -> no one bit found 1416 */ 1417 tgen_movcond_int(s, TCG_TYPE_I64, dest, a2, a2const, TCG_REG_R0, 8, 2); 1418} 1419 1420static void tgen_ctpop(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) 1421{ 1422 /* With MIE3, and bit 0 of m4 set, we get the complete result. */ 1423 if (HAVE_FACILITY(MISC_INSN_EXT3)) { 1424 if (type == TCG_TYPE_I32) { 1425 tcg_out_ext32u(s, dest, src); 1426 src = dest; 1427 } 1428 tcg_out_insn(s, RRFc, POPCNT, dest, src, 8); 1429 return; 1430 } 1431 1432 /* Without MIE3, each byte gets the count of bits for the byte. */ 1433 tcg_out_insn(s, RRFc, POPCNT, dest, src, 0); 1434 1435 /* Multiply to sum each byte at the top of the word. */ 1436 if (type == TCG_TYPE_I32) { 1437 tcg_out_insn(s, RIL, MSFI, dest, 0x01010101); 1438 tcg_out_sh32(s, RS_SRL, dest, TCG_REG_NONE, 24); 1439 } else { 1440 tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 0x0101010101010101ull); 1441 tcg_out_insn(s, RRE, MSGR, dest, TCG_TMP0); 1442 tcg_out_sh64(s, RSY_SRLG, dest, dest, TCG_REG_NONE, 56); 1443 } 1444} 1445 1446static void tgen_deposit(TCGContext *s, TCGReg dest, TCGReg src, 1447 int ofs, int len, int z) 1448{ 1449 int lsb = (63 - ofs); 1450 int msb = lsb - (len - 1); 1451 tcg_out_risbg(s, dest, src, msb, lsb, ofs, z); 1452} 1453 1454static void tgen_extract(TCGContext *s, TCGReg dest, TCGReg src, 1455 int ofs, int len) 1456{ 1457 tcg_out_risbg(s, dest, src, 64 - len, 63, 64 - ofs, 1); 1458} 1459 1460static void tgen_gotoi(TCGContext *s, int cc, const tcg_insn_unit *dest) 1461{ 1462 ptrdiff_t off = tcg_pcrel_diff(s, dest) >> 1; 1463 if (off == (int16_t)off) { 1464 tcg_out_insn(s, RI, BRC, cc, off); 1465 } else if (off == (int32_t)off) { 1466 tcg_out_insn(s, RIL, BRCL, cc, off); 1467 } else { 1468 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)dest); 1469 tcg_out_insn(s, RR, BCR, cc, TCG_TMP0); 1470 } 1471} 1472 1473static void tgen_branch(TCGContext *s, int cc, TCGLabel *l) 1474{ 1475 if (l->has_value) { 1476 tgen_gotoi(s, cc, l->u.value_ptr); 1477 } else { 1478 tcg_out16(s, RI_BRC | (cc << 4)); 1479 tcg_out_reloc(s, s->code_ptr, R_390_PC16DBL, l, 2); 1480 s->code_ptr += 1; 1481 } 1482} 1483 1484static void tgen_compare_branch(TCGContext *s, S390Opcode opc, int cc, 1485 TCGReg r1, TCGReg r2, TCGLabel *l) 1486{ 1487 tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2); 1488 /* Format RIE-b */ 1489 tcg_out16(s, (opc & 0xff00) | (r1 << 4) | r2); 1490 tcg_out16(s, 0); 1491 tcg_out16(s, cc << 12 | (opc & 0xff)); 1492} 1493 1494static void tgen_compare_imm_branch(TCGContext *s, S390Opcode opc, int cc, 1495 TCGReg r1, int i2, TCGLabel *l) 1496{ 1497 tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2); 1498 /* Format RIE-c */ 1499 tcg_out16(s, (opc & 0xff00) | (r1 << 4) | cc); 1500 tcg_out16(s, 0); 1501 tcg_out16(s, (i2 << 8) | (opc & 0xff)); 1502} 1503 1504static void tgen_brcond(TCGContext *s, TCGType type, TCGCond c, 1505 TCGReg r1, TCGArg c2, int c2const, TCGLabel *l) 1506{ 1507 int cc; 1508 bool is_unsigned = is_unsigned_cond(c); 1509 bool in_range; 1510 S390Opcode opc; 1511 1512 cc = tcg_cond_to_s390_cond[c]; 1513 1514 if (!c2const) { 1515 opc = (type == TCG_TYPE_I32 1516 ? (is_unsigned ? RIEb_CLRJ : RIEb_CRJ) 1517 : (is_unsigned ? RIEb_CLGRJ : RIEb_CGRJ)); 1518 tgen_compare_branch(s, opc, cc, r1, c2, l); 1519 return; 1520 } 1521 1522 /* 1523 * COMPARE IMMEDIATE AND BRANCH RELATIVE has an 8-bit immediate field. 1524 * If the immediate we've been given does not fit that range, we'll 1525 * fall back to separate compare and branch instructions using the 1526 * larger comparison range afforded by COMPARE IMMEDIATE. 1527 */ 1528 if (type == TCG_TYPE_I32) { 1529 if (is_unsigned) { 1530 opc = RIEc_CLIJ; 1531 in_range = (uint32_t)c2 == (uint8_t)c2; 1532 } else { 1533 opc = RIEc_CIJ; 1534 in_range = (int32_t)c2 == (int8_t)c2; 1535 } 1536 } else { 1537 if (is_unsigned) { 1538 opc = RIEc_CLGIJ; 1539 in_range = (uint64_t)c2 == (uint8_t)c2; 1540 } else { 1541 opc = RIEc_CGIJ; 1542 in_range = (int64_t)c2 == (int8_t)c2; 1543 } 1544 } 1545 if (in_range) { 1546 tgen_compare_imm_branch(s, opc, cc, r1, c2, l); 1547 return; 1548 } 1549 1550 cc = tgen_cmp(s, type, c, r1, c2, c2const, false); 1551 tgen_branch(s, cc, l); 1552} 1553 1554static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *dest) 1555{ 1556 ptrdiff_t off = tcg_pcrel_diff(s, dest) >> 1; 1557 if (off == (int32_t)off) { 1558 tcg_out_insn(s, RIL, BRASL, TCG_REG_R14, off); 1559 } else { 1560 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)dest); 1561 tcg_out_insn(s, RR, BASR, TCG_REG_R14, TCG_TMP0); 1562 } 1563} 1564 1565static void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest, 1566 const TCGHelperInfo *info) 1567{ 1568 tcg_out_call_int(s, dest); 1569} 1570 1571typedef struct { 1572 TCGReg base; 1573 TCGReg index; 1574 int disp; 1575} HostAddress; 1576 1577static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg data, 1578 HostAddress h) 1579{ 1580 switch (opc & (MO_SSIZE | MO_BSWAP)) { 1581 case MO_UB: 1582 tcg_out_insn(s, RXY, LLGC, data, h.base, h.index, h.disp); 1583 break; 1584 case MO_SB: 1585 tcg_out_insn(s, RXY, LGB, data, h.base, h.index, h.disp); 1586 break; 1587 1588 case MO_UW | MO_BSWAP: 1589 /* swapped unsigned halfword load with upper bits zeroed */ 1590 tcg_out_insn(s, RXY, LRVH, data, h.base, h.index, h.disp); 1591 tcg_out_ext16u(s, data, data); 1592 break; 1593 case MO_UW: 1594 tcg_out_insn(s, RXY, LLGH, data, h.base, h.index, h.disp); 1595 break; 1596 1597 case MO_SW | MO_BSWAP: 1598 /* swapped sign-extended halfword load */ 1599 tcg_out_insn(s, RXY, LRVH, data, h.base, h.index, h.disp); 1600 tcg_out_ext16s(s, TCG_TYPE_REG, data, data); 1601 break; 1602 case MO_SW: 1603 tcg_out_insn(s, RXY, LGH, data, h.base, h.index, h.disp); 1604 break; 1605 1606 case MO_UL | MO_BSWAP: 1607 /* swapped unsigned int load with upper bits zeroed */ 1608 tcg_out_insn(s, RXY, LRV, data, h.base, h.index, h.disp); 1609 tcg_out_ext32u(s, data, data); 1610 break; 1611 case MO_UL: 1612 tcg_out_insn(s, RXY, LLGF, data, h.base, h.index, h.disp); 1613 break; 1614 1615 case MO_SL | MO_BSWAP: 1616 /* swapped sign-extended int load */ 1617 tcg_out_insn(s, RXY, LRV, data, h.base, h.index, h.disp); 1618 tcg_out_ext32s(s, data, data); 1619 break; 1620 case MO_SL: 1621 tcg_out_insn(s, RXY, LGF, data, h.base, h.index, h.disp); 1622 break; 1623 1624 case MO_UQ | MO_BSWAP: 1625 tcg_out_insn(s, RXY, LRVG, data, h.base, h.index, h.disp); 1626 break; 1627 case MO_UQ: 1628 tcg_out_insn(s, RXY, LG, data, h.base, h.index, h.disp); 1629 break; 1630 1631 default: 1632 g_assert_not_reached(); 1633 } 1634} 1635 1636static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg data, 1637 HostAddress h) 1638{ 1639 switch (opc & (MO_SIZE | MO_BSWAP)) { 1640 case MO_UB: 1641 if (h.disp >= 0 && h.disp < 0x1000) { 1642 tcg_out_insn(s, RX, STC, data, h.base, h.index, h.disp); 1643 } else { 1644 tcg_out_insn(s, RXY, STCY, data, h.base, h.index, h.disp); 1645 } 1646 break; 1647 1648 case MO_UW | MO_BSWAP: 1649 tcg_out_insn(s, RXY, STRVH, data, h.base, h.index, h.disp); 1650 break; 1651 case MO_UW: 1652 if (h.disp >= 0 && h.disp < 0x1000) { 1653 tcg_out_insn(s, RX, STH, data, h.base, h.index, h.disp); 1654 } else { 1655 tcg_out_insn(s, RXY, STHY, data, h.base, h.index, h.disp); 1656 } 1657 break; 1658 1659 case MO_UL | MO_BSWAP: 1660 tcg_out_insn(s, RXY, STRV, data, h.base, h.index, h.disp); 1661 break; 1662 case MO_UL: 1663 if (h.disp >= 0 && h.disp < 0x1000) { 1664 tcg_out_insn(s, RX, ST, data, h.base, h.index, h.disp); 1665 } else { 1666 tcg_out_insn(s, RXY, STY, data, h.base, h.index, h.disp); 1667 } 1668 break; 1669 1670 case MO_UQ | MO_BSWAP: 1671 tcg_out_insn(s, RXY, STRVG, data, h.base, h.index, h.disp); 1672 break; 1673 case MO_UQ: 1674 tcg_out_insn(s, RXY, STG, data, h.base, h.index, h.disp); 1675 break; 1676 1677 default: 1678 g_assert_not_reached(); 1679 } 1680} 1681 1682#if defined(CONFIG_SOFTMMU) 1683static const TCGLdstHelperParam ldst_helper_param = { 1684 .ntmp = 1, .tmp = { TCG_TMP0 } 1685}; 1686 1687static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1688{ 1689 MemOp opc = get_memop(lb->oi); 1690 1691 if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL, 1692 (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 2)) { 1693 return false; 1694 } 1695 1696 tcg_out_ld_helper_args(s, lb, &ldst_helper_param); 1697 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE]); 1698 tcg_out_ld_helper_ret(s, lb, false, &ldst_helper_param); 1699 1700 tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr); 1701 return true; 1702} 1703 1704static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1705{ 1706 MemOp opc = get_memop(lb->oi); 1707 1708 if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL, 1709 (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 2)) { 1710 return false; 1711 } 1712 1713 tcg_out_st_helper_args(s, lb, &ldst_helper_param); 1714 tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE]); 1715 1716 tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr); 1717 return true; 1718} 1719#else 1720static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) 1721{ 1722 if (!patch_reloc(l->label_ptr[0], R_390_PC16DBL, 1723 (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 2)) { 1724 return false; 1725 } 1726 1727 tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_R3, l->addrlo_reg); 1728 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0); 1729 1730 /* "Tail call" to the helper, with the return address back inline. */ 1731 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R14, (uintptr_t)l->raddr); 1732 tgen_gotoi(s, S390_CC_ALWAYS, (const void *)(l->is_ld ? helper_unaligned_ld 1733 : helper_unaligned_st)); 1734 return true; 1735} 1736 1737static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1738{ 1739 return tcg_out_fail_alignment(s, l); 1740} 1741 1742static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1743{ 1744 return tcg_out_fail_alignment(s, l); 1745} 1746#endif /* CONFIG_SOFTMMU */ 1747 1748/* 1749 * For softmmu, perform the TLB load and compare. 1750 * For useronly, perform any required alignment tests. 1751 * In both cases, return a TCGLabelQemuLdst structure if the slow path 1752 * is required and fill in @h with the host address for the fast path. 1753 */ 1754static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 1755 TCGReg addr_reg, MemOpIdx oi, 1756 bool is_ld) 1757{ 1758 TCGLabelQemuLdst *ldst = NULL; 1759 MemOp opc = get_memop(oi); 1760 unsigned a_bits = get_alignment_bits(opc); 1761 unsigned a_mask = (1u << a_bits) - 1; 1762 1763#ifdef CONFIG_SOFTMMU 1764 unsigned s_bits = opc & MO_SIZE; 1765 unsigned s_mask = (1 << s_bits) - 1; 1766 int mem_index = get_mmuidx(oi); 1767 int fast_off = TLB_MASK_TABLE_OFS(mem_index); 1768 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); 1769 int table_off = fast_off + offsetof(CPUTLBDescFast, table); 1770 int ofs, a_off; 1771 uint64_t tlb_mask; 1772 1773 ldst = new_ldst_label(s); 1774 ldst->is_ld = is_ld; 1775 ldst->oi = oi; 1776 ldst->addrlo_reg = addr_reg; 1777 1778 tcg_out_sh64(s, RSY_SRLG, TCG_TMP0, addr_reg, TCG_REG_NONE, 1779 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); 1780 1781 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); 1782 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 19)); 1783 tcg_out_insn(s, RXY, NG, TCG_TMP0, TCG_AREG0, TCG_REG_NONE, mask_off); 1784 tcg_out_insn(s, RXY, AG, TCG_TMP0, TCG_AREG0, TCG_REG_NONE, table_off); 1785 1786 /* 1787 * For aligned accesses, we check the first byte and include the alignment 1788 * bits within the address. For unaligned access, we check that we don't 1789 * cross pages using the address of the last byte of the access. 1790 */ 1791 a_off = (a_bits >= s_bits ? 0 : s_mask - a_mask); 1792 tlb_mask = (uint64_t)TARGET_PAGE_MASK | a_mask; 1793 if (a_off == 0) { 1794 tgen_andi_risbg(s, TCG_REG_R0, addr_reg, tlb_mask); 1795 } else { 1796 tcg_out_insn(s, RX, LA, TCG_REG_R0, addr_reg, TCG_REG_NONE, a_off); 1797 tgen_andi(s, TCG_TYPE_TL, TCG_REG_R0, tlb_mask); 1798 } 1799 1800 if (is_ld) { 1801 ofs = offsetof(CPUTLBEntry, addr_read); 1802 } else { 1803 ofs = offsetof(CPUTLBEntry, addr_write); 1804 } 1805 if (TARGET_LONG_BITS == 32) { 1806 tcg_out_insn(s, RX, C, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs); 1807 } else { 1808 tcg_out_insn(s, RXY, CG, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs); 1809 } 1810 1811 tcg_out16(s, RI_BRC | (S390_CC_NE << 4)); 1812 ldst->label_ptr[0] = s->code_ptr++; 1813 1814 h->index = TCG_TMP0; 1815 tcg_out_insn(s, RXY, LG, h->index, TCG_TMP0, TCG_REG_NONE, 1816 offsetof(CPUTLBEntry, addend)); 1817 1818 if (TARGET_LONG_BITS == 32) { 1819 tcg_out_insn(s, RRE, ALGFR, h->index, addr_reg); 1820 h->base = TCG_REG_NONE; 1821 } else { 1822 h->base = addr_reg; 1823 } 1824 h->disp = 0; 1825#else 1826 if (a_mask) { 1827 ldst = new_ldst_label(s); 1828 ldst->is_ld = is_ld; 1829 ldst->oi = oi; 1830 ldst->addrlo_reg = addr_reg; 1831 1832 /* We are expecting a_bits to max out at 7, much lower than TMLL. */ 1833 tcg_debug_assert(a_bits < 16); 1834 tcg_out_insn(s, RI, TMLL, addr_reg, a_mask); 1835 1836 tcg_out16(s, RI_BRC | (7 << 4)); /* CC in {1,2,3} */ 1837 ldst->label_ptr[0] = s->code_ptr++; 1838 } 1839 1840 h->base = addr_reg; 1841 if (TARGET_LONG_BITS == 32) { 1842 tcg_out_ext32u(s, TCG_TMP0, addr_reg); 1843 h->base = TCG_TMP0; 1844 } 1845 if (guest_base < 0x80000) { 1846 h->index = TCG_REG_NONE; 1847 h->disp = guest_base; 1848 } else { 1849 h->index = TCG_GUEST_BASE_REG; 1850 h->disp = 0; 1851 } 1852#endif 1853 1854 return ldst; 1855} 1856 1857static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_reg, 1858 MemOpIdx oi, TCGType data_type) 1859{ 1860 TCGLabelQemuLdst *ldst; 1861 HostAddress h; 1862 1863 ldst = prepare_host_addr(s, &h, addr_reg, oi, true); 1864 tcg_out_qemu_ld_direct(s, get_memop(oi), data_reg, h); 1865 1866 if (ldst) { 1867 ldst->type = data_type; 1868 ldst->datalo_reg = data_reg; 1869 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1870 } 1871} 1872 1873static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_reg, 1874 MemOpIdx oi, TCGType data_type) 1875{ 1876 TCGLabelQemuLdst *ldst; 1877 HostAddress h; 1878 1879 ldst = prepare_host_addr(s, &h, addr_reg, oi, false); 1880 tcg_out_qemu_st_direct(s, get_memop(oi), data_reg, h); 1881 1882 if (ldst) { 1883 ldst->type = data_type; 1884 ldst->datalo_reg = data_reg; 1885 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1886 } 1887} 1888 1889static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) 1890{ 1891 /* Reuse the zeroing that exists for goto_ptr. */ 1892 if (a0 == 0) { 1893 tgen_gotoi(s, S390_CC_ALWAYS, tcg_code_gen_epilogue); 1894 } else { 1895 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, a0); 1896 tgen_gotoi(s, S390_CC_ALWAYS, tb_ret_addr); 1897 } 1898} 1899 1900static void tcg_out_goto_tb(TCGContext *s, int which) 1901{ 1902 /* 1903 * Branch displacement must be aligned for atomic patching; 1904 * see if we need to add extra nop before branch 1905 */ 1906 if (!QEMU_PTR_IS_ALIGNED(s->code_ptr + 1, 4)) { 1907 tcg_out16(s, NOP); 1908 } 1909 tcg_out16(s, RIL_BRCL | (S390_CC_ALWAYS << 4)); 1910 set_jmp_insn_offset(s, which); 1911 s->code_ptr += 2; 1912 set_jmp_reset_offset(s, which); 1913} 1914 1915void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1916 uintptr_t jmp_rx, uintptr_t jmp_rw) 1917{ 1918 if (!HAVE_FACILITY(GEN_INST_EXT)) { 1919 return; 1920 } 1921 /* patch the branch destination */ 1922 uintptr_t addr = tb->jmp_target_addr[n]; 1923 intptr_t disp = addr - (jmp_rx - 2); 1924 qatomic_set((int32_t *)jmp_rw, disp / 2); 1925 /* no need to flush icache explicitly */ 1926} 1927 1928# define OP_32_64(x) \ 1929 case glue(glue(INDEX_op_,x),_i32): \ 1930 case glue(glue(INDEX_op_,x),_i64) 1931 1932static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, 1933 const TCGArg args[TCG_MAX_OP_ARGS], 1934 const int const_args[TCG_MAX_OP_ARGS]) 1935{ 1936 S390Opcode op, op2; 1937 TCGArg a0, a1, a2; 1938 1939 switch (opc) { 1940 case INDEX_op_goto_ptr: 1941 a0 = args[0]; 1942 tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, a0); 1943 break; 1944 1945 OP_32_64(ld8u): 1946 /* ??? LLC (RXY format) is only present with the extended-immediate 1947 facility, whereas LLGC is always present. */ 1948 tcg_out_mem(s, 0, RXY_LLGC, args[0], args[1], TCG_REG_NONE, args[2]); 1949 break; 1950 1951 OP_32_64(ld8s): 1952 /* ??? LB is no smaller than LGB, so no point to using it. */ 1953 tcg_out_mem(s, 0, RXY_LGB, args[0], args[1], TCG_REG_NONE, args[2]); 1954 break; 1955 1956 OP_32_64(ld16u): 1957 /* ??? LLH (RXY format) is only present with the extended-immediate 1958 facility, whereas LLGH is always present. */ 1959 tcg_out_mem(s, 0, RXY_LLGH, args[0], args[1], TCG_REG_NONE, args[2]); 1960 break; 1961 1962 case INDEX_op_ld16s_i32: 1963 tcg_out_mem(s, RX_LH, RXY_LHY, args[0], args[1], TCG_REG_NONE, args[2]); 1964 break; 1965 1966 case INDEX_op_ld_i32: 1967 tcg_out_ld(s, TCG_TYPE_I32, args[0], args[1], args[2]); 1968 break; 1969 1970 OP_32_64(st8): 1971 tcg_out_mem(s, RX_STC, RXY_STCY, args[0], args[1], 1972 TCG_REG_NONE, args[2]); 1973 break; 1974 1975 OP_32_64(st16): 1976 tcg_out_mem(s, RX_STH, RXY_STHY, args[0], args[1], 1977 TCG_REG_NONE, args[2]); 1978 break; 1979 1980 case INDEX_op_st_i32: 1981 tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]); 1982 break; 1983 1984 case INDEX_op_add_i32: 1985 a0 = args[0], a1 = args[1], a2 = (int32_t)args[2]; 1986 if (const_args[2]) { 1987 do_addi_32: 1988 if (a0 == a1) { 1989 if (a2 == (int16_t)a2) { 1990 tcg_out_insn(s, RI, AHI, a0, a2); 1991 break; 1992 } 1993 tcg_out_insn(s, RIL, AFI, a0, a2); 1994 break; 1995 } 1996 tcg_out_mem(s, RX_LA, RXY_LAY, a0, a1, TCG_REG_NONE, a2); 1997 } else if (a0 == a1) { 1998 tcg_out_insn(s, RR, AR, a0, a2); 1999 } else { 2000 tcg_out_insn(s, RX, LA, a0, a1, a2, 0); 2001 } 2002 break; 2003 case INDEX_op_sub_i32: 2004 a0 = args[0], a1 = args[1], a2 = (int32_t)args[2]; 2005 if (const_args[2]) { 2006 a2 = -a2; 2007 goto do_addi_32; 2008 } else if (a0 == a1) { 2009 tcg_out_insn(s, RR, SR, a0, a2); 2010 } else { 2011 tcg_out_insn(s, RRFa, SRK, a0, a1, a2); 2012 } 2013 break; 2014 2015 case INDEX_op_and_i32: 2016 a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; 2017 if (const_args[2]) { 2018 tcg_out_mov(s, TCG_TYPE_I32, a0, a1); 2019 tgen_andi(s, TCG_TYPE_I32, a0, a2); 2020 } else if (a0 == a1) { 2021 tcg_out_insn(s, RR, NR, a0, a2); 2022 } else { 2023 tcg_out_insn(s, RRFa, NRK, a0, a1, a2); 2024 } 2025 break; 2026 case INDEX_op_or_i32: 2027 a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; 2028 if (const_args[2]) { 2029 tcg_out_mov(s, TCG_TYPE_I32, a0, a1); 2030 tgen_ori(s, a0, a2); 2031 } else if (a0 == a1) { 2032 tcg_out_insn(s, RR, OR, a0, a2); 2033 } else { 2034 tcg_out_insn(s, RRFa, ORK, a0, a1, a2); 2035 } 2036 break; 2037 case INDEX_op_xor_i32: 2038 a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; 2039 if (const_args[2]) { 2040 tcg_out_mov(s, TCG_TYPE_I32, a0, a1); 2041 tcg_out_insn(s, RIL, XILF, a0, a2); 2042 } else if (a0 == a1) { 2043 tcg_out_insn(s, RR, XR, args[0], args[2]); 2044 } else { 2045 tcg_out_insn(s, RRFa, XRK, a0, a1, a2); 2046 } 2047 break; 2048 2049 case INDEX_op_andc_i32: 2050 a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; 2051 if (const_args[2]) { 2052 tcg_out_mov(s, TCG_TYPE_I32, a0, a1); 2053 tgen_andi(s, TCG_TYPE_I32, a0, (uint32_t)~a2); 2054 } else { 2055 tcg_out_insn(s, RRFa, NCRK, a0, a1, a2); 2056 } 2057 break; 2058 case INDEX_op_orc_i32: 2059 a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; 2060 if (const_args[2]) { 2061 tcg_out_mov(s, TCG_TYPE_I32, a0, a1); 2062 tgen_ori(s, a0, (uint32_t)~a2); 2063 } else { 2064 tcg_out_insn(s, RRFa, OCRK, a0, a1, a2); 2065 } 2066 break; 2067 case INDEX_op_eqv_i32: 2068 a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; 2069 if (const_args[2]) { 2070 tcg_out_mov(s, TCG_TYPE_I32, a0, a1); 2071 tcg_out_insn(s, RIL, XILF, a0, ~a2); 2072 } else { 2073 tcg_out_insn(s, RRFa, NXRK, a0, a1, a2); 2074 } 2075 break; 2076 case INDEX_op_nand_i32: 2077 tcg_out_insn(s, RRFa, NNRK, args[0], args[1], args[2]); 2078 break; 2079 case INDEX_op_nor_i32: 2080 tcg_out_insn(s, RRFa, NORK, args[0], args[1], args[2]); 2081 break; 2082 2083 case INDEX_op_neg_i32: 2084 tcg_out_insn(s, RR, LCR, args[0], args[1]); 2085 break; 2086 case INDEX_op_not_i32: 2087 tcg_out_insn(s, RRFa, NORK, args[0], args[1], args[1]); 2088 break; 2089 2090 case INDEX_op_mul_i32: 2091 a0 = args[0], a1 = args[1], a2 = (int32_t)args[2]; 2092 if (const_args[2]) { 2093 tcg_out_mov(s, TCG_TYPE_I32, a0, a1); 2094 if (a2 == (int16_t)a2) { 2095 tcg_out_insn(s, RI, MHI, a0, a2); 2096 } else { 2097 tcg_out_insn(s, RIL, MSFI, a0, a2); 2098 } 2099 } else if (a0 == a1) { 2100 tcg_out_insn(s, RRE, MSR, a0, a2); 2101 } else { 2102 tcg_out_insn(s, RRFa, MSRKC, a0, a1, a2); 2103 } 2104 break; 2105 2106 case INDEX_op_div2_i32: 2107 tcg_debug_assert(args[0] == args[2]); 2108 tcg_debug_assert(args[1] == args[3]); 2109 tcg_debug_assert((args[1] & 1) == 0); 2110 tcg_debug_assert(args[0] == args[1] + 1); 2111 tcg_out_insn(s, RR, DR, args[1], args[4]); 2112 break; 2113 case INDEX_op_divu2_i32: 2114 tcg_debug_assert(args[0] == args[2]); 2115 tcg_debug_assert(args[1] == args[3]); 2116 tcg_debug_assert((args[1] & 1) == 0); 2117 tcg_debug_assert(args[0] == args[1] + 1); 2118 tcg_out_insn(s, RRE, DLR, args[1], args[4]); 2119 break; 2120 2121 case INDEX_op_shl_i32: 2122 op = RS_SLL; 2123 op2 = RSY_SLLK; 2124 do_shift32: 2125 a0 = args[0], a1 = args[1], a2 = (int32_t)args[2]; 2126 if (a0 == a1) { 2127 if (const_args[2]) { 2128 tcg_out_sh32(s, op, a0, TCG_REG_NONE, a2); 2129 } else { 2130 tcg_out_sh32(s, op, a0, a2, 0); 2131 } 2132 } else { 2133 /* Using tcg_out_sh64 here for the format; it is a 32-bit shift. */ 2134 if (const_args[2]) { 2135 tcg_out_sh64(s, op2, a0, a1, TCG_REG_NONE, a2); 2136 } else { 2137 tcg_out_sh64(s, op2, a0, a1, a2, 0); 2138 } 2139 } 2140 break; 2141 case INDEX_op_shr_i32: 2142 op = RS_SRL; 2143 op2 = RSY_SRLK; 2144 goto do_shift32; 2145 case INDEX_op_sar_i32: 2146 op = RS_SRA; 2147 op2 = RSY_SRAK; 2148 goto do_shift32; 2149 2150 case INDEX_op_rotl_i32: 2151 /* ??? Using tcg_out_sh64 here for the format; it is a 32-bit rol. */ 2152 if (const_args[2]) { 2153 tcg_out_sh64(s, RSY_RLL, args[0], args[1], TCG_REG_NONE, args[2]); 2154 } else { 2155 tcg_out_sh64(s, RSY_RLL, args[0], args[1], args[2], 0); 2156 } 2157 break; 2158 case INDEX_op_rotr_i32: 2159 if (const_args[2]) { 2160 tcg_out_sh64(s, RSY_RLL, args[0], args[1], 2161 TCG_REG_NONE, (32 - args[2]) & 31); 2162 } else { 2163 tcg_out_insn(s, RR, LCR, TCG_TMP0, args[2]); 2164 tcg_out_sh64(s, RSY_RLL, args[0], args[1], TCG_TMP0, 0); 2165 } 2166 break; 2167 2168 case INDEX_op_bswap16_i32: 2169 a0 = args[0], a1 = args[1], a2 = args[2]; 2170 tcg_out_insn(s, RRE, LRVR, a0, a1); 2171 if (a2 & TCG_BSWAP_OS) { 2172 tcg_out_sh32(s, RS_SRA, a0, TCG_REG_NONE, 16); 2173 } else { 2174 tcg_out_sh32(s, RS_SRL, a0, TCG_REG_NONE, 16); 2175 } 2176 break; 2177 case INDEX_op_bswap16_i64: 2178 a0 = args[0], a1 = args[1], a2 = args[2]; 2179 tcg_out_insn(s, RRE, LRVGR, a0, a1); 2180 if (a2 & TCG_BSWAP_OS) { 2181 tcg_out_sh64(s, RSY_SRAG, a0, a0, TCG_REG_NONE, 48); 2182 } else { 2183 tcg_out_sh64(s, RSY_SRLG, a0, a0, TCG_REG_NONE, 48); 2184 } 2185 break; 2186 2187 case INDEX_op_bswap32_i32: 2188 tcg_out_insn(s, RRE, LRVR, args[0], args[1]); 2189 break; 2190 case INDEX_op_bswap32_i64: 2191 a0 = args[0], a1 = args[1], a2 = args[2]; 2192 tcg_out_insn(s, RRE, LRVR, a0, a1); 2193 if (a2 & TCG_BSWAP_OS) { 2194 tcg_out_ext32s(s, a0, a0); 2195 } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 2196 tcg_out_ext32u(s, a0, a0); 2197 } 2198 break; 2199 2200 case INDEX_op_add2_i32: 2201 if (const_args[4]) { 2202 tcg_out_insn(s, RIL, ALFI, args[0], args[4]); 2203 } else { 2204 tcg_out_insn(s, RR, ALR, args[0], args[4]); 2205 } 2206 tcg_out_insn(s, RRE, ALCR, args[1], args[5]); 2207 break; 2208 case INDEX_op_sub2_i32: 2209 if (const_args[4]) { 2210 tcg_out_insn(s, RIL, SLFI, args[0], args[4]); 2211 } else { 2212 tcg_out_insn(s, RR, SLR, args[0], args[4]); 2213 } 2214 tcg_out_insn(s, RRE, SLBR, args[1], args[5]); 2215 break; 2216 2217 case INDEX_op_br: 2218 tgen_branch(s, S390_CC_ALWAYS, arg_label(args[0])); 2219 break; 2220 2221 case INDEX_op_brcond_i32: 2222 tgen_brcond(s, TCG_TYPE_I32, args[2], args[0], 2223 args[1], const_args[1], arg_label(args[3])); 2224 break; 2225 case INDEX_op_setcond_i32: 2226 tgen_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], 2227 args[2], const_args[2]); 2228 break; 2229 case INDEX_op_movcond_i32: 2230 tgen_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], 2231 args[2], const_args[2], args[3], const_args[3], args[4]); 2232 break; 2233 2234 case INDEX_op_qemu_ld_i32: 2235 tcg_out_qemu_ld(s, args[0], args[1], args[2], TCG_TYPE_I32); 2236 break; 2237 case INDEX_op_qemu_ld_i64: 2238 tcg_out_qemu_ld(s, args[0], args[1], args[2], TCG_TYPE_I64); 2239 break; 2240 case INDEX_op_qemu_st_i32: 2241 tcg_out_qemu_st(s, args[0], args[1], args[2], TCG_TYPE_I32); 2242 break; 2243 case INDEX_op_qemu_st_i64: 2244 tcg_out_qemu_st(s, args[0], args[1], args[2], TCG_TYPE_I64); 2245 break; 2246 2247 case INDEX_op_ld16s_i64: 2248 tcg_out_mem(s, 0, RXY_LGH, args[0], args[1], TCG_REG_NONE, args[2]); 2249 break; 2250 case INDEX_op_ld32u_i64: 2251 tcg_out_mem(s, 0, RXY_LLGF, args[0], args[1], TCG_REG_NONE, args[2]); 2252 break; 2253 case INDEX_op_ld32s_i64: 2254 tcg_out_mem(s, 0, RXY_LGF, args[0], args[1], TCG_REG_NONE, args[2]); 2255 break; 2256 case INDEX_op_ld_i64: 2257 tcg_out_ld(s, TCG_TYPE_I64, args[0], args[1], args[2]); 2258 break; 2259 2260 case INDEX_op_st32_i64: 2261 tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]); 2262 break; 2263 case INDEX_op_st_i64: 2264 tcg_out_st(s, TCG_TYPE_I64, args[0], args[1], args[2]); 2265 break; 2266 2267 case INDEX_op_add_i64: 2268 a0 = args[0], a1 = args[1], a2 = args[2]; 2269 if (const_args[2]) { 2270 do_addi_64: 2271 if (a0 == a1) { 2272 if (a2 == (int16_t)a2) { 2273 tcg_out_insn(s, RI, AGHI, a0, a2); 2274 break; 2275 } 2276 if (a2 == (int32_t)a2) { 2277 tcg_out_insn(s, RIL, AGFI, a0, a2); 2278 break; 2279 } 2280 if (a2 == (uint32_t)a2) { 2281 tcg_out_insn(s, RIL, ALGFI, a0, a2); 2282 break; 2283 } 2284 if (-a2 == (uint32_t)-a2) { 2285 tcg_out_insn(s, RIL, SLGFI, a0, -a2); 2286 break; 2287 } 2288 } 2289 tcg_out_mem(s, RX_LA, RXY_LAY, a0, a1, TCG_REG_NONE, a2); 2290 } else if (a0 == a1) { 2291 tcg_out_insn(s, RRE, AGR, a0, a2); 2292 } else { 2293 tcg_out_insn(s, RX, LA, a0, a1, a2, 0); 2294 } 2295 break; 2296 case INDEX_op_sub_i64: 2297 a0 = args[0], a1 = args[1], a2 = args[2]; 2298 if (const_args[2]) { 2299 a2 = -a2; 2300 goto do_addi_64; 2301 } else { 2302 tcg_out_insn(s, RRFa, SGRK, a0, a1, a2); 2303 } 2304 break; 2305 2306 case INDEX_op_and_i64: 2307 a0 = args[0], a1 = args[1], a2 = args[2]; 2308 if (const_args[2]) { 2309 tcg_out_mov(s, TCG_TYPE_I64, a0, a1); 2310 tgen_andi(s, TCG_TYPE_I64, args[0], args[2]); 2311 } else { 2312 tcg_out_insn(s, RRFa, NGRK, a0, a1, a2); 2313 } 2314 break; 2315 case INDEX_op_or_i64: 2316 a0 = args[0], a1 = args[1], a2 = args[2]; 2317 if (const_args[2]) { 2318 tcg_out_mov(s, TCG_TYPE_I64, a0, a1); 2319 tgen_ori(s, a0, a2); 2320 } else { 2321 tcg_out_insn(s, RRFa, OGRK, a0, a1, a2); 2322 } 2323 break; 2324 case INDEX_op_xor_i64: 2325 a0 = args[0], a1 = args[1], a2 = args[2]; 2326 if (const_args[2]) { 2327 tcg_out_mov(s, TCG_TYPE_I64, a0, a1); 2328 tgen_xori(s, a0, a2); 2329 } else { 2330 tcg_out_insn(s, RRFa, XGRK, a0, a1, a2); 2331 } 2332 break; 2333 2334 case INDEX_op_andc_i64: 2335 a0 = args[0], a1 = args[1], a2 = args[2]; 2336 if (const_args[2]) { 2337 tcg_out_mov(s, TCG_TYPE_I64, a0, a1); 2338 tgen_andi(s, TCG_TYPE_I64, a0, ~a2); 2339 } else { 2340 tcg_out_insn(s, RRFa, NCGRK, a0, a1, a2); 2341 } 2342 break; 2343 case INDEX_op_orc_i64: 2344 a0 = args[0], a1 = args[1], a2 = args[2]; 2345 if (const_args[2]) { 2346 tcg_out_mov(s, TCG_TYPE_I64, a0, a1); 2347 tgen_ori(s, a0, ~a2); 2348 } else { 2349 tcg_out_insn(s, RRFa, OCGRK, a0, a1, a2); 2350 } 2351 break; 2352 case INDEX_op_eqv_i64: 2353 a0 = args[0], a1 = args[1], a2 = args[2]; 2354 if (const_args[2]) { 2355 tcg_out_mov(s, TCG_TYPE_I64, a0, a1); 2356 tgen_xori(s, a0, ~a2); 2357 } else { 2358 tcg_out_insn(s, RRFa, NXGRK, a0, a1, a2); 2359 } 2360 break; 2361 case INDEX_op_nand_i64: 2362 tcg_out_insn(s, RRFa, NNGRK, args[0], args[1], args[2]); 2363 break; 2364 case INDEX_op_nor_i64: 2365 tcg_out_insn(s, RRFa, NOGRK, args[0], args[1], args[2]); 2366 break; 2367 2368 case INDEX_op_neg_i64: 2369 tcg_out_insn(s, RRE, LCGR, args[0], args[1]); 2370 break; 2371 case INDEX_op_not_i64: 2372 tcg_out_insn(s, RRFa, NOGRK, args[0], args[1], args[1]); 2373 break; 2374 case INDEX_op_bswap64_i64: 2375 tcg_out_insn(s, RRE, LRVGR, args[0], args[1]); 2376 break; 2377 2378 case INDEX_op_mul_i64: 2379 a0 = args[0], a1 = args[1], a2 = args[2]; 2380 if (const_args[2]) { 2381 tcg_out_mov(s, TCG_TYPE_I64, a0, a1); 2382 if (a2 == (int16_t)a2) { 2383 tcg_out_insn(s, RI, MGHI, a0, a2); 2384 } else { 2385 tcg_out_insn(s, RIL, MSGFI, a0, a2); 2386 } 2387 } else if (a0 == a1) { 2388 tcg_out_insn(s, RRE, MSGR, a0, a2); 2389 } else { 2390 tcg_out_insn(s, RRFa, MSGRKC, a0, a1, a2); 2391 } 2392 break; 2393 2394 case INDEX_op_div2_i64: 2395 /* 2396 * ??? We get an unnecessary sign-extension of the dividend 2397 * into op0 with this definition, but as we do in fact always 2398 * produce both quotient and remainder using INDEX_op_div_i64 2399 * instead requires jumping through even more hoops. 2400 */ 2401 tcg_debug_assert(args[0] == args[2]); 2402 tcg_debug_assert(args[1] == args[3]); 2403 tcg_debug_assert((args[1] & 1) == 0); 2404 tcg_debug_assert(args[0] == args[1] + 1); 2405 tcg_out_insn(s, RRE, DSGR, args[1], args[4]); 2406 break; 2407 case INDEX_op_divu2_i64: 2408 tcg_debug_assert(args[0] == args[2]); 2409 tcg_debug_assert(args[1] == args[3]); 2410 tcg_debug_assert((args[1] & 1) == 0); 2411 tcg_debug_assert(args[0] == args[1] + 1); 2412 tcg_out_insn(s, RRE, DLGR, args[1], args[4]); 2413 break; 2414 case INDEX_op_mulu2_i64: 2415 tcg_debug_assert(args[0] == args[2]); 2416 tcg_debug_assert((args[1] & 1) == 0); 2417 tcg_debug_assert(args[0] == args[1] + 1); 2418 tcg_out_insn(s, RRE, MLGR, args[1], args[3]); 2419 break; 2420 case INDEX_op_muls2_i64: 2421 tcg_debug_assert((args[1] & 1) == 0); 2422 tcg_debug_assert(args[0] == args[1] + 1); 2423 tcg_out_insn(s, RRFa, MGRK, args[1], args[2], args[3]); 2424 break; 2425 2426 case INDEX_op_shl_i64: 2427 op = RSY_SLLG; 2428 do_shift64: 2429 if (const_args[2]) { 2430 tcg_out_sh64(s, op, args[0], args[1], TCG_REG_NONE, args[2]); 2431 } else { 2432 tcg_out_sh64(s, op, args[0], args[1], args[2], 0); 2433 } 2434 break; 2435 case INDEX_op_shr_i64: 2436 op = RSY_SRLG; 2437 goto do_shift64; 2438 case INDEX_op_sar_i64: 2439 op = RSY_SRAG; 2440 goto do_shift64; 2441 2442 case INDEX_op_rotl_i64: 2443 if (const_args[2]) { 2444 tcg_out_sh64(s, RSY_RLLG, args[0], args[1], 2445 TCG_REG_NONE, args[2]); 2446 } else { 2447 tcg_out_sh64(s, RSY_RLLG, args[0], args[1], args[2], 0); 2448 } 2449 break; 2450 case INDEX_op_rotr_i64: 2451 if (const_args[2]) { 2452 tcg_out_sh64(s, RSY_RLLG, args[0], args[1], 2453 TCG_REG_NONE, (64 - args[2]) & 63); 2454 } else { 2455 /* We can use the smaller 32-bit negate because only the 2456 low 6 bits are examined for the rotate. */ 2457 tcg_out_insn(s, RR, LCR, TCG_TMP0, args[2]); 2458 tcg_out_sh64(s, RSY_RLLG, args[0], args[1], TCG_TMP0, 0); 2459 } 2460 break; 2461 2462 case INDEX_op_add2_i64: 2463 if (const_args[4]) { 2464 if ((int64_t)args[4] >= 0) { 2465 tcg_out_insn(s, RIL, ALGFI, args[0], args[4]); 2466 } else { 2467 tcg_out_insn(s, RIL, SLGFI, args[0], -args[4]); 2468 } 2469 } else { 2470 tcg_out_insn(s, RRE, ALGR, args[0], args[4]); 2471 } 2472 tcg_out_insn(s, RRE, ALCGR, args[1], args[5]); 2473 break; 2474 case INDEX_op_sub2_i64: 2475 if (const_args[4]) { 2476 if ((int64_t)args[4] >= 0) { 2477 tcg_out_insn(s, RIL, SLGFI, args[0], args[4]); 2478 } else { 2479 tcg_out_insn(s, RIL, ALGFI, args[0], -args[4]); 2480 } 2481 } else { 2482 tcg_out_insn(s, RRE, SLGR, args[0], args[4]); 2483 } 2484 tcg_out_insn(s, RRE, SLBGR, args[1], args[5]); 2485 break; 2486 2487 case INDEX_op_brcond_i64: 2488 tgen_brcond(s, TCG_TYPE_I64, args[2], args[0], 2489 args[1], const_args[1], arg_label(args[3])); 2490 break; 2491 case INDEX_op_setcond_i64: 2492 tgen_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], 2493 args[2], const_args[2]); 2494 break; 2495 case INDEX_op_movcond_i64: 2496 tgen_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], 2497 args[2], const_args[2], args[3], const_args[3], args[4]); 2498 break; 2499 2500 OP_32_64(deposit): 2501 a0 = args[0], a1 = args[1], a2 = args[2]; 2502 if (const_args[1]) { 2503 tgen_deposit(s, a0, a2, args[3], args[4], 1); 2504 } else { 2505 /* Since we can't support "0Z" as a constraint, we allow a1 in 2506 any register. Fix things up as if a matching constraint. */ 2507 if (a0 != a1) { 2508 TCGType type = (opc == INDEX_op_deposit_i64); 2509 if (a0 == a2) { 2510 tcg_out_mov(s, type, TCG_TMP0, a2); 2511 a2 = TCG_TMP0; 2512 } 2513 tcg_out_mov(s, type, a0, a1); 2514 } 2515 tgen_deposit(s, a0, a2, args[3], args[4], 0); 2516 } 2517 break; 2518 2519 OP_32_64(extract): 2520 tgen_extract(s, args[0], args[1], args[2], args[3]); 2521 break; 2522 2523 case INDEX_op_clz_i64: 2524 tgen_clz(s, args[0], args[1], args[2], const_args[2]); 2525 break; 2526 2527 case INDEX_op_ctpop_i32: 2528 tgen_ctpop(s, TCG_TYPE_I32, args[0], args[1]); 2529 break; 2530 case INDEX_op_ctpop_i64: 2531 tgen_ctpop(s, TCG_TYPE_I64, args[0], args[1]); 2532 break; 2533 2534 case INDEX_op_mb: 2535 /* The host memory model is quite strong, we simply need to 2536 serialize the instruction stream. */ 2537 if (args[0] & TCG_MO_ST_LD) { 2538 /* fast-bcr-serialization facility (45) is present */ 2539 tcg_out_insn(s, RR, BCR, 14, 0); 2540 } 2541 break; 2542 2543 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ 2544 case INDEX_op_mov_i64: 2545 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2546 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 2547 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 2548 case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ 2549 case INDEX_op_ext8s_i64: 2550 case INDEX_op_ext8u_i32: 2551 case INDEX_op_ext8u_i64: 2552 case INDEX_op_ext16s_i32: 2553 case INDEX_op_ext16s_i64: 2554 case INDEX_op_ext16u_i32: 2555 case INDEX_op_ext16u_i64: 2556 case INDEX_op_ext32s_i64: 2557 case INDEX_op_ext32u_i64: 2558 case INDEX_op_ext_i32_i64: 2559 case INDEX_op_extu_i32_i64: 2560 case INDEX_op_extrl_i64_i32: 2561 default: 2562 g_assert_not_reached(); 2563 } 2564} 2565 2566static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 2567 TCGReg dst, TCGReg src) 2568{ 2569 if (is_general_reg(src)) { 2570 /* Replicate general register into two MO_64. */ 2571 tcg_out_insn(s, VRRf, VLVGP, dst, src, src); 2572 if (vece == MO_64) { 2573 return true; 2574 } 2575 src = dst; 2576 } 2577 2578 /* 2579 * Recall that the "standard" integer, within a vector, is the 2580 * rightmost element of the leftmost doubleword, a-la VLLEZ. 2581 */ 2582 tcg_out_insn(s, VRIc, VREP, dst, (8 >> vece) - 1, src, vece); 2583 return true; 2584} 2585 2586static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 2587 TCGReg dst, TCGReg base, intptr_t offset) 2588{ 2589 tcg_out_vrx_mem(s, VRX_VLREP, dst, base, TCG_REG_NONE, offset, vece); 2590 return true; 2591} 2592 2593static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 2594 TCGReg dst, int64_t val) 2595{ 2596 int i, mask, msb, lsb; 2597 2598 /* Look for int16_t elements. */ 2599 if (vece <= MO_16 || 2600 (vece == MO_32 ? (int32_t)val : val) == (int16_t)val) { 2601 tcg_out_insn(s, VRIa, VREPI, dst, val, vece); 2602 return; 2603 } 2604 2605 /* Look for bit masks. */ 2606 if (vece == MO_32) { 2607 if (risbg_mask((int32_t)val)) { 2608 /* Handle wraparound by swapping msb and lsb. */ 2609 if ((val & 0x80000001u) == 0x80000001u) { 2610 msb = 32 - ctz32(~val); 2611 lsb = clz32(~val) - 1; 2612 } else { 2613 msb = clz32(val); 2614 lsb = 31 - ctz32(val); 2615 } 2616 tcg_out_insn(s, VRIb, VGM, dst, msb, lsb, MO_32); 2617 return; 2618 } 2619 } else { 2620 if (risbg_mask(val)) { 2621 /* Handle wraparound by swapping msb and lsb. */ 2622 if ((val & 0x8000000000000001ull) == 0x8000000000000001ull) { 2623 /* Handle wraparound by swapping msb and lsb. */ 2624 msb = 64 - ctz64(~val); 2625 lsb = clz64(~val) - 1; 2626 } else { 2627 msb = clz64(val); 2628 lsb = 63 - ctz64(val); 2629 } 2630 tcg_out_insn(s, VRIb, VGM, dst, msb, lsb, MO_64); 2631 return; 2632 } 2633 } 2634 2635 /* Look for all bytes 0x00 or 0xff. */ 2636 for (i = mask = 0; i < 8; i++) { 2637 uint8_t byte = val >> (i * 8); 2638 if (byte == 0xff) { 2639 mask |= 1 << i; 2640 } else if (byte != 0) { 2641 break; 2642 } 2643 } 2644 if (i == 8) { 2645 tcg_out_insn(s, VRIa, VGBM, dst, mask * 0x0101, 0); 2646 return; 2647 } 2648 2649 /* Otherwise, stuff it in the constant pool. */ 2650 tcg_out_insn(s, RIL, LARL, TCG_TMP0, 0); 2651 new_pool_label(s, val, R_390_PC32DBL, s->code_ptr - 2, 2); 2652 tcg_out_insn(s, VRX, VLREP, dst, TCG_TMP0, TCG_REG_NONE, 0, MO_64); 2653} 2654 2655static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 2656 unsigned vecl, unsigned vece, 2657 const TCGArg args[TCG_MAX_OP_ARGS], 2658 const int const_args[TCG_MAX_OP_ARGS]) 2659{ 2660 TCGType type = vecl + TCG_TYPE_V64; 2661 TCGArg a0 = args[0], a1 = args[1], a2 = args[2]; 2662 2663 switch (opc) { 2664 case INDEX_op_ld_vec: 2665 tcg_out_ld(s, type, a0, a1, a2); 2666 break; 2667 case INDEX_op_st_vec: 2668 tcg_out_st(s, type, a0, a1, a2); 2669 break; 2670 case INDEX_op_dupm_vec: 2671 tcg_out_dupm_vec(s, type, vece, a0, a1, a2); 2672 break; 2673 2674 case INDEX_op_abs_vec: 2675 tcg_out_insn(s, VRRa, VLP, a0, a1, vece); 2676 break; 2677 case INDEX_op_neg_vec: 2678 tcg_out_insn(s, VRRa, VLC, a0, a1, vece); 2679 break; 2680 case INDEX_op_not_vec: 2681 tcg_out_insn(s, VRRc, VNO, a0, a1, a1, 0); 2682 break; 2683 2684 case INDEX_op_add_vec: 2685 tcg_out_insn(s, VRRc, VA, a0, a1, a2, vece); 2686 break; 2687 case INDEX_op_sub_vec: 2688 tcg_out_insn(s, VRRc, VS, a0, a1, a2, vece); 2689 break; 2690 case INDEX_op_and_vec: 2691 tcg_out_insn(s, VRRc, VN, a0, a1, a2, 0); 2692 break; 2693 case INDEX_op_andc_vec: 2694 tcg_out_insn(s, VRRc, VNC, a0, a1, a2, 0); 2695 break; 2696 case INDEX_op_mul_vec: 2697 tcg_out_insn(s, VRRc, VML, a0, a1, a2, vece); 2698 break; 2699 case INDEX_op_or_vec: 2700 tcg_out_insn(s, VRRc, VO, a0, a1, a2, 0); 2701 break; 2702 case INDEX_op_orc_vec: 2703 tcg_out_insn(s, VRRc, VOC, a0, a1, a2, 0); 2704 break; 2705 case INDEX_op_xor_vec: 2706 tcg_out_insn(s, VRRc, VX, a0, a1, a2, 0); 2707 break; 2708 case INDEX_op_nand_vec: 2709 tcg_out_insn(s, VRRc, VNN, a0, a1, a2, 0); 2710 break; 2711 case INDEX_op_nor_vec: 2712 tcg_out_insn(s, VRRc, VNO, a0, a1, a2, 0); 2713 break; 2714 case INDEX_op_eqv_vec: 2715 tcg_out_insn(s, VRRc, VNX, a0, a1, a2, 0); 2716 break; 2717 2718 case INDEX_op_shli_vec: 2719 tcg_out_insn(s, VRSa, VESL, a0, a2, TCG_REG_NONE, a1, vece); 2720 break; 2721 case INDEX_op_shri_vec: 2722 tcg_out_insn(s, VRSa, VESRL, a0, a2, TCG_REG_NONE, a1, vece); 2723 break; 2724 case INDEX_op_sari_vec: 2725 tcg_out_insn(s, VRSa, VESRA, a0, a2, TCG_REG_NONE, a1, vece); 2726 break; 2727 case INDEX_op_rotli_vec: 2728 tcg_out_insn(s, VRSa, VERLL, a0, a2, TCG_REG_NONE, a1, vece); 2729 break; 2730 case INDEX_op_shls_vec: 2731 tcg_out_insn(s, VRSa, VESL, a0, 0, a2, a1, vece); 2732 break; 2733 case INDEX_op_shrs_vec: 2734 tcg_out_insn(s, VRSa, VESRL, a0, 0, a2, a1, vece); 2735 break; 2736 case INDEX_op_sars_vec: 2737 tcg_out_insn(s, VRSa, VESRA, a0, 0, a2, a1, vece); 2738 break; 2739 case INDEX_op_rotls_vec: 2740 tcg_out_insn(s, VRSa, VERLL, a0, 0, a2, a1, vece); 2741 break; 2742 case INDEX_op_shlv_vec: 2743 tcg_out_insn(s, VRRc, VESLV, a0, a1, a2, vece); 2744 break; 2745 case INDEX_op_shrv_vec: 2746 tcg_out_insn(s, VRRc, VESRLV, a0, a1, a2, vece); 2747 break; 2748 case INDEX_op_sarv_vec: 2749 tcg_out_insn(s, VRRc, VESRAV, a0, a1, a2, vece); 2750 break; 2751 case INDEX_op_rotlv_vec: 2752 tcg_out_insn(s, VRRc, VERLLV, a0, a1, a2, vece); 2753 break; 2754 2755 case INDEX_op_smin_vec: 2756 tcg_out_insn(s, VRRc, VMN, a0, a1, a2, vece); 2757 break; 2758 case INDEX_op_smax_vec: 2759 tcg_out_insn(s, VRRc, VMX, a0, a1, a2, vece); 2760 break; 2761 case INDEX_op_umin_vec: 2762 tcg_out_insn(s, VRRc, VMNL, a0, a1, a2, vece); 2763 break; 2764 case INDEX_op_umax_vec: 2765 tcg_out_insn(s, VRRc, VMXL, a0, a1, a2, vece); 2766 break; 2767 2768 case INDEX_op_bitsel_vec: 2769 tcg_out_insn(s, VRRe, VSEL, a0, a2, args[3], a1); 2770 break; 2771 2772 case INDEX_op_cmp_vec: 2773 switch ((TCGCond)args[3]) { 2774 case TCG_COND_EQ: 2775 tcg_out_insn(s, VRRc, VCEQ, a0, a1, a2, vece); 2776 break; 2777 case TCG_COND_GT: 2778 tcg_out_insn(s, VRRc, VCH, a0, a1, a2, vece); 2779 break; 2780 case TCG_COND_GTU: 2781 tcg_out_insn(s, VRRc, VCHL, a0, a1, a2, vece); 2782 break; 2783 default: 2784 g_assert_not_reached(); 2785 } 2786 break; 2787 2788 case INDEX_op_s390_vuph_vec: 2789 tcg_out_insn(s, VRRa, VUPH, a0, a1, vece); 2790 break; 2791 case INDEX_op_s390_vupl_vec: 2792 tcg_out_insn(s, VRRa, VUPL, a0, a1, vece); 2793 break; 2794 case INDEX_op_s390_vpks_vec: 2795 tcg_out_insn(s, VRRc, VPKS, a0, a1, a2, vece); 2796 break; 2797 2798 case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ 2799 case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ 2800 default: 2801 g_assert_not_reached(); 2802 } 2803} 2804 2805int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) 2806{ 2807 switch (opc) { 2808 case INDEX_op_abs_vec: 2809 case INDEX_op_add_vec: 2810 case INDEX_op_and_vec: 2811 case INDEX_op_andc_vec: 2812 case INDEX_op_bitsel_vec: 2813 case INDEX_op_eqv_vec: 2814 case INDEX_op_nand_vec: 2815 case INDEX_op_neg_vec: 2816 case INDEX_op_nor_vec: 2817 case INDEX_op_not_vec: 2818 case INDEX_op_or_vec: 2819 case INDEX_op_orc_vec: 2820 case INDEX_op_rotli_vec: 2821 case INDEX_op_rotls_vec: 2822 case INDEX_op_rotlv_vec: 2823 case INDEX_op_sari_vec: 2824 case INDEX_op_sars_vec: 2825 case INDEX_op_sarv_vec: 2826 case INDEX_op_shli_vec: 2827 case INDEX_op_shls_vec: 2828 case INDEX_op_shlv_vec: 2829 case INDEX_op_shri_vec: 2830 case INDEX_op_shrs_vec: 2831 case INDEX_op_shrv_vec: 2832 case INDEX_op_smax_vec: 2833 case INDEX_op_smin_vec: 2834 case INDEX_op_sub_vec: 2835 case INDEX_op_umax_vec: 2836 case INDEX_op_umin_vec: 2837 case INDEX_op_xor_vec: 2838 return 1; 2839 case INDEX_op_cmp_vec: 2840 case INDEX_op_cmpsel_vec: 2841 case INDEX_op_rotrv_vec: 2842 return -1; 2843 case INDEX_op_mul_vec: 2844 return vece < MO_64; 2845 case INDEX_op_ssadd_vec: 2846 case INDEX_op_sssub_vec: 2847 return vece < MO_64 ? -1 : 0; 2848 default: 2849 return 0; 2850 } 2851} 2852 2853static bool expand_vec_cmp_noinv(TCGType type, unsigned vece, TCGv_vec v0, 2854 TCGv_vec v1, TCGv_vec v2, TCGCond cond) 2855{ 2856 bool need_swap = false, need_inv = false; 2857 2858 switch (cond) { 2859 case TCG_COND_EQ: 2860 case TCG_COND_GT: 2861 case TCG_COND_GTU: 2862 break; 2863 case TCG_COND_NE: 2864 case TCG_COND_LE: 2865 case TCG_COND_LEU: 2866 need_inv = true; 2867 break; 2868 case TCG_COND_LT: 2869 case TCG_COND_LTU: 2870 need_swap = true; 2871 break; 2872 case TCG_COND_GE: 2873 case TCG_COND_GEU: 2874 need_swap = need_inv = true; 2875 break; 2876 default: 2877 g_assert_not_reached(); 2878 } 2879 2880 if (need_inv) { 2881 cond = tcg_invert_cond(cond); 2882 } 2883 if (need_swap) { 2884 TCGv_vec t1; 2885 t1 = v1, v1 = v2, v2 = t1; 2886 cond = tcg_swap_cond(cond); 2887 } 2888 2889 vec_gen_4(INDEX_op_cmp_vec, type, vece, tcgv_vec_arg(v0), 2890 tcgv_vec_arg(v1), tcgv_vec_arg(v2), cond); 2891 2892 return need_inv; 2893} 2894 2895static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0, 2896 TCGv_vec v1, TCGv_vec v2, TCGCond cond) 2897{ 2898 if (expand_vec_cmp_noinv(type, vece, v0, v1, v2, cond)) { 2899 tcg_gen_not_vec(vece, v0, v0); 2900 } 2901} 2902 2903static void expand_vec_cmpsel(TCGType type, unsigned vece, TCGv_vec v0, 2904 TCGv_vec c1, TCGv_vec c2, 2905 TCGv_vec v3, TCGv_vec v4, TCGCond cond) 2906{ 2907 TCGv_vec t = tcg_temp_new_vec(type); 2908 2909 if (expand_vec_cmp_noinv(type, vece, t, c1, c2, cond)) { 2910 /* Invert the sense of the compare by swapping arguments. */ 2911 tcg_gen_bitsel_vec(vece, v0, t, v4, v3); 2912 } else { 2913 tcg_gen_bitsel_vec(vece, v0, t, v3, v4); 2914 } 2915 tcg_temp_free_vec(t); 2916} 2917 2918static void expand_vec_sat(TCGType type, unsigned vece, TCGv_vec v0, 2919 TCGv_vec v1, TCGv_vec v2, TCGOpcode add_sub_opc) 2920{ 2921 TCGv_vec h1 = tcg_temp_new_vec(type); 2922 TCGv_vec h2 = tcg_temp_new_vec(type); 2923 TCGv_vec l1 = tcg_temp_new_vec(type); 2924 TCGv_vec l2 = tcg_temp_new_vec(type); 2925 2926 tcg_debug_assert (vece < MO_64); 2927 2928 /* Unpack with sign-extension. */ 2929 vec_gen_2(INDEX_op_s390_vuph_vec, type, vece, 2930 tcgv_vec_arg(h1), tcgv_vec_arg(v1)); 2931 vec_gen_2(INDEX_op_s390_vuph_vec, type, vece, 2932 tcgv_vec_arg(h2), tcgv_vec_arg(v2)); 2933 2934 vec_gen_2(INDEX_op_s390_vupl_vec, type, vece, 2935 tcgv_vec_arg(l1), tcgv_vec_arg(v1)); 2936 vec_gen_2(INDEX_op_s390_vupl_vec, type, vece, 2937 tcgv_vec_arg(l2), tcgv_vec_arg(v2)); 2938 2939 /* Arithmetic on a wider element size. */ 2940 vec_gen_3(add_sub_opc, type, vece + 1, tcgv_vec_arg(h1), 2941 tcgv_vec_arg(h1), tcgv_vec_arg(h2)); 2942 vec_gen_3(add_sub_opc, type, vece + 1, tcgv_vec_arg(l1), 2943 tcgv_vec_arg(l1), tcgv_vec_arg(l2)); 2944 2945 /* Pack with saturation. */ 2946 vec_gen_3(INDEX_op_s390_vpks_vec, type, vece + 1, 2947 tcgv_vec_arg(v0), tcgv_vec_arg(h1), tcgv_vec_arg(l1)); 2948 2949 tcg_temp_free_vec(h1); 2950 tcg_temp_free_vec(h2); 2951 tcg_temp_free_vec(l1); 2952 tcg_temp_free_vec(l2); 2953} 2954 2955void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, 2956 TCGArg a0, ...) 2957{ 2958 va_list va; 2959 TCGv_vec v0, v1, v2, v3, v4, t0; 2960 2961 va_start(va, a0); 2962 v0 = temp_tcgv_vec(arg_temp(a0)); 2963 v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); 2964 v2 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); 2965 2966 switch (opc) { 2967 case INDEX_op_cmp_vec: 2968 expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg)); 2969 break; 2970 2971 case INDEX_op_cmpsel_vec: 2972 v3 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); 2973 v4 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); 2974 expand_vec_cmpsel(type, vece, v0, v1, v2, v3, v4, va_arg(va, TCGArg)); 2975 break; 2976 2977 case INDEX_op_rotrv_vec: 2978 t0 = tcg_temp_new_vec(type); 2979 tcg_gen_neg_vec(vece, t0, v2); 2980 tcg_gen_rotlv_vec(vece, v0, v1, t0); 2981 tcg_temp_free_vec(t0); 2982 break; 2983 2984 case INDEX_op_ssadd_vec: 2985 expand_vec_sat(type, vece, v0, v1, v2, INDEX_op_add_vec); 2986 break; 2987 case INDEX_op_sssub_vec: 2988 expand_vec_sat(type, vece, v0, v1, v2, INDEX_op_sub_vec); 2989 break; 2990 2991 default: 2992 g_assert_not_reached(); 2993 } 2994 va_end(va); 2995} 2996 2997static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) 2998{ 2999 switch (op) { 3000 case INDEX_op_goto_ptr: 3001 return C_O0_I1(r); 3002 3003 case INDEX_op_ld8u_i32: 3004 case INDEX_op_ld8u_i64: 3005 case INDEX_op_ld8s_i32: 3006 case INDEX_op_ld8s_i64: 3007 case INDEX_op_ld16u_i32: 3008 case INDEX_op_ld16u_i64: 3009 case INDEX_op_ld16s_i32: 3010 case INDEX_op_ld16s_i64: 3011 case INDEX_op_ld_i32: 3012 case INDEX_op_ld32u_i64: 3013 case INDEX_op_ld32s_i64: 3014 case INDEX_op_ld_i64: 3015 return C_O1_I1(r, r); 3016 3017 case INDEX_op_st8_i32: 3018 case INDEX_op_st8_i64: 3019 case INDEX_op_st16_i32: 3020 case INDEX_op_st16_i64: 3021 case INDEX_op_st_i32: 3022 case INDEX_op_st32_i64: 3023 case INDEX_op_st_i64: 3024 return C_O0_I2(r, r); 3025 3026 case INDEX_op_add_i32: 3027 case INDEX_op_add_i64: 3028 case INDEX_op_shl_i64: 3029 case INDEX_op_shr_i64: 3030 case INDEX_op_sar_i64: 3031 case INDEX_op_rotl_i32: 3032 case INDEX_op_rotl_i64: 3033 case INDEX_op_rotr_i32: 3034 case INDEX_op_rotr_i64: 3035 case INDEX_op_setcond_i32: 3036 return C_O1_I2(r, r, ri); 3037 case INDEX_op_setcond_i64: 3038 return C_O1_I2(r, r, rA); 3039 3040 case INDEX_op_clz_i64: 3041 return C_O1_I2(r, r, rI); 3042 3043 case INDEX_op_sub_i32: 3044 case INDEX_op_sub_i64: 3045 case INDEX_op_and_i32: 3046 case INDEX_op_or_i32: 3047 case INDEX_op_xor_i32: 3048 return C_O1_I2(r, r, ri); 3049 case INDEX_op_and_i64: 3050 return C_O1_I2(r, r, rNKR); 3051 case INDEX_op_or_i64: 3052 case INDEX_op_xor_i64: 3053 return C_O1_I2(r, r, rK); 3054 3055 case INDEX_op_andc_i32: 3056 case INDEX_op_orc_i32: 3057 case INDEX_op_eqv_i32: 3058 return C_O1_I2(r, r, ri); 3059 case INDEX_op_andc_i64: 3060 return C_O1_I2(r, r, rKR); 3061 case INDEX_op_orc_i64: 3062 case INDEX_op_eqv_i64: 3063 return C_O1_I2(r, r, rNK); 3064 3065 case INDEX_op_nand_i32: 3066 case INDEX_op_nand_i64: 3067 case INDEX_op_nor_i32: 3068 case INDEX_op_nor_i64: 3069 return C_O1_I2(r, r, r); 3070 3071 case INDEX_op_mul_i32: 3072 return (HAVE_FACILITY(MISC_INSN_EXT2) 3073 ? C_O1_I2(r, r, ri) 3074 : C_O1_I2(r, 0, ri)); 3075 case INDEX_op_mul_i64: 3076 return (HAVE_FACILITY(MISC_INSN_EXT2) 3077 ? C_O1_I2(r, r, rJ) 3078 : C_O1_I2(r, 0, rJ)); 3079 3080 case INDEX_op_shl_i32: 3081 case INDEX_op_shr_i32: 3082 case INDEX_op_sar_i32: 3083 return C_O1_I2(r, r, ri); 3084 3085 case INDEX_op_brcond_i32: 3086 return C_O0_I2(r, ri); 3087 case INDEX_op_brcond_i64: 3088 return C_O0_I2(r, rA); 3089 3090 case INDEX_op_bswap16_i32: 3091 case INDEX_op_bswap16_i64: 3092 case INDEX_op_bswap32_i32: 3093 case INDEX_op_bswap32_i64: 3094 case INDEX_op_bswap64_i64: 3095 case INDEX_op_neg_i32: 3096 case INDEX_op_neg_i64: 3097 case INDEX_op_not_i32: 3098 case INDEX_op_not_i64: 3099 case INDEX_op_ext8s_i32: 3100 case INDEX_op_ext8s_i64: 3101 case INDEX_op_ext8u_i32: 3102 case INDEX_op_ext8u_i64: 3103 case INDEX_op_ext16s_i32: 3104 case INDEX_op_ext16s_i64: 3105 case INDEX_op_ext16u_i32: 3106 case INDEX_op_ext16u_i64: 3107 case INDEX_op_ext32s_i64: 3108 case INDEX_op_ext32u_i64: 3109 case INDEX_op_ext_i32_i64: 3110 case INDEX_op_extu_i32_i64: 3111 case INDEX_op_extract_i32: 3112 case INDEX_op_extract_i64: 3113 case INDEX_op_ctpop_i32: 3114 case INDEX_op_ctpop_i64: 3115 return C_O1_I1(r, r); 3116 3117 case INDEX_op_qemu_ld_i32: 3118 case INDEX_op_qemu_ld_i64: 3119 return C_O1_I1(r, r); 3120 case INDEX_op_qemu_st_i64: 3121 case INDEX_op_qemu_st_i32: 3122 return C_O0_I2(r, r); 3123 3124 case INDEX_op_deposit_i32: 3125 case INDEX_op_deposit_i64: 3126 return C_O1_I2(r, rZ, r); 3127 3128 case INDEX_op_movcond_i32: 3129 return C_O1_I4(r, r, ri, rI, r); 3130 case INDEX_op_movcond_i64: 3131 return C_O1_I4(r, r, rA, rI, r); 3132 3133 case INDEX_op_div2_i32: 3134 case INDEX_op_div2_i64: 3135 case INDEX_op_divu2_i32: 3136 case INDEX_op_divu2_i64: 3137 return C_O2_I3(o, m, 0, 1, r); 3138 3139 case INDEX_op_mulu2_i64: 3140 return C_O2_I2(o, m, 0, r); 3141 case INDEX_op_muls2_i64: 3142 return C_O2_I2(o, m, r, r); 3143 3144 case INDEX_op_add2_i32: 3145 case INDEX_op_sub2_i32: 3146 return C_O2_I4(r, r, 0, 1, ri, r); 3147 3148 case INDEX_op_add2_i64: 3149 case INDEX_op_sub2_i64: 3150 return C_O2_I4(r, r, 0, 1, rA, r); 3151 3152 case INDEX_op_st_vec: 3153 return C_O0_I2(v, r); 3154 case INDEX_op_ld_vec: 3155 case INDEX_op_dupm_vec: 3156 return C_O1_I1(v, r); 3157 case INDEX_op_dup_vec: 3158 return C_O1_I1(v, vr); 3159 case INDEX_op_abs_vec: 3160 case INDEX_op_neg_vec: 3161 case INDEX_op_not_vec: 3162 case INDEX_op_rotli_vec: 3163 case INDEX_op_sari_vec: 3164 case INDEX_op_shli_vec: 3165 case INDEX_op_shri_vec: 3166 case INDEX_op_s390_vuph_vec: 3167 case INDEX_op_s390_vupl_vec: 3168 return C_O1_I1(v, v); 3169 case INDEX_op_add_vec: 3170 case INDEX_op_sub_vec: 3171 case INDEX_op_and_vec: 3172 case INDEX_op_andc_vec: 3173 case INDEX_op_or_vec: 3174 case INDEX_op_orc_vec: 3175 case INDEX_op_xor_vec: 3176 case INDEX_op_nand_vec: 3177 case INDEX_op_nor_vec: 3178 case INDEX_op_eqv_vec: 3179 case INDEX_op_cmp_vec: 3180 case INDEX_op_mul_vec: 3181 case INDEX_op_rotlv_vec: 3182 case INDEX_op_rotrv_vec: 3183 case INDEX_op_shlv_vec: 3184 case INDEX_op_shrv_vec: 3185 case INDEX_op_sarv_vec: 3186 case INDEX_op_smax_vec: 3187 case INDEX_op_smin_vec: 3188 case INDEX_op_umax_vec: 3189 case INDEX_op_umin_vec: 3190 case INDEX_op_s390_vpks_vec: 3191 return C_O1_I2(v, v, v); 3192 case INDEX_op_rotls_vec: 3193 case INDEX_op_shls_vec: 3194 case INDEX_op_shrs_vec: 3195 case INDEX_op_sars_vec: 3196 return C_O1_I2(v, v, r); 3197 case INDEX_op_bitsel_vec: 3198 return C_O1_I3(v, v, v, v); 3199 3200 default: 3201 g_assert_not_reached(); 3202 } 3203} 3204 3205/* 3206 * Mainline glibc added HWCAP_S390_VX before it was kernel abi. 3207 * Some distros have fixed this up locally, others have not. 3208 */ 3209#ifndef HWCAP_S390_VXRS 3210#define HWCAP_S390_VXRS 2048 3211#endif 3212 3213static void query_s390_facilities(void) 3214{ 3215 unsigned long hwcap = qemu_getauxval(AT_HWCAP); 3216 const char *which; 3217 3218 /* Is STORE FACILITY LIST EXTENDED available? Honestly, I believe this 3219 is present on all 64-bit systems, but let's check for it anyway. */ 3220 if (hwcap & HWCAP_S390_STFLE) { 3221 register int r0 __asm__("0") = ARRAY_SIZE(s390_facilities) - 1; 3222 register void *r1 __asm__("1") = s390_facilities; 3223 3224 /* stfle 0(%r1) */ 3225 asm volatile(".word 0xb2b0,0x1000" 3226 : "=r"(r0) : "r"(r0), "r"(r1) : "memory", "cc"); 3227 } 3228 3229 /* 3230 * Use of vector registers requires os support beyond the facility bit. 3231 * If the kernel does not advertise support, disable the facility bits. 3232 * There is nothing else we currently care about in the 3rd word, so 3233 * disable VECTOR with one store. 3234 */ 3235 if (!(hwcap & HWCAP_S390_VXRS)) { 3236 s390_facilities[2] = 0; 3237 } 3238 3239 /* 3240 * Minimum supported cpu revision is z196. 3241 * Check for all required facilities. 3242 * ZARCH_ACTIVE is done via preprocessor check for 64-bit. 3243 */ 3244 if (!HAVE_FACILITY(LONG_DISP)) { 3245 which = "long-displacement"; 3246 goto fail; 3247 } 3248 if (!HAVE_FACILITY(EXT_IMM)) { 3249 which = "extended-immediate"; 3250 goto fail; 3251 } 3252 if (!HAVE_FACILITY(GEN_INST_EXT)) { 3253 which = "general-instructions-extension"; 3254 goto fail; 3255 } 3256 /* 3257 * Facility 45 is a big bin that contains: distinct-operands, 3258 * fast-BCR-serialization, high-word, population-count, 3259 * interlocked-access-1, and load/store-on-condition-1 3260 */ 3261 if (!HAVE_FACILITY(45)) { 3262 which = "45"; 3263 goto fail; 3264 } 3265 return; 3266 3267 fail: 3268 error_report("%s: missing required facility %s", __func__, which); 3269 exit(EXIT_FAILURE); 3270} 3271 3272static void tcg_target_init(TCGContext *s) 3273{ 3274 query_s390_facilities(); 3275 3276 tcg_target_available_regs[TCG_TYPE_I32] = 0xffff; 3277 tcg_target_available_regs[TCG_TYPE_I64] = 0xffff; 3278 if (HAVE_FACILITY(VECTOR)) { 3279 tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull; 3280 tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull; 3281 } 3282 3283 tcg_target_call_clobber_regs = 0; 3284 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0); 3285 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1); 3286 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2); 3287 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3); 3288 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R4); 3289 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R5); 3290 /* The r6 register is technically call-saved, but it's also a parameter 3291 register, so it can get killed by setup for the qemu_st helper. */ 3292 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R6); 3293 /* The return register can be considered call-clobbered. */ 3294 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14); 3295 3296 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); 3297 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); 3298 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V2); 3299 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V3); 3300 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V4); 3301 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V5); 3302 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V6); 3303 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V7); 3304 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V16); 3305 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V17); 3306 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V18); 3307 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V19); 3308 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V20); 3309 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V21); 3310 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V22); 3311 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V23); 3312 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V24); 3313 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V25); 3314 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V26); 3315 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V27); 3316 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V28); 3317 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V29); 3318 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V30); 3319 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V31); 3320 3321 s->reserved_regs = 0; 3322 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); 3323 /* XXX many insns can't be used with R0, so we better avoid it for now */ 3324 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); 3325 tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); 3326} 3327 3328#define FRAME_SIZE ((int)(TCG_TARGET_CALL_STACK_OFFSET \ 3329 + TCG_STATIC_CALL_ARGS_SIZE \ 3330 + CPU_TEMP_BUF_NLONGS * sizeof(long))) 3331 3332static void tcg_target_qemu_prologue(TCGContext *s) 3333{ 3334 /* stmg %r6,%r15,48(%r15) (save registers) */ 3335 tcg_out_insn(s, RXY, STMG, TCG_REG_R6, TCG_REG_R15, TCG_REG_R15, 48); 3336 3337 /* aghi %r15,-frame_size */ 3338 tcg_out_insn(s, RI, AGHI, TCG_REG_R15, -FRAME_SIZE); 3339 3340 tcg_set_frame(s, TCG_REG_CALL_STACK, 3341 TCG_STATIC_CALL_ARGS_SIZE + TCG_TARGET_CALL_STACK_OFFSET, 3342 CPU_TEMP_BUF_NLONGS * sizeof(long)); 3343 3344#ifndef CONFIG_SOFTMMU 3345 if (guest_base >= 0x80000) { 3346 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); 3347 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 3348 } 3349#endif 3350 3351 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 3352 3353 /* br %r3 (go to TB) */ 3354 tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, tcg_target_call_iarg_regs[1]); 3355 3356 /* 3357 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 3358 * and fall through to the rest of the epilogue. 3359 */ 3360 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 3361 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, 0); 3362 3363 /* TB epilogue */ 3364 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 3365 3366 /* lmg %r6,%r15,fs+48(%r15) (restore registers) */ 3367 tcg_out_insn(s, RXY, LMG, TCG_REG_R6, TCG_REG_R15, TCG_REG_R15, 3368 FRAME_SIZE + 48); 3369 3370 /* br %r14 (return) */ 3371 tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_R14); 3372} 3373 3374static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 3375{ 3376 memset(p, 0x07, count * sizeof(tcg_insn_unit)); 3377} 3378 3379typedef struct { 3380 DebugFrameHeader h; 3381 uint8_t fde_def_cfa[4]; 3382 uint8_t fde_reg_ofs[18]; 3383} DebugFrame; 3384 3385/* We're expecting a 2 byte uleb128 encoded value. */ 3386QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14)); 3387 3388#define ELF_HOST_MACHINE EM_S390 3389 3390static const DebugFrame debug_frame = { 3391 .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ 3392 .h.cie.id = -1, 3393 .h.cie.version = 1, 3394 .h.cie.code_align = 1, 3395 .h.cie.data_align = 8, /* sleb128 8 */ 3396 .h.cie.return_column = TCG_REG_R14, 3397 3398 /* Total FDE size does not include the "len" member. */ 3399 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 3400 3401 .fde_def_cfa = { 3402 12, TCG_REG_CALL_STACK, /* DW_CFA_def_cfa %r15, ... */ 3403 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 3404 (FRAME_SIZE >> 7) 3405 }, 3406 .fde_reg_ofs = { 3407 0x86, 6, /* DW_CFA_offset, %r6, 48 */ 3408 0x87, 7, /* DW_CFA_offset, %r7, 56 */ 3409 0x88, 8, /* DW_CFA_offset, %r8, 64 */ 3410 0x89, 9, /* DW_CFA_offset, %r92, 72 */ 3411 0x8a, 10, /* DW_CFA_offset, %r10, 80 */ 3412 0x8b, 11, /* DW_CFA_offset, %r11, 88 */ 3413 0x8c, 12, /* DW_CFA_offset, %r12, 96 */ 3414 0x8d, 13, /* DW_CFA_offset, %r13, 104 */ 3415 0x8e, 14, /* DW_CFA_offset, %r14, 112 */ 3416 } 3417}; 3418 3419void tcg_register_jit(const void *buf, size_t buf_size) 3420{ 3421 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 3422} 3423