xref: /openbmc/qemu/tcg/riscv/tcg-target.h (revision 4d8722183932d9502e405ae86b1889e1d8a475e5) 
1 /*
2  * Tiny Code Generator for QEMU
3  *
4  * Copyright (c) 2018 SiFive, Inc
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a copy
7  * of this software and associated documentation files (the "Software"), to deal
8  * in the Software without restriction, including without limitation the rights
9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10  * copies of the Software, and to permit persons to whom the Software is
11  * furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22  * THE SOFTWARE.
23  */
24 
25 #ifndef RISCV_TCG_TARGET_H
26 #define RISCV_TCG_TARGET_H
27 
28 #include "host/cpuinfo.h"
29 
30 #define TCG_TARGET_INSN_UNIT_SIZE 4
31 #define TCG_TARGET_NB_REGS 64
32 #define MAX_CODE_GEN_BUFFER_SIZE  ((size_t)-1)
33 
34 typedef enum {
35     TCG_REG_ZERO, TCG_REG_RA,  TCG_REG_SP,  TCG_REG_GP,
36     TCG_REG_TP,   TCG_REG_T0,  TCG_REG_T1,  TCG_REG_T2,
37     TCG_REG_S0,   TCG_REG_S1,  TCG_REG_A0,  TCG_REG_A1,
38     TCG_REG_A2,   TCG_REG_A3,  TCG_REG_A4,  TCG_REG_A5,
39     TCG_REG_A6,   TCG_REG_A7,  TCG_REG_S2,  TCG_REG_S3,
40     TCG_REG_S4,   TCG_REG_S5,  TCG_REG_S6,  TCG_REG_S7,
41     TCG_REG_S8,   TCG_REG_S9,  TCG_REG_S10, TCG_REG_S11,
42     TCG_REG_T3,   TCG_REG_T4,  TCG_REG_T5,  TCG_REG_T6,
43 
44     /* RISC-V V Extension registers */
45     TCG_REG_V0,   TCG_REG_V1,  TCG_REG_V2,  TCG_REG_V3,
46     TCG_REG_V4,   TCG_REG_V5,  TCG_REG_V6,  TCG_REG_V7,
47     TCG_REG_V8,   TCG_REG_V9,  TCG_REG_V10, TCG_REG_V11,
48     TCG_REG_V12,  TCG_REG_V13, TCG_REG_V14, TCG_REG_V15,
49     TCG_REG_V16,  TCG_REG_V17, TCG_REG_V18, TCG_REG_V19,
50     TCG_REG_V20,  TCG_REG_V21, TCG_REG_V22, TCG_REG_V23,
51     TCG_REG_V24,  TCG_REG_V25, TCG_REG_V26, TCG_REG_V27,
52     TCG_REG_V28,  TCG_REG_V29, TCG_REG_V30, TCG_REG_V31,
53 
54     /* aliases */
55     TCG_AREG0          = TCG_REG_S0,
56     TCG_GUEST_BASE_REG = TCG_REG_S1,
57     TCG_REG_TMP0       = TCG_REG_T6,
58     TCG_REG_TMP1       = TCG_REG_T5,
59     TCG_REG_TMP2       = TCG_REG_T4,
60 } TCGReg;
61 
62 /* optional instructions */
63 #define TCG_TARGET_HAS_negsetcond_i32   1
64 #define TCG_TARGET_HAS_div_i32          1
65 #define TCG_TARGET_HAS_rem_i32          1
66 #define TCG_TARGET_HAS_div2_i32         0
67 #define TCG_TARGET_HAS_rot_i32          (cpuinfo & CPUINFO_ZBB)
68 #define TCG_TARGET_HAS_deposit_i32      0
69 #define TCG_TARGET_HAS_extract_i32      0
70 #define TCG_TARGET_HAS_sextract_i32     0
71 #define TCG_TARGET_HAS_extract2_i32     0
72 #define TCG_TARGET_HAS_add2_i32         1
73 #define TCG_TARGET_HAS_sub2_i32         1
74 #define TCG_TARGET_HAS_mulu2_i32        0
75 #define TCG_TARGET_HAS_muls2_i32        0
76 #define TCG_TARGET_HAS_muluh_i32        0
77 #define TCG_TARGET_HAS_mulsh_i32        0
78 #define TCG_TARGET_HAS_ext8s_i32        1
79 #define TCG_TARGET_HAS_ext16s_i32       1
80 #define TCG_TARGET_HAS_ext8u_i32        1
81 #define TCG_TARGET_HAS_ext16u_i32       1
82 #define TCG_TARGET_HAS_bswap16_i32      (cpuinfo & CPUINFO_ZBB)
83 #define TCG_TARGET_HAS_bswap32_i32      (cpuinfo & CPUINFO_ZBB)
84 #define TCG_TARGET_HAS_not_i32          1
85 #define TCG_TARGET_HAS_andc_i32         (cpuinfo & CPUINFO_ZBB)
86 #define TCG_TARGET_HAS_orc_i32          (cpuinfo & CPUINFO_ZBB)
87 #define TCG_TARGET_HAS_eqv_i32          (cpuinfo & CPUINFO_ZBB)
88 #define TCG_TARGET_HAS_nand_i32         0
89 #define TCG_TARGET_HAS_nor_i32          0
90 #define TCG_TARGET_HAS_clz_i32          (cpuinfo & CPUINFO_ZBB)
91 #define TCG_TARGET_HAS_ctz_i32          (cpuinfo & CPUINFO_ZBB)
92 #define TCG_TARGET_HAS_ctpop_i32        (cpuinfo & CPUINFO_ZBB)
93 #define TCG_TARGET_HAS_brcond2          1
94 #define TCG_TARGET_HAS_setcond2         1
95 #define TCG_TARGET_HAS_qemu_st8_i32     0
96 
97 #define TCG_TARGET_HAS_negsetcond_i64   1
98 #define TCG_TARGET_HAS_div_i64          1
99 #define TCG_TARGET_HAS_rem_i64          1
100 #define TCG_TARGET_HAS_div2_i64         0
101 #define TCG_TARGET_HAS_rot_i64          (cpuinfo & CPUINFO_ZBB)
102 #define TCG_TARGET_HAS_deposit_i64      0
103 #define TCG_TARGET_HAS_extract_i64      0
104 #define TCG_TARGET_HAS_sextract_i64     0
105 #define TCG_TARGET_HAS_extract2_i64     0
106 #define TCG_TARGET_HAS_extr_i64_i32     1
107 #define TCG_TARGET_HAS_ext8s_i64        1
108 #define TCG_TARGET_HAS_ext16s_i64       1
109 #define TCG_TARGET_HAS_ext32s_i64       1
110 #define TCG_TARGET_HAS_ext8u_i64        1
111 #define TCG_TARGET_HAS_ext16u_i64       1
112 #define TCG_TARGET_HAS_ext32u_i64       1
113 #define TCG_TARGET_HAS_bswap16_i64      (cpuinfo & CPUINFO_ZBB)
114 #define TCG_TARGET_HAS_bswap32_i64      (cpuinfo & CPUINFO_ZBB)
115 #define TCG_TARGET_HAS_bswap64_i64      (cpuinfo & CPUINFO_ZBB)
116 #define TCG_TARGET_HAS_not_i64          1
117 #define TCG_TARGET_HAS_andc_i64         (cpuinfo & CPUINFO_ZBB)
118 #define TCG_TARGET_HAS_orc_i64          (cpuinfo & CPUINFO_ZBB)
119 #define TCG_TARGET_HAS_eqv_i64          (cpuinfo & CPUINFO_ZBB)
120 #define TCG_TARGET_HAS_nand_i64         0
121 #define TCG_TARGET_HAS_nor_i64          0
122 #define TCG_TARGET_HAS_clz_i64          (cpuinfo & CPUINFO_ZBB)
123 #define TCG_TARGET_HAS_ctz_i64          (cpuinfo & CPUINFO_ZBB)
124 #define TCG_TARGET_HAS_ctpop_i64        (cpuinfo & CPUINFO_ZBB)
125 #define TCG_TARGET_HAS_add2_i64         1
126 #define TCG_TARGET_HAS_sub2_i64         1
127 #define TCG_TARGET_HAS_mulu2_i64        0
128 #define TCG_TARGET_HAS_muls2_i64        0
129 #define TCG_TARGET_HAS_muluh_i64        1
130 #define TCG_TARGET_HAS_mulsh_i64        1
131 
132 #define TCG_TARGET_HAS_qemu_ldst_i128   0
133 
134 #define TCG_TARGET_HAS_tst              0
135 
136 /* vector instructions */
137 #define TCG_TARGET_HAS_v64              (cpuinfo & CPUINFO_ZVE64X)
138 #define TCG_TARGET_HAS_v128             (cpuinfo & CPUINFO_ZVE64X)
139 #define TCG_TARGET_HAS_v256             (cpuinfo & CPUINFO_ZVE64X)
140 #define TCG_TARGET_HAS_andc_vec         0
141 #define TCG_TARGET_HAS_orc_vec          0
142 #define TCG_TARGET_HAS_nand_vec         0
143 #define TCG_TARGET_HAS_nor_vec          0
144 #define TCG_TARGET_HAS_eqv_vec          0
145 #define TCG_TARGET_HAS_not_vec          1
146 #define TCG_TARGET_HAS_neg_vec          1
147 #define TCG_TARGET_HAS_abs_vec          0
148 #define TCG_TARGET_HAS_roti_vec         1
149 #define TCG_TARGET_HAS_rots_vec         1
150 #define TCG_TARGET_HAS_rotv_vec         1
151 #define TCG_TARGET_HAS_shi_vec          1
152 #define TCG_TARGET_HAS_shs_vec          1
153 #define TCG_TARGET_HAS_shv_vec          1
154 #define TCG_TARGET_HAS_mul_vec          1
155 #define TCG_TARGET_HAS_sat_vec          1
156 #define TCG_TARGET_HAS_minmax_vec       1
157 #define TCG_TARGET_HAS_bitsel_vec       0
158 #define TCG_TARGET_HAS_cmpsel_vec       1
159 
160 #define TCG_TARGET_HAS_tst_vec          0
161 
162 #define TCG_TARGET_DEFAULT_MO (0)
163 
164 #define TCG_TARGET_NEED_LDST_LABELS
165 #define TCG_TARGET_NEED_POOL_LABELS
166 
167 #endif
168