1 /* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2018 SiFive, Inc 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #ifndef RISCV_TCG_TARGET_H 26 #define RISCV_TCG_TARGET_H 27 28 #if __riscv_xlen == 32 29 # define TCG_TARGET_REG_BITS 32 30 #elif __riscv_xlen == 64 31 # define TCG_TARGET_REG_BITS 64 32 #endif 33 34 #define TCG_TARGET_INSN_UNIT_SIZE 4 35 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 20 36 #define TCG_TARGET_NB_REGS 32 37 #define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) 38 39 typedef enum { 40 TCG_REG_ZERO, 41 TCG_REG_RA, 42 TCG_REG_SP, 43 TCG_REG_GP, 44 TCG_REG_TP, 45 TCG_REG_T0, 46 TCG_REG_T1, 47 TCG_REG_T2, 48 TCG_REG_S0, 49 TCG_REG_S1, 50 TCG_REG_A0, 51 TCG_REG_A1, 52 TCG_REG_A2, 53 TCG_REG_A3, 54 TCG_REG_A4, 55 TCG_REG_A5, 56 TCG_REG_A6, 57 TCG_REG_A7, 58 TCG_REG_S2, 59 TCG_REG_S3, 60 TCG_REG_S4, 61 TCG_REG_S5, 62 TCG_REG_S6, 63 TCG_REG_S7, 64 TCG_REG_S8, 65 TCG_REG_S9, 66 TCG_REG_S10, 67 TCG_REG_S11, 68 TCG_REG_T3, 69 TCG_REG_T4, 70 TCG_REG_T5, 71 TCG_REG_T6, 72 73 /* aliases */ 74 TCG_AREG0 = TCG_REG_S0, 75 TCG_GUEST_BASE_REG = TCG_REG_S1, 76 TCG_REG_TMP0 = TCG_REG_T6, 77 TCG_REG_TMP1 = TCG_REG_T5, 78 TCG_REG_TMP2 = TCG_REG_T4, 79 } TCGReg; 80 81 /* used for function call generation */ 82 #define TCG_REG_CALL_STACK TCG_REG_SP 83 #define TCG_TARGET_STACK_ALIGN 16 84 #define TCG_TARGET_CALL_STACK_OFFSET 0 85 #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL 86 #if TCG_TARGET_REG_BITS == 32 87 #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN 88 #define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN 89 #else 90 #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL 91 #define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL 92 #endif 93 #define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL 94 95 /* optional instructions */ 96 #define TCG_TARGET_HAS_movcond_i32 0 97 #define TCG_TARGET_HAS_div_i32 1 98 #define TCG_TARGET_HAS_rem_i32 1 99 #define TCG_TARGET_HAS_div2_i32 0 100 #define TCG_TARGET_HAS_rot_i32 0 101 #define TCG_TARGET_HAS_deposit_i32 0 102 #define TCG_TARGET_HAS_extract_i32 0 103 #define TCG_TARGET_HAS_sextract_i32 0 104 #define TCG_TARGET_HAS_extract2_i32 0 105 #define TCG_TARGET_HAS_add2_i32 1 106 #define TCG_TARGET_HAS_sub2_i32 1 107 #define TCG_TARGET_HAS_mulu2_i32 0 108 #define TCG_TARGET_HAS_muls2_i32 0 109 #define TCG_TARGET_HAS_muluh_i32 (TCG_TARGET_REG_BITS == 32) 110 #define TCG_TARGET_HAS_mulsh_i32 (TCG_TARGET_REG_BITS == 32) 111 #define TCG_TARGET_HAS_ext8s_i32 1 112 #define TCG_TARGET_HAS_ext16s_i32 1 113 #define TCG_TARGET_HAS_ext8u_i32 1 114 #define TCG_TARGET_HAS_ext16u_i32 1 115 #define TCG_TARGET_HAS_bswap16_i32 0 116 #define TCG_TARGET_HAS_bswap32_i32 0 117 #define TCG_TARGET_HAS_not_i32 1 118 #define TCG_TARGET_HAS_neg_i32 1 119 #define TCG_TARGET_HAS_andc_i32 0 120 #define TCG_TARGET_HAS_orc_i32 0 121 #define TCG_TARGET_HAS_eqv_i32 0 122 #define TCG_TARGET_HAS_nand_i32 0 123 #define TCG_TARGET_HAS_nor_i32 0 124 #define TCG_TARGET_HAS_clz_i32 0 125 #define TCG_TARGET_HAS_ctz_i32 0 126 #define TCG_TARGET_HAS_ctpop_i32 0 127 #define TCG_TARGET_HAS_brcond2 1 128 #define TCG_TARGET_HAS_setcond2 1 129 #define TCG_TARGET_HAS_qemu_st8_i32 0 130 131 #if TCG_TARGET_REG_BITS == 64 132 #define TCG_TARGET_HAS_movcond_i64 0 133 #define TCG_TARGET_HAS_div_i64 1 134 #define TCG_TARGET_HAS_rem_i64 1 135 #define TCG_TARGET_HAS_div2_i64 0 136 #define TCG_TARGET_HAS_rot_i64 0 137 #define TCG_TARGET_HAS_deposit_i64 0 138 #define TCG_TARGET_HAS_extract_i64 0 139 #define TCG_TARGET_HAS_sextract_i64 0 140 #define TCG_TARGET_HAS_extract2_i64 0 141 #define TCG_TARGET_HAS_extrl_i64_i32 1 142 #define TCG_TARGET_HAS_extrh_i64_i32 1 143 #define TCG_TARGET_HAS_ext8s_i64 1 144 #define TCG_TARGET_HAS_ext16s_i64 1 145 #define TCG_TARGET_HAS_ext32s_i64 1 146 #define TCG_TARGET_HAS_ext8u_i64 1 147 #define TCG_TARGET_HAS_ext16u_i64 1 148 #define TCG_TARGET_HAS_ext32u_i64 1 149 #define TCG_TARGET_HAS_bswap16_i64 0 150 #define TCG_TARGET_HAS_bswap32_i64 0 151 #define TCG_TARGET_HAS_bswap64_i64 0 152 #define TCG_TARGET_HAS_not_i64 1 153 #define TCG_TARGET_HAS_neg_i64 1 154 #define TCG_TARGET_HAS_andc_i64 0 155 #define TCG_TARGET_HAS_orc_i64 0 156 #define TCG_TARGET_HAS_eqv_i64 0 157 #define TCG_TARGET_HAS_nand_i64 0 158 #define TCG_TARGET_HAS_nor_i64 0 159 #define TCG_TARGET_HAS_clz_i64 0 160 #define TCG_TARGET_HAS_ctz_i64 0 161 #define TCG_TARGET_HAS_ctpop_i64 0 162 #define TCG_TARGET_HAS_add2_i64 1 163 #define TCG_TARGET_HAS_sub2_i64 1 164 #define TCG_TARGET_HAS_mulu2_i64 0 165 #define TCG_TARGET_HAS_muls2_i64 0 166 #define TCG_TARGET_HAS_muluh_i64 1 167 #define TCG_TARGET_HAS_mulsh_i64 1 168 #endif 169 170 #define TCG_TARGET_DEFAULT_MO (0) 171 172 #define TCG_TARGET_NEED_LDST_LABELS 173 #define TCG_TARGET_NEED_POOL_LABELS 174 175 #define TCG_TARGET_HAS_MEMORY_BSWAP 0 176 177 #endif 178