1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2018 SiFive, Inc 5 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org> 6 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net> 7 * Copyright (c) 2008 Fabrice Bellard 8 * 9 * Based on i386/tcg-target.c and mips/tcg-target.c 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a copy 12 * of this software and associated documentation files (the "Software"), to deal 13 * in the Software without restriction, including without limitation the rights 14 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 15 * copies of the Software, and to permit persons to whom the Software is 16 * furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice shall be included in 19 * all copies or substantial portions of the Software. 20 * 21 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 22 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 23 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 24 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 25 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 26 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 27 * THE SOFTWARE. 28 */ 29 30/* Used for function call generation. */ 31#define TCG_REG_CALL_STACK TCG_REG_SP 32#define TCG_TARGET_STACK_ALIGN 16 33#define TCG_TARGET_CALL_STACK_OFFSET 0 34#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL 35#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL 36#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL 37#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL 38 39#ifdef CONFIG_DEBUG_TCG 40static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 41 "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", 42 "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", 43 "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", 44 "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", 45 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 46 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 47 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 48 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 49}; 50#endif 51 52static const int tcg_target_reg_alloc_order[] = { 53 /* Call saved registers */ 54 /* TCG_REG_S0 reserved for TCG_AREG0 */ 55 TCG_REG_S1, 56 TCG_REG_S2, 57 TCG_REG_S3, 58 TCG_REG_S4, 59 TCG_REG_S5, 60 TCG_REG_S6, 61 TCG_REG_S7, 62 TCG_REG_S8, 63 TCG_REG_S9, 64 TCG_REG_S10, 65 TCG_REG_S11, 66 67 /* Call clobbered registers */ 68 TCG_REG_T0, 69 TCG_REG_T1, 70 TCG_REG_T2, 71 TCG_REG_T3, 72 TCG_REG_T4, 73 TCG_REG_T5, 74 TCG_REG_T6, 75 76 /* Argument registers */ 77 TCG_REG_A0, 78 TCG_REG_A1, 79 TCG_REG_A2, 80 TCG_REG_A3, 81 TCG_REG_A4, 82 TCG_REG_A5, 83 TCG_REG_A6, 84 TCG_REG_A7, 85 86 /* Vector registers and TCG_REG_V0 reserved for mask. */ 87 TCG_REG_V1, TCG_REG_V2, TCG_REG_V3, TCG_REG_V4, 88 TCG_REG_V5, TCG_REG_V6, TCG_REG_V7, TCG_REG_V8, 89 TCG_REG_V9, TCG_REG_V10, TCG_REG_V11, TCG_REG_V12, 90 TCG_REG_V13, TCG_REG_V14, TCG_REG_V15, TCG_REG_V16, 91 TCG_REG_V17, TCG_REG_V18, TCG_REG_V19, TCG_REG_V20, 92 TCG_REG_V21, TCG_REG_V22, TCG_REG_V23, TCG_REG_V24, 93 TCG_REG_V25, TCG_REG_V26, TCG_REG_V27, TCG_REG_V28, 94 TCG_REG_V29, TCG_REG_V30, TCG_REG_V31, 95}; 96 97static const int tcg_target_call_iarg_regs[] = { 98 TCG_REG_A0, 99 TCG_REG_A1, 100 TCG_REG_A2, 101 TCG_REG_A3, 102 TCG_REG_A4, 103 TCG_REG_A5, 104 TCG_REG_A6, 105 TCG_REG_A7, 106}; 107 108static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 109{ 110 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 111 tcg_debug_assert(slot >= 0 && slot <= 1); 112 return TCG_REG_A0 + slot; 113} 114 115#define TCG_CT_CONST_S12 0x100 116#define TCG_CT_CONST_M12 0x200 117#define TCG_CT_CONST_S5 0x400 118#define TCG_CT_CONST_CMP_VI 0x800 119 120#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) 121#define ALL_VECTOR_REGS MAKE_64BIT_MASK(32, 32) 122#define ALL_DVECTOR_REG_GROUPS 0x5555555500000000 123#define ALL_QVECTOR_REG_GROUPS 0x1111111100000000 124 125#define sextreg sextract64 126 127/* 128 * RISC-V Base ISA opcodes (IM) 129 */ 130 131#define V_OPIVV (0x0 << 12) 132#define V_OPFVV (0x1 << 12) 133#define V_OPMVV (0x2 << 12) 134#define V_OPIVI (0x3 << 12) 135#define V_OPIVX (0x4 << 12) 136#define V_OPFVF (0x5 << 12) 137#define V_OPMVX (0x6 << 12) 138#define V_OPCFG (0x7 << 12) 139 140/* NF <= 7 && NF >= 0 */ 141#define V_NF(x) (x << 29) 142#define V_UNIT_STRIDE (0x0 << 20) 143#define V_UNIT_STRIDE_WHOLE_REG (0x8 << 20) 144 145typedef enum { 146 VLMUL_M1 = 0, /* LMUL=1 */ 147 VLMUL_M2, /* LMUL=2 */ 148 VLMUL_M4, /* LMUL=4 */ 149 VLMUL_M8, /* LMUL=8 */ 150 VLMUL_RESERVED, 151 VLMUL_MF8, /* LMUL=1/8 */ 152 VLMUL_MF4, /* LMUL=1/4 */ 153 VLMUL_MF2, /* LMUL=1/2 */ 154} RISCVVlmul; 155 156typedef enum { 157 OPC_ADD = 0x33, 158 OPC_ADDI = 0x13, 159 OPC_AND = 0x7033, 160 OPC_ANDI = 0x7013, 161 OPC_AUIPC = 0x17, 162 OPC_BEQ = 0x63, 163 OPC_BEXTI = 0x48005013, 164 OPC_BGE = 0x5063, 165 OPC_BGEU = 0x7063, 166 OPC_BLT = 0x4063, 167 OPC_BLTU = 0x6063, 168 OPC_BNE = 0x1063, 169 OPC_DIV = 0x2004033, 170 OPC_DIVU = 0x2005033, 171 OPC_JAL = 0x6f, 172 OPC_JALR = 0x67, 173 OPC_LB = 0x3, 174 OPC_LBU = 0x4003, 175 OPC_LD = 0x3003, 176 OPC_LH = 0x1003, 177 OPC_LHU = 0x5003, 178 OPC_LUI = 0x37, 179 OPC_LW = 0x2003, 180 OPC_LWU = 0x6003, 181 OPC_MUL = 0x2000033, 182 OPC_MULH = 0x2001033, 183 OPC_MULHSU = 0x2002033, 184 OPC_MULHU = 0x2003033, 185 OPC_OR = 0x6033, 186 OPC_ORI = 0x6013, 187 OPC_REM = 0x2006033, 188 OPC_REMU = 0x2007033, 189 OPC_SB = 0x23, 190 OPC_SD = 0x3023, 191 OPC_SH = 0x1023, 192 OPC_SLL = 0x1033, 193 OPC_SLLI = 0x1013, 194 OPC_SLT = 0x2033, 195 OPC_SLTI = 0x2013, 196 OPC_SLTIU = 0x3013, 197 OPC_SLTU = 0x3033, 198 OPC_SRA = 0x40005033, 199 OPC_SRAI = 0x40005013, 200 OPC_SRL = 0x5033, 201 OPC_SRLI = 0x5013, 202 OPC_SUB = 0x40000033, 203 OPC_SW = 0x2023, 204 OPC_XOR = 0x4033, 205 OPC_XORI = 0x4013, 206 207 OPC_ADDIW = 0x1b, 208 OPC_ADDW = 0x3b, 209 OPC_DIVUW = 0x200503b, 210 OPC_DIVW = 0x200403b, 211 OPC_MULW = 0x200003b, 212 OPC_REMUW = 0x200703b, 213 OPC_REMW = 0x200603b, 214 OPC_SLLIW = 0x101b, 215 OPC_SLLW = 0x103b, 216 OPC_SRAIW = 0x4000501b, 217 OPC_SRAW = 0x4000503b, 218 OPC_SRLIW = 0x501b, 219 OPC_SRLW = 0x503b, 220 OPC_SUBW = 0x4000003b, 221 222 OPC_FENCE = 0x0000000f, 223 OPC_NOP = OPC_ADDI, /* nop = addi r0,r0,0 */ 224 225 /* Zba: Bit manipulation extension, address generation */ 226 OPC_ADD_UW = 0x0800003b, 227 228 /* Zbb: Bit manipulation extension, basic bit manipulation */ 229 OPC_ANDN = 0x40007033, 230 OPC_CLZ = 0x60001013, 231 OPC_CLZW = 0x6000101b, 232 OPC_CPOP = 0x60201013, 233 OPC_CPOPW = 0x6020101b, 234 OPC_CTZ = 0x60101013, 235 OPC_CTZW = 0x6010101b, 236 OPC_ORN = 0x40006033, 237 OPC_REV8 = 0x6b805013, 238 OPC_ROL = 0x60001033, 239 OPC_ROLW = 0x6000103b, 240 OPC_ROR = 0x60005033, 241 OPC_RORW = 0x6000503b, 242 OPC_RORI = 0x60005013, 243 OPC_RORIW = 0x6000501b, 244 OPC_SEXT_B = 0x60401013, 245 OPC_SEXT_H = 0x60501013, 246 OPC_XNOR = 0x40004033, 247 OPC_ZEXT_H = 0x0800403b, 248 249 /* Zicond: integer conditional operations */ 250 OPC_CZERO_EQZ = 0x0e005033, 251 OPC_CZERO_NEZ = 0x0e007033, 252 253 /* V: Vector extension 1.0 */ 254 OPC_VSETVLI = 0x57 | V_OPCFG, 255 OPC_VSETIVLI = 0xc0000057 | V_OPCFG, 256 OPC_VSETVL = 0x80000057 | V_OPCFG, 257 258 OPC_VLE8_V = 0x7 | V_UNIT_STRIDE, 259 OPC_VLE16_V = 0x5007 | V_UNIT_STRIDE, 260 OPC_VLE32_V = 0x6007 | V_UNIT_STRIDE, 261 OPC_VLE64_V = 0x7007 | V_UNIT_STRIDE, 262 OPC_VSE8_V = 0x27 | V_UNIT_STRIDE, 263 OPC_VSE16_V = 0x5027 | V_UNIT_STRIDE, 264 OPC_VSE32_V = 0x6027 | V_UNIT_STRIDE, 265 OPC_VSE64_V = 0x7027 | V_UNIT_STRIDE, 266 267 OPC_VL1RE64_V = 0x2007007 | V_UNIT_STRIDE_WHOLE_REG | V_NF(0), 268 OPC_VL2RE64_V = 0x2007007 | V_UNIT_STRIDE_WHOLE_REG | V_NF(1), 269 OPC_VL4RE64_V = 0x2007007 | V_UNIT_STRIDE_WHOLE_REG | V_NF(3), 270 OPC_VL8RE64_V = 0x2007007 | V_UNIT_STRIDE_WHOLE_REG | V_NF(7), 271 272 OPC_VS1R_V = 0x2000027 | V_UNIT_STRIDE_WHOLE_REG | V_NF(0), 273 OPC_VS2R_V = 0x2000027 | V_UNIT_STRIDE_WHOLE_REG | V_NF(1), 274 OPC_VS4R_V = 0x2000027 | V_UNIT_STRIDE_WHOLE_REG | V_NF(3), 275 OPC_VS8R_V = 0x2000027 | V_UNIT_STRIDE_WHOLE_REG | V_NF(7), 276 277 OPC_VMERGE_VIM = 0x5c000057 | V_OPIVI, 278 OPC_VMERGE_VVM = 0x5c000057 | V_OPIVV, 279 280 OPC_VADD_VV = 0x57 | V_OPIVV, 281 OPC_VADD_VI = 0x57 | V_OPIVI, 282 OPC_VSUB_VV = 0x8000057 | V_OPIVV, 283 OPC_VRSUB_VI = 0xc000057 | V_OPIVI, 284 OPC_VAND_VV = 0x24000057 | V_OPIVV, 285 OPC_VAND_VI = 0x24000057 | V_OPIVI, 286 OPC_VOR_VV = 0x28000057 | V_OPIVV, 287 OPC_VOR_VI = 0x28000057 | V_OPIVI, 288 OPC_VXOR_VV = 0x2c000057 | V_OPIVV, 289 OPC_VXOR_VI = 0x2c000057 | V_OPIVI, 290 291 OPC_VMUL_VV = 0x94000057 | V_OPMVV, 292 OPC_VSADD_VV = 0x84000057 | V_OPIVV, 293 OPC_VSADD_VI = 0x84000057 | V_OPIVI, 294 OPC_VSSUB_VV = 0x8c000057 | V_OPIVV, 295 OPC_VSSUB_VI = 0x8c000057 | V_OPIVI, 296 OPC_VSADDU_VV = 0x80000057 | V_OPIVV, 297 OPC_VSADDU_VI = 0x80000057 | V_OPIVI, 298 OPC_VSSUBU_VV = 0x88000057 | V_OPIVV, 299 OPC_VSSUBU_VI = 0x88000057 | V_OPIVI, 300 301 OPC_VMAX_VV = 0x1c000057 | V_OPIVV, 302 OPC_VMAX_VI = 0x1c000057 | V_OPIVI, 303 OPC_VMAXU_VV = 0x18000057 | V_OPIVV, 304 OPC_VMAXU_VI = 0x18000057 | V_OPIVI, 305 OPC_VMIN_VV = 0x14000057 | V_OPIVV, 306 OPC_VMIN_VI = 0x14000057 | V_OPIVI, 307 OPC_VMINU_VV = 0x10000057 | V_OPIVV, 308 OPC_VMINU_VI = 0x10000057 | V_OPIVI, 309 310 OPC_VMSEQ_VV = 0x60000057 | V_OPIVV, 311 OPC_VMSEQ_VI = 0x60000057 | V_OPIVI, 312 OPC_VMSEQ_VX = 0x60000057 | V_OPIVX, 313 OPC_VMSNE_VV = 0x64000057 | V_OPIVV, 314 OPC_VMSNE_VI = 0x64000057 | V_OPIVI, 315 OPC_VMSNE_VX = 0x64000057 | V_OPIVX, 316 317 OPC_VMSLTU_VV = 0x68000057 | V_OPIVV, 318 OPC_VMSLTU_VX = 0x68000057 | V_OPIVX, 319 OPC_VMSLT_VV = 0x6c000057 | V_OPIVV, 320 OPC_VMSLT_VX = 0x6c000057 | V_OPIVX, 321 OPC_VMSLEU_VV = 0x70000057 | V_OPIVV, 322 OPC_VMSLEU_VX = 0x70000057 | V_OPIVX, 323 OPC_VMSLE_VV = 0x74000057 | V_OPIVV, 324 OPC_VMSLE_VX = 0x74000057 | V_OPIVX, 325 326 OPC_VMSLEU_VI = 0x70000057 | V_OPIVI, 327 OPC_VMSLE_VI = 0x74000057 | V_OPIVI, 328 OPC_VMSGTU_VI = 0x78000057 | V_OPIVI, 329 OPC_VMSGTU_VX = 0x78000057 | V_OPIVX, 330 OPC_VMSGT_VI = 0x7c000057 | V_OPIVI, 331 OPC_VMSGT_VX = 0x7c000057 | V_OPIVX, 332 333 OPC_VSLL_VV = 0x94000057 | V_OPIVV, 334 OPC_VSLL_VI = 0x94000057 | V_OPIVI, 335 OPC_VSLL_VX = 0x94000057 | V_OPIVX, 336 OPC_VSRL_VV = 0xa0000057 | V_OPIVV, 337 OPC_VSRL_VI = 0xa0000057 | V_OPIVI, 338 OPC_VSRL_VX = 0xa0000057 | V_OPIVX, 339 OPC_VSRA_VV = 0xa4000057 | V_OPIVV, 340 OPC_VSRA_VI = 0xa4000057 | V_OPIVI, 341 OPC_VSRA_VX = 0xa4000057 | V_OPIVX, 342 343 OPC_VMV_V_V = 0x5e000057 | V_OPIVV, 344 OPC_VMV_V_I = 0x5e000057 | V_OPIVI, 345 OPC_VMV_V_X = 0x5e000057 | V_OPIVX, 346 347 OPC_VMVNR_V = 0x9e000057 | V_OPIVI, 348} RISCVInsn; 349 350static const struct { 351 RISCVInsn op; 352 bool swap; 353} tcg_cmpcond_to_rvv_vv[] = { 354 [TCG_COND_EQ] = { OPC_VMSEQ_VV, false }, 355 [TCG_COND_NE] = { OPC_VMSNE_VV, false }, 356 [TCG_COND_LT] = { OPC_VMSLT_VV, false }, 357 [TCG_COND_GE] = { OPC_VMSLE_VV, true }, 358 [TCG_COND_GT] = { OPC_VMSLT_VV, true }, 359 [TCG_COND_LE] = { OPC_VMSLE_VV, false }, 360 [TCG_COND_LTU] = { OPC_VMSLTU_VV, false }, 361 [TCG_COND_GEU] = { OPC_VMSLEU_VV, true }, 362 [TCG_COND_GTU] = { OPC_VMSLTU_VV, true }, 363 [TCG_COND_LEU] = { OPC_VMSLEU_VV, false } 364}; 365 366static const struct { 367 RISCVInsn op; 368 int min; 369 int max; 370 bool adjust; 371} tcg_cmpcond_to_rvv_vi[] = { 372 [TCG_COND_EQ] = { OPC_VMSEQ_VI, -16, 15, false }, 373 [TCG_COND_NE] = { OPC_VMSNE_VI, -16, 15, false }, 374 [TCG_COND_GT] = { OPC_VMSGT_VI, -16, 15, false }, 375 [TCG_COND_LE] = { OPC_VMSLE_VI, -16, 15, false }, 376 [TCG_COND_LT] = { OPC_VMSLE_VI, -15, 16, true }, 377 [TCG_COND_GE] = { OPC_VMSGT_VI, -15, 16, true }, 378 [TCG_COND_LEU] = { OPC_VMSLEU_VI, 0, 15, false }, 379 [TCG_COND_GTU] = { OPC_VMSGTU_VI, 0, 15, false }, 380 [TCG_COND_LTU] = { OPC_VMSLEU_VI, 1, 16, true }, 381 [TCG_COND_GEU] = { OPC_VMSGTU_VI, 1, 16, true }, 382}; 383 384/* test if a constant matches the constraint */ 385static bool tcg_target_const_match(int64_t val, int ct, 386 TCGType type, TCGCond cond, int vece) 387{ 388 if (ct & TCG_CT_CONST) { 389 return 1; 390 } 391 if (type >= TCG_TYPE_V64) { 392 /* Val is replicated by VECE; extract the highest element. */ 393 val >>= (-8 << vece) & 63; 394 } 395 /* 396 * Sign extended from 12 bits: [-0x800, 0x7ff]. 397 * Used for most arithmetic, as this is the isa field. 398 */ 399 if ((ct & TCG_CT_CONST_S12) && val >= -0x800 && val <= 0x7ff) { 400 return 1; 401 } 402 /* 403 * Sign extended from 12 bits, +/- matching: [-0x7ff, 0x7ff]. 404 * Used by addsub2 and movcond, which may need the negative value, 405 * and requires the modified constant to be representable. 406 */ 407 if ((ct & TCG_CT_CONST_M12) && val >= -0x7ff && val <= 0x7ff) { 408 return 1; 409 } 410 /* 411 * Sign extended from 5 bits: [-0x10, 0x0f]. 412 * Used for vector-immediate. 413 */ 414 if ((ct & TCG_CT_CONST_S5) && val >= -0x10 && val <= 0x0f) { 415 return 1; 416 } 417 /* 418 * Used for vector compare OPIVI instructions. 419 */ 420 if ((ct & TCG_CT_CONST_CMP_VI) && 421 val >= tcg_cmpcond_to_rvv_vi[cond].min && 422 val <= tcg_cmpcond_to_rvv_vi[cond].max) { 423 return true; 424 } 425 return 0; 426} 427 428/* 429 * RISC-V immediate and instruction encoders (excludes 16-bit RVC) 430 */ 431 432/* Type-R */ 433 434static int32_t encode_r(RISCVInsn opc, TCGReg rd, TCGReg rs1, TCGReg rs2) 435{ 436 return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20; 437} 438 439/* Type-I */ 440 441static int32_t encode_imm12(uint32_t imm) 442{ 443 return (imm & 0xfff) << 20; 444} 445 446static int32_t encode_i(RISCVInsn opc, TCGReg rd, TCGReg rs1, uint32_t imm) 447{ 448 return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | encode_imm12(imm); 449} 450 451/* Type-S */ 452 453static int32_t encode_simm12(uint32_t imm) 454{ 455 int32_t ret = 0; 456 457 ret |= (imm & 0xFE0) << 20; 458 ret |= (imm & 0x1F) << 7; 459 460 return ret; 461} 462 463static int32_t encode_s(RISCVInsn opc, TCGReg rs1, TCGReg rs2, uint32_t imm) 464{ 465 return opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20 | encode_simm12(imm); 466} 467 468/* Type-SB */ 469 470static int32_t encode_sbimm12(uint32_t imm) 471{ 472 int32_t ret = 0; 473 474 ret |= (imm & 0x1000) << 19; 475 ret |= (imm & 0x7e0) << 20; 476 ret |= (imm & 0x1e) << 7; 477 ret |= (imm & 0x800) >> 4; 478 479 return ret; 480} 481 482static int32_t encode_sb(RISCVInsn opc, TCGReg rs1, TCGReg rs2, uint32_t imm) 483{ 484 return opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20 | encode_sbimm12(imm); 485} 486 487/* Type-U */ 488 489static int32_t encode_uimm20(uint32_t imm) 490{ 491 return imm & 0xfffff000; 492} 493 494static int32_t encode_u(RISCVInsn opc, TCGReg rd, uint32_t imm) 495{ 496 return opc | (rd & 0x1f) << 7 | encode_uimm20(imm); 497} 498 499/* Type-UJ */ 500 501static int32_t encode_ujimm20(uint32_t imm) 502{ 503 int32_t ret = 0; 504 505 ret |= (imm & 0x0007fe) << (21 - 1); 506 ret |= (imm & 0x000800) << (20 - 11); 507 ret |= (imm & 0x0ff000) << (12 - 12); 508 ret |= (imm & 0x100000) << (31 - 20); 509 510 return ret; 511} 512 513static int32_t encode_uj(RISCVInsn opc, TCGReg rd, uint32_t imm) 514{ 515 return opc | (rd & 0x1f) << 7 | encode_ujimm20(imm); 516} 517 518 519/* Type-OPIVI */ 520 521static int32_t encode_vi(RISCVInsn opc, TCGReg rd, int32_t imm, 522 TCGReg vs2, bool vm) 523{ 524 return opc | (rd & 0x1f) << 7 | (imm & 0x1f) << 15 | 525 (vs2 & 0x1f) << 20 | (vm << 25); 526} 527 528/* Type-OPIVV/OPMVV/OPIVX/OPMVX, Vector load and store */ 529 530static int32_t encode_v(RISCVInsn opc, TCGReg d, TCGReg s1, 531 TCGReg s2, bool vm) 532{ 533 return opc | (d & 0x1f) << 7 | (s1 & 0x1f) << 15 | 534 (s2 & 0x1f) << 20 | (vm << 25); 535} 536 537/* Vector vtype */ 538 539static uint32_t encode_vtype(bool vta, bool vma, 540 MemOp vsew, RISCVVlmul vlmul) 541{ 542 return vma << 7 | vta << 6 | vsew << 3 | vlmul; 543} 544 545static int32_t encode_vset(RISCVInsn opc, TCGReg rd, 546 TCGArg rs1, uint32_t vtype) 547{ 548 return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | (vtype & 0x7ff) << 20; 549} 550 551static int32_t encode_vseti(RISCVInsn opc, TCGReg rd, 552 uint32_t uimm, uint32_t vtype) 553{ 554 return opc | (rd & 0x1f) << 7 | (uimm & 0x1f) << 15 | (vtype & 0x3ff) << 20; 555} 556 557/* 558 * RISC-V instruction emitters 559 */ 560 561static void tcg_out_opc_reg(TCGContext *s, RISCVInsn opc, 562 TCGReg rd, TCGReg rs1, TCGReg rs2) 563{ 564 tcg_out32(s, encode_r(opc, rd, rs1, rs2)); 565} 566 567static void tcg_out_opc_imm(TCGContext *s, RISCVInsn opc, 568 TCGReg rd, TCGReg rs1, TCGArg imm) 569{ 570 tcg_out32(s, encode_i(opc, rd, rs1, imm)); 571} 572 573static void tcg_out_opc_store(TCGContext *s, RISCVInsn opc, 574 TCGReg rs1, TCGReg rs2, uint32_t imm) 575{ 576 tcg_out32(s, encode_s(opc, rs1, rs2, imm)); 577} 578 579static void tcg_out_opc_branch(TCGContext *s, RISCVInsn opc, 580 TCGReg rs1, TCGReg rs2, uint32_t imm) 581{ 582 tcg_out32(s, encode_sb(opc, rs1, rs2, imm)); 583} 584 585static void tcg_out_opc_upper(TCGContext *s, RISCVInsn opc, 586 TCGReg rd, uint32_t imm) 587{ 588 tcg_out32(s, encode_u(opc, rd, imm)); 589} 590 591static void tcg_out_opc_jump(TCGContext *s, RISCVInsn opc, 592 TCGReg rd, uint32_t imm) 593{ 594 tcg_out32(s, encode_uj(opc, rd, imm)); 595} 596 597static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 598{ 599 int i; 600 for (i = 0; i < count; ++i) { 601 p[i] = OPC_NOP; 602 } 603} 604 605/* 606 * Relocations 607 */ 608 609static bool reloc_sbimm12(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 610{ 611 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 612 intptr_t offset = (intptr_t)target - (intptr_t)src_rx; 613 614 tcg_debug_assert((offset & 1) == 0); 615 if (offset == sextreg(offset, 0, 12)) { 616 *src_rw |= encode_sbimm12(offset); 617 return true; 618 } 619 620 return false; 621} 622 623static bool reloc_jimm20(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 624{ 625 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 626 intptr_t offset = (intptr_t)target - (intptr_t)src_rx; 627 628 tcg_debug_assert((offset & 1) == 0); 629 if (offset == sextreg(offset, 0, 20)) { 630 *src_rw |= encode_ujimm20(offset); 631 return true; 632 } 633 634 return false; 635} 636 637static bool reloc_call(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 638{ 639 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 640 intptr_t offset = (intptr_t)target - (intptr_t)src_rx; 641 int32_t lo = sextreg(offset, 0, 12); 642 int32_t hi = offset - lo; 643 644 if (offset == hi + lo) { 645 src_rw[0] |= encode_uimm20(hi); 646 src_rw[1] |= encode_imm12(lo); 647 return true; 648 } 649 650 return false; 651} 652 653static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 654 intptr_t value, intptr_t addend) 655{ 656 tcg_debug_assert(addend == 0); 657 switch (type) { 658 case R_RISCV_BRANCH: 659 return reloc_sbimm12(code_ptr, (tcg_insn_unit *)value); 660 case R_RISCV_JAL: 661 return reloc_jimm20(code_ptr, (tcg_insn_unit *)value); 662 case R_RISCV_CALL: 663 return reloc_call(code_ptr, (tcg_insn_unit *)value); 664 default: 665 g_assert_not_reached(); 666 } 667} 668 669/* 670 * RISC-V vector instruction emitters 671 */ 672 673/* 674 * Vector registers uses the same 5 lower bits as GPR registers, 675 * and vm=0 (vm = false) means vector masking ENABLED. 676 * With RVV 1.0, vs2 is the first operand, while rs1/imm is the 677 * second operand. 678 */ 679static void tcg_out_opc_vv(TCGContext *s, RISCVInsn opc, 680 TCGReg vd, TCGReg vs2, TCGReg vs1) 681{ 682 tcg_out32(s, encode_v(opc, vd, vs1, vs2, true)); 683} 684 685static void tcg_out_opc_vx(TCGContext *s, RISCVInsn opc, 686 TCGReg vd, TCGReg vs2, TCGReg rs1) 687{ 688 tcg_out32(s, encode_v(opc, vd, rs1, vs2, true)); 689} 690 691static void tcg_out_opc_vi(TCGContext *s, RISCVInsn opc, 692 TCGReg vd, TCGReg vs2, int32_t imm) 693{ 694 tcg_out32(s, encode_vi(opc, vd, imm, vs2, true)); 695} 696 697static void tcg_out_opc_vv_vi(TCGContext *s, RISCVInsn o_vv, RISCVInsn o_vi, 698 TCGReg vd, TCGReg vs2, TCGArg vi1, int c_vi1) 699{ 700 if (c_vi1) { 701 tcg_out_opc_vi(s, o_vi, vd, vs2, vi1); 702 } else { 703 tcg_out_opc_vv(s, o_vv, vd, vs2, vi1); 704 } 705} 706 707static void tcg_out_opc_vim_mask(TCGContext *s, RISCVInsn opc, TCGReg vd, 708 TCGReg vs2, int32_t imm) 709{ 710 tcg_out32(s, encode_vi(opc, vd, imm, vs2, false)); 711} 712 713static void tcg_out_opc_vvm_mask(TCGContext *s, RISCVInsn opc, TCGReg vd, 714 TCGReg vs2, TCGReg vs1) 715{ 716 tcg_out32(s, encode_v(opc, vd, vs1, vs2, false)); 717} 718 719typedef struct VsetCache { 720 uint32_t movi_insn; 721 uint32_t vset_insn; 722} VsetCache; 723 724static VsetCache riscv_vset_cache[3][4]; 725 726static void set_vtype(TCGContext *s, TCGType type, MemOp vsew) 727{ 728 const VsetCache *p = &riscv_vset_cache[type - TCG_TYPE_V64][vsew]; 729 730 s->riscv_cur_type = type; 731 s->riscv_cur_vsew = vsew; 732 733 if (p->movi_insn) { 734 tcg_out32(s, p->movi_insn); 735 } 736 tcg_out32(s, p->vset_insn); 737} 738 739static MemOp set_vtype_len(TCGContext *s, TCGType type) 740{ 741 if (type != s->riscv_cur_type) { 742 set_vtype(s, type, MO_64); 743 } 744 return s->riscv_cur_vsew; 745} 746 747static void set_vtype_len_sew(TCGContext *s, TCGType type, MemOp vsew) 748{ 749 if (type != s->riscv_cur_type || vsew != s->riscv_cur_vsew) { 750 set_vtype(s, type, vsew); 751 } 752} 753 754/* 755 * TCG intrinsics 756 */ 757 758static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 759{ 760 if (ret == arg) { 761 return true; 762 } 763 switch (type) { 764 case TCG_TYPE_I32: 765 case TCG_TYPE_I64: 766 tcg_out_opc_imm(s, OPC_ADDI, ret, arg, 0); 767 break; 768 case TCG_TYPE_V64: 769 case TCG_TYPE_V128: 770 case TCG_TYPE_V256: 771 { 772 int lmul = type - riscv_lg2_vlenb; 773 int nf = 1 << MAX(lmul, 0); 774 tcg_out_opc_vi(s, OPC_VMVNR_V, ret, arg, nf - 1); 775 } 776 break; 777 default: 778 g_assert_not_reached(); 779 } 780 return true; 781} 782 783static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, 784 tcg_target_long val) 785{ 786 tcg_target_long lo, hi, tmp; 787 int shift, ret; 788 789 if (type == TCG_TYPE_I32) { 790 val = (int32_t)val; 791 } 792 793 lo = sextreg(val, 0, 12); 794 if (val == lo) { 795 tcg_out_opc_imm(s, OPC_ADDI, rd, TCG_REG_ZERO, lo); 796 return; 797 } 798 799 hi = val - lo; 800 if (val == (int32_t)val) { 801 tcg_out_opc_upper(s, OPC_LUI, rd, hi); 802 if (lo != 0) { 803 tcg_out_opc_imm(s, OPC_ADDIW, rd, rd, lo); 804 } 805 return; 806 } 807 808 tmp = tcg_pcrel_diff(s, (void *)val); 809 if (tmp == (int32_t)tmp) { 810 tcg_out_opc_upper(s, OPC_AUIPC, rd, 0); 811 tcg_out_opc_imm(s, OPC_ADDI, rd, rd, 0); 812 ret = reloc_call(s->code_ptr - 2, (const tcg_insn_unit *)val); 813 tcg_debug_assert(ret == true); 814 return; 815 } 816 817 /* Look for a single 20-bit section. */ 818 shift = ctz64(val); 819 tmp = val >> shift; 820 if (tmp == sextreg(tmp, 0, 20)) { 821 tcg_out_opc_upper(s, OPC_LUI, rd, tmp << 12); 822 if (shift > 12) { 823 tcg_out_opc_imm(s, OPC_SLLI, rd, rd, shift - 12); 824 } else { 825 tcg_out_opc_imm(s, OPC_SRAI, rd, rd, 12 - shift); 826 } 827 return; 828 } 829 830 /* Look for a few high zero bits, with lots of bits set in the middle. */ 831 shift = clz64(val); 832 tmp = val << shift; 833 if (tmp == sextreg(tmp, 12, 20) << 12) { 834 tcg_out_opc_upper(s, OPC_LUI, rd, tmp); 835 tcg_out_opc_imm(s, OPC_SRLI, rd, rd, shift); 836 return; 837 } else if (tmp == sextreg(tmp, 0, 12)) { 838 tcg_out_opc_imm(s, OPC_ADDI, rd, TCG_REG_ZERO, tmp); 839 tcg_out_opc_imm(s, OPC_SRLI, rd, rd, shift); 840 return; 841 } 842 843 /* Drop into the constant pool. */ 844 new_pool_label(s, val, R_RISCV_CALL, s->code_ptr, 0); 845 tcg_out_opc_upper(s, OPC_AUIPC, rd, 0); 846 tcg_out_opc_imm(s, OPC_LD, rd, rd, 0); 847} 848 849static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 850{ 851 return false; 852} 853 854static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 855 tcg_target_long imm) 856{ 857 /* This function is only used for passing structs by reference. */ 858 g_assert_not_reached(); 859} 860 861static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg) 862{ 863 tcg_out_opc_imm(s, OPC_ANDI, ret, arg, 0xff); 864} 865 866static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg) 867{ 868 if (cpuinfo & CPUINFO_ZBB) { 869 tcg_out_opc_reg(s, OPC_ZEXT_H, ret, arg, TCG_REG_ZERO); 870 } else { 871 tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16); 872 tcg_out_opc_imm(s, OPC_SRLIW, ret, ret, 16); 873 } 874} 875 876static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) 877{ 878 if (cpuinfo & CPUINFO_ZBA) { 879 tcg_out_opc_reg(s, OPC_ADD_UW, ret, arg, TCG_REG_ZERO); 880 } else { 881 tcg_out_opc_imm(s, OPC_SLLI, ret, arg, 32); 882 tcg_out_opc_imm(s, OPC_SRLI, ret, ret, 32); 883 } 884} 885 886static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 887{ 888 if (cpuinfo & CPUINFO_ZBB) { 889 tcg_out_opc_imm(s, OPC_SEXT_B, ret, arg, 0); 890 } else { 891 tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 24); 892 tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 24); 893 } 894} 895 896static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 897{ 898 if (cpuinfo & CPUINFO_ZBB) { 899 tcg_out_opc_imm(s, OPC_SEXT_H, ret, arg, 0); 900 } else { 901 tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16); 902 tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 16); 903 } 904} 905 906static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg) 907{ 908 tcg_out_opc_imm(s, OPC_ADDIW, ret, arg, 0); 909} 910 911static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg) 912{ 913 if (ret != arg) { 914 tcg_out_ext32s(s, ret, arg); 915 } 916} 917 918static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg) 919{ 920 tcg_out_ext32u(s, ret, arg); 921} 922 923static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg ret, TCGReg arg) 924{ 925 tcg_out_ext32s(s, ret, arg); 926} 927 928static void tcg_out_ldst(TCGContext *s, RISCVInsn opc, TCGReg data, 929 TCGReg addr, intptr_t offset) 930{ 931 intptr_t imm12 = sextreg(offset, 0, 12); 932 933 if (offset != imm12) { 934 intptr_t diff = tcg_pcrel_diff(s, (void *)offset); 935 936 if (addr == TCG_REG_ZERO && diff == (int32_t)diff) { 937 imm12 = sextreg(diff, 0, 12); 938 tcg_out_opc_upper(s, OPC_AUIPC, TCG_REG_TMP2, diff - imm12); 939 } else { 940 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP2, offset - imm12); 941 if (addr != TCG_REG_ZERO) { 942 tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, addr); 943 } 944 } 945 addr = TCG_REG_TMP2; 946 } 947 948 switch (opc) { 949 case OPC_SB: 950 case OPC_SH: 951 case OPC_SW: 952 case OPC_SD: 953 tcg_out_opc_store(s, opc, addr, data, imm12); 954 break; 955 case OPC_LB: 956 case OPC_LBU: 957 case OPC_LH: 958 case OPC_LHU: 959 case OPC_LW: 960 case OPC_LWU: 961 case OPC_LD: 962 tcg_out_opc_imm(s, opc, data, addr, imm12); 963 break; 964 default: 965 g_assert_not_reached(); 966 } 967} 968 969static void tcg_out_vec_ldst(TCGContext *s, RISCVInsn opc, TCGReg data, 970 TCGReg addr, intptr_t offset) 971{ 972 tcg_debug_assert(data >= TCG_REG_V0); 973 tcg_debug_assert(addr < TCG_REG_V0); 974 975 if (offset) { 976 tcg_debug_assert(addr != TCG_REG_ZERO); 977 if (offset == sextreg(offset, 0, 12)) { 978 tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_TMP0, addr, offset); 979 } else { 980 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, offset); 981 tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP0, addr); 982 } 983 addr = TCG_REG_TMP0; 984 } 985 tcg_out32(s, encode_v(opc, data, addr, 0, true)); 986} 987 988static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, 989 TCGReg arg1, intptr_t arg2) 990{ 991 RISCVInsn insn; 992 993 switch (type) { 994 case TCG_TYPE_I32: 995 tcg_out_ldst(s, OPC_LW, arg, arg1, arg2); 996 break; 997 case TCG_TYPE_I64: 998 tcg_out_ldst(s, OPC_LD, arg, arg1, arg2); 999 break; 1000 case TCG_TYPE_V64: 1001 case TCG_TYPE_V128: 1002 case TCG_TYPE_V256: 1003 if (type >= riscv_lg2_vlenb) { 1004 static const RISCVInsn whole_reg_ld[] = { 1005 OPC_VL1RE64_V, OPC_VL2RE64_V, OPC_VL4RE64_V, OPC_VL8RE64_V 1006 }; 1007 unsigned idx = type - riscv_lg2_vlenb; 1008 1009 tcg_debug_assert(idx < ARRAY_SIZE(whole_reg_ld)); 1010 insn = whole_reg_ld[idx]; 1011 } else { 1012 static const RISCVInsn unit_stride_ld[] = { 1013 OPC_VLE8_V, OPC_VLE16_V, OPC_VLE32_V, OPC_VLE64_V 1014 }; 1015 MemOp prev_vsew = set_vtype_len(s, type); 1016 1017 tcg_debug_assert(prev_vsew < ARRAY_SIZE(unit_stride_ld)); 1018 insn = unit_stride_ld[prev_vsew]; 1019 } 1020 tcg_out_vec_ldst(s, insn, arg, arg1, arg2); 1021 break; 1022 default: 1023 g_assert_not_reached(); 1024 } 1025} 1026 1027static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 1028 TCGReg arg1, intptr_t arg2) 1029{ 1030 RISCVInsn insn; 1031 1032 switch (type) { 1033 case TCG_TYPE_I32: 1034 tcg_out_ldst(s, OPC_SW, arg, arg1, arg2); 1035 break; 1036 case TCG_TYPE_I64: 1037 tcg_out_ldst(s, OPC_SD, arg, arg1, arg2); 1038 break; 1039 case TCG_TYPE_V64: 1040 case TCG_TYPE_V128: 1041 case TCG_TYPE_V256: 1042 if (type >= riscv_lg2_vlenb) { 1043 static const RISCVInsn whole_reg_st[] = { 1044 OPC_VS1R_V, OPC_VS2R_V, OPC_VS4R_V, OPC_VS8R_V 1045 }; 1046 unsigned idx = type - riscv_lg2_vlenb; 1047 1048 tcg_debug_assert(idx < ARRAY_SIZE(whole_reg_st)); 1049 insn = whole_reg_st[idx]; 1050 } else { 1051 static const RISCVInsn unit_stride_st[] = { 1052 OPC_VSE8_V, OPC_VSE16_V, OPC_VSE32_V, OPC_VSE64_V 1053 }; 1054 MemOp prev_vsew = set_vtype_len(s, type); 1055 1056 tcg_debug_assert(prev_vsew < ARRAY_SIZE(unit_stride_st)); 1057 insn = unit_stride_st[prev_vsew]; 1058 } 1059 tcg_out_vec_ldst(s, insn, arg, arg1, arg2); 1060 break; 1061 default: 1062 g_assert_not_reached(); 1063 } 1064} 1065 1066static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 1067 TCGReg base, intptr_t ofs) 1068{ 1069 if (val == 0) { 1070 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); 1071 return true; 1072 } 1073 return false; 1074} 1075 1076static void tcg_out_addsub2(TCGContext *s, 1077 TCGReg rl, TCGReg rh, 1078 TCGReg al, TCGReg ah, 1079 TCGArg bl, TCGArg bh, 1080 bool cbl, bool cbh, bool is_sub, bool is32bit) 1081{ 1082 const RISCVInsn opc_add = is32bit ? OPC_ADDW : OPC_ADD; 1083 const RISCVInsn opc_addi = is32bit ? OPC_ADDIW : OPC_ADDI; 1084 const RISCVInsn opc_sub = is32bit ? OPC_SUBW : OPC_SUB; 1085 TCGReg th = TCG_REG_TMP1; 1086 1087 /* If we have a negative constant such that negating it would 1088 make the high part zero, we can (usually) eliminate one insn. */ 1089 if (cbl && cbh && bh == -1 && bl != 0) { 1090 bl = -bl; 1091 bh = 0; 1092 is_sub = !is_sub; 1093 } 1094 1095 /* By operating on the high part first, we get to use the final 1096 carry operation to move back from the temporary. */ 1097 if (!cbh) { 1098 tcg_out_opc_reg(s, (is_sub ? opc_sub : opc_add), th, ah, bh); 1099 } else if (bh != 0 || ah == rl) { 1100 tcg_out_opc_imm(s, opc_addi, th, ah, (is_sub ? -bh : bh)); 1101 } else { 1102 th = ah; 1103 } 1104 1105 /* Note that tcg optimization should eliminate the bl == 0 case. */ 1106 if (is_sub) { 1107 if (cbl) { 1108 tcg_out_opc_imm(s, OPC_SLTIU, TCG_REG_TMP0, al, bl); 1109 tcg_out_opc_imm(s, opc_addi, rl, al, -bl); 1110 } else { 1111 tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_TMP0, al, bl); 1112 tcg_out_opc_reg(s, opc_sub, rl, al, bl); 1113 } 1114 tcg_out_opc_reg(s, opc_sub, rh, th, TCG_REG_TMP0); 1115 } else { 1116 if (cbl) { 1117 tcg_out_opc_imm(s, opc_addi, rl, al, bl); 1118 tcg_out_opc_imm(s, OPC_SLTIU, TCG_REG_TMP0, rl, bl); 1119 } else if (al == bl) { 1120 /* 1121 * If the input regs overlap, this is a simple doubling 1122 * and carry-out is the input msb. This special case is 1123 * required when the output reg overlaps the input, 1124 * but we might as well use it always. 1125 */ 1126 tcg_out_opc_imm(s, OPC_SLTI, TCG_REG_TMP0, al, 0); 1127 tcg_out_opc_reg(s, opc_add, rl, al, al); 1128 } else { 1129 tcg_out_opc_reg(s, opc_add, rl, al, bl); 1130 tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_TMP0, 1131 rl, (rl == bl ? al : bl)); 1132 } 1133 tcg_out_opc_reg(s, opc_add, rh, th, TCG_REG_TMP0); 1134 } 1135} 1136 1137static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 1138 TCGReg dst, TCGReg src) 1139{ 1140 set_vtype_len_sew(s, type, vece); 1141 tcg_out_opc_vx(s, OPC_VMV_V_X, dst, 0, src); 1142 return true; 1143} 1144 1145static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 1146 TCGReg dst, TCGReg base, intptr_t offset) 1147{ 1148 tcg_out_ld(s, TCG_TYPE_REG, TCG_REG_TMP0, base, offset); 1149 return tcg_out_dup_vec(s, type, vece, dst, TCG_REG_TMP0); 1150} 1151 1152static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 1153 TCGReg dst, int64_t arg) 1154{ 1155 /* Arg is replicated by VECE; extract the highest element. */ 1156 arg >>= (-8 << vece) & 63; 1157 1158 if (arg >= -16 && arg < 16) { 1159 if (arg == 0 || arg == -1) { 1160 set_vtype_len(s, type); 1161 } else { 1162 set_vtype_len_sew(s, type, vece); 1163 } 1164 tcg_out_opc_vi(s, OPC_VMV_V_I, dst, 0, arg); 1165 return; 1166 } 1167 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP0, arg); 1168 tcg_out_dup_vec(s, type, vece, dst, TCG_REG_TMP0); 1169} 1170 1171static const struct { 1172 RISCVInsn op; 1173 bool swap; 1174} tcg_brcond_to_riscv[] = { 1175 [TCG_COND_EQ] = { OPC_BEQ, false }, 1176 [TCG_COND_NE] = { OPC_BNE, false }, 1177 [TCG_COND_LT] = { OPC_BLT, false }, 1178 [TCG_COND_GE] = { OPC_BGE, false }, 1179 [TCG_COND_LE] = { OPC_BGE, true }, 1180 [TCG_COND_GT] = { OPC_BLT, true }, 1181 [TCG_COND_LTU] = { OPC_BLTU, false }, 1182 [TCG_COND_GEU] = { OPC_BGEU, false }, 1183 [TCG_COND_LEU] = { OPC_BGEU, true }, 1184 [TCG_COND_GTU] = { OPC_BLTU, true } 1185}; 1186 1187static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, 1188 TCGReg arg2, TCGLabel *l) 1189{ 1190 RISCVInsn op = tcg_brcond_to_riscv[cond].op; 1191 1192 tcg_debug_assert(op != 0); 1193 1194 if (tcg_brcond_to_riscv[cond].swap) { 1195 TCGReg t = arg1; 1196 arg1 = arg2; 1197 arg2 = t; 1198 } 1199 1200 tcg_out_reloc(s, s->code_ptr, R_RISCV_BRANCH, l, 0); 1201 tcg_out_opc_branch(s, op, arg1, arg2, 0); 1202} 1203 1204#define SETCOND_INV TCG_TARGET_NB_REGS 1205#define SETCOND_NEZ (SETCOND_INV << 1) 1206#define SETCOND_FLAGS (SETCOND_INV | SETCOND_NEZ) 1207 1208static int tcg_out_setcond_int(TCGContext *s, TCGCond cond, TCGReg ret, 1209 TCGReg arg1, tcg_target_long arg2, bool c2) 1210{ 1211 int flags = 0; 1212 1213 switch (cond) { 1214 case TCG_COND_EQ: /* -> NE */ 1215 case TCG_COND_GE: /* -> LT */ 1216 case TCG_COND_GEU: /* -> LTU */ 1217 case TCG_COND_GT: /* -> LE */ 1218 case TCG_COND_GTU: /* -> LEU */ 1219 cond = tcg_invert_cond(cond); 1220 flags ^= SETCOND_INV; 1221 break; 1222 default: 1223 break; 1224 } 1225 1226 switch (cond) { 1227 case TCG_COND_LE: 1228 case TCG_COND_LEU: 1229 /* 1230 * If we have a constant input, the most efficient way to implement 1231 * LE is by adding 1 and using LT. Watch out for wrap around for LEU. 1232 * We don't need to care for this for LE because the constant input 1233 * is constrained to signed 12-bit, and 0x800 is representable in the 1234 * temporary register. 1235 */ 1236 if (c2) { 1237 if (cond == TCG_COND_LEU) { 1238 /* unsigned <= -1 is true */ 1239 if (arg2 == -1) { 1240 tcg_out_movi(s, TCG_TYPE_REG, ret, !(flags & SETCOND_INV)); 1241 return ret; 1242 } 1243 cond = TCG_COND_LTU; 1244 } else { 1245 cond = TCG_COND_LT; 1246 } 1247 tcg_debug_assert(arg2 <= 0x7ff); 1248 if (++arg2 == 0x800) { 1249 tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_TMP0, arg2); 1250 arg2 = TCG_REG_TMP0; 1251 c2 = false; 1252 } 1253 } else { 1254 TCGReg tmp = arg2; 1255 arg2 = arg1; 1256 arg1 = tmp; 1257 cond = tcg_swap_cond(cond); /* LE -> GE */ 1258 cond = tcg_invert_cond(cond); /* GE -> LT */ 1259 flags ^= SETCOND_INV; 1260 } 1261 break; 1262 default: 1263 break; 1264 } 1265 1266 switch (cond) { 1267 case TCG_COND_NE: 1268 flags |= SETCOND_NEZ; 1269 if (!c2) { 1270 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); 1271 } else if (arg2 == 0) { 1272 ret = arg1; 1273 } else { 1274 tcg_out_opc_imm(s, OPC_XORI, ret, arg1, arg2); 1275 } 1276 break; 1277 1278 case TCG_COND_LT: 1279 if (c2) { 1280 tcg_out_opc_imm(s, OPC_SLTI, ret, arg1, arg2); 1281 } else { 1282 tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2); 1283 } 1284 break; 1285 1286 case TCG_COND_LTU: 1287 if (c2) { 1288 tcg_out_opc_imm(s, OPC_SLTIU, ret, arg1, arg2); 1289 } else { 1290 tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2); 1291 } 1292 break; 1293 1294 default: 1295 g_assert_not_reached(); 1296 } 1297 1298 return ret | flags; 1299} 1300 1301static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret, 1302 TCGReg arg1, tcg_target_long arg2, bool c2) 1303{ 1304 int tmpflags = tcg_out_setcond_int(s, cond, ret, arg1, arg2, c2); 1305 1306 if (tmpflags != ret) { 1307 TCGReg tmp = tmpflags & ~SETCOND_FLAGS; 1308 1309 switch (tmpflags & SETCOND_FLAGS) { 1310 case SETCOND_INV: 1311 /* Intermediate result is boolean: simply invert. */ 1312 tcg_out_opc_imm(s, OPC_XORI, ret, tmp, 1); 1313 break; 1314 case SETCOND_NEZ: 1315 /* Intermediate result is zero/non-zero: test != 0. */ 1316 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, tmp); 1317 break; 1318 case SETCOND_NEZ | SETCOND_INV: 1319 /* Intermediate result is zero/non-zero: test == 0. */ 1320 tcg_out_opc_imm(s, OPC_SLTIU, ret, tmp, 1); 1321 break; 1322 default: 1323 g_assert_not_reached(); 1324 } 1325 } 1326} 1327 1328static void tcg_out_negsetcond(TCGContext *s, TCGCond cond, TCGReg ret, 1329 TCGReg arg1, tcg_target_long arg2, bool c2) 1330{ 1331 int tmpflags; 1332 TCGReg tmp; 1333 1334 /* For LT/GE comparison against 0, replicate the sign bit. */ 1335 if (c2 && arg2 == 0) { 1336 switch (cond) { 1337 case TCG_COND_GE: 1338 tcg_out_opc_imm(s, OPC_XORI, ret, arg1, -1); 1339 arg1 = ret; 1340 /* fall through */ 1341 case TCG_COND_LT: 1342 tcg_out_opc_imm(s, OPC_SRAI, ret, arg1, TCG_TARGET_REG_BITS - 1); 1343 return; 1344 default: 1345 break; 1346 } 1347 } 1348 1349 tmpflags = tcg_out_setcond_int(s, cond, ret, arg1, arg2, c2); 1350 tmp = tmpflags & ~SETCOND_FLAGS; 1351 1352 /* If intermediate result is zero/non-zero: test != 0. */ 1353 if (tmpflags & SETCOND_NEZ) { 1354 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, tmp); 1355 tmp = ret; 1356 } 1357 1358 /* Produce the 0/-1 result. */ 1359 if (tmpflags & SETCOND_INV) { 1360 tcg_out_opc_imm(s, OPC_ADDI, ret, tmp, -1); 1361 } else { 1362 tcg_out_opc_reg(s, OPC_SUB, ret, TCG_REG_ZERO, tmp); 1363 } 1364} 1365 1366static void tcg_out_movcond_zicond(TCGContext *s, TCGReg ret, TCGReg test_ne, 1367 int val1, bool c_val1, 1368 int val2, bool c_val2) 1369{ 1370 if (val1 == 0) { 1371 if (c_val2) { 1372 tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_TMP1, val2); 1373 val2 = TCG_REG_TMP1; 1374 } 1375 tcg_out_opc_reg(s, OPC_CZERO_NEZ, ret, val2, test_ne); 1376 return; 1377 } 1378 1379 if (val2 == 0) { 1380 if (c_val1) { 1381 tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_TMP1, val1); 1382 val1 = TCG_REG_TMP1; 1383 } 1384 tcg_out_opc_reg(s, OPC_CZERO_EQZ, ret, val1, test_ne); 1385 return; 1386 } 1387 1388 if (c_val2) { 1389 if (c_val1) { 1390 tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_TMP1, val1 - val2); 1391 } else { 1392 tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_TMP1, val1, -val2); 1393 } 1394 tcg_out_opc_reg(s, OPC_CZERO_EQZ, ret, TCG_REG_TMP1, test_ne); 1395 tcg_out_opc_imm(s, OPC_ADDI, ret, ret, val2); 1396 return; 1397 } 1398 1399 if (c_val1) { 1400 tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_TMP1, val2, -val1); 1401 tcg_out_opc_reg(s, OPC_CZERO_NEZ, ret, TCG_REG_TMP1, test_ne); 1402 tcg_out_opc_imm(s, OPC_ADDI, ret, ret, val1); 1403 return; 1404 } 1405 1406 tcg_out_opc_reg(s, OPC_CZERO_NEZ, TCG_REG_TMP1, val2, test_ne); 1407 tcg_out_opc_reg(s, OPC_CZERO_EQZ, TCG_REG_TMP0, val1, test_ne); 1408 tcg_out_opc_reg(s, OPC_OR, ret, TCG_REG_TMP0, TCG_REG_TMP1); 1409} 1410 1411static void tcg_out_movcond_br1(TCGContext *s, TCGCond cond, TCGReg ret, 1412 TCGReg cmp1, TCGReg cmp2, 1413 int val, bool c_val) 1414{ 1415 RISCVInsn op; 1416 int disp = 8; 1417 1418 tcg_debug_assert((unsigned)cond < ARRAY_SIZE(tcg_brcond_to_riscv)); 1419 op = tcg_brcond_to_riscv[cond].op; 1420 tcg_debug_assert(op != 0); 1421 1422 if (tcg_brcond_to_riscv[cond].swap) { 1423 tcg_out_opc_branch(s, op, cmp2, cmp1, disp); 1424 } else { 1425 tcg_out_opc_branch(s, op, cmp1, cmp2, disp); 1426 } 1427 if (c_val) { 1428 tcg_out_opc_imm(s, OPC_ADDI, ret, TCG_REG_ZERO, val); 1429 } else { 1430 tcg_out_opc_imm(s, OPC_ADDI, ret, val, 0); 1431 } 1432} 1433 1434static void tcg_out_movcond_br2(TCGContext *s, TCGCond cond, TCGReg ret, 1435 TCGReg cmp1, TCGReg cmp2, 1436 int val1, bool c_val1, 1437 int val2, bool c_val2) 1438{ 1439 TCGReg tmp; 1440 1441 /* TCG optimizer reorders to prefer ret matching val2. */ 1442 if (!c_val2 && ret == val2) { 1443 cond = tcg_invert_cond(cond); 1444 tcg_out_movcond_br1(s, cond, ret, cmp1, cmp2, val1, c_val1); 1445 return; 1446 } 1447 1448 if (!c_val1 && ret == val1) { 1449 tcg_out_movcond_br1(s, cond, ret, cmp1, cmp2, val2, c_val2); 1450 return; 1451 } 1452 1453 tmp = (ret == cmp1 || ret == cmp2 ? TCG_REG_TMP1 : ret); 1454 if (c_val1) { 1455 tcg_out_movi(s, TCG_TYPE_REG, tmp, val1); 1456 } else { 1457 tcg_out_mov(s, TCG_TYPE_REG, tmp, val1); 1458 } 1459 tcg_out_movcond_br1(s, cond, tmp, cmp1, cmp2, val2, c_val2); 1460 tcg_out_mov(s, TCG_TYPE_REG, ret, tmp); 1461} 1462 1463static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, 1464 TCGReg cmp1, int cmp2, bool c_cmp2, 1465 TCGReg val1, bool c_val1, 1466 TCGReg val2, bool c_val2) 1467{ 1468 int tmpflags; 1469 TCGReg t; 1470 1471 if (!(cpuinfo & CPUINFO_ZICOND) && (!c_cmp2 || cmp2 == 0)) { 1472 tcg_out_movcond_br2(s, cond, ret, cmp1, cmp2, 1473 val1, c_val1, val2, c_val2); 1474 return; 1475 } 1476 1477 tmpflags = tcg_out_setcond_int(s, cond, TCG_REG_TMP0, cmp1, cmp2, c_cmp2); 1478 t = tmpflags & ~SETCOND_FLAGS; 1479 1480 if (cpuinfo & CPUINFO_ZICOND) { 1481 if (tmpflags & SETCOND_INV) { 1482 tcg_out_movcond_zicond(s, ret, t, val2, c_val2, val1, c_val1); 1483 } else { 1484 tcg_out_movcond_zicond(s, ret, t, val1, c_val1, val2, c_val2); 1485 } 1486 } else { 1487 cond = tmpflags & SETCOND_INV ? TCG_COND_EQ : TCG_COND_NE; 1488 tcg_out_movcond_br2(s, cond, ret, t, TCG_REG_ZERO, 1489 val1, c_val1, val2, c_val2); 1490 } 1491} 1492 1493static void tcg_out_cltz(TCGContext *s, TCGType type, RISCVInsn insn, 1494 TCGReg ret, TCGReg src1, int src2, bool c_src2) 1495{ 1496 tcg_out_opc_imm(s, insn, ret, src1, 0); 1497 1498 if (!c_src2 || src2 != (type == TCG_TYPE_I32 ? 32 : 64)) { 1499 /* 1500 * The requested zero result does not match the insn, so adjust. 1501 * Note that constraints put 'ret' in a new register, so the 1502 * computation above did not clobber either 'src1' or 'src2'. 1503 */ 1504 tcg_out_movcond(s, TCG_COND_EQ, ret, src1, 0, true, 1505 src2, c_src2, ret, false); 1506 } 1507} 1508 1509static void tcg_out_cmpsel(TCGContext *s, TCGType type, unsigned vece, 1510 TCGCond cond, TCGReg ret, 1511 TCGReg cmp1, TCGReg cmp2, bool c_cmp2, 1512 TCGReg val1, bool c_val1, 1513 TCGReg val2, bool c_val2) 1514{ 1515 set_vtype_len_sew(s, type, vece); 1516 1517 /* Use only vmerge_vim if possible, by inverting the test. */ 1518 if (c_val2 && !c_val1) { 1519 TCGArg temp = val1; 1520 cond = tcg_invert_cond(cond); 1521 val1 = val2; 1522 val2 = temp; 1523 c_val1 = true; 1524 c_val2 = false; 1525 } 1526 1527 /* Perform the comparison into V0 mask. */ 1528 if (c_cmp2) { 1529 tcg_out_opc_vi(s, tcg_cmpcond_to_rvv_vi[cond].op, TCG_REG_V0, cmp1, 1530 cmp2 - tcg_cmpcond_to_rvv_vi[cond].adjust); 1531 } else if (tcg_cmpcond_to_rvv_vv[cond].swap) { 1532 tcg_out_opc_vv(s, tcg_cmpcond_to_rvv_vv[cond].op, 1533 TCG_REG_V0, cmp2, cmp1); 1534 } else { 1535 tcg_out_opc_vv(s, tcg_cmpcond_to_rvv_vv[cond].op, 1536 TCG_REG_V0, cmp1, cmp2); 1537 } 1538 if (c_val1) { 1539 if (c_val2) { 1540 tcg_out_opc_vi(s, OPC_VMV_V_I, ret, 0, val2); 1541 val2 = ret; 1542 } 1543 /* vd[i] == v0.mask[i] ? imm : vs2[i] */ 1544 tcg_out_opc_vim_mask(s, OPC_VMERGE_VIM, ret, val2, val1); 1545 } else { 1546 /* vd[i] == v0.mask[i] ? vs1[i] : vs2[i] */ 1547 tcg_out_opc_vvm_mask(s, OPC_VMERGE_VVM, ret, val2, val1); 1548 } 1549} 1550 1551static void tcg_out_vshifti(TCGContext *s, RISCVInsn opc_vi, RISCVInsn opc_vx, 1552 TCGReg dst, TCGReg src, unsigned imm) 1553{ 1554 if (imm < 32) { 1555 tcg_out_opc_vi(s, opc_vi, dst, src, imm); 1556 } else { 1557 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_TMP0, imm); 1558 tcg_out_opc_vx(s, opc_vx, dst, src, TCG_REG_TMP0); 1559 } 1560} 1561 1562static void init_setting_vtype(TCGContext *s) 1563{ 1564 s->riscv_cur_type = TCG_TYPE_COUNT; 1565} 1566 1567static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) 1568{ 1569 TCGReg link = tail ? TCG_REG_ZERO : TCG_REG_RA; 1570 ptrdiff_t offset = tcg_pcrel_diff(s, arg); 1571 int ret; 1572 1573 init_setting_vtype(s); 1574 1575 tcg_debug_assert((offset & 1) == 0); 1576 if (offset == sextreg(offset, 0, 20)) { 1577 /* short jump: -2097150 to 2097152 */ 1578 tcg_out_opc_jump(s, OPC_JAL, link, offset); 1579 } else if (offset == (int32_t)offset) { 1580 /* long jump: -2147483646 to 2147483648 */ 1581 tcg_out_opc_upper(s, OPC_AUIPC, TCG_REG_TMP0, 0); 1582 tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, 0); 1583 ret = reloc_call(s->code_ptr - 2, arg); 1584 tcg_debug_assert(ret == true); 1585 } else { 1586 /* far jump: 64-bit */ 1587 tcg_target_long imm = sextreg((tcg_target_long)arg, 0, 12); 1588 tcg_target_long base = (tcg_target_long)arg - imm; 1589 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, base); 1590 tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, imm); 1591 } 1592} 1593 1594static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg, 1595 const TCGHelperInfo *info) 1596{ 1597 tcg_out_call_int(s, arg, false); 1598} 1599 1600static void tcg_out_mb(TCGContext *s, TCGArg a0) 1601{ 1602 tcg_insn_unit insn = OPC_FENCE; 1603 1604 if (a0 & TCG_MO_LD_LD) { 1605 insn |= 0x02200000; 1606 } 1607 if (a0 & TCG_MO_ST_LD) { 1608 insn |= 0x01200000; 1609 } 1610 if (a0 & TCG_MO_LD_ST) { 1611 insn |= 0x02100000; 1612 } 1613 if (a0 & TCG_MO_ST_ST) { 1614 insn |= 0x01100000; 1615 } 1616 tcg_out32(s, insn); 1617} 1618 1619/* 1620 * Load/store and TLB 1621 */ 1622 1623static void tcg_out_goto(TCGContext *s, const tcg_insn_unit *target) 1624{ 1625 tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, 0); 1626 bool ok = reloc_jimm20(s->code_ptr - 1, target); 1627 tcg_debug_assert(ok); 1628} 1629 1630bool tcg_target_has_memory_bswap(MemOp memop) 1631{ 1632 return false; 1633} 1634 1635/* We have three temps, we might as well expose them. */ 1636static const TCGLdstHelperParam ldst_helper_param = { 1637 .ntmp = 3, .tmp = { TCG_REG_TMP0, TCG_REG_TMP1, TCG_REG_TMP2 } 1638}; 1639 1640static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1641{ 1642 MemOp opc = get_memop(l->oi); 1643 1644 /* resolve label address */ 1645 if (!reloc_sbimm12(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 1646 return false; 1647 } 1648 1649 /* call load helper */ 1650 tcg_out_ld_helper_args(s, l, &ldst_helper_param); 1651 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SSIZE], false); 1652 tcg_out_ld_helper_ret(s, l, true, &ldst_helper_param); 1653 1654 tcg_out_goto(s, l->raddr); 1655 return true; 1656} 1657 1658static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1659{ 1660 MemOp opc = get_memop(l->oi); 1661 1662 /* resolve label address */ 1663 if (!reloc_sbimm12(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 1664 return false; 1665 } 1666 1667 /* call store helper */ 1668 tcg_out_st_helper_args(s, l, &ldst_helper_param); 1669 tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE], false); 1670 1671 tcg_out_goto(s, l->raddr); 1672 return true; 1673} 1674 1675/* We expect to use a 12-bit negative offset from ENV. */ 1676#define MIN_TLB_MASK_TABLE_OFS -(1 << 11) 1677 1678/* 1679 * For system-mode, perform the TLB load and compare. 1680 * For user-mode, perform any required alignment tests. 1681 * In both cases, return a TCGLabelQemuLdst structure if the slow path 1682 * is required and fill in @h with the host address for the fast path. 1683 */ 1684static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase, 1685 TCGReg addr_reg, MemOpIdx oi, 1686 bool is_ld) 1687{ 1688 TCGType addr_type = s->addr_type; 1689 TCGLabelQemuLdst *ldst = NULL; 1690 MemOp opc = get_memop(oi); 1691 TCGAtomAlign aa; 1692 unsigned a_mask; 1693 1694 aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); 1695 a_mask = (1u << aa.align) - 1; 1696 1697 if (tcg_use_softmmu) { 1698 unsigned s_bits = opc & MO_SIZE; 1699 unsigned s_mask = (1u << s_bits) - 1; 1700 int mem_index = get_mmuidx(oi); 1701 int fast_ofs = tlb_mask_table_ofs(s, mem_index); 1702 int mask_ofs = fast_ofs + offsetof(CPUTLBDescFast, mask); 1703 int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table); 1704 int compare_mask; 1705 TCGReg addr_adj; 1706 1707 ldst = new_ldst_label(s); 1708 ldst->is_ld = is_ld; 1709 ldst->oi = oi; 1710 ldst->addr_reg = addr_reg; 1711 1712 init_setting_vtype(s); 1713 1714 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_AREG0, mask_ofs); 1715 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, table_ofs); 1716 1717 tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP2, addr_reg, 1718 s->page_bits - CPU_TLB_ENTRY_BITS); 1719 tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0); 1720 tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1); 1721 1722 /* 1723 * For aligned accesses, we check the first byte and include the 1724 * alignment bits within the address. For unaligned access, we 1725 * check that we don't cross pages using the address of the last 1726 * byte of the access. 1727 */ 1728 addr_adj = addr_reg; 1729 if (a_mask < s_mask) { 1730 addr_adj = TCG_REG_TMP0; 1731 tcg_out_opc_imm(s, addr_type == TCG_TYPE_I32 ? OPC_ADDIW : OPC_ADDI, 1732 addr_adj, addr_reg, s_mask - a_mask); 1733 } 1734 compare_mask = s->page_mask | a_mask; 1735 if (compare_mask == sextreg(compare_mask, 0, 12)) { 1736 tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr_adj, compare_mask); 1737 } else { 1738 tcg_out_movi(s, addr_type, TCG_REG_TMP1, compare_mask); 1739 tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP1, TCG_REG_TMP1, addr_adj); 1740 } 1741 1742 /* Load the tlb comparator and the addend. */ 1743 QEMU_BUILD_BUG_ON(HOST_BIG_ENDIAN); 1744 tcg_out_ld(s, addr_type, TCG_REG_TMP0, TCG_REG_TMP2, 1745 is_ld ? offsetof(CPUTLBEntry, addr_read) 1746 : offsetof(CPUTLBEntry, addr_write)); 1747 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2, 1748 offsetof(CPUTLBEntry, addend)); 1749 1750 /* Compare masked address with the TLB entry. */ 1751 ldst->label_ptr[0] = s->code_ptr; 1752 tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0); 1753 1754 /* TLB Hit - translate address using addend. */ 1755 if (addr_type != TCG_TYPE_I32) { 1756 tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, addr_reg, TCG_REG_TMP2); 1757 } else if (cpuinfo & CPUINFO_ZBA) { 1758 tcg_out_opc_reg(s, OPC_ADD_UW, TCG_REG_TMP0, 1759 addr_reg, TCG_REG_TMP2); 1760 } else { 1761 tcg_out_ext32u(s, TCG_REG_TMP0, addr_reg); 1762 tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, 1763 TCG_REG_TMP0, TCG_REG_TMP2); 1764 } 1765 *pbase = TCG_REG_TMP0; 1766 } else { 1767 TCGReg base; 1768 1769 if (a_mask) { 1770 ldst = new_ldst_label(s); 1771 ldst->is_ld = is_ld; 1772 ldst->oi = oi; 1773 ldst->addr_reg = addr_reg; 1774 1775 init_setting_vtype(s); 1776 1777 /* We are expecting alignment max 7, so we can always use andi. */ 1778 tcg_debug_assert(a_mask == sextreg(a_mask, 0, 12)); 1779 tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr_reg, a_mask); 1780 1781 ldst->label_ptr[0] = s->code_ptr; 1782 tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP1, TCG_REG_ZERO, 0); 1783 } 1784 1785 if (guest_base != 0) { 1786 base = TCG_REG_TMP0; 1787 if (addr_type != TCG_TYPE_I32) { 1788 tcg_out_opc_reg(s, OPC_ADD, base, addr_reg, 1789 TCG_GUEST_BASE_REG); 1790 } else if (cpuinfo & CPUINFO_ZBA) { 1791 tcg_out_opc_reg(s, OPC_ADD_UW, base, addr_reg, 1792 TCG_GUEST_BASE_REG); 1793 } else { 1794 tcg_out_ext32u(s, base, addr_reg); 1795 tcg_out_opc_reg(s, OPC_ADD, base, base, TCG_GUEST_BASE_REG); 1796 } 1797 } else if (addr_type != TCG_TYPE_I32) { 1798 base = addr_reg; 1799 } else { 1800 base = TCG_REG_TMP0; 1801 tcg_out_ext32u(s, base, addr_reg); 1802 } 1803 *pbase = base; 1804 } 1805 1806 return ldst; 1807} 1808 1809static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg val, 1810 TCGReg base, MemOp opc, TCGType type) 1811{ 1812 /* Byte swapping is left to middle-end expansion. */ 1813 tcg_debug_assert((opc & MO_BSWAP) == 0); 1814 1815 switch (opc & (MO_SSIZE)) { 1816 case MO_UB: 1817 tcg_out_opc_imm(s, OPC_LBU, val, base, 0); 1818 break; 1819 case MO_SB: 1820 tcg_out_opc_imm(s, OPC_LB, val, base, 0); 1821 break; 1822 case MO_UW: 1823 tcg_out_opc_imm(s, OPC_LHU, val, base, 0); 1824 break; 1825 case MO_SW: 1826 tcg_out_opc_imm(s, OPC_LH, val, base, 0); 1827 break; 1828 case MO_UL: 1829 if (type == TCG_TYPE_I64) { 1830 tcg_out_opc_imm(s, OPC_LWU, val, base, 0); 1831 break; 1832 } 1833 /* FALLTHRU */ 1834 case MO_SL: 1835 tcg_out_opc_imm(s, OPC_LW, val, base, 0); 1836 break; 1837 case MO_UQ: 1838 tcg_out_opc_imm(s, OPC_LD, val, base, 0); 1839 break; 1840 default: 1841 g_assert_not_reached(); 1842 } 1843} 1844 1845static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, 1846 MemOpIdx oi, TCGType data_type) 1847{ 1848 TCGLabelQemuLdst *ldst; 1849 TCGReg base; 1850 1851 ldst = prepare_host_addr(s, &base, addr_reg, oi, true); 1852 tcg_out_qemu_ld_direct(s, data_reg, base, get_memop(oi), data_type); 1853 1854 if (ldst) { 1855 ldst->type = data_type; 1856 ldst->datalo_reg = data_reg; 1857 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1858 } 1859} 1860 1861static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg val, 1862 TCGReg base, MemOp opc) 1863{ 1864 /* Byte swapping is left to middle-end expansion. */ 1865 tcg_debug_assert((opc & MO_BSWAP) == 0); 1866 1867 switch (opc & (MO_SSIZE)) { 1868 case MO_8: 1869 tcg_out_opc_store(s, OPC_SB, base, val, 0); 1870 break; 1871 case MO_16: 1872 tcg_out_opc_store(s, OPC_SH, base, val, 0); 1873 break; 1874 case MO_32: 1875 tcg_out_opc_store(s, OPC_SW, base, val, 0); 1876 break; 1877 case MO_64: 1878 tcg_out_opc_store(s, OPC_SD, base, val, 0); 1879 break; 1880 default: 1881 g_assert_not_reached(); 1882 } 1883} 1884 1885static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, 1886 MemOpIdx oi, TCGType data_type) 1887{ 1888 TCGLabelQemuLdst *ldst; 1889 TCGReg base; 1890 1891 ldst = prepare_host_addr(s, &base, addr_reg, oi, false); 1892 tcg_out_qemu_st_direct(s, data_reg, base, get_memop(oi)); 1893 1894 if (ldst) { 1895 ldst->type = data_type; 1896 ldst->datalo_reg = data_reg; 1897 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1898 } 1899} 1900 1901static const tcg_insn_unit *tb_ret_addr; 1902 1903static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) 1904{ 1905 /* Reuse the zeroing that exists for goto_ptr. */ 1906 if (a0 == 0) { 1907 tcg_out_call_int(s, tcg_code_gen_epilogue, true); 1908 } else { 1909 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A0, a0); 1910 tcg_out_call_int(s, tb_ret_addr, true); 1911 } 1912} 1913 1914static void tcg_out_goto_tb(TCGContext *s, int which) 1915{ 1916 /* Direct branch will be patched by tb_target_set_jmp_target. */ 1917 set_jmp_insn_offset(s, which); 1918 tcg_out32(s, OPC_JAL); 1919 1920 /* When branch is out of range, fall through to indirect. */ 1921 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_REG_ZERO, 1922 get_jmp_target_addr(s, which)); 1923 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_TMP0, 0); 1924 set_jmp_reset_offset(s, which); 1925} 1926 1927void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1928 uintptr_t jmp_rx, uintptr_t jmp_rw) 1929{ 1930 uintptr_t addr = tb->jmp_target_addr[n]; 1931 ptrdiff_t offset = addr - jmp_rx; 1932 tcg_insn_unit insn; 1933 1934 /* Either directly branch, or fall through to indirect branch. */ 1935 if (offset == sextreg(offset, 0, 20)) { 1936 insn = encode_uj(OPC_JAL, TCG_REG_ZERO, offset); 1937 } else { 1938 insn = OPC_NOP; 1939 } 1940 qatomic_set((uint32_t *)jmp_rw, insn); 1941 flush_idcache_range(jmp_rx, jmp_rw, 4); 1942} 1943 1944 1945static void tgen_add(TCGContext *s, TCGType type, 1946 TCGReg a0, TCGReg a1, TCGReg a2) 1947{ 1948 RISCVInsn insn = type == TCG_TYPE_I32 ? OPC_ADDW : OPC_ADD; 1949 tcg_out_opc_reg(s, insn, a0, a1, a2); 1950} 1951 1952static void tgen_addi(TCGContext *s, TCGType type, 1953 TCGReg a0, TCGReg a1, tcg_target_long a2) 1954{ 1955 RISCVInsn insn = type == TCG_TYPE_I32 ? OPC_ADDIW : OPC_ADDI; 1956 tcg_out_opc_imm(s, insn, a0, a1, a2); 1957} 1958 1959static const TCGOutOpBinary outop_add = { 1960 .base.static_constraint = C_O1_I2(r, r, rI), 1961 .out_rrr = tgen_add, 1962 .out_rri = tgen_addi, 1963}; 1964 1965static void tgen_and(TCGContext *s, TCGType type, 1966 TCGReg a0, TCGReg a1, TCGReg a2) 1967{ 1968 tcg_out_opc_reg(s, OPC_AND, a0, a1, a2); 1969} 1970 1971static void tgen_andi(TCGContext *s, TCGType type, 1972 TCGReg a0, TCGReg a1, tcg_target_long a2) 1973{ 1974 tcg_out_opc_imm(s, OPC_ANDI, a0, a1, a2); 1975} 1976 1977static const TCGOutOpBinary outop_and = { 1978 .base.static_constraint = C_O1_I2(r, r, rI), 1979 .out_rrr = tgen_and, 1980 .out_rri = tgen_andi, 1981}; 1982 1983static void tgen_andc(TCGContext *s, TCGType type, 1984 TCGReg a0, TCGReg a1, TCGReg a2) 1985{ 1986 tcg_out_opc_reg(s, OPC_ANDN, a0, a1, a2); 1987} 1988 1989static TCGConstraintSetIndex cset_zbb_rrr(TCGType type, unsigned flags) 1990{ 1991 return cpuinfo & CPUINFO_ZBB ? C_O1_I2(r, r, r) : C_NotImplemented; 1992} 1993 1994static const TCGOutOpBinary outop_andc = { 1995 .base.static_constraint = C_Dynamic, 1996 .base.dynamic_constraint = cset_zbb_rrr, 1997 .out_rrr = tgen_andc, 1998}; 1999 2000static void tgen_eqv(TCGContext *s, TCGType type, 2001 TCGReg a0, TCGReg a1, TCGReg a2) 2002{ 2003 tcg_out_opc_reg(s, OPC_XNOR, a0, a1, a2); 2004} 2005 2006static const TCGOutOpBinary outop_eqv = { 2007 .base.static_constraint = C_Dynamic, 2008 .base.dynamic_constraint = cset_zbb_rrr, 2009 .out_rrr = tgen_eqv, 2010}; 2011 2012static void tgen_mul(TCGContext *s, TCGType type, 2013 TCGReg a0, TCGReg a1, TCGReg a2) 2014{ 2015 RISCVInsn insn = type == TCG_TYPE_I32 ? OPC_MULW : OPC_MUL; 2016 tcg_out_opc_reg(s, insn, a0, a1, a2); 2017} 2018 2019static const TCGOutOpBinary outop_mul = { 2020 .base.static_constraint = C_O1_I2(r, r, r), 2021 .out_rrr = tgen_mul, 2022}; 2023 2024static const TCGOutOpBinary outop_nand = { 2025 .base.static_constraint = C_NotImplemented, 2026}; 2027 2028static const TCGOutOpBinary outop_nor = { 2029 .base.static_constraint = C_NotImplemented, 2030}; 2031 2032static void tgen_or(TCGContext *s, TCGType type, 2033 TCGReg a0, TCGReg a1, TCGReg a2) 2034{ 2035 tcg_out_opc_reg(s, OPC_OR, a0, a1, a2); 2036} 2037 2038static void tgen_ori(TCGContext *s, TCGType type, 2039 TCGReg a0, TCGReg a1, tcg_target_long a2) 2040{ 2041 tcg_out_opc_imm(s, OPC_ORI, a0, a1, a2); 2042} 2043 2044static const TCGOutOpBinary outop_or = { 2045 .base.static_constraint = C_O1_I2(r, r, rI), 2046 .out_rrr = tgen_or, 2047 .out_rri = tgen_ori, 2048}; 2049 2050static void tgen_orc(TCGContext *s, TCGType type, 2051 TCGReg a0, TCGReg a1, TCGReg a2) 2052{ 2053 tcg_out_opc_reg(s, OPC_ORN, a0, a1, a2); 2054} 2055 2056static const TCGOutOpBinary outop_orc = { 2057 .base.static_constraint = C_Dynamic, 2058 .base.dynamic_constraint = cset_zbb_rrr, 2059 .out_rrr = tgen_orc, 2060}; 2061 2062static void tgen_sub(TCGContext *s, TCGType type, 2063 TCGReg a0, TCGReg a1, TCGReg a2) 2064{ 2065 RISCVInsn insn = type == TCG_TYPE_I32 ? OPC_SUBW : OPC_SUB; 2066 tcg_out_opc_reg(s, insn, a0, a1, a2); 2067} 2068 2069static const TCGOutOpSubtract outop_sub = { 2070 .base.static_constraint = C_O1_I2(r, r, r), 2071 .out_rrr = tgen_sub, 2072}; 2073 2074static void tgen_xor(TCGContext *s, TCGType type, 2075 TCGReg a0, TCGReg a1, TCGReg a2) 2076{ 2077 tcg_out_opc_reg(s, OPC_XOR, a0, a1, a2); 2078} 2079 2080static void tgen_xori(TCGContext *s, TCGType type, 2081 TCGReg a0, TCGReg a1, tcg_target_long a2) 2082{ 2083 tcg_out_opc_imm(s, OPC_XORI, a0, a1, a2); 2084} 2085 2086static const TCGOutOpBinary outop_xor = { 2087 .base.static_constraint = C_O1_I2(r, r, rI), 2088 .out_rrr = tgen_xor, 2089 .out_rri = tgen_xori, 2090}; 2091 2092static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2093{ 2094 tgen_sub(s, type, a0, TCG_REG_ZERO, a1); 2095} 2096 2097static const TCGOutOpUnary outop_neg = { 2098 .base.static_constraint = C_O1_I1(r, r), 2099 .out_rr = tgen_neg, 2100}; 2101 2102static void tgen_not(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2103{ 2104 tgen_xori(s, type, a0, a1, -1); 2105} 2106 2107static const TCGOutOpUnary outop_not = { 2108 .base.static_constraint = C_O1_I1(r, r), 2109 .out_rr = tgen_not, 2110}; 2111 2112 2113static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, 2114 const TCGArg args[TCG_MAX_OP_ARGS], 2115 const int const_args[TCG_MAX_OP_ARGS]) 2116{ 2117 TCGArg a0 = args[0]; 2118 TCGArg a1 = args[1]; 2119 TCGArg a2 = args[2]; 2120 int c2 = const_args[2]; 2121 2122 switch (opc) { 2123 case INDEX_op_goto_ptr: 2124 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, a0, 0); 2125 break; 2126 2127 case INDEX_op_br: 2128 tcg_out_reloc(s, s->code_ptr, R_RISCV_JAL, arg_label(a0), 0); 2129 tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, 0); 2130 break; 2131 2132 case INDEX_op_ld8u_i32: 2133 case INDEX_op_ld8u_i64: 2134 tcg_out_ldst(s, OPC_LBU, a0, a1, a2); 2135 break; 2136 case INDEX_op_ld8s_i32: 2137 case INDEX_op_ld8s_i64: 2138 tcg_out_ldst(s, OPC_LB, a0, a1, a2); 2139 break; 2140 case INDEX_op_ld16u_i32: 2141 case INDEX_op_ld16u_i64: 2142 tcg_out_ldst(s, OPC_LHU, a0, a1, a2); 2143 break; 2144 case INDEX_op_ld16s_i32: 2145 case INDEX_op_ld16s_i64: 2146 tcg_out_ldst(s, OPC_LH, a0, a1, a2); 2147 break; 2148 case INDEX_op_ld32u_i64: 2149 tcg_out_ldst(s, OPC_LWU, a0, a1, a2); 2150 break; 2151 case INDEX_op_ld_i32: 2152 case INDEX_op_ld32s_i64: 2153 tcg_out_ldst(s, OPC_LW, a0, a1, a2); 2154 break; 2155 case INDEX_op_ld_i64: 2156 tcg_out_ldst(s, OPC_LD, a0, a1, a2); 2157 break; 2158 2159 case INDEX_op_st8_i32: 2160 case INDEX_op_st8_i64: 2161 tcg_out_ldst(s, OPC_SB, a0, a1, a2); 2162 break; 2163 case INDEX_op_st16_i32: 2164 case INDEX_op_st16_i64: 2165 tcg_out_ldst(s, OPC_SH, a0, a1, a2); 2166 break; 2167 case INDEX_op_st_i32: 2168 case INDEX_op_st32_i64: 2169 tcg_out_ldst(s, OPC_SW, a0, a1, a2); 2170 break; 2171 case INDEX_op_st_i64: 2172 tcg_out_ldst(s, OPC_SD, a0, a1, a2); 2173 break; 2174 2175 case INDEX_op_div_i32: 2176 tcg_out_opc_reg(s, OPC_DIVW, a0, a1, a2); 2177 break; 2178 case INDEX_op_div_i64: 2179 tcg_out_opc_reg(s, OPC_DIV, a0, a1, a2); 2180 break; 2181 2182 case INDEX_op_divu_i32: 2183 tcg_out_opc_reg(s, OPC_DIVUW, a0, a1, a2); 2184 break; 2185 case INDEX_op_divu_i64: 2186 tcg_out_opc_reg(s, OPC_DIVU, a0, a1, a2); 2187 break; 2188 2189 case INDEX_op_rem_i32: 2190 tcg_out_opc_reg(s, OPC_REMW, a0, a1, a2); 2191 break; 2192 case INDEX_op_rem_i64: 2193 tcg_out_opc_reg(s, OPC_REM, a0, a1, a2); 2194 break; 2195 2196 case INDEX_op_remu_i32: 2197 tcg_out_opc_reg(s, OPC_REMUW, a0, a1, a2); 2198 break; 2199 case INDEX_op_remu_i64: 2200 tcg_out_opc_reg(s, OPC_REMU, a0, a1, a2); 2201 break; 2202 2203 case INDEX_op_shl_i32: 2204 if (c2) { 2205 tcg_out_opc_imm(s, OPC_SLLIW, a0, a1, a2 & 0x1f); 2206 } else { 2207 tcg_out_opc_reg(s, OPC_SLLW, a0, a1, a2); 2208 } 2209 break; 2210 case INDEX_op_shl_i64: 2211 if (c2) { 2212 tcg_out_opc_imm(s, OPC_SLLI, a0, a1, a2 & 0x3f); 2213 } else { 2214 tcg_out_opc_reg(s, OPC_SLL, a0, a1, a2); 2215 } 2216 break; 2217 2218 case INDEX_op_shr_i32: 2219 if (c2) { 2220 tcg_out_opc_imm(s, OPC_SRLIW, a0, a1, a2 & 0x1f); 2221 } else { 2222 tcg_out_opc_reg(s, OPC_SRLW, a0, a1, a2); 2223 } 2224 break; 2225 case INDEX_op_shr_i64: 2226 if (c2) { 2227 tcg_out_opc_imm(s, OPC_SRLI, a0, a1, a2 & 0x3f); 2228 } else { 2229 tcg_out_opc_reg(s, OPC_SRL, a0, a1, a2); 2230 } 2231 break; 2232 2233 case INDEX_op_sar_i32: 2234 if (c2) { 2235 tcg_out_opc_imm(s, OPC_SRAIW, a0, a1, a2 & 0x1f); 2236 } else { 2237 tcg_out_opc_reg(s, OPC_SRAW, a0, a1, a2); 2238 } 2239 break; 2240 case INDEX_op_sar_i64: 2241 if (c2) { 2242 tcg_out_opc_imm(s, OPC_SRAI, a0, a1, a2 & 0x3f); 2243 } else { 2244 tcg_out_opc_reg(s, OPC_SRA, a0, a1, a2); 2245 } 2246 break; 2247 2248 case INDEX_op_rotl_i32: 2249 if (c2) { 2250 tcg_out_opc_imm(s, OPC_RORIW, a0, a1, -a2 & 0x1f); 2251 } else { 2252 tcg_out_opc_reg(s, OPC_ROLW, a0, a1, a2); 2253 } 2254 break; 2255 case INDEX_op_rotl_i64: 2256 if (c2) { 2257 tcg_out_opc_imm(s, OPC_RORI, a0, a1, -a2 & 0x3f); 2258 } else { 2259 tcg_out_opc_reg(s, OPC_ROL, a0, a1, a2); 2260 } 2261 break; 2262 2263 case INDEX_op_rotr_i32: 2264 if (c2) { 2265 tcg_out_opc_imm(s, OPC_RORIW, a0, a1, a2 & 0x1f); 2266 } else { 2267 tcg_out_opc_reg(s, OPC_RORW, a0, a1, a2); 2268 } 2269 break; 2270 case INDEX_op_rotr_i64: 2271 if (c2) { 2272 tcg_out_opc_imm(s, OPC_RORI, a0, a1, a2 & 0x3f); 2273 } else { 2274 tcg_out_opc_reg(s, OPC_ROR, a0, a1, a2); 2275 } 2276 break; 2277 2278 case INDEX_op_bswap64_i64: 2279 tcg_out_opc_imm(s, OPC_REV8, a0, a1, 0); 2280 break; 2281 case INDEX_op_bswap32_i32: 2282 a2 = 0; 2283 /* fall through */ 2284 case INDEX_op_bswap32_i64: 2285 tcg_out_opc_imm(s, OPC_REV8, a0, a1, 0); 2286 if (a2 & TCG_BSWAP_OZ) { 2287 tcg_out_opc_imm(s, OPC_SRLI, a0, a0, 32); 2288 } else { 2289 tcg_out_opc_imm(s, OPC_SRAI, a0, a0, 32); 2290 } 2291 break; 2292 case INDEX_op_bswap16_i64: 2293 case INDEX_op_bswap16_i32: 2294 tcg_out_opc_imm(s, OPC_REV8, a0, a1, 0); 2295 if (a2 & TCG_BSWAP_OZ) { 2296 tcg_out_opc_imm(s, OPC_SRLI, a0, a0, 48); 2297 } else { 2298 tcg_out_opc_imm(s, OPC_SRAI, a0, a0, 48); 2299 } 2300 break; 2301 2302 case INDEX_op_ctpop_i32: 2303 tcg_out_opc_imm(s, OPC_CPOPW, a0, a1, 0); 2304 break; 2305 case INDEX_op_ctpop_i64: 2306 tcg_out_opc_imm(s, OPC_CPOP, a0, a1, 0); 2307 break; 2308 2309 case INDEX_op_clz_i32: 2310 tcg_out_cltz(s, TCG_TYPE_I32, OPC_CLZW, a0, a1, a2, c2); 2311 break; 2312 case INDEX_op_clz_i64: 2313 tcg_out_cltz(s, TCG_TYPE_I64, OPC_CLZ, a0, a1, a2, c2); 2314 break; 2315 case INDEX_op_ctz_i32: 2316 tcg_out_cltz(s, TCG_TYPE_I32, OPC_CTZW, a0, a1, a2, c2); 2317 break; 2318 case INDEX_op_ctz_i64: 2319 tcg_out_cltz(s, TCG_TYPE_I64, OPC_CTZ, a0, a1, a2, c2); 2320 break; 2321 2322 case INDEX_op_add2_i32: 2323 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 2324 const_args[4], const_args[5], false, true); 2325 break; 2326 case INDEX_op_add2_i64: 2327 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 2328 const_args[4], const_args[5], false, false); 2329 break; 2330 case INDEX_op_sub2_i32: 2331 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 2332 const_args[4], const_args[5], true, true); 2333 break; 2334 case INDEX_op_sub2_i64: 2335 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 2336 const_args[4], const_args[5], true, false); 2337 break; 2338 2339 case INDEX_op_brcond_i32: 2340 case INDEX_op_brcond_i64: 2341 tcg_out_brcond(s, a2, a0, a1, arg_label(args[3])); 2342 break; 2343 2344 case INDEX_op_setcond_i32: 2345 case INDEX_op_setcond_i64: 2346 tcg_out_setcond(s, args[3], a0, a1, a2, c2); 2347 break; 2348 2349 case INDEX_op_negsetcond_i32: 2350 case INDEX_op_negsetcond_i64: 2351 tcg_out_negsetcond(s, args[3], a0, a1, a2, c2); 2352 break; 2353 2354 case INDEX_op_movcond_i32: 2355 case INDEX_op_movcond_i64: 2356 tcg_out_movcond(s, args[5], a0, a1, a2, c2, 2357 args[3], const_args[3], args[4], const_args[4]); 2358 break; 2359 2360 case INDEX_op_qemu_ld_i32: 2361 tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32); 2362 break; 2363 case INDEX_op_qemu_ld_i64: 2364 tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64); 2365 break; 2366 case INDEX_op_qemu_st_i32: 2367 tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32); 2368 break; 2369 case INDEX_op_qemu_st_i64: 2370 tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64); 2371 break; 2372 2373 case INDEX_op_extrh_i64_i32: 2374 tcg_out_opc_imm(s, OPC_SRAI, a0, a1, 32); 2375 break; 2376 2377 case INDEX_op_mulsh_i32: 2378 case INDEX_op_mulsh_i64: 2379 tcg_out_opc_reg(s, OPC_MULH, a0, a1, a2); 2380 break; 2381 2382 case INDEX_op_muluh_i32: 2383 case INDEX_op_muluh_i64: 2384 tcg_out_opc_reg(s, OPC_MULHU, a0, a1, a2); 2385 break; 2386 2387 case INDEX_op_mb: 2388 tcg_out_mb(s, a0); 2389 break; 2390 2391 case INDEX_op_extract_i64: 2392 if (a2 + args[3] == 32) { 2393 if (a2 == 0) { 2394 tcg_out_ext32u(s, a0, a1); 2395 } else { 2396 tcg_out_opc_imm(s, OPC_SRLIW, a0, a1, a2); 2397 } 2398 break; 2399 } 2400 /* FALLTHRU */ 2401 case INDEX_op_extract_i32: 2402 switch (args[3]) { 2403 case 1: 2404 tcg_out_opc_imm(s, OPC_BEXTI, a0, a1, a2); 2405 break; 2406 case 16: 2407 tcg_debug_assert(a2 == 0); 2408 tcg_out_ext16u(s, a0, a1); 2409 break; 2410 default: 2411 g_assert_not_reached(); 2412 } 2413 break; 2414 2415 case INDEX_op_sextract_i64: 2416 if (a2 + args[3] == 32) { 2417 if (a2 == 0) { 2418 tcg_out_ext32s(s, a0, a1); 2419 } else { 2420 tcg_out_opc_imm(s, OPC_SRAIW, a0, a1, a2); 2421 } 2422 break; 2423 } 2424 /* FALLTHRU */ 2425 case INDEX_op_sextract_i32: 2426 if (a2 == 0 && args[3] == 8) { 2427 tcg_out_ext8s(s, TCG_TYPE_REG, a0, a1); 2428 } else if (a2 == 0 && args[3] == 16) { 2429 tcg_out_ext16s(s, TCG_TYPE_REG, a0, a1); 2430 } else { 2431 g_assert_not_reached(); 2432 } 2433 break; 2434 2435 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2436 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 2437 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 2438 case INDEX_op_ext_i32_i64: /* Always emitted via tcg_reg_alloc_op. */ 2439 case INDEX_op_extu_i32_i64: 2440 case INDEX_op_extrl_i64_i32: 2441 default: 2442 g_assert_not_reached(); 2443 } 2444} 2445 2446static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 2447 unsigned vecl, unsigned vece, 2448 const TCGArg args[TCG_MAX_OP_ARGS], 2449 const int const_args[TCG_MAX_OP_ARGS]) 2450{ 2451 TCGType type = vecl + TCG_TYPE_V64; 2452 TCGArg a0, a1, a2; 2453 int c2; 2454 2455 a0 = args[0]; 2456 a1 = args[1]; 2457 a2 = args[2]; 2458 c2 = const_args[2]; 2459 2460 switch (opc) { 2461 case INDEX_op_dupm_vec: 2462 tcg_out_dupm_vec(s, type, vece, a0, a1, a2); 2463 break; 2464 case INDEX_op_ld_vec: 2465 tcg_out_ld(s, type, a0, a1, a2); 2466 break; 2467 case INDEX_op_st_vec: 2468 tcg_out_st(s, type, a0, a1, a2); 2469 break; 2470 case INDEX_op_add_vec: 2471 set_vtype_len_sew(s, type, vece); 2472 tcg_out_opc_vv_vi(s, OPC_VADD_VV, OPC_VADD_VI, a0, a1, a2, c2); 2473 break; 2474 case INDEX_op_sub_vec: 2475 set_vtype_len_sew(s, type, vece); 2476 if (const_args[1]) { 2477 tcg_out_opc_vi(s, OPC_VRSUB_VI, a0, a2, a1); 2478 } else { 2479 tcg_out_opc_vv(s, OPC_VSUB_VV, a0, a1, a2); 2480 } 2481 break; 2482 case INDEX_op_and_vec: 2483 set_vtype_len(s, type); 2484 tcg_out_opc_vv_vi(s, OPC_VAND_VV, OPC_VAND_VI, a0, a1, a2, c2); 2485 break; 2486 case INDEX_op_or_vec: 2487 set_vtype_len(s, type); 2488 tcg_out_opc_vv_vi(s, OPC_VOR_VV, OPC_VOR_VI, a0, a1, a2, c2); 2489 break; 2490 case INDEX_op_xor_vec: 2491 set_vtype_len(s, type); 2492 tcg_out_opc_vv_vi(s, OPC_VXOR_VV, OPC_VXOR_VI, a0, a1, a2, c2); 2493 break; 2494 case INDEX_op_not_vec: 2495 set_vtype_len(s, type); 2496 tcg_out_opc_vi(s, OPC_VXOR_VI, a0, a1, -1); 2497 break; 2498 case INDEX_op_neg_vec: 2499 set_vtype_len_sew(s, type, vece); 2500 tcg_out_opc_vi(s, OPC_VRSUB_VI, a0, a1, 0); 2501 break; 2502 case INDEX_op_mul_vec: 2503 set_vtype_len_sew(s, type, vece); 2504 tcg_out_opc_vv(s, OPC_VMUL_VV, a0, a1, a2); 2505 break; 2506 case INDEX_op_ssadd_vec: 2507 set_vtype_len_sew(s, type, vece); 2508 tcg_out_opc_vv_vi(s, OPC_VSADD_VV, OPC_VSADD_VI, a0, a1, a2, c2); 2509 break; 2510 case INDEX_op_sssub_vec: 2511 set_vtype_len_sew(s, type, vece); 2512 tcg_out_opc_vv_vi(s, OPC_VSSUB_VV, OPC_VSSUB_VI, a0, a1, a2, c2); 2513 break; 2514 case INDEX_op_usadd_vec: 2515 set_vtype_len_sew(s, type, vece); 2516 tcg_out_opc_vv_vi(s, OPC_VSADDU_VV, OPC_VSADDU_VI, a0, a1, a2, c2); 2517 break; 2518 case INDEX_op_ussub_vec: 2519 set_vtype_len_sew(s, type, vece); 2520 tcg_out_opc_vv_vi(s, OPC_VSSUBU_VV, OPC_VSSUBU_VI, a0, a1, a2, c2); 2521 break; 2522 case INDEX_op_smax_vec: 2523 set_vtype_len_sew(s, type, vece); 2524 tcg_out_opc_vv_vi(s, OPC_VMAX_VV, OPC_VMAX_VI, a0, a1, a2, c2); 2525 break; 2526 case INDEX_op_smin_vec: 2527 set_vtype_len_sew(s, type, vece); 2528 tcg_out_opc_vv_vi(s, OPC_VMIN_VV, OPC_VMIN_VI, a0, a1, a2, c2); 2529 break; 2530 case INDEX_op_umax_vec: 2531 set_vtype_len_sew(s, type, vece); 2532 tcg_out_opc_vv_vi(s, OPC_VMAXU_VV, OPC_VMAXU_VI, a0, a1, a2, c2); 2533 break; 2534 case INDEX_op_umin_vec: 2535 set_vtype_len_sew(s, type, vece); 2536 tcg_out_opc_vv_vi(s, OPC_VMINU_VV, OPC_VMINU_VI, a0, a1, a2, c2); 2537 break; 2538 case INDEX_op_shls_vec: 2539 set_vtype_len_sew(s, type, vece); 2540 tcg_out_opc_vx(s, OPC_VSLL_VX, a0, a1, a2); 2541 break; 2542 case INDEX_op_shrs_vec: 2543 set_vtype_len_sew(s, type, vece); 2544 tcg_out_opc_vx(s, OPC_VSRL_VX, a0, a1, a2); 2545 break; 2546 case INDEX_op_sars_vec: 2547 set_vtype_len_sew(s, type, vece); 2548 tcg_out_opc_vx(s, OPC_VSRA_VX, a0, a1, a2); 2549 break; 2550 case INDEX_op_shlv_vec: 2551 set_vtype_len_sew(s, type, vece); 2552 tcg_out_opc_vv(s, OPC_VSLL_VV, a0, a1, a2); 2553 break; 2554 case INDEX_op_shrv_vec: 2555 set_vtype_len_sew(s, type, vece); 2556 tcg_out_opc_vv(s, OPC_VSRL_VV, a0, a1, a2); 2557 break; 2558 case INDEX_op_sarv_vec: 2559 set_vtype_len_sew(s, type, vece); 2560 tcg_out_opc_vv(s, OPC_VSRA_VV, a0, a1, a2); 2561 break; 2562 case INDEX_op_shli_vec: 2563 set_vtype_len_sew(s, type, vece); 2564 tcg_out_vshifti(s, OPC_VSLL_VI, OPC_VSLL_VX, a0, a1, a2); 2565 break; 2566 case INDEX_op_shri_vec: 2567 set_vtype_len_sew(s, type, vece); 2568 tcg_out_vshifti(s, OPC_VSRL_VI, OPC_VSRL_VX, a0, a1, a2); 2569 break; 2570 case INDEX_op_sari_vec: 2571 set_vtype_len_sew(s, type, vece); 2572 tcg_out_vshifti(s, OPC_VSRA_VI, OPC_VSRA_VX, a0, a1, a2); 2573 break; 2574 case INDEX_op_rotli_vec: 2575 set_vtype_len_sew(s, type, vece); 2576 tcg_out_vshifti(s, OPC_VSLL_VI, OPC_VSLL_VX, TCG_REG_V0, a1, a2); 2577 tcg_out_vshifti(s, OPC_VSRL_VI, OPC_VSRL_VX, a0, a1, 2578 -a2 & ((8 << vece) - 1)); 2579 tcg_out_opc_vv(s, OPC_VOR_VV, a0, a0, TCG_REG_V0); 2580 break; 2581 case INDEX_op_rotls_vec: 2582 set_vtype_len_sew(s, type, vece); 2583 tcg_out_opc_vx(s, OPC_VSLL_VX, TCG_REG_V0, a1, a2); 2584 tcg_out_opc_reg(s, OPC_SUBW, TCG_REG_TMP0, TCG_REG_ZERO, a2); 2585 tcg_out_opc_vx(s, OPC_VSRL_VX, a0, a1, TCG_REG_TMP0); 2586 tcg_out_opc_vv(s, OPC_VOR_VV, a0, a0, TCG_REG_V0); 2587 break; 2588 case INDEX_op_rotlv_vec: 2589 set_vtype_len_sew(s, type, vece); 2590 tcg_out_opc_vi(s, OPC_VRSUB_VI, TCG_REG_V0, a2, 0); 2591 tcg_out_opc_vv(s, OPC_VSRL_VV, TCG_REG_V0, a1, TCG_REG_V0); 2592 tcg_out_opc_vv(s, OPC_VSLL_VV, a0, a1, a2); 2593 tcg_out_opc_vv(s, OPC_VOR_VV, a0, a0, TCG_REG_V0); 2594 break; 2595 case INDEX_op_rotrv_vec: 2596 set_vtype_len_sew(s, type, vece); 2597 tcg_out_opc_vi(s, OPC_VRSUB_VI, TCG_REG_V0, a2, 0); 2598 tcg_out_opc_vv(s, OPC_VSLL_VV, TCG_REG_V0, a1, TCG_REG_V0); 2599 tcg_out_opc_vv(s, OPC_VSRL_VV, a0, a1, a2); 2600 tcg_out_opc_vv(s, OPC_VOR_VV, a0, a0, TCG_REG_V0); 2601 break; 2602 case INDEX_op_cmp_vec: 2603 tcg_out_cmpsel(s, type, vece, args[3], a0, a1, a2, c2, 2604 -1, true, 0, true); 2605 break; 2606 case INDEX_op_cmpsel_vec: 2607 tcg_out_cmpsel(s, type, vece, args[5], a0, a1, a2, c2, 2608 args[3], const_args[3], args[4], const_args[4]); 2609 break; 2610 case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ 2611 case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ 2612 default: 2613 g_assert_not_reached(); 2614 } 2615} 2616 2617void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, 2618 TCGArg a0, ...) 2619{ 2620 g_assert_not_reached(); 2621} 2622 2623int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) 2624{ 2625 switch (opc) { 2626 case INDEX_op_add_vec: 2627 case INDEX_op_sub_vec: 2628 case INDEX_op_and_vec: 2629 case INDEX_op_or_vec: 2630 case INDEX_op_xor_vec: 2631 case INDEX_op_not_vec: 2632 case INDEX_op_neg_vec: 2633 case INDEX_op_mul_vec: 2634 case INDEX_op_ssadd_vec: 2635 case INDEX_op_sssub_vec: 2636 case INDEX_op_usadd_vec: 2637 case INDEX_op_ussub_vec: 2638 case INDEX_op_smax_vec: 2639 case INDEX_op_smin_vec: 2640 case INDEX_op_umax_vec: 2641 case INDEX_op_umin_vec: 2642 case INDEX_op_shls_vec: 2643 case INDEX_op_shrs_vec: 2644 case INDEX_op_sars_vec: 2645 case INDEX_op_shlv_vec: 2646 case INDEX_op_shrv_vec: 2647 case INDEX_op_sarv_vec: 2648 case INDEX_op_shri_vec: 2649 case INDEX_op_shli_vec: 2650 case INDEX_op_sari_vec: 2651 case INDEX_op_rotls_vec: 2652 case INDEX_op_rotlv_vec: 2653 case INDEX_op_rotrv_vec: 2654 case INDEX_op_rotli_vec: 2655 case INDEX_op_cmp_vec: 2656 case INDEX_op_cmpsel_vec: 2657 return 1; 2658 default: 2659 return 0; 2660 } 2661} 2662 2663static TCGConstraintSetIndex 2664tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) 2665{ 2666 switch (op) { 2667 case INDEX_op_goto_ptr: 2668 return C_O0_I1(r); 2669 2670 case INDEX_op_ld8u_i32: 2671 case INDEX_op_ld8s_i32: 2672 case INDEX_op_ld16u_i32: 2673 case INDEX_op_ld16s_i32: 2674 case INDEX_op_ld_i32: 2675 case INDEX_op_ld8u_i64: 2676 case INDEX_op_ld8s_i64: 2677 case INDEX_op_ld16u_i64: 2678 case INDEX_op_ld16s_i64: 2679 case INDEX_op_ld32s_i64: 2680 case INDEX_op_ld32u_i64: 2681 case INDEX_op_ld_i64: 2682 case INDEX_op_extu_i32_i64: 2683 case INDEX_op_extrl_i64_i32: 2684 case INDEX_op_extrh_i64_i32: 2685 case INDEX_op_ext_i32_i64: 2686 case INDEX_op_extract_i32: 2687 case INDEX_op_extract_i64: 2688 case INDEX_op_sextract_i32: 2689 case INDEX_op_sextract_i64: 2690 case INDEX_op_bswap16_i32: 2691 case INDEX_op_bswap32_i32: 2692 case INDEX_op_bswap16_i64: 2693 case INDEX_op_bswap32_i64: 2694 case INDEX_op_bswap64_i64: 2695 case INDEX_op_ctpop_i32: 2696 case INDEX_op_ctpop_i64: 2697 return C_O1_I1(r, r); 2698 2699 case INDEX_op_st8_i32: 2700 case INDEX_op_st16_i32: 2701 case INDEX_op_st_i32: 2702 case INDEX_op_st8_i64: 2703 case INDEX_op_st16_i64: 2704 case INDEX_op_st32_i64: 2705 case INDEX_op_st_i64: 2706 return C_O0_I2(rz, r); 2707 2708 case INDEX_op_setcond_i32: 2709 case INDEX_op_setcond_i64: 2710 case INDEX_op_negsetcond_i32: 2711 case INDEX_op_negsetcond_i64: 2712 return C_O1_I2(r, r, rI); 2713 2714 case INDEX_op_mulsh_i32: 2715 case INDEX_op_muluh_i32: 2716 case INDEX_op_div_i32: 2717 case INDEX_op_divu_i32: 2718 case INDEX_op_rem_i32: 2719 case INDEX_op_remu_i32: 2720 case INDEX_op_mulsh_i64: 2721 case INDEX_op_muluh_i64: 2722 case INDEX_op_div_i64: 2723 case INDEX_op_divu_i64: 2724 case INDEX_op_rem_i64: 2725 case INDEX_op_remu_i64: 2726 return C_O1_I2(r, rz, rz); 2727 2728 case INDEX_op_shl_i32: 2729 case INDEX_op_shr_i32: 2730 case INDEX_op_sar_i32: 2731 case INDEX_op_rotl_i32: 2732 case INDEX_op_rotr_i32: 2733 case INDEX_op_shl_i64: 2734 case INDEX_op_shr_i64: 2735 case INDEX_op_sar_i64: 2736 case INDEX_op_rotl_i64: 2737 case INDEX_op_rotr_i64: 2738 return C_O1_I2(r, r, ri); 2739 2740 case INDEX_op_clz_i32: 2741 case INDEX_op_clz_i64: 2742 case INDEX_op_ctz_i32: 2743 case INDEX_op_ctz_i64: 2744 return C_N1_I2(r, r, rM); 2745 2746 case INDEX_op_brcond_i32: 2747 case INDEX_op_brcond_i64: 2748 return C_O0_I2(rz, rz); 2749 2750 case INDEX_op_movcond_i32: 2751 case INDEX_op_movcond_i64: 2752 return C_O1_I4(r, r, rI, rM, rM); 2753 2754 case INDEX_op_add2_i32: 2755 case INDEX_op_add2_i64: 2756 case INDEX_op_sub2_i32: 2757 case INDEX_op_sub2_i64: 2758 return C_O2_I4(r, r, rz, rz, rM, rM); 2759 2760 case INDEX_op_qemu_ld_i32: 2761 case INDEX_op_qemu_ld_i64: 2762 return C_O1_I1(r, r); 2763 case INDEX_op_qemu_st_i32: 2764 case INDEX_op_qemu_st_i64: 2765 return C_O0_I2(rz, r); 2766 2767 case INDEX_op_st_vec: 2768 return C_O0_I2(v, r); 2769 case INDEX_op_dup_vec: 2770 case INDEX_op_dupm_vec: 2771 case INDEX_op_ld_vec: 2772 return C_O1_I1(v, r); 2773 case INDEX_op_neg_vec: 2774 case INDEX_op_not_vec: 2775 case INDEX_op_shli_vec: 2776 case INDEX_op_shri_vec: 2777 case INDEX_op_sari_vec: 2778 case INDEX_op_rotli_vec: 2779 return C_O1_I1(v, v); 2780 case INDEX_op_add_vec: 2781 case INDEX_op_and_vec: 2782 case INDEX_op_or_vec: 2783 case INDEX_op_xor_vec: 2784 case INDEX_op_ssadd_vec: 2785 case INDEX_op_sssub_vec: 2786 case INDEX_op_usadd_vec: 2787 case INDEX_op_ussub_vec: 2788 case INDEX_op_smax_vec: 2789 case INDEX_op_smin_vec: 2790 case INDEX_op_umax_vec: 2791 case INDEX_op_umin_vec: 2792 return C_O1_I2(v, v, vK); 2793 case INDEX_op_sub_vec: 2794 return C_O1_I2(v, vK, v); 2795 case INDEX_op_mul_vec: 2796 case INDEX_op_shlv_vec: 2797 case INDEX_op_shrv_vec: 2798 case INDEX_op_sarv_vec: 2799 case INDEX_op_rotlv_vec: 2800 case INDEX_op_rotrv_vec: 2801 return C_O1_I2(v, v, v); 2802 case INDEX_op_shls_vec: 2803 case INDEX_op_shrs_vec: 2804 case INDEX_op_sars_vec: 2805 case INDEX_op_rotls_vec: 2806 return C_O1_I2(v, v, r); 2807 case INDEX_op_cmp_vec: 2808 return C_O1_I2(v, v, vL); 2809 case INDEX_op_cmpsel_vec: 2810 return C_O1_I4(v, v, vL, vK, vK); 2811 default: 2812 return C_NotImplemented; 2813 } 2814} 2815 2816static const int tcg_target_callee_save_regs[] = { 2817 TCG_REG_S0, /* used for the global env (TCG_AREG0) */ 2818 TCG_REG_S1, 2819 TCG_REG_S2, 2820 TCG_REG_S3, 2821 TCG_REG_S4, 2822 TCG_REG_S5, 2823 TCG_REG_S6, 2824 TCG_REG_S7, 2825 TCG_REG_S8, 2826 TCG_REG_S9, 2827 TCG_REG_S10, 2828 TCG_REG_S11, 2829 TCG_REG_RA, /* should be last for ABI compliance */ 2830}; 2831 2832/* Stack frame parameters. */ 2833#define REG_SIZE (TCG_TARGET_REG_BITS / 8) 2834#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) 2835#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) 2836#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ 2837 + TCG_TARGET_STACK_ALIGN - 1) \ 2838 & -TCG_TARGET_STACK_ALIGN) 2839#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) 2840 2841/* We're expecting to be able to use an immediate for frame allocation. */ 2842QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7ff); 2843 2844/* Generate global QEMU prologue and epilogue code */ 2845static void tcg_target_qemu_prologue(TCGContext *s) 2846{ 2847 int i; 2848 2849 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); 2850 2851 /* TB prologue */ 2852 tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); 2853 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2854 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2855 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2856 } 2857 2858 if (!tcg_use_softmmu && guest_base) { 2859 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); 2860 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 2861 } 2862 2863 /* Call generated code */ 2864 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 2865 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 0); 2866 2867 /* Return path for goto_ptr. Set return value to 0 */ 2868 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 2869 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_A0, TCG_REG_ZERO); 2870 2871 /* TB epilogue */ 2872 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 2873 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2874 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2875 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2876 } 2877 2878 tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); 2879 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_RA, 0); 2880} 2881 2882static void tcg_out_tb_start(TCGContext *s) 2883{ 2884 init_setting_vtype(s); 2885} 2886 2887static bool vtype_check(unsigned vtype) 2888{ 2889 unsigned long tmp; 2890 2891 /* vsetvl tmp, zero, vtype */ 2892 asm(".insn r 0x57, 7, 0x40, %0, zero, %1" : "=r"(tmp) : "r"(vtype)); 2893 return tmp != 0; 2894} 2895 2896static void probe_frac_lmul_1(TCGType type, MemOp vsew) 2897{ 2898 VsetCache *p = &riscv_vset_cache[type - TCG_TYPE_V64][vsew]; 2899 unsigned avl = tcg_type_size(type) >> vsew; 2900 int lmul = type - riscv_lg2_vlenb; 2901 unsigned vtype = encode_vtype(true, true, vsew, lmul & 7); 2902 bool lmul_eq_avl = true; 2903 2904 /* Guaranteed by Zve64x. */ 2905 assert(lmul < 3); 2906 2907 /* 2908 * For LMUL < -3, the host vector size is so large that TYPE 2909 * is smaller than the minimum 1/8 fraction. 2910 * 2911 * For other fractional LMUL settings, implementations must 2912 * support SEW settings between SEW_MIN and LMUL * ELEN, inclusive. 2913 * So if ELEN = 64, LMUL = 1/2, then SEW will support e8, e16, e32, 2914 * but e64 may not be supported. In other words, the hardware only 2915 * guarantees SEW_MIN <= SEW <= LMUL * ELEN. Check. 2916 */ 2917 if (lmul < 0 && (lmul < -3 || !vtype_check(vtype))) { 2918 vtype = encode_vtype(true, true, vsew, VLMUL_M1); 2919 lmul_eq_avl = false; 2920 } 2921 2922 if (avl < 32) { 2923 p->vset_insn = encode_vseti(OPC_VSETIVLI, TCG_REG_ZERO, avl, vtype); 2924 } else if (lmul_eq_avl) { 2925 /* rd != 0 and rs1 == 0 uses vlmax */ 2926 p->vset_insn = encode_vset(OPC_VSETVLI, TCG_REG_TMP0, TCG_REG_ZERO, vtype); 2927 } else { 2928 p->movi_insn = encode_i(OPC_ADDI, TCG_REG_TMP0, TCG_REG_ZERO, avl); 2929 p->vset_insn = encode_vset(OPC_VSETVLI, TCG_REG_ZERO, TCG_REG_TMP0, vtype); 2930 } 2931} 2932 2933static void probe_frac_lmul(void) 2934{ 2935 /* Match riscv_lg2_vlenb to TCG_TYPE_V64. */ 2936 QEMU_BUILD_BUG_ON(TCG_TYPE_V64 != 3); 2937 2938 for (TCGType t = TCG_TYPE_V64; t <= TCG_TYPE_V256; t++) { 2939 for (MemOp e = MO_8; e <= MO_64; e++) { 2940 probe_frac_lmul_1(t, e); 2941 } 2942 } 2943} 2944 2945static void tcg_target_init(TCGContext *s) 2946{ 2947 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; 2948 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; 2949 2950 tcg_target_call_clobber_regs = -1; 2951 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S0); 2952 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S1); 2953 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S2); 2954 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S3); 2955 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S4); 2956 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S5); 2957 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S6); 2958 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S7); 2959 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S8); 2960 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S9); 2961 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S10); 2962 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S11); 2963 2964 s->reserved_regs = 0; 2965 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); 2966 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP0); 2967 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); 2968 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2); 2969 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); 2970 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); 2971 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TP); 2972 2973 if (cpuinfo & CPUINFO_ZVE64X) { 2974 switch (riscv_lg2_vlenb) { 2975 case TCG_TYPE_V64: 2976 tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS; 2977 tcg_target_available_regs[TCG_TYPE_V128] = ALL_DVECTOR_REG_GROUPS; 2978 tcg_target_available_regs[TCG_TYPE_V256] = ALL_QVECTOR_REG_GROUPS; 2979 s->reserved_regs |= (~ALL_QVECTOR_REG_GROUPS & ALL_VECTOR_REGS); 2980 break; 2981 case TCG_TYPE_V128: 2982 tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS; 2983 tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS; 2984 tcg_target_available_regs[TCG_TYPE_V256] = ALL_DVECTOR_REG_GROUPS; 2985 s->reserved_regs |= (~ALL_DVECTOR_REG_GROUPS & ALL_VECTOR_REGS); 2986 break; 2987 default: 2988 /* Guaranteed by Zve64x. */ 2989 tcg_debug_assert(riscv_lg2_vlenb >= TCG_TYPE_V256); 2990 tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS; 2991 tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS; 2992 tcg_target_available_regs[TCG_TYPE_V256] = ALL_VECTOR_REGS; 2993 break; 2994 } 2995 tcg_regset_set_reg(s->reserved_regs, TCG_REG_V0); 2996 probe_frac_lmul(); 2997 } 2998} 2999 3000typedef struct { 3001 DebugFrameHeader h; 3002 uint8_t fde_def_cfa[4]; 3003 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2]; 3004} DebugFrame; 3005 3006#define ELF_HOST_MACHINE EM_RISCV 3007 3008static const DebugFrame debug_frame = { 3009 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ 3010 .h.cie.id = -1, 3011 .h.cie.version = 1, 3012 .h.cie.code_align = 1, 3013 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ 3014 .h.cie.return_column = TCG_REG_RA, 3015 3016 /* Total FDE size does not include the "len" member. */ 3017 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 3018 3019 .fde_def_cfa = { 3020 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ 3021 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 3022 (FRAME_SIZE >> 7) 3023 }, 3024 .fde_reg_ofs = { 3025 0x80 + 9, 12, /* DW_CFA_offset, s1, -96 */ 3026 0x80 + 18, 11, /* DW_CFA_offset, s2, -88 */ 3027 0x80 + 19, 10, /* DW_CFA_offset, s3, -80 */ 3028 0x80 + 20, 9, /* DW_CFA_offset, s4, -72 */ 3029 0x80 + 21, 8, /* DW_CFA_offset, s5, -64 */ 3030 0x80 + 22, 7, /* DW_CFA_offset, s6, -56 */ 3031 0x80 + 23, 6, /* DW_CFA_offset, s7, -48 */ 3032 0x80 + 24, 5, /* DW_CFA_offset, s8, -40 */ 3033 0x80 + 25, 4, /* DW_CFA_offset, s9, -32 */ 3034 0x80 + 26, 3, /* DW_CFA_offset, s10, -24 */ 3035 0x80 + 27, 2, /* DW_CFA_offset, s11, -16 */ 3036 0x80 + 1 , 1, /* DW_CFA_offset, ra, -8 */ 3037 } 3038}; 3039 3040void tcg_register_jit(const void *buf, size_t buf_size) 3041{ 3042 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 3043} 3044